Coverage Report

Created: 2018-09-25 17:16

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
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//===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the MachineRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
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#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/PointerUnion.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringSet.h"
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#include "llvm/ADT/iterator_range.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/LowLevelType.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/MC/LaneBitmask.h"
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#include <cassert>
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#include <cstddef>
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#include <cstdint>
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#include <iterator>
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#include <memory>
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#include <utility>
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#include <vector>
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42
namespace llvm {
43
44
class PSetIterator;
45
46
/// Convenient type to represent either a register class or a register bank.
47
using RegClassOrRegBank =
48
    PointerUnion<const TargetRegisterClass *, const RegisterBank *>;
49
50
/// MachineRegisterInfo - Keep track of information for virtual and physical
51
/// registers, including vreg register classes, use/def chains for registers,
52
/// etc.
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class MachineRegisterInfo {
54
public:
55
  class Delegate {
56
    virtual void anchor();
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58
  public:
59
1.33M
    virtual ~Delegate() = default;
60
61
    virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
62
  };
63
64
private:
65
  MachineFunction *MF;
66
  Delegate *TheDelegate = nullptr;
67
68
  /// True if subregister liveness is tracked.
69
  const bool TracksSubRegLiveness;
70
71
  /// VRegInfo - Information we keep for each virtual register.
72
  ///
73
  /// Each element in this list contains the register class of the vreg and the
74
  /// start of the use/def list for the register.
75
  IndexedMap<std::pair<RegClassOrRegBank, MachineOperand *>,
76
             VirtReg2IndexFunctor>
77
      VRegInfo;
78
79
  /// Map for recovering vreg name from vreg number.
80
  /// This map is used by the MIR Printer.
81
  IndexedMap<std::string, VirtReg2IndexFunctor> VReg2Name;
82
83
  /// StringSet that is used to unique vreg names.
84
  StringSet<> VRegNames;
85
86
  /// The flag is true upon \p UpdatedCSRs initialization
87
  /// and false otherwise.
88
  bool IsUpdatedCSRsInitialized;
89
90
  /// Contains the updated callee saved register list.
91
  /// As opposed to the static list defined in register info,
92
  /// all registers that were disabled are removed from the list.
93
  SmallVector<MCPhysReg, 16> UpdatedCSRs;
94
95
  /// RegAllocHints - This vector records register allocation hints for
96
  /// virtual registers. For each virtual register, it keeps a pair of hint
97
  /// type and hints vector making up the allocation hints. Only the first
98
  /// hint may be target specific, and in that case this is reflected by the
99
  /// first member of the pair being non-zero. If the hinted register is
100
  /// virtual, it means the allocator should prefer the physical register
101
  /// allocated to it if any.
102
  IndexedMap<std::pair<unsigned, SmallVector<unsigned, 4>>,
103
             VirtReg2IndexFunctor> RegAllocHints;
104
105
  /// PhysRegUseDefLists - This is an array of the head of the use/def list for
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  /// physical registers.
107
  std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
108
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  /// getRegUseDefListHead - Return the head pointer for the register use/def
110
  /// list for the specified virtual or physical register.
111
336M
  MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
112
336M
    if (TargetRegisterInfo::isVirtualRegister(RegNo))
113
158M
      return VRegInfo[RegNo].second;
114
178M
    return PhysRegUseDefLists[RegNo];
115
178M
  }
116
117
852M
  MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
118
852M
    if (TargetRegisterInfo::isVirtualRegister(RegNo))
119
414M
      return VRegInfo[RegNo].second;
120
437M
    return PhysRegUseDefLists[RegNo];
121
437M
  }
122
123
  /// Get the next element in the use-def chain.
124
417M
  static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
125
417M
    assert(MO && MO->isReg() && "This is not a register operand!");
126
417M
    return MO->Contents.Reg.Next;
127
417M
  }
128
129
  /// UsedPhysRegMask - Additional used physregs including aliases.
130
  /// This bit vector represents all the registers clobbered by function calls.
131
  BitVector UsedPhysRegMask;
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133
  /// ReservedRegs - This is a bit vector of reserved registers.  The target
134
  /// may change its mind about which registers should be reserved.  This
135
  /// vector is the frozen set of reserved registers when register allocation
136
  /// started.
137
  BitVector ReservedRegs;
138
139
  using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;
140
  /// Map generic virtual registers to their low-level type.
141
  VRegToTypeMap VRegToType;
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  /// Keep track of the physical registers that are live in to the function.
144
  /// Live in values are typically arguments in registers.  LiveIn values are
145
  /// allowed to have virtual registers associated with them, stored in the
146
  /// second element.
147
  std::vector<std::pair<unsigned, unsigned>> LiveIns;
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public:
150
  explicit MachineRegisterInfo(MachineFunction *MF);
151
  MachineRegisterInfo(const MachineRegisterInfo &) = delete;
152
  MachineRegisterInfo &operator=(const MachineRegisterInfo &) = delete;
153
154
143M
  const TargetRegisterInfo *getTargetRegisterInfo() const {
155
143M
    return MF->getSubtarget().getRegisterInfo();
156
143M
  }
157
158
1.33M
  void resetDelegate(Delegate *delegate) {
159
1.33M
    // Ensure another delegate does not take over unless the current
160
1.33M
    // delegate first unattaches itself. If we ever need to multicast
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1.33M
    // notifications, we will need to change to using a list.
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1.33M
    assert(TheDelegate == delegate &&
163
1.33M
           "Only the current delegate can perform reset!");
164
1.33M
    TheDelegate = nullptr;
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1.33M
  }
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167
1.33M
  void setDelegate(Delegate *delegate) {
168
1.33M
    assert(delegate && !TheDelegate &&
169
1.33M
           "Attempted to set delegate to null, or to change it without "
170
1.33M
           "first resetting it!");
171
1.33M
172
1.33M
    TheDelegate = delegate;
173
1.33M
  }
174
175
  //===--------------------------------------------------------------------===//
176
  // Function State
177
  //===--------------------------------------------------------------------===//
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  // isSSA - Returns true when the machine function is in SSA form. Early
180
  // passes require the machine function to be in SSA form where every virtual
181
  // register has a single defining instruction.
182
  //
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  // The TwoAddressInstructionPass and PHIElimination passes take the machine
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  // function out of SSA form when they introduce multiple defs per virtual
185
  // register.
186
85.7M
  bool isSSA() const {
187
85.7M
    return MF->getProperties().hasProperty(
188
85.7M
        MachineFunctionProperties::Property::IsSSA);
189
85.7M
  }
190
191
  // leaveSSA - Indicates that the machine function is no longer in SSA form.
192
931k
  void leaveSSA() {
193
931k
    MF->getProperties().reset(MachineFunctionProperties::Property::IsSSA);
194
931k
  }
195
196
  /// tracksLiveness - Returns true when tracking register liveness accurately.
197
  /// (see MachineFUnctionProperties::Property description for details)
198
64.8M
  bool tracksLiveness() const {
199
64.8M
    return MF->getProperties().hasProperty(
200
64.8M
        MachineFunctionProperties::Property::TracksLiveness);
201
64.8M
  }
202
203
  /// invalidateLiveness - Indicates that register liveness is no longer being
204
  /// tracked accurately.
205
  ///
206
  /// This should be called by late passes that invalidate the liveness
207
  /// information.
208
46.2k
  void invalidateLiveness() {
209
46.2k
    MF->getProperties().reset(
210
46.2k
        MachineFunctionProperties::Property::TracksLiveness);
211
46.2k
  }
212
213
  /// Returns true if liveness for register class @p RC should be tracked at
214
  /// the subregister level.
215
33.1M
  bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const {
216
33.1M
    return subRegLivenessEnabled() && 
RC.HasDisjunctSubRegs2.27M
;
217
33.1M
  }
218
28.8M
  bool shouldTrackSubRegLiveness(unsigned VReg) const {
219
28.8M
    assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Must pass a VReg");
220
28.8M
    return shouldTrackSubRegLiveness(*getRegClass(VReg));
221
28.8M
  }
222
49.9M
  bool subRegLivenessEnabled() const {
223
49.9M
    return TracksSubRegLiveness;
224
49.9M
  }
225
226
  //===--------------------------------------------------------------------===//
227
  // Register Info
228
  //===--------------------------------------------------------------------===//
229
230
  /// Returns true if the updated CSR list was initialized and false otherwise.
231
4.58k
  bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
232
233
  /// Disables the register from the list of CSRs.
234
  /// I.e. the register will not appear as part of the CSR mask.
235
  /// \see UpdatedCalleeSavedRegs.
236
  void disableCalleeSavedRegister(unsigned Reg);
237
238
  /// Returns list of callee saved registers.
239
  /// The function returns the updated CSR list (after taking into account
240
  /// registers that are disabled from the CSR list).
241
  const MCPhysReg *getCalleeSavedRegs() const;
242
243
  /// Sets the updated Callee Saved Registers list.
244
  /// Notice that it will override ant previously disabled/saved CSRs.
245
  void setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs);
246
247
  // Strictly for use by MachineInstr.cpp.
248
  void addRegOperandToUseList(MachineOperand *MO);
249
250
  // Strictly for use by MachineInstr.cpp.
251
  void removeRegOperandFromUseList(MachineOperand *MO);
252
253
  // Strictly for use by MachineInstr.cpp.
254
  void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
255
256
  /// Verify the sanity of the use list for Reg.
257
  void verifyUseList(unsigned Reg) const;
258
259
  /// Verify the use list of all registers.
260
  void verifyUseLists() const;
261
262
  /// reg_begin/reg_end - Provide iteration support to walk over all definitions
263
  /// and uses of a register within the MachineFunction that corresponds to this
264
  /// MachineRegisterInfo object.
265
  template<bool Uses, bool Defs, bool SkipDebug,
266
           bool ByOperand, bool ByInstr, bool ByBundle>
267
  class defusechain_iterator;
268
  template<bool Uses, bool Defs, bool SkipDebug,
269
           bool ByOperand, bool ByInstr, bool ByBundle>
270
  class defusechain_instr_iterator;
271
272
  // Make it a friend so it can access getNextOperandForReg().
273
  template<bool, bool, bool, bool, bool, bool>
274
    friend class defusechain_iterator;
275
  template<bool, bool, bool, bool, bool, bool>
276
    friend class defusechain_instr_iterator;
277
278
  /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
279
  /// register.
280
  using reg_iterator =
281
      defusechain_iterator<true, true, false, true, false, false>;
282
54.0M
  reg_iterator reg_begin(unsigned RegNo) const {
283
54.0M
    return reg_iterator(getRegUseDefListHead(RegNo));
284
54.0M
  }
285
53.9M
  static reg_iterator reg_end() { return reg_iterator(nullptr); }
286
287
258k
  inline iterator_range<reg_iterator>  reg_operands(unsigned Reg) const {
288
258k
    return make_range(reg_begin(Reg), reg_end());
289
258k
  }
290
291
  /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
292
  /// of the specified register, stepping by MachineInstr.
293
  using reg_instr_iterator =
294
      defusechain_instr_iterator<true, true, false, false, true, false>;
295
13.1M
  reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
296
13.1M
    return reg_instr_iterator(getRegUseDefListHead(RegNo));
297
13.1M
  }
298
13.1M
  static reg_instr_iterator reg_instr_end() {
299
13.1M
    return reg_instr_iterator(nullptr);
300
13.1M
  }
301
302
  inline iterator_range<reg_instr_iterator>
303
649k
  reg_instructions(unsigned Reg) const {
304
649k
    return make_range(reg_instr_begin(Reg), reg_instr_end());
305
649k
  }
306
307
  /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
308
  /// of the specified register, stepping by bundle.
309
  using reg_bundle_iterator =
310
      defusechain_instr_iterator<true, true, false, false, false, true>;
311
276k
  reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
312
276k
    return reg_bundle_iterator(getRegUseDefListHead(RegNo));
313
276k
  }
314
276k
  static reg_bundle_iterator reg_bundle_end() {
315
276k
    return reg_bundle_iterator(nullptr);
316
276k
  }
317
318
0
  inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const {
319
0
    return make_range(reg_bundle_begin(Reg), reg_bundle_end());
320
0
  }
321
322
  /// reg_empty - Return true if there are no instructions using or defining the
323
  /// specified register (it may be live-in).
324
52.3M
  bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
325
326
  /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
327
  /// of the specified register, skipping those marked as Debug.
328
  using reg_nodbg_iterator =
329
      defusechain_iterator<true, true, true, true, false, false>;
330
312M
  reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
331
312M
    return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
332
312M
  }
333
312M
  static reg_nodbg_iterator reg_nodbg_end() {
334
312M
    return reg_nodbg_iterator(nullptr);
335
312M
  }
336
337
  inline iterator_range<reg_nodbg_iterator>
338
27.6M
  reg_nodbg_operands(unsigned Reg) const {
339
27.6M
    return make_range(reg_nodbg_begin(Reg), reg_nodbg_end());
340
27.6M
  }
341
342
  /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
343
  /// all defs and uses of the specified register, stepping by MachineInstr,
344
  /// skipping those marked as Debug.
345
  using reg_instr_nodbg_iterator =
346
      defusechain_instr_iterator<true, true, true, false, true, false>;
347
925k
  reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const {
348
925k
    return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
349
925k
  }
350
925k
  static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
351
925k
    return reg_instr_nodbg_iterator(nullptr);
352
925k
  }
353
354
  inline iterator_range<reg_instr_nodbg_iterator>
355
863k
  reg_nodbg_instructions(unsigned Reg) const {
356
863k
    return make_range(reg_instr_nodbg_begin(Reg), reg_instr_nodbg_end());
357
863k
  }
358
359
  /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
360
  /// all defs and uses of the specified register, stepping by bundle,
361
  /// skipping those marked as Debug.
362
  using reg_bundle_nodbg_iterator =
363
      defusechain_instr_iterator<true, true, true, false, false, true>;
364
0
  reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const {
365
0
    return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
366
0
  }
367
0
  static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
368
0
    return reg_bundle_nodbg_iterator(nullptr);
369
0
  }
370
371
  inline iterator_range<reg_bundle_nodbg_iterator>
372
0
  reg_nodbg_bundles(unsigned Reg) const {
373
0
    return make_range(reg_bundle_nodbg_begin(Reg), reg_bundle_nodbg_end());
374
0
  }
375
376
  /// reg_nodbg_empty - Return true if the only instructions using or defining
377
  /// Reg are Debug instructions.
378
284M
  bool reg_nodbg_empty(unsigned RegNo) const {
379
284M
    return reg_nodbg_begin(RegNo) == reg_nodbg_end();
380
284M
  }
381
382
  /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
383
  using def_iterator =
384
      defusechain_iterator<false, true, false, true, false, false>;
385
257M
  def_iterator def_begin(unsigned RegNo) const {
386
257M
    return def_iterator(getRegUseDefListHead(RegNo));
387
257M
  }
388
250M
  static def_iterator def_end() { return def_iterator(nullptr); }
389
390
2.38M
  inline iterator_range<def_iterator> def_operands(unsigned Reg) const {
391
2.38M
    return make_range(def_begin(Reg), def_end());
392
2.38M
  }
393
394
  /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
395
  /// specified register, stepping by MachineInst.
396
  using def_instr_iterator =
397
      defusechain_instr_iterator<false, true, false, false, true, false>;
398
60.7M
  def_instr_iterator def_instr_begin(unsigned RegNo) const {
399
60.7M
    return def_instr_iterator(getRegUseDefListHead(RegNo));
400
60.7M
  }
401
5.87M
  static def_instr_iterator def_instr_end() {
402
5.87M
    return def_instr_iterator(nullptr);
403
5.87M
  }
404
405
  inline iterator_range<def_instr_iterator>
406
2.42M
  def_instructions(unsigned Reg) const {
407
2.42M
    return make_range(def_instr_begin(Reg), def_instr_end());
408
2.42M
  }
409
410
  /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
411
  /// specified register, stepping by bundle.
412
  using def_bundle_iterator =
413
      defusechain_instr_iterator<false, true, false, false, false, true>;
414
0
  def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
415
0
    return def_bundle_iterator(getRegUseDefListHead(RegNo));
416
0
  }
417
0
  static def_bundle_iterator def_bundle_end() {
418
0
    return def_bundle_iterator(nullptr);
419
0
  }
420
421
0
  inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const {
422
0
    return make_range(def_bundle_begin(Reg), def_bundle_end());
423
0
  }
424
425
  /// def_empty - Return true if there are no instructions defining the
426
  /// specified register (it may be live-in).
427
78.1M
  bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
428
429
81.2k
  StringRef getVRegName(unsigned Reg) const {
430
81.2k
    return VReg2Name.inBounds(Reg) ? 
StringRef(VReg2Name[Reg])339
:
""80.8k
;
431
81.2k
  }
432
433
24.2M
  void insertVRegByName(StringRef Name, unsigned Reg) {
434
24.2M
    assert((Name.empty() || VRegNames.find(Name) == VRegNames.end()) &&
435
24.2M
           "Named VRegs Must be Unique.");
436
24.2M
    if (!Name.empty()) {
437
94
      VRegNames.insert(Name);
438
94
      VReg2Name.grow(Reg);
439
94
      VReg2Name[Reg] = Name.str();
440
94
    }
441
24.2M
  }
442
443
  /// Return true if there is exactly one operand defining the specified
444
  /// register.
445
8.95M
  bool hasOneDef(unsigned RegNo) const {
446
8.95M
    def_iterator DI = def_begin(RegNo);
447
8.95M
    if (DI == def_end())
448
379k
      return false;
449
8.57M
    return ++DI == def_end();
450
8.57M
  }
451
452
  /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
453
  using use_iterator =
454
      defusechain_iterator<true, false, false, true, false, false>;
455
13.7M
  use_iterator use_begin(unsigned RegNo) const {
456
13.7M
    return use_iterator(getRegUseDefListHead(RegNo));
457
13.7M
  }
458
14.4M
  static use_iterator use_end() { return use_iterator(nullptr); }
459
460
10.4M
  inline iterator_range<use_iterator> use_operands(unsigned Reg) const {
461
10.4M
    return make_range(use_begin(Reg), use_end());
462
10.4M
  }
463
464
  /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
465
  /// specified register, stepping by MachineInstr.
466
  using use_instr_iterator =
467
      defusechain_instr_iterator<true, false, false, false, true, false>;
468
5.93M
  use_instr_iterator use_instr_begin(unsigned RegNo) const {
469
5.93M
    return use_instr_iterator(getRegUseDefListHead(RegNo));
470
5.93M
  }
471
5.91M
  static use_instr_iterator use_instr_end() {
472
5.91M
    return use_instr_iterator(nullptr);
473
5.91M
  }
474
475
  inline iterator_range<use_instr_iterator>
476
2.73M
  use_instructions(unsigned Reg) const {
477
2.73M
    return make_range(use_instr_begin(Reg), use_instr_end());
478
2.73M
  }
479
480
  /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
481
  /// specified register, stepping by bundle.
482
  using use_bundle_iterator =
483
      defusechain_instr_iterator<true, false, false, false, false, true>;
484
0
  use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
485
0
    return use_bundle_iterator(getRegUseDefListHead(RegNo));
486
0
  }
487
0
  static use_bundle_iterator use_bundle_end() {
488
0
    return use_bundle_iterator(nullptr);
489
0
  }
490
491
0
  inline iterator_range<use_bundle_iterator> use_bundles(unsigned Reg) const {
492
0
    return make_range(use_bundle_begin(Reg), use_bundle_end());
493
0
  }
494
495
  /// use_empty - Return true if there are no instructions using the specified
496
  /// register.
497
2.03M
  bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
498
499
  /// hasOneUse - Return true if there is exactly one instruction using the
500
  /// specified register.
501
649k
  bool hasOneUse(unsigned RegNo) const {
502
649k
    use_iterator UI = use_begin(RegNo);
503
649k
    if (UI == use_end())
504
32
      return false;
505
649k
    return ++UI == use_end();
506
649k
  }
507
508
  /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
509
  /// specified register, skipping those marked as Debug.
510
  using use_nodbg_iterator =
511
      defusechain_iterator<true, false, true, true, false, false>;
512
128M
  use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
513
128M
    return use_nodbg_iterator(getRegUseDefListHead(RegNo));
514
128M
  }
515
149M
  static use_nodbg_iterator use_nodbg_end() {
516
149M
    return use_nodbg_iterator(nullptr);
517
149M
  }
518
519
  inline iterator_range<use_nodbg_iterator>
520
37.3M
  use_nodbg_operands(unsigned Reg) const {
521
37.3M
    return make_range(use_nodbg_begin(Reg), use_nodbg_end());
522
37.3M
  }
523
524
  /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
525
  /// all uses of the specified register, stepping by MachineInstr, skipping
526
  /// those marked as Debug.
527
  using use_instr_nodbg_iterator =
528
      defusechain_instr_iterator<true, false, true, false, true, false>;
529
5.53M
  use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const {
530
5.53M
    return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
531
5.53M
  }
532
3.05M
  static use_instr_nodbg_iterator use_instr_nodbg_end() {
533
3.05M
    return use_instr_nodbg_iterator(nullptr);
534
3.05M
  }
535
536
  inline iterator_range<use_instr_nodbg_iterator>
537
2.95M
  use_nodbg_instructions(unsigned Reg) const {
538
2.95M
    return make_range(use_instr_nodbg_begin(Reg), use_instr_nodbg_end());
539
2.95M
  }
540
541
  /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
542
  /// all uses of the specified register, stepping by bundle, skipping
543
  /// those marked as Debug.
544
  using use_bundle_nodbg_iterator =
545
      defusechain_instr_iterator<true, false, true, false, false, true>;
546
0
  use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const {
547
0
    return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
548
0
  }
549
0
  static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
550
0
    return use_bundle_nodbg_iterator(nullptr);
551
0
  }
552
553
  inline iterator_range<use_bundle_nodbg_iterator>
554
0
  use_nodbg_bundles(unsigned Reg) const {
555
0
    return make_range(use_bundle_nodbg_begin(Reg), use_bundle_nodbg_end());
556
0
  }
557
558
  /// use_nodbg_empty - Return true if there are no non-Debug instructions
559
  /// using the specified register.
560
71.1M
  bool use_nodbg_empty(unsigned RegNo) const {
561
71.1M
    return use_nodbg_begin(RegNo) == use_nodbg_end();
562
71.1M
  }
563
564
  /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
565
  /// instruction using the specified register.
566
  bool hasOneNonDBGUse(unsigned RegNo) const;
567
568
  /// replaceRegWith - Replace all instances of FromReg with ToReg in the
569
  /// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
570
  /// except that it also changes any definitions of the register as well.
571
  ///
572
  /// Note that it is usually necessary to first constrain ToReg's register
573
  /// class and register bank to match the FromReg constraints using one of the
574
  /// methods:
575
  ///
576
  ///   constrainRegClass(ToReg, getRegClass(FromReg))
577
  ///   constrainRegAttrs(ToReg, FromReg)
578
  ///   RegisterBankInfo::constrainGenericRegister(ToReg,
579
  ///       *MRI.getRegClass(FromReg), MRI)
580
  ///
581
  /// These functions will return a falsy result if the virtual registers have
582
  /// incompatible constraints.
583
  ///
584
  /// Note that if ToReg is a physical register the function will replace and
585
  /// apply sub registers to ToReg in order to obtain a final/proper physical
586
  /// register.
587
  void replaceRegWith(unsigned FromReg, unsigned ToReg);
588
589
  /// getVRegDef - Return the machine instr that defines the specified virtual
590
  /// register or null if none is found.  This assumes that the code is in SSA
591
  /// form, so there should only be one definition.
592
  MachineInstr *getVRegDef(unsigned Reg) const;
593
594
  /// getUniqueVRegDef - Return the unique machine instr that defines the
595
  /// specified virtual register or null if none is found.  If there are
596
  /// multiple definitions or no definition, return null.
597
  MachineInstr *getUniqueVRegDef(unsigned Reg) const;
598
599
  /// clearKillFlags - Iterate over all the uses of the given register and
600
  /// clear the kill flag from the MachineOperand. This function is used by
601
  /// optimization passes which extend register lifetimes and need only
602
  /// preserve conservative kill flag information.
603
  void clearKillFlags(unsigned Reg) const;
604
605
  void dumpUses(unsigned RegNo) const;
606
607
  /// Returns true if PhysReg is unallocatable and constant throughout the
608
  /// function. Writing to a constant register has no effect.
609
  bool isConstantPhysReg(unsigned PhysReg) const;
610
611
  /// Returns true if either isConstantPhysReg or TRI->isCallerPreservedPhysReg
612
  /// returns true. This is a utility member function.
613
  bool isCallerPreservedOrConstPhysReg(unsigned PhysReg) const;
614
615
  /// Get an iterator over the pressure sets affected by the given physical or
616
  /// virtual register. If RegUnit is physical, it must be a register unit (from
617
  /// MCRegUnitIterator).
618
  PSetIterator getPressureSets(unsigned RegUnit) const;
619
620
  //===--------------------------------------------------------------------===//
621
  // Virtual Register Info
622
  //===--------------------------------------------------------------------===//
623
624
  /// Return the register class of the specified virtual register.
625
  /// This shouldn't be used directly unless \p Reg has a register class.
626
  /// \see getRegClassOrNull when this might happen.
627
190M
  const TargetRegisterClass *getRegClass(unsigned Reg) const {
628
190M
    assert(VRegInfo[Reg].first.is<const TargetRegisterClass *>() &&
629
190M
           "Register class not set, wrong accessor");
630
190M
    return VRegInfo[Reg].first.get<const TargetRegisterClass *>();
631
190M
  }
632
633
  /// Return the register class of \p Reg, or null if Reg has not been assigned
634
  /// a register class yet.
635
  ///
636
  /// \note A null register class can only happen when these two
637
  /// conditions are met:
638
  /// 1. Generic virtual registers are created.
639
  /// 2. The machine function has not completely been through the
640
  ///    instruction selection process.
641
  /// None of this condition is possible without GlobalISel for now.
642
  /// In other words, if GlobalISel is not used or if the query happens after
643
  /// the select pass, using getRegClass is safe.
644
31.1M
  const TargetRegisterClass *getRegClassOrNull(unsigned Reg) const {
645
31.1M
    const RegClassOrRegBank &Val = VRegInfo[Reg].first;
646
31.1M
    return Val.dyn_cast<const TargetRegisterClass *>();
647
31.1M
  }
648
649
  /// Return the register bank of \p Reg, or null if Reg has not been assigned
650
  /// a register bank or has been assigned a register class.
651
  /// \note It is possible to get the register bank from the register class via
652
  /// RegisterBankInfo::getRegBankFromRegClass.
653
66.1k
  const RegisterBank *getRegBankOrNull(unsigned Reg) const {
654
66.1k
    const RegClassOrRegBank &Val = VRegInfo[Reg].first;
655
66.1k
    return Val.dyn_cast<const RegisterBank *>();
656
66.1k
  }
657
658
  /// Return the register bank or register class of \p Reg.
659
  /// \note Before the register bank gets assigned (i.e., before the
660
  /// RegBankSelect pass) \p Reg may not have either.
661
43.2M
  const RegClassOrRegBank &getRegClassOrRegBank(unsigned Reg) const {
662
43.2M
    return VRegInfo[Reg].first;
663
43.2M
  }
664
665
  /// setRegClass - Set the register class of the specified virtual register.
666
  void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
667
668
  /// Set the register bank to \p RegBank for \p Reg.
669
  void setRegBank(unsigned Reg, const RegisterBank &RegBank);
670
671
  void setRegClassOrRegBank(unsigned Reg,
672
90
                            const RegClassOrRegBank &RCOrRB){
673
90
    VRegInfo[Reg].first = RCOrRB;
674
90
  }
675
676
  /// constrainRegClass - Constrain the register class of the specified virtual
677
  /// register to be a common subclass of RC and the current register class,
678
  /// but only if the new class has at least MinNumRegs registers.  Return the
679
  /// new register class, or NULL if no such class exists.
680
  /// This should only be used when the constraint is known to be trivial, like
681
  /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
682
  ///
683
  /// \note Assumes that the register has a register class assigned.
684
  /// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's
685
  /// InstructionSelect pass and constrainRegAttrs in every other pass,
686
  /// including non-select passes of GlobalISel, instead.
687
  const TargetRegisterClass *constrainRegClass(unsigned Reg,
688
                                               const TargetRegisterClass *RC,
689
                                               unsigned MinNumRegs = 0);
690
691
  /// Constrain the register class or the register bank of the virtual register
692
  /// \p Reg to be a common subclass and a common bank of both registers
693
  /// provided respectively. Do nothing if any of the attributes (classes,
694
  /// banks, or low-level types) of the registers are deemed incompatible, or if
695
  /// the resulting register will have a class smaller than before and of size
696
  /// less than \p MinNumRegs. Return true if such register attributes exist,
697
  /// false otherwise.
698
  ///
699
  /// \note Assumes that each register has either a low-level type or a class
700
  /// assigned, but not both. Use this method instead of constrainRegClass and
701
  /// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG
702
  /// ISel / FastISel and GlobalISel's InstructionSelect pass respectively.
703
  bool constrainRegAttrs(unsigned Reg, unsigned ConstrainingReg,
704
                         unsigned MinNumRegs = 0);
705
706
  /// recomputeRegClass - Try to find a legal super-class of Reg's register
707
  /// class that still satisfies the constraints from the instructions using
708
  /// Reg.  Returns true if Reg was upgraded.
709
  ///
710
  /// This method can be used after constraints have been removed from a
711
  /// virtual register, for example after removing instructions or splitting
712
  /// the live range.
713
  bool recomputeRegClass(unsigned Reg);
714
715
  /// createVirtualRegister - Create and return a new virtual register in the
716
  /// function with the specified register class.
717
  unsigned createVirtualRegister(const TargetRegisterClass *RegClass,
718
                                 StringRef Name = "");
719
720
  /// Get the low-level type of \p Reg or LLT{} if Reg is not a generic
721
  /// (target independent) virtual register.
722
75.2M
  LLT getType(unsigned Reg) const {
723
75.2M
    if (TargetRegisterInfo::isVirtualRegister(Reg) && 
VRegToType.inBounds(Reg)71.2M
)
724
63.4M
      return VRegToType[Reg];
725
11.8M
    return LLT{};
726
11.8M
  }
727
728
  /// Set the low-level type of \p VReg to \p Ty.
729
  void setType(unsigned VReg, LLT Ty);
730
731
  /// Create and return a new generic virtual register with low-level
732
  /// type \p Ty.
733
  unsigned createGenericVirtualRegister(LLT Ty, StringRef Name = "");
734
735
  /// Remove all types associated to virtual registers (after instruction
736
  /// selection and constraining of all generic virtual registers).
737
  void clearVirtRegTypes();
738
739
  /// Creates a new virtual register that has no register class, register bank
740
  /// or size assigned yet. This is only allowed to be used
741
  /// temporarily while constructing machine instructions. Most operations are
742
  /// undefined on an incomplete register until one of setRegClass(),
743
  /// setRegBank() or setSize() has been called on it.
744
  unsigned createIncompleteVirtualRegister(StringRef Name = "");
745
746
  /// getNumVirtRegs - Return the number of virtual registers created.
747
36.4M
  unsigned getNumVirtRegs() const { return VRegInfo.size(); }
748
749
  /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
750
  void clearVirtRegs();
751
752
  /// setRegAllocationHint - Specify a register allocation hint for the
753
  /// specified virtual register. This is typically used by target, and in case
754
  /// of an earlier hint it will be overwritten.
755
20.1k
  void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) {
756
20.1k
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
757
20.1k
    RegAllocHints[VReg].first  = Type;
758
20.1k
    RegAllocHints[VReg].second.clear();
759
20.1k
    RegAllocHints[VReg].second.push_back(PrefReg);
760
20.1k
  }
761
762
  /// addRegAllocationHint - Add a register allocation hint to the hints
763
  /// vector for VReg.
764
5.85M
  void addRegAllocationHint(unsigned VReg, unsigned PrefReg) {
765
5.85M
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
766
5.85M
    RegAllocHints[VReg].second.push_back(PrefReg);
767
5.85M
  }
768
769
  /// Specify the preferred (target independent) register allocation hint for
770
  /// the specified virtual register.
771
44
  void setSimpleHint(unsigned VReg, unsigned PrefReg) {
772
44
    setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
773
44
  }
774
775
857
  void clearSimpleHint(unsigned VReg) {
776
857
    assert (RegAllocHints[VReg].first == 0 &&
777
857
            "Expected to clear a non-target hint!");
778
857
    RegAllocHints[VReg].second.clear();
779
857
  }
780
781
  /// getRegAllocationHint - Return the register allocation hint for the
782
  /// specified virtual register. If there are many hints, this returns the
783
  /// one with the greatest weight.
784
  std::pair<unsigned, unsigned>
785
33.3M
  getRegAllocationHint(unsigned VReg) const {
786
33.3M
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
787
33.3M
    unsigned BestHint = (RegAllocHints[VReg].second.size() ?
788
23.8M
                         
RegAllocHints[VReg].second[0]9.43M
: 0);
789
33.3M
    return std::pair<unsigned, unsigned>(RegAllocHints[VReg].first, BestHint);
790
33.3M
  }
791
792
  /// getSimpleHint - same as getRegAllocationHint except it will only return
793
  /// a target independent hint.
794
16.5M
  unsigned getSimpleHint(unsigned VReg) const {
795
16.5M
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
796
16.5M
    std::pair<unsigned, unsigned> Hint = getRegAllocationHint(VReg);
797
16.5M
    return Hint.first ? 
053
:
Hint.second16.5M
;
798
16.5M
  }
799
800
  /// getRegAllocationHints - Return a reference to the vector of all
801
  /// register allocation hints for VReg.
802
  const std::pair<unsigned, SmallVector<unsigned, 4>>
803
11.3M
  &getRegAllocationHints(unsigned VReg) const {
804
11.3M
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
805
11.3M
    return RegAllocHints[VReg];
806
11.3M
  }
807
808
  /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
809
  /// specified register as undefined which causes the DBG_VALUE to be
810
  /// deleted during LiveDebugVariables analysis.
811
  void markUsesInDebugValueAsUndef(unsigned Reg) const;
812
813
  /// Return true if the specified register is modified in this function.
814
  /// This checks that no defining machine operands exist for the register or
815
  /// any of its aliases. Definitions found on functions marked noreturn are
816
  /// ignored, to consider them pass 'true' for optional parameter
817
  /// SkipNoReturnDef. The register is also considered modified when it is set
818
  /// in the UsedPhysRegMask.
819
  bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef = false) const;
820
821
  /// Return true if the specified register is modified or read in this
822
  /// function. This checks that no machine operands exist for the register or
823
  /// any of its aliases. The register is also considered used when it is set
824
  /// in the UsedPhysRegMask.
825
  bool isPhysRegUsed(unsigned PhysReg) const;
826
827
  /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
828
  /// This corresponds to the bit mask attached to register mask operands.
829
1.52M
  void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
830
1.52M
    UsedPhysRegMask.setBitsNotInMask(RegMask);
831
1.52M
  }
832
833
19.1k
  const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
834
835
  //===--------------------------------------------------------------------===//
836
  // Reserved Register Info
837
  //===--------------------------------------------------------------------===//
838
  //
839
  // The set of reserved registers must be invariant during register
840
  // allocation.  For example, the target cannot suddenly decide it needs a
841
  // frame pointer when the register allocator has already used the frame
842
  // pointer register for something else.
843
  //
844
  // These methods can be used by target hooks like hasFP() to avoid changing
845
  // the reserved register set during register allocation.
846
847
  /// freezeReservedRegs - Called by the register allocator to freeze the set
848
  /// of reserved registers before allocation begins.
849
  void freezeReservedRegs(const MachineFunction&);
850
851
  /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
852
  /// to ensure the set of reserved registers stays constant.
853
1.79M
  bool reservedRegsFrozen() const {
854
1.79M
    return !ReservedRegs.empty();
855
1.79M
  }
856
857
  /// canReserveReg - Returns true if PhysReg can be used as a reserved
858
  /// register.  Any register can be reserved before freezeReservedRegs() is
859
  /// called.
860
172k
  bool canReserveReg(unsigned PhysReg) const {
861
172k
    return !reservedRegsFrozen() || 
ReservedRegs.test(PhysReg)168k
;
862
172k
  }
863
864
  /// getReservedRegs - Returns a reference to the frozen set of reserved
865
  /// registers. This method should always be preferred to calling
866
  /// TRI::getReservedRegs() when possible.
867
176M
  const BitVector &getReservedRegs() const {
868
176M
    assert(reservedRegsFrozen() &&
869
176M
           "Reserved registers haven't been frozen yet. "
870
176M
           "Use TRI::getReservedRegs().");
871
176M
    return ReservedRegs;
872
176M
  }
873
874
  /// isReserved - Returns true when PhysReg is a reserved register.
875
  ///
876
  /// Reserved registers may belong to an allocatable register class, but the
877
  /// target has explicitly requested that they are not used.
878
167M
  bool isReserved(unsigned PhysReg) const {
879
167M
    return getReservedRegs().test(PhysReg);
880
167M
  }
881
882
  /// Returns true when the given register unit is considered reserved.
883
  ///
884
  /// Register units are considered reserved when for at least one of their
885
  /// root registers, the root register and all super registers are reserved.
886
  /// This currently iterates the register hierarchy and may be slower than
887
  /// expected.
888
  bool isReservedRegUnit(unsigned Unit) const;
889
890
  /// isAllocatable - Returns true when PhysReg belongs to an allocatable
891
  /// register class and it hasn't been reserved.
892
  ///
893
  /// Allocatable registers may show up in the allocation order of some virtual
894
  /// register, so a register allocator needs to track its liveness and
895
  /// availability.
896
34.8M
  bool isAllocatable(unsigned PhysReg) const {
897
34.8M
    return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
898
34.8M
      
!isReserved(PhysReg)30.7M
;
899
34.8M
  }
900
901
  //===--------------------------------------------------------------------===//
902
  // LiveIn Management
903
  //===--------------------------------------------------------------------===//
904
905
  /// addLiveIn - Add the specified register as a live-in.  Note that it
906
  /// is an error to add the same register to the same set more than once.
907
574k
  void addLiveIn(unsigned Reg, unsigned vreg = 0) {
908
574k
    LiveIns.push_back(std::make_pair(Reg, vreg));
909
574k
  }
910
911
  // Iteration support for the live-ins set.  It's kept in sorted order
912
  // by register number.
913
  using livein_iterator =
914
      std::vector<std::pair<unsigned,unsigned>>::const_iterator;
915
2.85M
  livein_iterator livein_begin() const { return LiveIns.begin(); }
916
2.85M
  livein_iterator livein_end()   const { return LiveIns.end(); }
917
3.34k
  bool            livein_empty() const { return LiveIns.empty(); }
918
919
86.7k
  ArrayRef<std::pair<unsigned, unsigned>> liveins() const {
920
86.7k
    return LiveIns;
921
86.7k
  }
922
923
  bool isLiveIn(unsigned Reg) const;
924
925
  /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
926
  /// corresponding live-in physical register.
927
  unsigned getLiveInPhysReg(unsigned VReg) const;
928
929
  /// getLiveInVirtReg - If PReg is a live-in physical register, return the
930
  /// corresponding live-in physical register.
931
  unsigned getLiveInVirtReg(unsigned PReg) const;
932
933
  /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
934
  /// into the given entry block.
935
  void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
936
                        const TargetRegisterInfo &TRI,
937
                        const TargetInstrInfo &TII);
938
939
  /// Returns a mask covering all bits that can appear in lane masks of
940
  /// subregisters of the virtual register @p Reg.
941
  LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const;
942
943
  /// defusechain_iterator - This class provides iterator support for machine
944
  /// operands in the function that use or define a specific register.  If
945
  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
946
  /// returns defs.  If neither are true then you are silly and it always
947
  /// returns end().  If SkipDebug is true it skips uses marked Debug
948
  /// when incrementing.
949
  template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
950
           bool ByOperand, bool ByInstr, bool ByBundle>
951
  class defusechain_iterator
952
    : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
953
    friend class MachineRegisterInfo;
954
955
    MachineOperand *Op = nullptr;
956
957
1.54G
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
958
1.54G
      // If the first node isn't one we're interested in, advance to one that
959
1.54G
      // we are interested in.
960
1.54G
      if (op) {
961
290M
        if ((!ReturnUses && 
op->isUse()63.7M
) ||
962
290M
            
(139M
!ReturnDefs139M
&&
op->isDef()139M
) ||
963
290M
            
(81.8M
SkipDebug81.8M
&&
op->isDebug()81.8M
))
964
139M
          advance();
965
290M
      }
966
1.54G
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
957
508M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
958
508M
      // If the first node isn't one we're interested in, advance to one that
959
508M
      // we are interested in.
960
508M
      if (op) {
961
63.7M
        if ((!ReturnUses && op->isUse()) ||
962
63.7M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
963
63.7M
            
(0
SkipDebug0
&&
op->isDebug()0
))
964
2.59M
          advance();
965
63.7M
      }
966
508M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
957
277M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
958
277M
      // If the first node isn't one we're interested in, advance to one that
959
277M
      // we are interested in.
960
277M
      if (op) {
961
128M
        if ((!ReturnUses && 
op->isUse()0
) ||
962
128M
            (!ReturnDefs && 
op->isDef()128M
) ||
963
128M
            
(550k
SkipDebug550k
&&
op->isDebug()550k
))
964
127M
          advance();
965
128M
      }
966
277M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
957
28.1M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
958
28.1M
      // If the first node isn't one we're interested in, advance to one that
959
28.1M
      // we are interested in.
960
28.1M
      if (op) {
961
11.8M
        if ((!ReturnUses && 
op->isUse()0
) ||
962
11.8M
            (!ReturnDefs && op->isDef()) ||
963
11.8M
            
(0
SkipDebug0
&&
op->isDebug()0
))
964
9.07M
          advance();
965
11.8M
      }
966
28.1M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
957
108M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
958
108M
      // If the first node isn't one we're interested in, advance to one that
959
108M
      // we are interested in.
960
108M
      if (op) {
961
5.46M
        if ((!ReturnUses && 
op->isUse()0
) ||
962
5.46M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
963
5.46M
            
(0
SkipDebug0
&&
op->isDebug()0
))
964
0
          advance();
965
5.46M
      }
966
108M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
957
624M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
958
624M
      // If the first node isn't one we're interested in, advance to one that
959
624M
      // we are interested in.
960
624M
      if (op) {
961
81.2M
        if ((!ReturnUses && 
op->isUse()0
) ||
962
81.2M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
963
81.2M
            (SkipDebug && op->isDebug()))
964
5
          advance();
965
81.2M
      }
966
624M
    }
967
968
311M
    void advance() {
969
311M
      assert(Op && "Cannot increment end iterator!");
970
311M
      Op = getNextOperandForReg(Op);
971
311M
972
311M
      // All defs come before the uses, so stop def_iterator early.
973
311M
      if (!ReturnUses) {
974
28.6M
        if (Op) {
975
27.0M
          if (Op->isUse())
976
19.3M
            Op = nullptr;
977
27.0M
          else
978
27.0M
            assert(!Op->isDebug() && "Can't have debug defs");
979
27.0M
        }
980
282M
      } else {
981
282M
        // If this is an operand we don't care about, skip it.
982
321M
        while (Op && 
(260M
(260M
!ReturnDefs260M
&&
Op->isDef()202M
) ||
983
260M
                      
(221M
SkipDebug221M
&&
Op->isDebug()195M
)))
984
38.7M
          Op = getNextOperandForReg(Op);
985
282M
      }
986
311M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::advance()
Line
Count
Source
968
28.6M
    void advance() {
969
28.6M
      assert(Op && "Cannot increment end iterator!");
970
28.6M
      Op = getNextOperandForReg(Op);
971
28.6M
972
28.6M
      // All defs come before the uses, so stop def_iterator early.
973
28.6M
      if (!ReturnUses) {
974
28.6M
        if (Op) {
975
27.0M
          if (Op->isUse())
976
19.3M
            Op = nullptr;
977
27.0M
          else
978
27.0M
            assert(!Op->isDebug() && "Can't have debug defs");
979
27.0M
        }
980
28.6M
      } else {
981
0
        // If this is an operand we don't care about, skip it.
982
0
        while (Op && ((!ReturnDefs && Op->isDef()) ||
983
0
                      (SkipDebug && Op->isDebug())))
984
0
          Op = getNextOperandForReg(Op);
985
0
      }
986
28.6M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::advance()
Line
Count
Source
968
161M
    void advance() {
969
161M
      assert(Op && "Cannot increment end iterator!");
970
161M
      Op = getNextOperandForReg(Op);
971
161M
972
161M
      // All defs come before the uses, so stop def_iterator early.
973
161M
      if (!ReturnUses) {
974
0
        if (Op) {
975
0
          if (Op->isUse())
976
0
            Op = nullptr;
977
0
          else
978
0
            assert(!Op->isDebug() && "Can't have debug defs");
979
0
        }
980
161M
      } else {
981
161M
        // If this is an operand we don't care about, skip it.
982
193M
        while (Op && 
(173M
(173M
!ReturnDefs173M
&&
Op->isDef()173M
) ||
983
173M
                      
(141M
SkipDebug141M
&&
Op->isDebug()141M
)))
984
32.3M
          Op = getNextOperandForReg(Op);
985
161M
      }
986
161M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::advance()
Line
Count
Source
968
33.8M
    void advance() {
969
33.8M
      assert(Op && "Cannot increment end iterator!");
970
33.8M
      Op = getNextOperandForReg(Op);
971
33.8M
972
33.8M
      // All defs come before the uses, so stop def_iterator early.
973
33.8M
      if (!ReturnUses) {
974
0
        if (Op) {
975
0
          if (Op->isUse())
976
0
            Op = nullptr;
977
0
          else
978
0
            assert(!Op->isDebug() && "Can't have debug defs");
979
0
        }
980
33.8M
      } else {
981
33.8M
        // If this is an operand we don't care about, skip it.
982
40.2M
        while (Op && 
(28.6M
(28.6M
!ReturnDefs28.6M
&&
Op->isDef()28.6M
) ||
983
28.6M
                      
(22.2M
SkipDebug22.2M
&&
Op->isDebug()0
)))
984
6.44M
          Op = getNextOperandForReg(Op);
985
33.8M
      }
986
33.8M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::advance()
Line
Count
Source
968
5.01M
    void advance() {
969
5.01M
      assert(Op && "Cannot increment end iterator!");
970
5.01M
      Op = getNextOperandForReg(Op);
971
5.01M
972
5.01M
      // All defs come before the uses, so stop def_iterator early.
973
5.01M
      if (!ReturnUses) {
974
0
        if (Op) {
975
0
          if (Op->isUse())
976
0
            Op = nullptr;
977
0
          else
978
0
            assert(!Op->isDebug() && "Can't have debug defs");
979
0
        }
980
5.01M
      } else {
981
5.01M
        // If this is an operand we don't care about, skip it.
982
5.01M
        while (Op && 
(3.46M
(3.46M
!ReturnDefs3.46M
&&
Op->isDef()0
) ||
983
3.46M
                      (SkipDebug && 
Op->isDebug()0
)))
984
0
          Op = getNextOperandForReg(Op);
985
5.01M
      }
986
5.01M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::advance()
Line
Count
Source
968
82.1M
    void advance() {
969
82.1M
      assert(Op && "Cannot increment end iterator!");
970
82.1M
      Op = getNextOperandForReg(Op);
971
82.1M
972
82.1M
      // All defs come before the uses, so stop def_iterator early.
973
82.1M
      if (!ReturnUses) {
974
0
        if (Op) {
975
0
          if (Op->isUse())
976
0
            Op = nullptr;
977
0
          else
978
0
            assert(!Op->isDebug() && "Can't have debug defs");
979
0
        }
980
82.1M
      } else {
981
82.1M
        // If this is an operand we don't care about, skip it.
982
82.1M
        while (Op && 
(54.5M
(54.5M
!ReturnDefs54.5M
&&
Op->isDef()0
) ||
983
54.5M
                      (SkipDebug && Op->isDebug())))
984
1.42k
          Op = getNextOperandForReg(Op);
985
82.1M
      }
986
82.1M
    }
987
988
  public:
989
    using reference = std::iterator<std::forward_iterator_tag,
990
                                    MachineInstr, ptrdiff_t>::reference;
991
    using pointer = std::iterator<std::forward_iterator_tag,
992
                                  MachineInstr, ptrdiff_t>::pointer;
993
994
101k
    defusechain_iterator() = default;
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::defusechain_iterator()
Line
Count
Source
994
101k
    defusechain_iterator() = default;
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::defusechain_iterator()
Line
Count
Source
994
264
    defusechain_iterator() = default;
995
996
913M
    bool operator==(const defusechain_iterator &x) const {
997
913M
      return Op == x.Op;
998
913M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false> const&) const
Line
Count
Source
996
258M
    bool operator==(const defusechain_iterator &x) const {
997
258M
      return Op == x.Op;
998
258M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false> const&) const
Line
Count
Source
996
162M
    bool operator==(const defusechain_iterator &x) const {
997
162M
      return Op == x.Op;
998
162M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false> const&) const
Line
Count
Source
996
38.5M
    bool operator==(const defusechain_iterator &x) const {
997
38.5M
      return Op == x.Op;
998
38.5M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false> const&) const
Line
Count
Source
996
58.8M
    bool operator==(const defusechain_iterator &x) const {
997
58.8M
      return Op == x.Op;
998
58.8M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false> const&) const
Line
Count
Source
996
394M
    bool operator==(const defusechain_iterator &x) const {
997
394M
      return Op == x.Op;
998
394M
    }
999
365M
    bool operator!=(const defusechain_iterator &x) const {
1000
365M
      return !operator==(x);
1001
365M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false> const&) const
Line
Count
Source
999
6.53M
    bool operator!=(const defusechain_iterator &x) const {
1000
6.53M
      return !operator==(x);
1001
6.53M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false> const&) const
Line
Count
Source
999
35.2M
    bool operator!=(const defusechain_iterator &x) const {
1000
35.2M
      return !operator==(x);
1001
35.2M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false> const&) const
Line
Count
Source
999
163M
    bool operator!=(const defusechain_iterator &x) const {
1000
163M
      return !operator==(x);
1001
163M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false> const&) const
Line
Count
Source
999
109M
    bool operator!=(const defusechain_iterator &x) const {
1000
109M
      return !operator==(x);
1001
109M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false> const&) const
Line
Count
Source
999
50.9M
    bool operator!=(const defusechain_iterator &x) const {
1000
50.9M
      return !operator==(x);
1001
50.9M
    }
1002
1003
    /// atEnd - return true if this iterator is equal to reg_end() on the value.
1004
    bool atEnd() const { return Op == nullptr; }
1005
1006
    // Iterator traversal: forward iteration only
1007
171M
    defusechain_iterator &operator++() {          // Preincrement
1008
171M
      assert(Op && "Cannot increment end iterator!");
1009
171M
      if (ByOperand)
1010
171M
        advance();
1011
0
      else if (ByInstr) {
1012
0
        MachineInstr *P = Op->getParent();
1013
0
        do {
1014
0
          advance();
1015
0
        } while (Op && Op->getParent() == P);
1016
0
      } else if (ByBundle) {
1017
0
        MachineBasicBlock::instr_iterator P =
1018
0
            getBundleStart(Op->getParent()->getIterator());
1019
0
        do {
1020
0
          advance();
1021
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1022
0
      }
1023
171M
1024
171M
      return *this;
1025
171M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator++()
Line
Count
Source
1007
26.1M
    defusechain_iterator &operator++() {          // Preincrement
1008
26.1M
      assert(Op && "Cannot increment end iterator!");
1009
26.1M
      if (ByOperand)
1010
26.1M
        advance();
1011
0
      else if (ByInstr) {
1012
0
        MachineInstr *P = Op->getParent();
1013
0
        do {
1014
0
          advance();
1015
0
        } while (Op && Op->getParent() == P);
1016
0
      } else if (ByBundle) {
1017
0
        MachineBasicBlock::instr_iterator P =
1018
0
            getBundleStart(Op->getParent()->getIterator());
1019
0
        do {
1020
0
          advance();
1021
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1022
0
      }
1023
26.1M
1024
26.1M
      return *this;
1025
26.1M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator++()
Line
Count
Source
1007
5.01M
    defusechain_iterator &operator++() {          // Preincrement
1008
5.01M
      assert(Op && "Cannot increment end iterator!");
1009
5.01M
      if (ByOperand)
1010
5.01M
        advance();
1011
0
      else if (ByInstr) {
1012
0
        MachineInstr *P = Op->getParent();
1013
0
        do {
1014
0
          advance();
1015
0
        } while (Op && Op->getParent() == P);
1016
0
      } else if (ByBundle) {
1017
0
        MachineBasicBlock::instr_iterator P =
1018
0
            getBundleStart(Op->getParent()->getIterator());
1019
0
        do {
1020
0
          advance();
1021
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1022
0
      }
1023
5.01M
1024
5.01M
      return *this;
1025
5.01M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator++()
Line
Count
Source
1007
24.7M
    defusechain_iterator &operator++() {          // Preincrement
1008
24.7M
      assert(Op && "Cannot increment end iterator!");
1009
24.7M
      if (ByOperand)
1010
24.7M
        advance();
1011
0
      else if (ByInstr) {
1012
0
        MachineInstr *P = Op->getParent();
1013
0
        do {
1014
0
          advance();
1015
0
        } while (Op && Op->getParent() == P);
1016
0
      } else if (ByBundle) {
1017
0
        MachineBasicBlock::instr_iterator P =
1018
0
            getBundleStart(Op->getParent()->getIterator());
1019
0
        do {
1020
0
          advance();
1021
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1022
0
      }
1023
24.7M
1024
24.7M
      return *this;
1025
24.7M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator++()
Line
Count
Source
1007
82.1M
    defusechain_iterator &operator++() {          // Preincrement
1008
82.1M
      assert(Op && "Cannot increment end iterator!");
1009
82.1M
      if (ByOperand)
1010
82.1M
        advance();
1011
0
      else if (ByInstr) {
1012
0
        MachineInstr *P = Op->getParent();
1013
0
        do {
1014
0
          advance();
1015
0
        } while (Op && Op->getParent() == P);
1016
0
      } else if (ByBundle) {
1017
0
        MachineBasicBlock::instr_iterator P =
1018
0
            getBundleStart(Op->getParent()->getIterator());
1019
0
        do {
1020
0
          advance();
1021
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1022
0
      }
1023
82.1M
1024
82.1M
      return *this;
1025
82.1M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator++()
Line
Count
Source
1007
33.9M
    defusechain_iterator &operator++() {          // Preincrement
1008
33.9M
      assert(Op && "Cannot increment end iterator!");
1009
33.9M
      if (ByOperand)
1010
33.9M
        advance();
1011
0
      else if (ByInstr) {
1012
0
        MachineInstr *P = Op->getParent();
1013
0
        do {
1014
0
          advance();
1015
0
        } while (Op && Op->getParent() == P);
1016
0
      } else if (ByBundle) {
1017
0
        MachineBasicBlock::instr_iterator P =
1018
0
            getBundleStart(Op->getParent()->getIterator());
1019
0
        do {
1020
0
          advance();
1021
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1022
0
      }
1023
33.9M
1024
33.9M
      return *this;
1025
33.9M
    }
1026
106k
    defusechain_iterator operator++(int) {        // Postincrement
1027
106k
      defusechain_iterator tmp = *this; ++*this; return tmp;
1028
106k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator++(int)
Line
Count
Source
1026
11.7k
    defusechain_iterator operator++(int) {        // Postincrement
1027
11.7k
      defusechain_iterator tmp = *this; ++*this; return tmp;
1028
11.7k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator++(int)
Line
Count
Source
1026
565
    defusechain_iterator operator++(int) {        // Postincrement
1027
565
      defusechain_iterator tmp = *this; ++*this; return tmp;
1028
565
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator++(int)
Line
Count
Source
1026
93.8k
    defusechain_iterator operator++(int) {        // Postincrement
1027
93.8k
      defusechain_iterator tmp = *this; ++*this; return tmp;
1028
93.8k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator++(int)
Line
Count
Source
1026
290
    defusechain_iterator operator++(int) {        // Postincrement
1027
290
      defusechain_iterator tmp = *this; ++*this; return tmp;
1028
290
    }
1029
1030
    /// getOperandNo - Return the operand # of this MachineOperand in its
1031
    /// MachineInstr.
1032
17.1M
    unsigned getOperandNo() const {
1033
17.1M
      assert(Op && "Cannot dereference end iterator!");
1034
17.1M
      return Op - &Op->getParent()->getOperand(0);
1035
17.1M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::getOperandNo() const
Line
Count
Source
1032
561k
    unsigned getOperandNo() const {
1033
561k
      assert(Op && "Cannot dereference end iterator!");
1034
561k
      return Op - &Op->getParent()->getOperand(0);
1035
561k
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::getOperandNo() const
Line
Count
Source
1032
16.5M
    unsigned getOperandNo() const {
1033
16.5M
      assert(Op && "Cannot dereference end iterator!");
1034
16.5M
      return Op - &Op->getParent()->getOperand(0);
1035
16.5M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::getOperandNo() const
Line
Count
Source
1032
1.75k
    unsigned getOperandNo() const {
1033
1.75k
      assert(Op && "Cannot dereference end iterator!");
1034
1.75k
      return Op - &Op->getParent()->getOperand(0);
1035
1.75k
    }
1036
1037
    // Retrieve a reference to the current operand.
1038
165M
    MachineOperand &operator*() const {
1039
165M
      assert(Op && "Cannot dereference end iterator!");
1040
165M
      return *Op;
1041
165M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator*() const
Line
Count
Source
1038
4.91M
    MachineOperand &operator*() const {
1039
4.91M
      assert(Op && "Cannot dereference end iterator!");
1040
4.91M
      return *Op;
1041
4.91M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator*() const
Line
Count
Source
1038
23.4M
    MachineOperand &operator*() const {
1039
23.4M
      assert(Op && "Cannot dereference end iterator!");
1040
23.4M
      return *Op;
1041
23.4M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator*() const
Line
Count
Source
1038
10.0M
    MachineOperand &operator*() const {
1039
10.0M
      assert(Op && "Cannot dereference end iterator!");
1040
10.0M
      return *Op;
1041
10.0M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator*() const
Line
Count
Source
1038
82.3M
    MachineOperand &operator*() const {
1039
82.3M
      assert(Op && "Cannot dereference end iterator!");
1040
82.3M
      return *Op;
1041
82.3M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator*() const
Line
Count
Source
1038
44.5M
    MachineOperand &operator*() const {
1039
44.5M
      assert(Op && "Cannot dereference end iterator!");
1040
44.5M
      return *Op;
1041
44.5M
    }
1042
1043
14.3M
    MachineOperand *operator->() const {
1044
14.3M
      assert(Op && "Cannot dereference end iterator!");
1045
14.3M
      return Op;
1046
14.3M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator->() const
Line
Count
Source
1043
997k
    MachineOperand *operator->() const {
1044
997k
      assert(Op && "Cannot dereference end iterator!");
1045
997k
      return Op;
1046
997k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator->() const
Line
Count
Source
1043
2.47k
    MachineOperand *operator->() const {
1044
2.47k
      assert(Op && "Cannot dereference end iterator!");
1045
2.47k
      return Op;
1046
2.47k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator->() const
Line
Count
Source
1043
396k
    MachineOperand *operator->() const {
1044
396k
      assert(Op && "Cannot dereference end iterator!");
1045
396k
      return Op;
1046
396k
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator->() const
Line
Count
Source
1043
12.9M
    MachineOperand *operator->() const {
1044
12.9M
      assert(Op && "Cannot dereference end iterator!");
1045
12.9M
      return Op;
1046
12.9M
    }
1047
  };
1048
1049
  /// defusechain_iterator - This class provides iterator support for machine
1050
  /// operands in the function that use or define a specific register.  If
1051
  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1052
  /// returns defs.  If neither are true then you are silly and it always
1053
  /// returns end().  If SkipDebug is true it skips uses marked Debug
1054
  /// when incrementing.
1055
  template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
1056
           bool ByOperand, bool ByInstr, bool ByBundle>
1057
  class defusechain_instr_iterator
1058
    : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
1059
    friend class MachineRegisterInfo;
1060
1061
    MachineOperand *Op = nullptr;
1062
1063
115M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1064
115M
      // If the first node isn't one we're interested in, advance to one that
1065
115M
      // we are interested in.
1066
115M
      if (op) {
1067
86.3M
        if ((!ReturnUses && 
op->isUse()60.7M
) ||
1068
86.3M
            
(11.4M
!ReturnDefs11.4M
&&
op->isDef()11.4M
) ||
1069
86.3M
            
(925k
SkipDebug925k
&&
op->isDebug()925k
))
1070
11.4M
          advance();
1071
86.3M
      }
1072
115M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1063
66.6M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1064
66.6M
      // If the first node isn't one we're interested in, advance to one that
1065
66.6M
      // we are interested in.
1066
66.6M
      if (op) {
1067
60.7M
        if ((!ReturnUses && op->isUse()) ||
1068
60.7M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
1069
60.7M
            
(0
SkipDebug0
&&
op->isDebug()0
))
1070
14.5k
          advance();
1071
60.7M
      }
1072
66.6M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1063
8.58M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1064
8.58M
      // If the first node isn't one we're interested in, advance to one that
1065
8.58M
      // we are interested in.
1066
8.58M
      if (op) {
1067
5.53M
        if ((!ReturnUses && 
op->isUse()0
) ||
1068
5.53M
            (!ReturnDefs && op->isDef()) ||
1069
5.53M
            
(0
SkipDebug0
&&
op->isDebug()0
))
1070
5.53M
          advance();
1071
5.53M
      }
1072
8.58M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1063
11.8M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1064
11.8M
      // If the first node isn't one we're interested in, advance to one that
1065
11.8M
      // we are interested in.
1066
11.8M
      if (op) {
1067
5.92M
        if ((!ReturnUses && 
op->isUse()0
) ||
1068
5.92M
            (!ReturnDefs && op->isDef()) ||
1069
5.92M
            
(0
SkipDebug0
&&
op->isDebug()0
))
1070
5.92M
          advance();
1071
5.92M
      }
1072
11.8M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1063
26.3M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1064
26.3M
      // If the first node isn't one we're interested in, advance to one that
1065
26.3M
      // we are interested in.
1066
26.3M
      if (op) {
1067
12.9M
        if ((!ReturnUses && 
op->isUse()0
) ||
1068
12.9M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
1069
12.9M
            
(0
SkipDebug0
&&
op->isDebug()0
))
1070
0
          advance();
1071
12.9M
      }
1072
26.3M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1063
1.85M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1064
1.85M
      // If the first node isn't one we're interested in, advance to one that
1065
1.85M
      // we are interested in.
1066
1.85M
      if (op) {
1067
925k
        if ((!ReturnUses && 
op->isUse()0
) ||
1068
925k
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
1069
925k
            (SkipDebug && op->isDebug()))
1070
0
          advance();
1071
925k
      }
1072
1.85M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1063
553k
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1064
553k
      // If the first node isn't one we're interested in, advance to one that
1065
553k
      // we are interested in.
1066
553k
      if (op) {
1067
276k
        if ((!ReturnUses && 
op->isUse()0
) ||
1068
276k
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
1069
276k
            
(0
SkipDebug0
&&
op->isDebug()0
))
1070
0
          advance();
1071
276k
      }
1072
553k
    }
1073
1074
64.9M
    void advance() {
1075
64.9M
      assert(Op && "Cannot increment end iterator!");
1076
64.9M
      Op = getNextOperandForReg(Op);
1077
64.9M
1078
64.9M
      // All defs come before the uses, so stop def_iterator early.
1079
64.9M
      if (!ReturnUses) {
1080
3.76M
        if (Op) {
1081
3.74M
          if (Op->isUse())
1082
3.66M
            Op = nullptr;
1083
3.74M
          else
1084
3.74M
            assert(!Op->isDebug() && "Can't have debug defs");
1085
3.74M
        }
1086
61.1M
      } else {
1087
61.1M
        // If this is an operand we don't care about, skip it.
1088
63.3M
        while (Op && 
(41.7M
(41.7M
!ReturnDefs41.7M
&&
Op->isDef()15.7M
) ||
1089
41.7M
                      
(39.5M
SkipDebug39.5M
&&
Op->isDebug()11.1M
)))
1090
2.24M
          Op = getNextOperandForReg(Op);
1091
61.1M
      }
1092
64.9M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::advance()
Line
Count
Source
1074
3.76M
    void advance() {
1075
3.76M
      assert(Op && "Cannot increment end iterator!");
1076
3.76M
      Op = getNextOperandForReg(Op);
1077
3.76M
1078
3.76M
      // All defs come before the uses, so stop def_iterator early.
1079
3.76M
      if (!ReturnUses) {
1080
3.76M
        if (Op) {
1081
3.74M
          if (Op->isUse())
1082
3.66M
            Op = nullptr;
1083
3.74M
          else
1084
3.74M
            assert(!Op->isDebug() && "Can't have debug defs");
1085
3.74M
        }
1086
3.76M
      } else {
1087
0
        // If this is an operand we don't care about, skip it.
1088
0
        while (Op && ((!ReturnDefs && Op->isDef()) ||
1089
0
                      (SkipDebug && Op->isDebug())))
1090
0
          Op = getNextOperandForReg(Op);
1091
0
      }
1092
3.76M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::advance()
Line
Count
Source
1074
9.32M
    void advance() {
1075
9.32M
      assert(Op && "Cannot increment end iterator!");
1076
9.32M
      Op = getNextOperandForReg(Op);
1077
9.32M
1078
9.32M
      // All defs come before the uses, so stop def_iterator early.
1079
9.32M
      if (!ReturnUses) {
1080
0
        if (Op) {
1081
0
          if (Op->isUse())
1082
0
            Op = nullptr;
1083
0
          else
1084
0
            assert(!Op->isDebug() && "Can't have debug defs");
1085
0
        }
1086
9.32M
      } else {
1087
9.32M
        // If this is an operand we don't care about, skip it.
1088
10.4M
        while (Op && 
(8.73M
(8.73M
!ReturnDefs8.73M
&&
Op->isDef()8.73M
) ||
1089
8.73M
                      
(7.61M
SkipDebug7.61M
&&
Op->isDebug()7.61M
)))
1090
1.11M
          Op = getNextOperandForReg(Op);
1091
9.32M
      }
1092
9.32M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::advance()
Line
Count
Source
1074
11.7M
    void advance() {
1075
11.7M
      assert(Op && "Cannot increment end iterator!");
1076
11.7M
      Op = getNextOperandForReg(Op);
1077
11.7M
1078
11.7M
      // All defs come before the uses, so stop def_iterator early.
1079
11.7M
      if (!ReturnUses) {
1080
0
        if (Op) {
1081
0
          if (Op->isUse())
1082
0
            Op = nullptr;
1083
0
          else
1084
0
            assert(!Op->isDebug() && "Can't have debug defs");
1085
0
        }
1086
11.7M
      } else {
1087
11.7M
        // If this is an operand we don't care about, skip it.
1088
12.8M
        while (Op && 
(7.02M
(7.02M
!ReturnDefs7.02M
&&
Op->isDef()7.02M
) ||
1089
7.02M
                      
(5.89M
SkipDebug5.89M
&&
Op->isDebug()0
)))
1090
1.12M
          Op = getNextOperandForReg(Op);
1091
11.7M
      }
1092
11.7M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::advance()
Line
Count
Source
1074
34.9M
    void advance() {
1075
34.9M
      assert(Op && "Cannot increment end iterator!");
1076
34.9M
      Op = getNextOperandForReg(Op);
1077
34.9M
1078
34.9M
      // All defs come before the uses, so stop def_iterator early.
1079
34.9M
      if (!ReturnUses) {
1080
0
        if (Op) {
1081
0
          if (Op->isUse())
1082
0
            Op = nullptr;
1083
0
          else
1084
0
            assert(!Op->isDebug() && "Can't have debug defs");
1085
0
        }
1086
34.9M
      } else {
1087
34.9M
        // If this is an operand we don't care about, skip it.
1088
34.9M
        while (Op && 
(21.9M
(21.9M
!ReturnDefs21.9M
&&
Op->isDef()0
) ||
1089
21.9M
                      (SkipDebug && 
Op->isDebug()0
)))
1090
0
          Op = getNextOperandForReg(Op);
1091
34.9M
      }
1092
34.9M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::advance()
Line
Count
Source
1074
4.43M
    void advance() {
1075
4.43M
      assert(Op && "Cannot increment end iterator!");
1076
4.43M
      Op = getNextOperandForReg(Op);
1077
4.43M
1078
4.43M
      // All defs come before the uses, so stop def_iterator early.
1079
4.43M
      if (!ReturnUses) {
1080
0
        if (Op) {
1081
0
          if (Op->isUse())
1082
0
            Op = nullptr;
1083
0
          else
1084
0
            assert(!Op->isDebug() && "Can't have debug defs");
1085
0
        }
1086
4.43M
      } else {
1087
4.43M
        // If this is an operand we don't care about, skip it.
1088
4.43M
        while (Op && 
(3.54M
(3.54M
!ReturnDefs3.54M
&&
Op->isDef()0
) ||
1089
3.54M
                      (SkipDebug && Op->isDebug())))
1090
0
          Op = getNextOperandForReg(Op);
1091
4.43M
      }
1092
4.43M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::advance()
Line
Count
Source
1074
747k
    void advance() {
1075
747k
      assert(Op && "Cannot increment end iterator!");
1076
747k
      Op = getNextOperandForReg(Op);
1077
747k
1078
747k
      // All defs come before the uses, so stop def_iterator early.
1079
747k
      if (!ReturnUses) {
1080
0
        if (Op) {
1081
0
          if (Op->isUse())
1082
0
            Op = nullptr;
1083
0
          else
1084
0
            assert(!Op->isDebug() && "Can't have debug defs");
1085
0
        }
1086
747k
      } else {
1087
747k
        // If this is an operand we don't care about, skip it.
1088
747k
        while (Op && 
(471k
(471k
!ReturnDefs471k
&&
Op->isDef()0
) ||
1089
471k
                      (SkipDebug && 
Op->isDebug()0
)))
1090
0
          Op = getNextOperandForReg(Op);
1091
747k
      }
1092
747k
    }
1093
1094
  public:
1095
    using reference = std::iterator<std::forward_iterator_tag,
1096
                                    MachineInstr, ptrdiff_t>::reference;
1097
    using pointer = std::iterator<std::forward_iterator_tag,
1098
                                  MachineInstr, ptrdiff_t>::pointer;
1099
1100
3.16M
    defusechain_instr_iterator() = default;
1101
1102
78.6M
    bool operator==(const defusechain_instr_iterator &x) const {
1103
78.6M
      return Op == x.Op;
1104
78.6M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false> const&) const
Line
Count
Source
1102
6.77M
    bool operator==(const defusechain_instr_iterator &x) const {
1103
6.77M
      return Op == x.Op;
1104
6.77M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false> const&) const
Line
Count
Source
1102
11.6M
    bool operator==(const defusechain_instr_iterator &x) const {
1103
11.6M
      return Op == x.Op;
1104
11.6M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false> const&) const
Line
Count
Source
1102
6.21M
    bool operator==(const defusechain_instr_iterator &x) const {
1103
6.21M
      return Op == x.Op;
1104
6.21M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false> const&) const
Line
Count
Source
1102
47.6M
    bool operator==(const defusechain_instr_iterator &x) const {
1103
47.6M
      return Op == x.Op;
1104
47.6M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false> const&) const
Line
Count
Source
1102
5.27M
    bool operator==(const defusechain_instr_iterator &x) const {
1103
5.27M
      return Op == x.Op;
1104
5.27M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true> const&) const
Line
Count
Source
1102
1.02M
    bool operator==(const defusechain_instr_iterator &x) const {
1103
1.02M
      return Op == x.Op;
1104
1.02M
    }
1105
78.6M
    bool operator!=(const defusechain_instr_iterator &x) const {
1106
78.6M
      return !operator==(x);
1107
78.6M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false> const&) const
Line
Count
Source
1105
6.77M
    bool operator!=(const defusechain_instr_iterator &x) const {
1106
6.77M
      return !operator==(x);
1107
6.77M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false> const&) const
Line
Count
Source
1105
11.6M
    bool operator!=(const defusechain_instr_iterator &x) const {
1106
11.6M
      return !operator==(x);
1107
11.6M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false> const&) const
Line
Count
Source
1105
6.21M
    bool operator!=(const defusechain_instr_iterator &x) const {
1106
6.21M
      return !operator==(x);
1107
6.21M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false> const&) const
Line
Count
Source
1105
47.6M
    bool operator!=(const defusechain_instr_iterator &x) const {
1106
47.6M
      return !operator==(x);
1107
47.6M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false> const&) const
Line
Count
Source
1105
5.27M
    bool operator!=(const defusechain_instr_iterator &x) const {
1106
5.27M
      return !operator==(x);
1107
5.27M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true> const&) const
Line
Count
Source
1105
1.02M
    bool operator!=(const defusechain_instr_iterator &x) const {
1106
1.02M
      return !operator==(x);
1107
1.02M
    }
1108
1109
    /// atEnd - return true if this iterator is equal to reg_end() on the value.
1110
50.5M
    bool atEnd() const { return Op == nullptr; }
1111
1112
    // Iterator traversal: forward iteration only
1113
52.9M
    defusechain_instr_iterator &operator++() {          // Preincrement
1114
52.9M
      assert(Op && "Cannot increment end iterator!");
1115
52.9M
      if (ByOperand)
1116
0
        advance();
1117
52.9M
      else if (ByInstr) {
1118
52.1M
        MachineInstr *P = Op->getParent();
1119
52.6M
        do {
1120
52.6M
          advance();
1121
52.6M
        } while (Op && 
Op->getParent() == P29.5M
);
1122
52.1M
      } else 
if (744k
ByBundle744k
) {
1123
744k
        MachineBasicBlock::instr_iterator P =
1124
744k
            getBundleStart(Op->getParent()->getIterator());
1125
747k
        do {
1126
747k
          advance();
1127
747k
        } while (Op && 
getBundleStart(Op->getParent()->getIterator()) == P471k
);
1128
744k
      }
1129
52.9M
1130
52.9M
      return *this;
1131
52.9M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator++()
Line
Count
Source
1113
3.72M
    defusechain_instr_iterator &operator++() {          // Preincrement
1114
3.72M
      assert(Op && "Cannot increment end iterator!");
1115
3.72M
      if (ByOperand)
1116
0
        advance();
1117
3.72M
      else if (ByInstr) {
1118
3.72M
        MachineInstr *P = Op->getParent();
1119
3.78M
        do {
1120
3.78M
          advance();
1121
3.78M
        } while (Op && 
Op->getParent() == P2.09M
);
1122
3.72M
      } else 
if (0
ByBundle0
) {
1123
0
        MachineBasicBlock::instr_iterator P =
1124
0
            getBundleStart(Op->getParent()->getIterator());
1125
0
        do {
1126
0
          advance();
1127
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1128
0
      }
1129
3.72M
1130
3.72M
      return *this;
1131
3.72M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator++()
Line
Count
Source
1113
5.76M
    defusechain_instr_iterator &operator++() {          // Preincrement
1114
5.76M
      assert(Op && "Cannot increment end iterator!");
1115
5.76M
      if (ByOperand)
1116
0
        advance();
1117
5.76M
      else if (ByInstr) {
1118
5.76M
        MachineInstr *P = Op->getParent();
1119
5.79M
        do {
1120
5.79M
          advance();
1121
5.79M
        } while (Op && 
Op->getParent() == P1.90M
);
1122
5.76M
      } else 
if (0
ByBundle0
) {
1123
0
        MachineBasicBlock::instr_iterator P =
1124
0
            getBundleStart(Op->getParent()->getIterator());
1125
0
        do {
1126
0
          advance();
1127
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1128
0
      }
1129
5.76M
1130
5.76M
      return *this;
1131
5.76M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator++()
Line
Count
Source
1113
3.74M
    defusechain_instr_iterator &operator++() {          // Preincrement
1114
3.74M
      assert(Op && "Cannot increment end iterator!");
1115
3.74M
      if (ByOperand)
1116
0
        advance();
1117
3.74M
      else if (ByInstr) {
1118
3.74M
        MachineInstr *P = Op->getParent();
1119
3.74M
        do {
1120
3.74M
          advance();
1121
3.74M
        } while (Op && 
Op->getParent() == P83.8k
);
1122
3.74M
      } else 
if (0
ByBundle0
) {
1123
0
        MachineBasicBlock::instr_iterator P =
1124
0
            getBundleStart(Op->getParent()->getIterator());
1125
0
        do {
1126
0
          advance();
1127
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1128
0
      }
1129
3.74M
1130
3.74M
      return *this;
1131
3.74M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator++()
Line
Count
Source
1113
34.5M
    defusechain_instr_iterator &operator++() {          // Preincrement
1114
34.5M
      assert(Op && "Cannot increment end iterator!");
1115
34.5M
      if (ByOperand)
1116
0
        advance();
1117
34.5M
      else if (ByInstr) {
1118
34.5M
        MachineInstr *P = Op->getParent();
1119
34.9M
        do {
1120
34.9M
          advance();
1121
34.9M
        } while (Op && 
Op->getParent() == P21.9M
);
1122
34.5M
      } else 
if (0
ByBundle0
) {
1123
0
        MachineBasicBlock::instr_iterator P =
1124
0
            getBundleStart(Op->getParent()->getIterator());
1125
0
        do {
1126
0
          advance();
1127
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1128
0
      }
1129
34.5M
1130
34.5M
      return *this;
1131
34.5M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator++()
Line
Count
Source
1113
4.40M
    defusechain_instr_iterator &operator++() {          // Preincrement
1114
4.40M
      assert(Op && "Cannot increment end iterator!");
1115
4.40M
      if (ByOperand)
1116
0
        advance();
1117
4.40M
      else if (ByInstr) {
1118
4.40M
        MachineInstr *P = Op->getParent();
1119
4.43M
        do {
1120
4.43M
          advance();
1121
4.43M
        } while (Op && 
Op->getParent() == P3.54M
);
1122
4.40M
      } else 
if (0
ByBundle0
) {
1123
0
        MachineBasicBlock::instr_iterator P =
1124
0
            getBundleStart(Op->getParent()->getIterator());
1125
0
        do {
1126
0
          advance();
1127
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1128
0
      }
1129
4.40M
1130
4.40M
      return *this;
1131
4.40M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator++()
Line
Count
Source
1113
744k
    defusechain_instr_iterator &operator++() {          // Preincrement
1114
744k
      assert(Op && "Cannot increment end iterator!");
1115
744k
      if (ByOperand)
1116
0
        advance();
1117
744k
      else if (ByInstr) {
1118
0
        MachineInstr *P = Op->getParent();
1119
0
        do {
1120
0
          advance();
1121
0
        } while (Op && Op->getParent() == P);
1122
744k
      } else if (ByBundle) {
1123
744k
        MachineBasicBlock::instr_iterator P =
1124
744k
            getBundleStart(Op->getParent()->getIterator());
1125
747k
        do {
1126
747k
          advance();
1127
747k
        } while (Op && 
getBundleStart(Op->getParent()->getIterator()) == P471k
);
1128
744k
      }
1129
744k
1130
744k
      return *this;
1131
744k
    }
1132
33.3M
    defusechain_instr_iterator operator++(int) {        // Postincrement
1133
33.3M
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1134
33.3M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator++(int)
Line
Count
Source
1132
32.0M
    defusechain_instr_iterator operator++(int) {        // Postincrement
1133
32.0M
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1134
32.0M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator++(int)
Line
Count
Source
1132
149k
    defusechain_instr_iterator operator++(int) {        // Postincrement
1133
149k
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1134
149k
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator++(int)
Line
Count
Source
1132
744k
    defusechain_instr_iterator operator++(int) {        // Postincrement
1133
744k
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1134
744k
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator++(int)
Line
Count
Source
1132
483k
    defusechain_instr_iterator operator++(int) {        // Postincrement
1133
483k
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1134
483k
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator++(int)
Line
Count
Source
1132
222
    defusechain_instr_iterator operator++(int) {        // Postincrement
1133
222
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1134
222
    }
1135
1136
    // Retrieve a reference to the current operand.
1137
113M
    MachineInstr &operator*() const {
1138
113M
      assert(Op && "Cannot dereference end iterator!");
1139
113M
      if (ByBundle)
1140
744k
        return *getBundleStart(Op->getParent()->getIterator());
1141
113M
      return *Op->getParent();
1142
113M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator*() const
Line
Count
Source
1137
60.7M
    MachineInstr &operator*() const {
1138
60.7M
      assert(Op && "Cannot dereference end iterator!");
1139
60.7M
      if (ByBundle)
1140
0
        return *getBundleStart(Op->getParent()->getIterator());
1141
60.7M
      return *Op->getParent();
1142
60.7M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator*() const
Line
Count
Source
1137
7.56M
    MachineInstr &operator*() const {
1138
7.56M
      assert(Op && "Cannot dereference end iterator!");
1139
7.56M
      if (ByBundle)
1140
0
        return *getBundleStart(Op->getParent()->getIterator());
1141
7.56M
      return *Op->getParent();
1142
7.56M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator*() const
Line
Count
Source
1137
5.86M
    MachineInstr &operator*() const {
1138
5.86M
      assert(Op && "Cannot dereference end iterator!");
1139
5.86M
      if (ByBundle)
1140
0
        return *getBundleStart(Op->getParent()->getIterator());
1141
5.86M
      return *Op->getParent();
1142
5.86M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator*() const
Line
Count
Source
1137
34.5M
    MachineInstr &operator*() const {
1138
34.5M
      assert(Op && "Cannot dereference end iterator!");
1139
34.5M
      if (ByBundle)
1140
0
        return *getBundleStart(Op->getParent()->getIterator());
1141
34.5M
      return *Op->getParent();
1142
34.5M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator*() const
Line
Count
Source
1137
4.40M
    MachineInstr &operator*() const {
1138
4.40M
      assert(Op && "Cannot dereference end iterator!");
1139
4.40M
      if (ByBundle)
1140
0
        return *getBundleStart(Op->getParent()->getIterator());
1141
4.40M
      return *Op->getParent();
1142
4.40M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator*() const
Line
Count
Source
1137
744k
    MachineInstr &operator*() const {
1138
744k
      assert(Op && "Cannot dereference end iterator!");
1139
744k
      if (ByBundle)
1140
744k
        return *getBundleStart(Op->getParent()->getIterator());
1141
0
      return *Op->getParent();
1142
0
    }
1143
1144
2.59k
    MachineInstr *operator->() const { return &operator*(); }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator->() const
Line
Count
Source
1144
616
    MachineInstr *operator->() const { return &operator*(); }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator->() const
Line
Count
Source
1144
60
    MachineInstr *operator->() const { return &operator*(); }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator->() const
Line
Count
Source
1144
1.92k
    MachineInstr *operator->() const { return &operator*(); }
1145
  };
1146
};
1147
1148
/// Iterate over the pressure sets affected by the given physical or virtual
1149
/// register. If Reg is physical, it must be a register unit (from
1150
/// MCRegUnitIterator).
1151
class PSetIterator {
1152
  const int *PSet = nullptr;
1153
  unsigned Weight = 0;
1154
1155
public:
1156
  PSetIterator() = default;
1157
1158
29.2M
  PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
1159
29.2M
    const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1160
29.2M
    if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
1161
26.5M
      const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
1162
26.5M
      PSet = TRI->getRegClassPressureSets(RC);
1163
26.5M
      Weight = TRI->getRegClassWeight(RC).RegWeight;
1164
26.5M
    }
1165
2.74M
    else {
1166
2.74M
      PSet = TRI->getRegUnitPressureSets(RegUnit);
1167
2.74M
      Weight = TRI->getRegUnitWeight(RegUnit);
1168
2.74M
    }
1169
29.2M
    if (*PSet == -1)
1170
451k
      PSet = nullptr;
1171
29.2M
  }
1172
1173
105M
  bool isValid() const { return PSet; }
1174
1175
29.2M
  unsigned getWeight() const { return Weight; }
1176
1177
244M
  unsigned operator*() const { return *PSet; }
1178
1179
76.7M
  void operator++() {
1180
76.7M
    assert(isValid() && "Invalid PSetIterator.");
1181
76.7M
    ++PSet;
1182
76.7M
    if (*PSet == -1)
1183
28.2M
      PSet = nullptr;
1184
76.7M
  }
1185
};
1186
1187
inline PSetIterator MachineRegisterInfo::
1188
29.2M
getPressureSets(unsigned RegUnit) const {
1189
29.2M
  return PSetIterator(RegUnit, this);
1190
29.2M
}
1191
1192
} // end namespace llvm
1193
1194
#endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H