Coverage Report

Created: 2018-07-12 09:57

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
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//===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the MachineRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
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#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/PointerUnion.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringSet.h"
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#include "llvm/ADT/iterator_range.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/LowLevelType.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/MC/LaneBitmask.h"
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#include <cassert>
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#include <cstddef>
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#include <cstdint>
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#include <iterator>
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#include <memory>
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#include <utility>
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#include <vector>
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namespace llvm {
43
44
class PSetIterator;
45
46
/// Convenient type to represent either a register class or a register bank.
47
using RegClassOrRegBank =
48
    PointerUnion<const TargetRegisterClass *, const RegisterBank *>;
49
50
/// MachineRegisterInfo - Keep track of information for virtual and physical
51
/// registers, including vreg register classes, use/def chains for registers,
52
/// etc.
53
class MachineRegisterInfo {
54
public:
55
  class Delegate {
56
    virtual void anchor();
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58
  public:
59
1.30M
    virtual ~Delegate() = default;
60
61
    virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
62
  };
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64
private:
65
  MachineFunction *MF;
66
  Delegate *TheDelegate = nullptr;
67
68
  /// True if subregister liveness is tracked.
69
  const bool TracksSubRegLiveness;
70
71
  /// VRegInfo - Information we keep for each virtual register.
72
  ///
73
  /// Each element in this list contains the register class of the vreg and the
74
  /// start of the use/def list for the register.
75
  IndexedMap<std::pair<RegClassOrRegBank, MachineOperand *>,
76
             VirtReg2IndexFunctor>
77
      VRegInfo;
78
79
  /// Map for recovering vreg name from vreg number.
80
  /// This map is used by the MIR Printer.
81
  IndexedMap<std::string, VirtReg2IndexFunctor> VReg2Name;
82
83
  /// StringSet that is used to unique vreg names.
84
  StringSet<> VRegNames;
85
86
  /// The flag is true upon \p UpdatedCSRs initialization
87
  /// and false otherwise.
88
  bool IsUpdatedCSRsInitialized;
89
90
  /// Contains the updated callee saved register list.
91
  /// As opposed to the static list defined in register info,
92
  /// all registers that were disabled are removed from the list.
93
  SmallVector<MCPhysReg, 16> UpdatedCSRs;
94
95
  /// RegAllocHints - This vector records register allocation hints for
96
  /// virtual registers. For each virtual register, it keeps a pair of hint
97
  /// type and hints vector making up the allocation hints. Only the first
98
  /// hint may be target specific, and in that case this is reflected by the
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  /// first member of the pair being non-zero. If the hinted register is
100
  /// virtual, it means the allocator should prefer the physical register
101
  /// allocated to it if any.
102
  IndexedMap<std::pair<unsigned, SmallVector<unsigned, 4>>,
103
             VirtReg2IndexFunctor> RegAllocHints;
104
105
  /// PhysRegUseDefLists - This is an array of the head of the use/def list for
106
  /// physical registers.
107
  std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
108
109
  /// getRegUseDefListHead - Return the head pointer for the register use/def
110
  /// list for the specified virtual or physical register.
111
328M
  MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
112
328M
    if (TargetRegisterInfo::isVirtualRegister(RegNo))
113
154M
      return VRegInfo[RegNo].second;
114
174M
    return PhysRegUseDefLists[RegNo];
115
174M
  }
116
117
807M
  MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
118
807M
    if (TargetRegisterInfo::isVirtualRegister(RegNo))
119
401M
      return VRegInfo[RegNo].second;
120
405M
    return PhysRegUseDefLists[RegNo];
121
405M
  }
122
123
  /// Get the next element in the use-def chain.
124
404M
  static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
125
404M
    assert(MO && MO->isReg() && "This is not a register operand!");
126
404M
    return MO->Contents.Reg.Next;
127
404M
  }
128
129
  /// UsedPhysRegMask - Additional used physregs including aliases.
130
  /// This bit vector represents all the registers clobbered by function calls.
131
  BitVector UsedPhysRegMask;
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133
  /// ReservedRegs - This is a bit vector of reserved registers.  The target
134
  /// may change its mind about which registers should be reserved.  This
135
  /// vector is the frozen set of reserved registers when register allocation
136
  /// started.
137
  BitVector ReservedRegs;
138
139
  using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;
140
  /// Map generic virtual registers to their low-level type.
141
  VRegToTypeMap VRegToType;
142
143
  /// Keep track of the physical registers that are live in to the function.
144
  /// Live in values are typically arguments in registers.  LiveIn values are
145
  /// allowed to have virtual registers associated with them, stored in the
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  /// second element.
147
  std::vector<std::pair<unsigned, unsigned>> LiveIns;
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public:
150
  explicit MachineRegisterInfo(MachineFunction *MF);
151
  MachineRegisterInfo(const MachineRegisterInfo &) = delete;
152
  MachineRegisterInfo &operator=(const MachineRegisterInfo &) = delete;
153
154
137M
  const TargetRegisterInfo *getTargetRegisterInfo() const {
155
137M
    return MF->getSubtarget().getRegisterInfo();
156
137M
  }
157
158
1.30M
  void resetDelegate(Delegate *delegate) {
159
1.30M
    // Ensure another delegate does not take over unless the current
160
1.30M
    // delegate first unattaches itself. If we ever need to multicast
161
1.30M
    // notifications, we will need to change to using a list.
162
1.30M
    assert(TheDelegate == delegate &&
163
1.30M
           "Only the current delegate can perform reset!");
164
1.30M
    TheDelegate = nullptr;
165
1.30M
  }
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167
1.30M
  void setDelegate(Delegate *delegate) {
168
1.30M
    assert(delegate && !TheDelegate &&
169
1.30M
           "Attempted to set delegate to null, or to change it without "
170
1.30M
           "first resetting it!");
171
1.30M
172
1.30M
    TheDelegate = delegate;
173
1.30M
  }
174
175
  //===--------------------------------------------------------------------===//
176
  // Function State
177
  //===--------------------------------------------------------------------===//
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  // isSSA - Returns true when the machine function is in SSA form. Early
180
  // passes require the machine function to be in SSA form where every virtual
181
  // register has a single defining instruction.
182
  //
183
  // The TwoAddressInstructionPass and PHIElimination passes take the machine
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  // function out of SSA form when they introduce multiple defs per virtual
185
  // register.
186
80.2M
  bool isSSA() const {
187
80.2M
    return MF->getProperties().hasProperty(
188
80.2M
        MachineFunctionProperties::Property::IsSSA);
189
80.2M
  }
190
191
  // leaveSSA - Indicates that the machine function is no longer in SSA form.
192
911k
  void leaveSSA() {
193
911k
    MF->getProperties().reset(MachineFunctionProperties::Property::IsSSA);
194
911k
  }
195
196
  /// tracksLiveness - Returns true when tracking register liveness accurately.
197
  /// (see MachineFUnctionProperties::Property description for details)
198
60.6M
  bool tracksLiveness() const {
199
60.6M
    return MF->getProperties().hasProperty(
200
60.6M
        MachineFunctionProperties::Property::TracksLiveness);
201
60.6M
  }
202
203
  /// invalidateLiveness - Indicates that register liveness is no longer being
204
  /// tracked accurately.
205
  ///
206
  /// This should be called by late passes that invalidate the liveness
207
  /// information.
208
45.1k
  void invalidateLiveness() {
209
45.1k
    MF->getProperties().reset(
210
45.1k
        MachineFunctionProperties::Property::TracksLiveness);
211
45.1k
  }
212
213
  /// Returns true if liveness for register class @p RC should be tracked at
214
  /// the subregister level.
215
32.1M
  bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const {
216
32.1M
    return subRegLivenessEnabled() && 
RC.HasDisjunctSubRegs1.93M
;
217
32.1M
  }
218
27.8M
  bool shouldTrackSubRegLiveness(unsigned VReg) const {
219
27.8M
    assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Must pass a VReg");
220
27.8M
    return shouldTrackSubRegLiveness(*getRegClass(VReg));
221
27.8M
  }
222
48.4M
  bool subRegLivenessEnabled() const {
223
48.4M
    return TracksSubRegLiveness;
224
48.4M
  }
225
226
  //===--------------------------------------------------------------------===//
227
  // Register Info
228
  //===--------------------------------------------------------------------===//
229
230
  /// Returns true if the updated CSR list was initialized and false otherwise.
231
4.13k
  bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
232
233
  /// Disables the register from the list of CSRs.
234
  /// I.e. the register will not appear as part of the CSR mask.
235
  /// \see UpdatedCalleeSavedRegs.
236
  void disableCalleeSavedRegister(unsigned Reg);
237
238
  /// Returns list of callee saved registers.
239
  /// The function returns the updated CSR list (after taking into account
240
  /// registers that are disabled from the CSR list).
241
  const MCPhysReg *getCalleeSavedRegs() const;
242
243
  /// Sets the updated Callee Saved Registers list.
244
  /// Notice that it will override ant previously disabled/saved CSRs.
245
  void setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs);
246
247
  // Strictly for use by MachineInstr.cpp.
248
  void addRegOperandToUseList(MachineOperand *MO);
249
250
  // Strictly for use by MachineInstr.cpp.
251
  void removeRegOperandFromUseList(MachineOperand *MO);
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253
  // Strictly for use by MachineInstr.cpp.
254
  void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
255
256
  /// Verify the sanity of the use list for Reg.
257
  void verifyUseList(unsigned Reg) const;
258
259
  /// Verify the use list of all registers.
260
  void verifyUseLists() const;
261
262
  /// reg_begin/reg_end - Provide iteration support to walk over all definitions
263
  /// and uses of a register within the MachineFunction that corresponds to this
264
  /// MachineRegisterInfo object.
265
  template<bool Uses, bool Defs, bool SkipDebug,
266
           bool ByOperand, bool ByInstr, bool ByBundle>
267
  class defusechain_iterator;
268
  template<bool Uses, bool Defs, bool SkipDebug,
269
           bool ByOperand, bool ByInstr, bool ByBundle>
270
  class defusechain_instr_iterator;
271
272
  // Make it a friend so it can access getNextOperandForReg().
273
  template<bool, bool, bool, bool, bool, bool>
274
    friend class defusechain_iterator;
275
  template<bool, bool, bool, bool, bool, bool>
276
    friend class defusechain_instr_iterator;
277
278
  /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
279
  /// register.
280
  using reg_iterator =
281
      defusechain_iterator<true, true, false, true, false, false>;
282
52.1M
  reg_iterator reg_begin(unsigned RegNo) const {
283
52.1M
    return reg_iterator(getRegUseDefListHead(RegNo));
284
52.1M
  }
285
52.0M
  static reg_iterator reg_end() { return reg_iterator(nullptr); }
286
287
246k
  inline iterator_range<reg_iterator>  reg_operands(unsigned Reg) const {
288
246k
    return make_range(reg_begin(Reg), reg_end());
289
246k
  }
290
291
  /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
292
  /// of the specified register, stepping by MachineInstr.
293
  using reg_instr_iterator =
294
      defusechain_instr_iterator<true, true, false, false, true, false>;
295
12.8M
  reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
296
12.8M
    return reg_instr_iterator(getRegUseDefListHead(RegNo));
297
12.8M
  }
298
12.8M
  static reg_instr_iterator reg_instr_end() {
299
12.8M
    return reg_instr_iterator(nullptr);
300
12.8M
  }
301
302
  inline iterator_range<reg_instr_iterator>
303
637k
  reg_instructions(unsigned Reg) const {
304
637k
    return make_range(reg_instr_begin(Reg), reg_instr_end());
305
637k
  }
306
307
  /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
308
  /// of the specified register, stepping by bundle.
309
  using reg_bundle_iterator =
310
      defusechain_instr_iterator<true, true, false, false, false, true>;
311
273k
  reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
312
273k
    return reg_bundle_iterator(getRegUseDefListHead(RegNo));
313
273k
  }
314
273k
  static reg_bundle_iterator reg_bundle_end() {
315
273k
    return reg_bundle_iterator(nullptr);
316
273k
  }
317
318
0
  inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const {
319
0
    return make_range(reg_bundle_begin(Reg), reg_bundle_end());
320
0
  }
321
322
  /// reg_empty - Return true if there are no instructions using or defining the
323
  /// specified register (it may be live-in).
324
50.5M
  bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
325
326
  /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
327
  /// of the specified register, skipping those marked as Debug.
328
  using reg_nodbg_iterator =
329
      defusechain_iterator<true, true, true, true, false, false>;
330
294M
  reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
331
294M
    return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
332
294M
  }
333
294M
  static reg_nodbg_iterator reg_nodbg_end() {
334
294M
    return reg_nodbg_iterator(nullptr);
335
294M
  }
336
337
  inline iterator_range<reg_nodbg_iterator>
338
26.9M
  reg_nodbg_operands(unsigned Reg) const {
339
26.9M
    return make_range(reg_nodbg_begin(Reg), reg_nodbg_end());
340
26.9M
  }
341
342
  /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
343
  /// all defs and uses of the specified register, stepping by MachineInstr,
344
  /// skipping those marked as Debug.
345
  using reg_instr_nodbg_iterator =
346
      defusechain_instr_iterator<true, true, true, false, true, false>;
347
921k
  reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const {
348
921k
    return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
349
921k
  }
350
921k
  static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
351
921k
    return reg_instr_nodbg_iterator(nullptr);
352
921k
  }
353
354
  inline iterator_range<reg_instr_nodbg_iterator>
355
860k
  reg_nodbg_instructions(unsigned Reg) const {
356
860k
    return make_range(reg_instr_nodbg_begin(Reg), reg_instr_nodbg_end());
357
860k
  }
358
359
  /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
360
  /// all defs and uses of the specified register, stepping by bundle,
361
  /// skipping those marked as Debug.
362
  using reg_bundle_nodbg_iterator =
363
      defusechain_instr_iterator<true, true, true, false, false, true>;
364
0
  reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const {
365
0
    return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
366
0
  }
367
0
  static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
368
0
    return reg_bundle_nodbg_iterator(nullptr);
369
0
  }
370
371
  inline iterator_range<reg_bundle_nodbg_iterator>
372
0
  reg_nodbg_bundles(unsigned Reg) const {
373
0
    return make_range(reg_bundle_nodbg_begin(Reg), reg_bundle_nodbg_end());
374
0
  }
375
376
  /// reg_nodbg_empty - Return true if the only instructions using or defining
377
  /// Reg are Debug instructions.
378
267M
  bool reg_nodbg_empty(unsigned RegNo) const {
379
267M
    return reg_nodbg_begin(RegNo) == reg_nodbg_end();
380
267M
  }
381
382
  /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
383
  using def_iterator =
384
      defusechain_iterator<false, true, false, true, false, false>;
385
238M
  def_iterator def_begin(unsigned RegNo) const {
386
238M
    return def_iterator(getRegUseDefListHead(RegNo));
387
238M
  }
388
232M
  static def_iterator def_end() { return def_iterator(nullptr); }
389
390
2.30M
  inline iterator_range<def_iterator> def_operands(unsigned Reg) const {
391
2.30M
    return make_range(def_begin(Reg), def_end());
392
2.30M
  }
393
394
  /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
395
  /// specified register, stepping by MachineInst.
396
  using def_instr_iterator =
397
      defusechain_instr_iterator<false, true, false, false, true, false>;
398
58.7M
  def_instr_iterator def_instr_begin(unsigned RegNo) const {
399
58.7M
    return def_instr_iterator(getRegUseDefListHead(RegNo));
400
58.7M
  }
401
5.28M
  static def_instr_iterator def_instr_end() {
402
5.28M
    return def_instr_iterator(nullptr);
403
5.28M
  }
404
405
  inline iterator_range<def_instr_iterator>
406
2.15M
  def_instructions(unsigned Reg) const {
407
2.15M
    return make_range(def_instr_begin(Reg), def_instr_end());
408
2.15M
  }
409
410
  /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
411
  /// specified register, stepping by bundle.
412
  using def_bundle_iterator =
413
      defusechain_instr_iterator<false, true, false, false, false, true>;
414
0
  def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
415
0
    return def_bundle_iterator(getRegUseDefListHead(RegNo));
416
0
  }
417
0
  static def_bundle_iterator def_bundle_end() {
418
0
    return def_bundle_iterator(nullptr);
419
0
  }
420
421
0
  inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const {
422
0
    return make_range(def_bundle_begin(Reg), def_bundle_end());
423
0
  }
424
425
  /// def_empty - Return true if there are no instructions defining the
426
  /// specified register (it may be live-in).
427
73.9M
  bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
428
429
74.6k
  StringRef getVRegName(unsigned Reg) const {
430
74.6k
    return VReg2Name.inBounds(Reg) ? 
StringRef(VReg2Name[Reg])339
:
""74.3k
;
431
74.6k
  }
432
433
23.5M
  void insertVRegByName(StringRef Name, unsigned Reg) {
434
23.5M
    assert((Name.empty() || VRegNames.find(Name) == VRegNames.end()) &&
435
23.5M
           "Named VRegs Must be Unique.");
436
23.5M
    if (!Name.empty()) {
437
94
      VRegNames.insert(Name);
438
94
      VReg2Name.grow(Reg);
439
94
      VReg2Name[Reg] = Name.str();
440
94
    }
441
23.5M
  }
442
443
  /// Return true if there is exactly one operand defining the specified
444
  /// register.
445
8.69M
  bool hasOneDef(unsigned RegNo) const {
446
8.69M
    def_iterator DI = def_begin(RegNo);
447
8.69M
    if (DI == def_end())
448
376k
      return false;
449
8.32M
    return ++DI == def_end();
450
8.32M
  }
451
452
  /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
453
  using use_iterator =
454
      defusechain_iterator<true, false, false, true, false, false>;
455
13.4M
  use_iterator use_begin(unsigned RegNo) const {
456
13.4M
    return use_iterator(getRegUseDefListHead(RegNo));
457
13.4M
  }
458
14.0M
  static use_iterator use_end() { return use_iterator(nullptr); }
459
460
10.1M
  inline iterator_range<use_iterator> use_operands(unsigned Reg) const {
461
10.1M
    return make_range(use_begin(Reg), use_end());
462
10.1M
  }
463
464
  /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
465
  /// specified register, stepping by MachineInstr.
466
  using use_instr_iterator =
467
      defusechain_instr_iterator<true, false, false, false, true, false>;
468
5.81M
  use_instr_iterator use_instr_begin(unsigned RegNo) const {
469
5.81M
    return use_instr_iterator(getRegUseDefListHead(RegNo));
470
5.81M
  }
471
5.79M
  static use_instr_iterator use_instr_end() {
472
5.79M
    return use_instr_iterator(nullptr);
473
5.79M
  }
474
475
  inline iterator_range<use_instr_iterator>
476
2.68M
  use_instructions(unsigned Reg) const {
477
2.68M
    return make_range(use_instr_begin(Reg), use_instr_end());
478
2.68M
  }
479
480
  /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
481
  /// specified register, stepping by bundle.
482
  using use_bundle_iterator =
483
      defusechain_instr_iterator<true, false, false, false, false, true>;
484
0
  use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
485
0
    return use_bundle_iterator(getRegUseDefListHead(RegNo));
486
0
  }
487
0
  static use_bundle_iterator use_bundle_end() {
488
0
    return use_bundle_iterator(nullptr);
489
0
  }
490
491
0
  inline iterator_range<use_bundle_iterator> use_bundles(unsigned Reg) const {
492
0
    return make_range(use_bundle_begin(Reg), use_bundle_end());
493
0
  }
494
495
  /// use_empty - Return true if there are no instructions using the specified
496
  /// register.
497
1.98M
  bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
498
499
  /// hasOneUse - Return true if there is exactly one instruction using the
500
  /// specified register.
501
644k
  bool hasOneUse(unsigned RegNo) const {
502
644k
    use_iterator UI = use_begin(RegNo);
503
644k
    if (UI == use_end())
504
32
      return false;
505
644k
    return ++UI == use_end();
506
644k
  }
507
508
  /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
509
  /// specified register, skipping those marked as Debug.
510
  using use_nodbg_iterator =
511
      defusechain_iterator<true, false, true, true, false, false>;
512
124M
  use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
513
124M
    return use_nodbg_iterator(getRegUseDefListHead(RegNo));
514
124M
  }
515
144M
  static use_nodbg_iterator use_nodbg_end() {
516
144M
    return use_nodbg_iterator(nullptr);
517
144M
  }
518
519
  inline iterator_range<use_nodbg_iterator>
520
35.6M
  use_nodbg_operands(unsigned Reg) const {
521
35.6M
    return make_range(use_nodbg_begin(Reg), use_nodbg_end());
522
35.6M
  }
523
524
  /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
525
  /// all uses of the specified register, stepping by MachineInstr, skipping
526
  /// those marked as Debug.
527
  using use_instr_nodbg_iterator =
528
      defusechain_instr_iterator<true, false, true, false, true, false>;
529
5.38M
  use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const {
530
5.38M
    return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
531
5.38M
  }
532
2.94M
  static use_instr_nodbg_iterator use_instr_nodbg_end() {
533
2.94M
    return use_instr_nodbg_iterator(nullptr);
534
2.94M
  }
535
536
  inline iterator_range<use_instr_nodbg_iterator>
537
2.85M
  use_nodbg_instructions(unsigned Reg) const {
538
2.85M
    return make_range(use_instr_nodbg_begin(Reg), use_instr_nodbg_end());
539
2.85M
  }
540
541
  /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
542
  /// all uses of the specified register, stepping by bundle, skipping
543
  /// those marked as Debug.
544
  using use_bundle_nodbg_iterator =
545
      defusechain_instr_iterator<true, false, true, false, false, true>;
546
0
  use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const {
547
0
    return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
548
0
  }
549
0
  static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
550
0
    return use_bundle_nodbg_iterator(nullptr);
551
0
  }
552
553
  inline iterator_range<use_bundle_nodbg_iterator>
554
0
  use_nodbg_bundles(unsigned Reg) const {
555
0
    return make_range(use_bundle_nodbg_begin(Reg), use_bundle_nodbg_end());
556
0
  }
557
558
  /// use_nodbg_empty - Return true if there are no non-Debug instructions
559
  /// using the specified register.
560
68.8M
  bool use_nodbg_empty(unsigned RegNo) const {
561
68.8M
    return use_nodbg_begin(RegNo) == use_nodbg_end();
562
68.8M
  }
563
564
  /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
565
  /// instruction using the specified register.
566
  bool hasOneNonDBGUse(unsigned RegNo) const;
567
568
  /// replaceRegWith - Replace all instances of FromReg with ToReg in the
569
  /// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
570
  /// except that it also changes any definitions of the register as well.
571
  ///
572
  /// Note that it is usually necessary to first constrain ToReg's register
573
  /// class and register bank to match the FromReg constraints using one of the
574
  /// methods:
575
  ///
576
  ///   constrainRegClass(ToReg, getRegClass(FromReg))
577
  ///   constrainRegAttrs(ToReg, FromReg)
578
  ///   RegisterBankInfo::constrainGenericRegister(ToReg,
579
  ///       *MRI.getRegClass(FromReg), MRI)
580
  ///
581
  /// These functions will return a falsy result if the virtual registers have
582
  /// incompatible constraints.
583
  ///
584
  /// Note that if ToReg is a physical register the function will replace and
585
  /// apply sub registers to ToReg in order to obtain a final/proper physical
586
  /// register.
587
  void replaceRegWith(unsigned FromReg, unsigned ToReg);
588
589
  /// getVRegDef - Return the machine instr that defines the specified virtual
590
  /// register or null if none is found.  This assumes that the code is in SSA
591
  /// form, so there should only be one definition.
592
  MachineInstr *getVRegDef(unsigned Reg) const;
593
594
  /// getUniqueVRegDef - Return the unique machine instr that defines the
595
  /// specified virtual register or null if none is found.  If there are
596
  /// multiple definitions or no definition, return null.
597
  MachineInstr *getUniqueVRegDef(unsigned Reg) const;
598
599
  /// clearKillFlags - Iterate over all the uses of the given register and
600
  /// clear the kill flag from the MachineOperand. This function is used by
601
  /// optimization passes which extend register lifetimes and need only
602
  /// preserve conservative kill flag information.
603
  void clearKillFlags(unsigned Reg) const;
604
605
  void dumpUses(unsigned RegNo) const;
606
607
  /// Returns true if PhysReg is unallocatable and constant throughout the
608
  /// function. Writing to a constant register has no effect.
609
  bool isConstantPhysReg(unsigned PhysReg) const;
610
611
  /// Returns true if either isConstantPhysReg or TRI->isCallerPreservedPhysReg
612
  /// returns true. This is a utility member function.
613
  bool isCallerPreservedOrConstPhysReg(unsigned PhysReg) const;
614
615
  /// Get an iterator over the pressure sets affected by the given physical or
616
  /// virtual register. If RegUnit is physical, it must be a register unit (from
617
  /// MCRegUnitIterator).
618
  PSetIterator getPressureSets(unsigned RegUnit) const;
619
620
  //===--------------------------------------------------------------------===//
621
  // Virtual Register Info
622
  //===--------------------------------------------------------------------===//
623
624
  /// Return the register class of the specified virtual register.
625
  /// This shouldn't be used directly unless \p Reg has a register class.
626
  /// \see getRegClassOrNull when this might happen.
627
183M
  const TargetRegisterClass *getRegClass(unsigned Reg) const {
628
183M
    assert(VRegInfo[Reg].first.is<const TargetRegisterClass *>() &&
629
183M
           "Register class not set, wrong accessor");
630
183M
    return VRegInfo[Reg].first.get<const TargetRegisterClass *>();
631
183M
  }
632
633
  /// Return the register class of \p Reg, or null if Reg has not been assigned
634
  /// a register class yet.
635
  ///
636
  /// \note A null register class can only happen when these two
637
  /// conditions are met:
638
  /// 1. Generic virtual registers are created.
639
  /// 2. The machine function has not completely been through the
640
  ///    instruction selection process.
641
  /// None of this condition is possible without GlobalISel for now.
642
  /// In other words, if GlobalISel is not used or if the query happens after
643
  /// the select pass, using getRegClass is safe.
644
29.4M
  const TargetRegisterClass *getRegClassOrNull(unsigned Reg) const {
645
29.4M
    const RegClassOrRegBank &Val = VRegInfo[Reg].first;
646
29.4M
    return Val.dyn_cast<const TargetRegisterClass *>();
647
29.4M
  }
648
649
  /// Return the register bank of \p Reg, or null if Reg has not been assigned
650
  /// a register bank or has been assigned a register class.
651
  /// \note It is possible to get the register bank from the register class via
652
  /// RegisterBankInfo::getRegBankFromRegClass.
653
56.0k
  const RegisterBank *getRegBankOrNull(unsigned Reg) const {
654
56.0k
    const RegClassOrRegBank &Val = VRegInfo[Reg].first;
655
56.0k
    return Val.dyn_cast<const RegisterBank *>();
656
56.0k
  }
657
658
  /// Return the register bank or register class of \p Reg.
659
  /// \note Before the register bank gets assigned (i.e., before the
660
  /// RegBankSelect pass) \p Reg may not have either.
661
42.6M
  const RegClassOrRegBank &getRegClassOrRegBank(unsigned Reg) const {
662
42.6M
    return VRegInfo[Reg].first;
663
42.6M
  }
664
665
  /// setRegClass - Set the register class of the specified virtual register.
666
  void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
667
668
  /// Set the register bank to \p RegBank for \p Reg.
669
  void setRegBank(unsigned Reg, const RegisterBank &RegBank);
670
671
  void setRegClassOrRegBank(unsigned Reg,
672
90
                            const RegClassOrRegBank &RCOrRB){
673
90
    VRegInfo[Reg].first = RCOrRB;
674
90
  }
675
676
  /// constrainRegClass - Constrain the register class of the specified virtual
677
  /// register to be a common subclass of RC and the current register class,
678
  /// but only if the new class has at least MinNumRegs registers.  Return the
679
  /// new register class, or NULL if no such class exists.
680
  /// This should only be used when the constraint is known to be trivial, like
681
  /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
682
  ///
683
  /// \note Assumes that the register has a register class assigned.
684
  /// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's
685
  /// InstructionSelect pass and constrainRegAttrs in every other pass,
686
  /// including non-select passes of GlobalISel, instead.
687
  const TargetRegisterClass *constrainRegClass(unsigned Reg,
688
                                               const TargetRegisterClass *RC,
689
                                               unsigned MinNumRegs = 0);
690
691
  /// Constrain the register class or the register bank of the virtual register
692
  /// \p Reg to be a common subclass and a common bank of both registers
693
  /// provided respectively. Do nothing if any of the attributes (classes,
694
  /// banks, or low-level types) of the registers are deemed incompatible, or if
695
  /// the resulting register will have a class smaller than before and of size
696
  /// less than \p MinNumRegs. Return true if such register attributes exist,
697
  /// false otherwise.
698
  ///
699
  /// \note Assumes that each register has either a low-level type or a class
700
  /// assigned, but not both. Use this method instead of constrainRegClass and
701
  /// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG
702
  /// ISel / FastISel and GlobalISel's InstructionSelect pass respectively.
703
  bool constrainRegAttrs(unsigned Reg, unsigned ConstrainingReg,
704
                         unsigned MinNumRegs = 0);
705
706
  /// recomputeRegClass - Try to find a legal super-class of Reg's register
707
  /// class that still satisfies the constraints from the instructions using
708
  /// Reg.  Returns true if Reg was upgraded.
709
  ///
710
  /// This method can be used after constraints have been removed from a
711
  /// virtual register, for example after removing instructions or splitting
712
  /// the live range.
713
  bool recomputeRegClass(unsigned Reg);
714
715
  /// createVirtualRegister - Create and return a new virtual register in the
716
  /// function with the specified register class.
717
  unsigned createVirtualRegister(const TargetRegisterClass *RegClass,
718
                                 StringRef Name = "");
719
720
  /// Get the low-level type of \p Reg or LLT{} if Reg is not a generic
721
  /// (target independent) virtual register.
722
73.1M
  LLT getType(unsigned Reg) const {
723
73.1M
    if (TargetRegisterInfo::isVirtualRegister(Reg) && 
VRegToType.inBounds(Reg)69.5M
)
724
62.2M
      return VRegToType[Reg];
725
10.8M
    return LLT{};
726
10.8M
  }
727
728
  /// Set the low-level type of \p VReg to \p Ty.
729
  void setType(unsigned VReg, LLT Ty);
730
731
  /// Create and return a new generic virtual register with low-level
732
  /// type \p Ty.
733
  unsigned createGenericVirtualRegister(LLT Ty, StringRef Name = "");
734
735
  /// Remove all types associated to virtual registers (after instruction
736
  /// selection and constraining of all generic virtual registers).
737
  void clearVirtRegTypes();
738
739
  /// Creates a new virtual register that has no register class, register bank
740
  /// or size assigned yet. This is only allowed to be used
741
  /// temporarily while constructing machine instructions. Most operations are
742
  /// undefined on an incomplete register until one of setRegClass(),
743
  /// setRegBank() or setSize() has been called on it.
744
  unsigned createIncompleteVirtualRegister(StringRef Name = "");
745
746
  /// getNumVirtRegs - Return the number of virtual registers created.
747
35.4M
  unsigned getNumVirtRegs() const { return VRegInfo.size(); }
748
749
  /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
750
  void clearVirtRegs();
751
752
  /// setRegAllocationHint - Specify a register allocation hint for the
753
  /// specified virtual register. This is typically used by target, and in case
754
  /// of an earlier hint it will be overwritten.
755
18.2k
  void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) {
756
18.2k
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
757
18.2k
    RegAllocHints[VReg].first  = Type;
758
18.2k
    RegAllocHints[VReg].second.clear();
759
18.2k
    RegAllocHints[VReg].second.push_back(PrefReg);
760
18.2k
  }
761
762
  /// addRegAllocationHint - Add a register allocation hint to the hints
763
  /// vector for VReg.
764
5.44M
  void addRegAllocationHint(unsigned VReg, unsigned PrefReg) {
765
5.44M
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
766
5.44M
    RegAllocHints[VReg].second.push_back(PrefReg);
767
5.44M
  }
768
769
  /// Specify the preferred (target independent) register allocation hint for
770
  /// the specified virtual register.
771
41
  void setSimpleHint(unsigned VReg, unsigned PrefReg) {
772
41
    setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
773
41
  }
774
775
851
  void clearSimpleHint(unsigned VReg) {
776
851
    assert (RegAllocHints[VReg].first == 0 &&
777
851
            "Expected to clear a non-target hint!");
778
851
    RegAllocHints[VReg].second.clear();
779
851
  }
780
781
  /// getRegAllocationHint - Return the register allocation hint for the
782
  /// specified virtual register. If there are many hints, this returns the
783
  /// one with the greatest weight.
784
  std::pair<unsigned, unsigned>
785
32.6M
  getRegAllocationHint(unsigned VReg) const {
786
32.6M
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
787
32.6M
    unsigned BestHint = (RegAllocHints[VReg].second.size() ?
788
23.3M
                         
RegAllocHints[VReg].second[0]9.29M
: 0);
789
32.6M
    return std::pair<unsigned, unsigned>(RegAllocHints[VReg].first, BestHint);
790
32.6M
  }
791
792
  /// getSimpleHint - same as getRegAllocationHint except it will only return
793
  /// a target independent hint.
794
16.2M
  unsigned getSimpleHint(unsigned VReg) const {
795
16.2M
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
796
16.2M
    std::pair<unsigned, unsigned> Hint = getRegAllocationHint(VReg);
797
16.2M
    return Hint.first ? 
053
:
Hint.second16.2M
;
798
16.2M
  }
799
800
  /// getRegAllocationHints - Return a reference to the vector of all
801
  /// register allocation hints for VReg.
802
  const std::pair<unsigned, SmallVector<unsigned, 4>>
803
11.1M
  &getRegAllocationHints(unsigned VReg) const {
804
11.1M
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
805
11.1M
    return RegAllocHints[VReg];
806
11.1M
  }
807
808
  /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
809
  /// specified register as undefined which causes the DBG_VALUE to be
810
  /// deleted during LiveDebugVariables analysis.
811
  void markUsesInDebugValueAsUndef(unsigned Reg) const;
812
813
  /// Return true if the specified register is modified in this function.
814
  /// This checks that no defining machine operands exist for the register or
815
  /// any of its aliases. Definitions found on functions marked noreturn are
816
  /// ignored, to consider them pass 'true' for optional parameter
817
  /// SkipNoReturnDef. The register is also considered modified when it is set
818
  /// in the UsedPhysRegMask.
819
  bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef = false) const;
820
821
  /// Return true if the specified register is modified or read in this
822
  /// function. This checks that no machine operands exist for the register or
823
  /// any of its aliases. The register is also considered used when it is set
824
  /// in the UsedPhysRegMask.
825
  bool isPhysRegUsed(unsigned PhysReg) const;
826
827
  /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
828
  /// This corresponds to the bit mask attached to register mask operands.
829
1.49M
  void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
830
1.49M
    UsedPhysRegMask.setBitsNotInMask(RegMask);
831
1.49M
  }
832
833
17.5k
  const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
834
835
  //===--------------------------------------------------------------------===//
836
  // Reserved Register Info
837
  //===--------------------------------------------------------------------===//
838
  //
839
  // The set of reserved registers must be invariant during register
840
  // allocation.  For example, the target cannot suddenly decide it needs a
841
  // frame pointer when the register allocator has already used the frame
842
  // pointer register for something else.
843
  //
844
  // These methods can be used by target hooks like hasFP() to avoid changing
845
  // the reserved register set during register allocation.
846
847
  /// freezeReservedRegs - Called by the register allocator to freeze the set
848
  /// of reserved registers before allocation begins.
849
  void freezeReservedRegs(const MachineFunction&);
850
851
  /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
852
  /// to ensure the set of reserved registers stays constant.
853
1.68M
  bool reservedRegsFrozen() const {
854
1.68M
    return !ReservedRegs.empty();
855
1.68M
  }
856
857
  /// canReserveReg - Returns true if PhysReg can be used as a reserved
858
  /// register.  Any register can be reserved before freezeReservedRegs() is
859
  /// called.
860
165k
  bool canReserveReg(unsigned PhysReg) const {
861
165k
    return !reservedRegsFrozen() || 
ReservedRegs.test(PhysReg)160k
;
862
165k
  }
863
864
  /// getReservedRegs - Returns a reference to the frozen set of reserved
865
  /// registers. This method should always be preferred to calling
866
  /// TRI::getReservedRegs() when possible.
867
172M
  const BitVector &getReservedRegs() const {
868
172M
    assert(reservedRegsFrozen() &&
869
172M
           "Reserved registers haven't been frozen yet. "
870
172M
           "Use TRI::getReservedRegs().");
871
172M
    return ReservedRegs;
872
172M
  }
873
874
  /// isReserved - Returns true when PhysReg is a reserved register.
875
  ///
876
  /// Reserved registers may belong to an allocatable register class, but the
877
  /// target has explicitly requested that they are not used.
878
163M
  bool isReserved(unsigned PhysReg) const {
879
163M
    return getReservedRegs().test(PhysReg);
880
163M
  }
881
882
  /// Returns true when the given register unit is considered reserved.
883
  ///
884
  /// Register units are considered reserved when for at least one of their
885
  /// root registers, the root register and all super registers are reserved.
886
  /// This currently iterates the register hierarchy and may be slower than
887
  /// expected.
888
  bool isReservedRegUnit(unsigned Unit) const;
889
890
  /// isAllocatable - Returns true when PhysReg belongs to an allocatable
891
  /// register class and it hasn't been reserved.
892
  ///
893
  /// Allocatable registers may show up in the allocation order of some virtual
894
  /// register, so a register allocator needs to track its liveness and
895
  /// availability.
896
33.9M
  bool isAllocatable(unsigned PhysReg) const {
897
33.9M
    return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
898
33.9M
      
!isReserved(PhysReg)29.8M
;
899
33.9M
  }
900
901
  //===--------------------------------------------------------------------===//
902
  // LiveIn Management
903
  //===--------------------------------------------------------------------===//
904
905
  /// addLiveIn - Add the specified register as a live-in.  Note that it
906
  /// is an error to add the same register to the same set more than once.
907
552k
  void addLiveIn(unsigned Reg, unsigned vreg = 0) {
908
552k
    LiveIns.push_back(std::make_pair(Reg, vreg));
909
552k
  }
910
911
  // Iteration support for the live-ins set.  It's kept in sorted order
912
  // by register number.
913
  using livein_iterator =
914
      std::vector<std::pair<unsigned,unsigned>>::const_iterator;
915
2.72M
  livein_iterator livein_begin() const { return LiveIns.begin(); }
916
2.72M
  livein_iterator livein_end()   const { return LiveIns.end(); }
917
3.30k
  bool            livein_empty() const { return LiveIns.empty(); }
918
919
83.8k
  ArrayRef<std::pair<unsigned, unsigned>> liveins() const {
920
83.8k
    return LiveIns;
921
83.8k
  }
922
923
  bool isLiveIn(unsigned Reg) const;
924
925
  /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
926
  /// corresponding live-in physical register.
927
  unsigned getLiveInPhysReg(unsigned VReg) const;
928
929
  /// getLiveInVirtReg - If PReg is a live-in physical register, return the
930
  /// corresponding live-in physical register.
931
  unsigned getLiveInVirtReg(unsigned PReg) const;
932
933
  /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
934
  /// into the given entry block.
935
  void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
936
                        const TargetRegisterInfo &TRI,
937
                        const TargetInstrInfo &TII);
938
939
  /// Returns a mask covering all bits that can appear in lane masks of
940
  /// subregisters of the virtual register @p Reg.
941
  LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const;
942
943
  /// defusechain_iterator - This class provides iterator support for machine
944
  /// operands in the function that use or define a specific register.  If
945
  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
946
  /// returns defs.  If neither are true then you are silly and it always
947
  /// returns end().  If SkipDebug is true it skips uses marked Debug
948
  /// when incrementing.
949
  template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
950
           bool ByOperand, bool ByInstr, bool ByBundle>
951
  class defusechain_iterator
952
    : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
953
    friend class MachineRegisterInfo;
954
955
    MachineOperand *Op = nullptr;
956
957
1.46G
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
958
1.46G
      // If the first node isn't one we're interested in, advance to one that
959
1.46G
      // we are interested in.
960
1.46G
      if (op) {
961
280M
        if ((!ReturnUses && 
op->isUse()60.9M
) ||
962
280M
            
(135M
!ReturnDefs135M
&&
op->isDef()135M
) ||
963
280M
            
(79.6M
SkipDebug79.6M
&&
op->isDebug()79.6M
))
964
134M
          advance();
965
280M
      }
966
1.46G
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
957
471M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
958
471M
      // If the first node isn't one we're interested in, advance to one that
959
471M
      // we are interested in.
960
471M
      if (op) {
961
60.9M
        if ((!ReturnUses && op->isUse()) ||
962
60.9M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
963
60.9M
            
(0
SkipDebug0
&&
op->isDebug()0
))
964
2.45M
          advance();
965
60.9M
      }
966
471M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
957
268M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
958
268M
      // If the first node isn't one we're interested in, advance to one that
959
268M
      // we are interested in.
960
268M
      if (op) {
961
123M
        if ((!ReturnUses && 
op->isUse()0
) ||
962
123M
            (!ReturnDefs && op->isDef()) ||
963
123M
            
(502k
SkipDebug502k
&&
op->isDebug()502k
))
964
123M
          advance();
965
123M
      }
966
268M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
957
27.5M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
958
27.5M
      // If the first node isn't one we're interested in, advance to one that
959
27.5M
      // we are interested in.
960
27.5M
      if (op) {
961
11.5M
        if ((!ReturnUses && 
op->isUse()0
) ||
962
11.5M
            
(11.5M
!ReturnDefs11.5M
&& op->isDef()) ||
963
11.5M
            
(0
SkipDebug0
&&
op->isDebug()0
))
964
8.85M
          advance();
965
11.5M
      }
966
27.5M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
957
104M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
958
104M
      // If the first node isn't one we're interested in, advance to one that
959
104M
      // we are interested in.
960
104M
      if (op) {
961
5.32M
        if ((!ReturnUses && 
op->isUse()0
) ||
962
5.32M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
963
5.32M
            
(0
SkipDebug0
&&
op->isDebug()0
))
964
0
          advance();
965
5.32M
      }
966
104M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
957
589M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
958
589M
      // If the first node isn't one we're interested in, advance to one that
959
589M
      // we are interested in.
960
589M
      if (op) {
961
79.1M
        if ((!ReturnUses && 
op->isUse()0
) ||
962
79.1M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
963
79.1M
            (SkipDebug && 
op->isDebug()79.1M
))
964
14
          advance();
965
79.1M
      }
966
589M
    }
967
968
300M
    void advance() {
969
300M
      assert(Op && "Cannot increment end iterator!");
970
300M
      Op = getNextOperandForReg(Op);
971
300M
972
300M
      // All defs come before the uses, so stop def_iterator early.
973
300M
      if (!ReturnUses) {
974
27.5M
        if (Op) {
975
25.9M
          if (Op->isUse())
976
18.4M
            Op = nullptr;
977
25.9M
          else
978
25.9M
            assert(!Op->isDebug() && "Can't have debug defs");
979
25.9M
        }
980
272M
      } else {
981
272M
        // If this is an operand we don't care about, skip it.
982
311M
        while (Op && 
(252M
(252M
!ReturnDefs252M
&&
Op->isDef()196M
) ||
983
252M
                      
(214M
SkipDebug214M
&&
Op->isDebug()188M
)))
984
38.5M
          Op = getNextOperandForReg(Op);
985
272M
      }
986
300M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::advance()
Line
Count
Source
968
27.5M
    void advance() {
969
27.5M
      assert(Op && "Cannot increment end iterator!");
970
27.5M
      Op = getNextOperandForReg(Op);
971
27.5M
972
27.5M
      // All defs come before the uses, so stop def_iterator early.
973
27.5M
      if (!ReturnUses) {
974
27.5M
        if (Op) {
975
25.9M
          if (Op->isUse())
976
18.4M
            Op = nullptr;
977
25.9M
          else
978
25.9M
            assert(!Op->isDebug() && "Can't have debug defs");
979
25.9M
        }
980
27.5M
      } else {
981
0
        // If this is an operand we don't care about, skip it.
982
0
        while (Op && ((!ReturnDefs && Op->isDef()) ||
983
0
                      (SkipDebug && Op->isDebug())))
984
0
          Op = getNextOperandForReg(Op);
985
0
      }
986
27.5M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::advance()
Line
Count
Source
968
154M
    void advance() {
969
154M
      assert(Op && "Cannot increment end iterator!");
970
154M
      Op = getNextOperandForReg(Op);
971
154M
972
154M
      // All defs come before the uses, so stop def_iterator early.
973
154M
      if (!ReturnUses) {
974
0
        if (Op) {
975
0
          if (Op->isUse())
976
0
            Op = nullptr;
977
0
          else
978
0
            assert(!Op->isDebug() && "Can't have debug defs");
979
0
        }
980
154M
      } else {
981
154M
        // If this is an operand we don't care about, skip it.
982
186M
        while (Op && 
(167M
(167M
!ReturnDefs167M
&&
Op->isDef()167M
) ||
983
167M
                      
(135M
SkipDebug135M
&&
Op->isDebug()135M
)))
984
32.2M
          Op = getNextOperandForReg(Op);
985
154M
      }
986
154M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::advance()
Line
Count
Source
968
33.0M
    void advance() {
969
33.0M
      assert(Op && "Cannot increment end iterator!");
970
33.0M
      Op = getNextOperandForReg(Op);
971
33.0M
972
33.0M
      // All defs come before the uses, so stop def_iterator early.
973
33.0M
      if (!ReturnUses) {
974
0
        if (Op) {
975
0
          if (Op->isUse())
976
0
            Op = nullptr;
977
0
          else
978
0
            assert(!Op->isDebug() && "Can't have debug defs");
979
0
        }
980
33.0M
      } else {
981
33.0M
        // If this is an operand we don't care about, skip it.
982
39.3M
        while (Op && 
(28.0M
(28.0M
!ReturnDefs28.0M
&&
Op->isDef()28.0M
) ||
983
28.0M
                      
(21.7M
SkipDebug21.7M
&&
Op->isDebug()0
)))
984
6.26M
          Op = getNextOperandForReg(Op);
985
33.0M
      }
986
33.0M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::advance()
Line
Count
Source
968
4.93M
    void advance() {
969
4.93M
      assert(Op && "Cannot increment end iterator!");
970
4.93M
      Op = getNextOperandForReg(Op);
971
4.93M
972
4.93M
      // All defs come before the uses, so stop def_iterator early.
973
4.93M
      if (!ReturnUses) {
974
0
        if (Op) {
975
0
          if (Op->isUse())
976
0
            Op = nullptr;
977
0
          else
978
0
            assert(!Op->isDebug() && "Can't have debug defs");
979
0
        }
980
4.93M
      } else {
981
4.93M
        // If this is an operand we don't care about, skip it.
982
4.93M
        while (Op && 
(3.41M
(3.41M
!ReturnDefs3.41M
&&
Op->isDef()0
) ||
983
3.41M
                      (SkipDebug && 
Op->isDebug()0
)))
984
0
          Op = getNextOperandForReg(Op);
985
4.93M
      }
986
4.93M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::advance()
Line
Count
Source
968
80.1M
    void advance() {
969
80.1M
      assert(Op && "Cannot increment end iterator!");
970
80.1M
      Op = getNextOperandForReg(Op);
971
80.1M
972
80.1M
      // All defs come before the uses, so stop def_iterator early.
973
80.1M
      if (!ReturnUses) {
974
0
        if (Op) {
975
0
          if (Op->isUse())
976
0
            Op = nullptr;
977
0
          else
978
0
            assert(!Op->isDebug() && "Can't have debug defs");
979
0
        }
980
80.1M
      } else {
981
80.1M
        // If this is an operand we don't care about, skip it.
982
80.1M
        while (Op && 
(53.2M
(53.2M
!ReturnDefs53.2M
&&
Op->isDef()0
) ||
983
53.2M
                      
(53.2M
SkipDebug53.2M
&& Op->isDebug())))
984
1.39k
          Op = getNextOperandForReg(Op);
985
80.1M
      }
986
80.1M
    }
987
988
  public:
989
    using reference = std::iterator<std::forward_iterator_tag,
990
                                    MachineInstr, ptrdiff_t>::reference;
991
    using pointer = std::iterator<std::forward_iterator_tag,
992
                                  MachineInstr, ptrdiff_t>::pointer;
993
994
96.3k
    defusechain_iterator() = default;
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::defusechain_iterator()
Line
Count
Source
994
96.1k
    defusechain_iterator() = default;
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::defusechain_iterator()
Line
Count
Source
994
264
    defusechain_iterator() = default;
995
996
865M
    bool operator==(const defusechain_iterator &x) const {
997
865M
      return Op == x.Op;
998
865M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false> const&) const
Line
Count
Source
996
240M
    bool operator==(const defusechain_iterator &x) const {
997
240M
      return Op == x.Op;
998
240M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false> const&) const
Line
Count
Source
996
155M
    bool operator==(const defusechain_iterator &x) const {
997
155M
      return Op == x.Op;
998
155M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false> const&) const
Line
Count
Source
996
37.7M
    bool operator==(const defusechain_iterator &x) const {
997
37.7M
      return Op == x.Op;
998
37.7M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false> const&) const
Line
Count
Source
996
56.9M
    bool operator==(const defusechain_iterator &x) const {
997
56.9M
      return Op == x.Op;
998
56.9M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false> const&) const
Line
Count
Source
996
375M
    bool operator==(const defusechain_iterator &x) const {
997
375M
      return Op == x.Op;
998
375M
    }
999
344M
    bool operator!=(const defusechain_iterator &x) const {
1000
344M
      return !operator==(x);
1001
344M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false> const&) const
Line
Count
Source
999
6.42M
    bool operator!=(const defusechain_iterator &x) const {
1000
6.42M
      return !operator==(x);
1001
6.42M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false> const&) const
Line
Count
Source
999
34.4M
    bool operator!=(const defusechain_iterator &x) const {
1000
34.4M
      return !operator==(x);
1001
34.4M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false> const&) const
Line
Count
Source
999
149M
    bool operator!=(const defusechain_iterator &x) const {
1000
149M
      return !operator==(x);
1001
149M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false> const&) const
Line
Count
Source
999
107M
    bool operator!=(const defusechain_iterator &x) const {
1000
107M
      return !operator==(x);
1001
107M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false> const&) const
Line
Count
Source
999
47.2M
    bool operator!=(const defusechain_iterator &x) const {
1000
47.2M
      return !operator==(x);
1001
47.2M
    }
1002
1003
    /// atEnd - return true if this iterator is equal to reg_end() on the value.
1004
    bool atEnd() const { return Op == nullptr; }
1005
1006
    // Iterator traversal: forward iteration only
1007
165M
    defusechain_iterator &operator++() {          // Preincrement
1008
165M
      assert(Op && "Cannot increment end iterator!");
1009
165M
      if (ByOperand)
1010
165M
        advance();
1011
0
      else if (ByInstr) {
1012
0
        MachineInstr *P = Op->getParent();
1013
0
        do {
1014
0
          advance();
1015
0
        } while (Op && Op->getParent() == P);
1016
0
      } else if (ByBundle) {
1017
0
        MachineBasicBlock::instr_iterator P =
1018
0
            getBundleStart(Op->getParent()->getIterator());
1019
0
        do {
1020
0
          advance();
1021
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1022
0
      }
1023
165M
1024
165M
      return *this;
1025
165M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator++()
Line
Count
Source
1007
25.0M
    defusechain_iterator &operator++() {          // Preincrement
1008
25.0M
      assert(Op && "Cannot increment end iterator!");
1009
25.0M
      if (ByOperand)
1010
25.0M
        advance();
1011
0
      else if (ByInstr) {
1012
0
        MachineInstr *P = Op->getParent();
1013
0
        do {
1014
0
          advance();
1015
0
        } while (Op && Op->getParent() == P);
1016
0
      } else if (ByBundle) {
1017
0
        MachineBasicBlock::instr_iterator P =
1018
0
            getBundleStart(Op->getParent()->getIterator());
1019
0
        do {
1020
0
          advance();
1021
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1022
0
      }
1023
25.0M
1024
25.0M
      return *this;
1025
25.0M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator++()
Line
Count
Source
1007
4.93M
    defusechain_iterator &operator++() {          // Preincrement
1008
4.93M
      assert(Op && "Cannot increment end iterator!");
1009
4.93M
      if (ByOperand)
1010
4.93M
        advance();
1011
0
      else if (ByInstr) {
1012
0
        MachineInstr *P = Op->getParent();
1013
0
        do {
1014
0
          advance();
1015
0
        } while (Op && Op->getParent() == P);
1016
0
      } else if (ByBundle) {
1017
0
        MachineBasicBlock::instr_iterator P =
1018
0
            getBundleStart(Op->getParent()->getIterator());
1019
0
        do {
1020
0
          advance();
1021
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1022
0
      }
1023
4.93M
1024
4.93M
      return *this;
1025
4.93M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator++()
Line
Count
Source
1007
24.2M
    defusechain_iterator &operator++() {          // Preincrement
1008
24.2M
      assert(Op && "Cannot increment end iterator!");
1009
24.2M
      if (ByOperand)
1010
24.2M
        advance();
1011
0
      else if (ByInstr) {
1012
0
        MachineInstr *P = Op->getParent();
1013
0
        do {
1014
0
          advance();
1015
0
        } while (Op && Op->getParent() == P);
1016
0
      } else if (ByBundle) {
1017
0
        MachineBasicBlock::instr_iterator P =
1018
0
            getBundleStart(Op->getParent()->getIterator());
1019
0
        do {
1020
0
          advance();
1021
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1022
0
      }
1023
24.2M
1024
24.2M
      return *this;
1025
24.2M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator++()
Line
Count
Source
1007
80.1M
    defusechain_iterator &operator++() {          // Preincrement
1008
80.1M
      assert(Op && "Cannot increment end iterator!");
1009
80.1M
      if (ByOperand)
1010
80.1M
        advance();
1011
0
      else if (ByInstr) {
1012
0
        MachineInstr *P = Op->getParent();
1013
0
        do {
1014
0
          advance();
1015
0
        } while (Op && Op->getParent() == P);
1016
0
      } else if (ByBundle) {
1017
0
        MachineBasicBlock::instr_iterator P =
1018
0
            getBundleStart(Op->getParent()->getIterator());
1019
0
        do {
1020
0
          advance();
1021
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1022
0
      }
1023
80.1M
1024
80.1M
      return *this;
1025
80.1M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator++()
Line
Count
Source
1007
31.3M
    defusechain_iterator &operator++() {          // Preincrement
1008
31.3M
      assert(Op && "Cannot increment end iterator!");
1009
31.3M
      if (ByOperand)
1010
31.3M
        advance();
1011
0
      else if (ByInstr) {
1012
0
        MachineInstr *P = Op->getParent();
1013
0
        do {
1014
0
          advance();
1015
0
        } while (Op && Op->getParent() == P);
1016
0
      } else if (ByBundle) {
1017
0
        MachineBasicBlock::instr_iterator P =
1018
0
            getBundleStart(Op->getParent()->getIterator());
1019
0
        do {
1020
0
          advance();
1021
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1022
0
      }
1023
31.3M
1024
31.3M
      return *this;
1025
31.3M
    }
1026
101k
    defusechain_iterator operator++(int) {        // Postincrement
1027
101k
      defusechain_iterator tmp = *this; ++*this; return tmp;
1028
101k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator++(int)
Line
Count
Source
1026
11.5k
    defusechain_iterator operator++(int) {        // Postincrement
1027
11.5k
      defusechain_iterator tmp = *this; ++*this; return tmp;
1028
11.5k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator++(int)
Line
Count
Source
1026
557
    defusechain_iterator operator++(int) {        // Postincrement
1027
557
      defusechain_iterator tmp = *this; ++*this; return tmp;
1028
557
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator++(int)
Line
Count
Source
1026
88.7k
    defusechain_iterator operator++(int) {        // Postincrement
1027
88.7k
      defusechain_iterator tmp = *this; ++*this; return tmp;
1028
88.7k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator++(int)
Line
Count
Source
1026
302
    defusechain_iterator operator++(int) {        // Postincrement
1027
302
      defusechain_iterator tmp = *this; ++*this; return tmp;
1028
302
    }
1029
1030
    /// getOperandNo - Return the operand # of this MachineOperand in its
1031
    /// MachineInstr.
1032
16.3M
    unsigned getOperandNo() const {
1033
16.3M
      assert(Op && "Cannot dereference end iterator!");
1034
16.3M
      return Op - &Op->getParent()->getOperand(0);
1035
16.3M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::getOperandNo() const
Line
Count
Source
1032
543k
    unsigned getOperandNo() const {
1033
543k
      assert(Op && "Cannot dereference end iterator!");
1034
543k
      return Op - &Op->getParent()->getOperand(0);
1035
543k
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::getOperandNo() const
Line
Count
Source
1032
15.7M
    unsigned getOperandNo() const {
1033
15.7M
      assert(Op && "Cannot dereference end iterator!");
1034
15.7M
      return Op - &Op->getParent()->getOperand(0);
1035
15.7M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::getOperandNo() const
Line
Count
Source
1032
1.70k
    unsigned getOperandNo() const {
1033
1.70k
      assert(Op && "Cannot dereference end iterator!");
1034
1.70k
      return Op - &Op->getParent()->getOperand(0);
1035
1.70k
    }
1036
1037
    // Retrieve a reference to the current operand.
1038
159M
    MachineOperand &operator*() const {
1039
159M
      assert(Op && "Cannot dereference end iterator!");
1040
159M
      return *Op;
1041
159M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator*() const
Line
Count
Source
1038
4.84M
    MachineOperand &operator*() const {
1039
4.84M
      assert(Op && "Cannot dereference end iterator!");
1040
4.84M
      return *Op;
1041
4.84M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator*() const
Line
Count
Source
1038
22.9M
    MachineOperand &operator*() const {
1039
22.9M
      assert(Op && "Cannot dereference end iterator!");
1040
22.9M
      return *Op;
1041
22.9M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator*() const
Line
Count
Source
1038
9.66M
    MachineOperand &operator*() const {
1039
9.66M
      assert(Op && "Cannot dereference end iterator!");
1040
9.66M
      return *Op;
1041
9.66M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator*() const
Line
Count
Source
1038
80.2M
    MachineOperand &operator*() const {
1039
80.2M
      assert(Op && "Cannot dereference end iterator!");
1040
80.2M
      return *Op;
1041
80.2M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator*() const
Line
Count
Source
1038
41.6M
    MachineOperand &operator*() const {
1039
41.6M
      assert(Op && "Cannot dereference end iterator!");
1040
41.6M
      return *Op;
1041
41.6M
    }
1042
1043
13.6M
    MachineOperand *operator->() const {
1044
13.6M
      assert(Op && "Cannot dereference end iterator!");
1045
13.6M
      return Op;
1046
13.6M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator->() const
Line
Count
Source
1043
976k
    MachineOperand *operator->() const {
1044
976k
      assert(Op && "Cannot dereference end iterator!");
1045
976k
      return Op;
1046
976k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator->() const
Line
Count
Source
1043
2.66k
    MachineOperand *operator->() const {
1044
2.66k
      assert(Op && "Cannot dereference end iterator!");
1045
2.66k
      return Op;
1046
2.66k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator->() const
Line
Count
Source
1043
389k
    MachineOperand *operator->() const {
1044
389k
      assert(Op && "Cannot dereference end iterator!");
1045
389k
      return Op;
1046
389k
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator->() const
Line
Count
Source
1043
12.2M
    MachineOperand *operator->() const {
1044
12.2M
      assert(Op && "Cannot dereference end iterator!");
1045
12.2M
      return Op;
1046
12.2M
    }
1047
  };
1048
1049
  /// defusechain_iterator - This class provides iterator support for machine
1050
  /// operands in the function that use or define a specific register.  If
1051
  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1052
  /// returns defs.  If neither are true then you are silly and it always
1053
  /// returns end().  If SkipDebug is true it skips uses marked Debug
1054
  /// when incrementing.
1055
  template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
1056
           bool ByOperand, bool ByInstr, bool ByBundle>
1057
  class defusechain_instr_iterator
1058
    : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
1059
    friend class MachineRegisterInfo;
1060
1061
    MachineOperand *Op = nullptr;
1062
1063
112M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1064
112M
      // If the first node isn't one we're interested in, advance to one that
1065
112M
      // we are interested in.
1066
112M
      if (op) {
1067
83.7M
        if ((!ReturnUses && 
op->isUse()58.7M
) ||
1068
83.7M
            
(11.1M
!ReturnDefs11.1M
&&
op->isDef()11.1M
) ||
1069
83.7M
            
(921k
SkipDebug921k
&&
op->isDebug()921k
))
1070
11.2M
          advance();
1071
83.7M
      }
1072
112M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1063
64.0M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1064
64.0M
      // If the first node isn't one we're interested in, advance to one that
1065
64.0M
      // we are interested in.
1066
64.0M
      if (op) {
1067
58.7M
        if ((!ReturnUses && op->isUse()) ||
1068
58.7M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
1069
58.7M
            
(0
SkipDebug0
&&
op->isDebug()0
))
1070
15.8k
          advance();
1071
58.7M
      }
1072
64.0M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1063
8.32M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1064
8.32M
      // If the first node isn't one we're interested in, advance to one that
1065
8.32M
      // we are interested in.
1066
8.32M
      if (op) {
1067
5.38M
        if ((!ReturnUses && 
op->isUse()0
) ||
1068
5.38M
            (!ReturnDefs && op->isDef()) ||
1069
5.38M
            
(0
SkipDebug0
&&
op->isDebug()0
))
1070
5.38M
          advance();
1071
5.38M
      }
1072
8.32M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1063
11.6M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1064
11.6M
      // If the first node isn't one we're interested in, advance to one that
1065
11.6M
      // we are interested in.
1066
11.6M
      if (op) {
1067
5.80M
        if ((!ReturnUses && 
op->isUse()0
) ||
1068
5.80M
            (!ReturnDefs && op->isDef()) ||
1069
5.80M
            
(0
SkipDebug0
&&
op->isDebug()0
))
1070
5.80M
          advance();
1071
5.80M
      }
1072
11.6M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1063
25.7M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1064
25.7M
      // If the first node isn't one we're interested in, advance to one that
1065
25.7M
      // we are interested in.
1066
25.7M
      if (op) {
1067
12.6M
        if ((!ReturnUses && 
op->isUse()0
) ||
1068
12.6M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
1069
12.6M
            
(0
SkipDebug0
&&
op->isDebug()0
))
1070
0
          advance();
1071
12.6M
      }
1072
25.7M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1063
1.84M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1064
1.84M
      // If the first node isn't one we're interested in, advance to one that
1065
1.84M
      // we are interested in.
1066
1.84M
      if (op) {
1067
921k
        if ((!ReturnUses && 
op->isUse()0
) ||
1068
921k
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
1069
921k
            (SkipDebug && op->isDebug()))
1070
0
          advance();
1071
921k
      }
1072
1.84M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1063
547k
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1064
547k
      // If the first node isn't one we're interested in, advance to one that
1065
547k
      // we are interested in.
1066
547k
      if (op) {
1067
273k
        if ((!ReturnUses && 
op->isUse()0
) ||
1068
273k
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
1069
273k
            
(0
SkipDebug0
&&
op->isDebug()0
))
1070
0
          advance();
1071
273k
      }
1072
547k
    }
1073
1074
63.2M
    void advance() {
1075
63.2M
      assert(Op && "Cannot increment end iterator!");
1076
63.2M
      Op = getNextOperandForReg(Op);
1077
63.2M
1078
63.2M
      // All defs come before the uses, so stop def_iterator early.
1079
63.2M
      if (!ReturnUses) {
1080
3.23M
        if (Op) {
1081
3.21M
          if (Op->isUse())
1082
3.16M
            Op = nullptr;
1083
3.21M
          else
1084
3.21M
            assert(!Op->isDebug() && "Can't have debug defs");
1085
3.21M
        }
1086
60.0M
      } else {
1087
60.0M
        // If this is an operand we don't care about, skip it.
1088
62.2M
        while (Op && 
(41.0M
(41.0M
!ReturnDefs41.0M
&&
Op->isDef()15.3M
) ||
1089
41.0M
                      
(38.8M
SkipDebug38.8M
&&
Op->isDebug()10.8M
)))
1090
2.20M
          Op = getNextOperandForReg(Op);
1091
60.0M
      }
1092
63.2M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::advance()
Line
Count
Source
1074
3.23M
    void advance() {
1075
3.23M
      assert(Op && "Cannot increment end iterator!");
1076
3.23M
      Op = getNextOperandForReg(Op);
1077
3.23M
1078
3.23M
      // All defs come before the uses, so stop def_iterator early.
1079
3.23M
      if (!ReturnUses) {
1080
3.23M
        if (Op) {
1081
3.21M
          if (Op->isUse())
1082
3.16M
            Op = nullptr;
1083
3.21M
          else
1084
3.21M
            assert(!Op->isDebug() && "Can't have debug defs");
1085
3.21M
        }
1086
3.23M
      } else {
1087
0
        // If this is an operand we don't care about, skip it.
1088
0
        while (Op && ((!ReturnDefs && Op->isDef()) ||
1089
0
                      (SkipDebug && Op->isDebug())))
1090
0
          Op = getNextOperandForReg(Op);
1091
0
      }
1092
3.23M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::advance()
Line
Count
Source
1074
9.05M
    void advance() {
1075
9.05M
      assert(Op && "Cannot increment end iterator!");
1076
9.05M
      Op = getNextOperandForReg(Op);
1077
9.05M
1078
9.05M
      // All defs come before the uses, so stop def_iterator early.
1079
9.05M
      if (!ReturnUses) {
1080
0
        if (Op) {
1081
0
          if (Op->isUse())
1082
0
            Op = nullptr;
1083
0
          else
1084
0
            assert(!Op->isDebug() && "Can't have debug defs");
1085
0
        }
1086
9.05M
      } else {
1087
9.05M
        // If this is an operand we don't care about, skip it.
1088
10.1M
        while (Op && 
(8.49M
(8.49M
!ReturnDefs8.49M
&&
Op->isDef()8.49M
) ||
1089
8.49M
                      
(7.40M
SkipDebug7.40M
&&
Op->isDebug()7.40M
)))
1090
1.09M
          Op = getNextOperandForReg(Op);
1091
9.05M
      }
1092
9.05M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::advance()
Line
Count
Source
1074
11.4M
    void advance() {
1075
11.4M
      assert(Op && "Cannot increment end iterator!");
1076
11.4M
      Op = getNextOperandForReg(Op);
1077
11.4M
1078
11.4M
      // All defs come before the uses, so stop def_iterator early.
1079
11.4M
      if (!ReturnUses) {
1080
0
        if (Op) {
1081
0
          if (Op->isUse())
1082
0
            Op = nullptr;
1083
0
          else
1084
0
            assert(!Op->isDebug() && "Can't have debug defs");
1085
0
        }
1086
11.4M
      } else {
1087
11.4M
        // If this is an operand we don't care about, skip it.
1088
12.5M
        while (Op && 
(6.89M
(6.89M
!ReturnDefs6.89M
&&
Op->isDef()6.89M
) ||
1089
6.89M
                      
(5.78M
SkipDebug5.78M
&&
Op->isDebug()0
)))
1090
1.11M
          Op = getNextOperandForReg(Op);
1091
11.4M
      }
1092
11.4M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::advance()
Line
Count
Source
1074
34.3M
    void advance() {
1075
34.3M
      assert(Op && "Cannot increment end iterator!");
1076
34.3M
      Op = getNextOperandForReg(Op);
1077
34.3M
1078
34.3M
      // All defs come before the uses, so stop def_iterator early.
1079
34.3M
      if (!ReturnUses) {
1080
0
        if (Op) {
1081
0
          if (Op->isUse())
1082
0
            Op = nullptr;
1083
0
          else
1084
0
            assert(!Op->isDebug() && "Can't have debug defs");
1085
0
        }
1086
34.3M
      } else {
1087
34.3M
        // If this is an operand we don't care about, skip it.
1088
34.3M
        while (Op && 
(21.7M
(21.7M
!ReturnDefs21.7M
&&
Op->isDef()0
) ||
1089
21.7M
                      (SkipDebug && 
Op->isDebug()0
)))
1090
0
          Op = getNextOperandForReg(Op);
1091
34.3M
      }
1092
34.3M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::advance()
Line
Count
Source
1074
4.37M
    void advance() {
1075
4.37M
      assert(Op && "Cannot increment end iterator!");
1076
4.37M
      Op = getNextOperandForReg(Op);
1077
4.37M
1078
4.37M
      // All defs come before the uses, so stop def_iterator early.
1079
4.37M
      if (!ReturnUses) {
1080
0
        if (Op) {
1081
0
          if (Op->isUse())
1082
0
            Op = nullptr;
1083
0
          else
1084
0
            assert(!Op->isDebug() && "Can't have debug defs");
1085
0
        }
1086
4.37M
      } else {
1087
4.37M
        // If this is an operand we don't care about, skip it.
1088
4.37M
        while (Op && 
(3.49M
(3.49M
!ReturnDefs3.49M
&&
Op->isDef()0
) ||
1089
3.49M
                      (SkipDebug && Op->isDebug())))
1090
0
          Op = getNextOperandForReg(Op);
1091
4.37M
      }
1092
4.37M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::advance()
Line
Count
Source
1074
739k
    void advance() {
1075
739k
      assert(Op && "Cannot increment end iterator!");
1076
739k
      Op = getNextOperandForReg(Op);
1077
739k
1078
739k
      // All defs come before the uses, so stop def_iterator early.
1079
739k
      if (!ReturnUses) {
1080
0
        if (Op) {
1081
0
          if (Op->isUse())
1082
0
            Op = nullptr;
1083
0
          else
1084
0
            assert(!Op->isDebug() && "Can't have debug defs");
1085
0
        }
1086
739k
      } else {
1087
739k
        // If this is an operand we don't care about, skip it.
1088
739k
        while (Op && 
(465k
(465k
!ReturnDefs465k
&&
Op->isDef()0
) ||
1089
465k
                      (SkipDebug && 
Op->isDebug()0
)))
1090
0
          Op = getNextOperandForReg(Op);
1091
739k
      }
1092
739k
    }
1093
1094
  public:
1095
    using reference = std::iterator<std::forward_iterator_tag,
1096
                                    MachineInstr, ptrdiff_t>::reference;
1097
    using pointer = std::iterator<std::forward_iterator_tag,
1098
                                  MachineInstr, ptrdiff_t>::pointer;
1099
1100
3.10M
    defusechain_instr_iterator() = default;
1101
1102
76.5M
    bool operator==(const defusechain_instr_iterator &x) const {
1103
76.5M
      return Op == x.Op;
1104
76.5M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false> const&) const
Line
Count
Source
1102
6.56M
    bool operator==(const defusechain_instr_iterator &x) const {
1103
6.56M
      return Op == x.Op;
1104
6.56M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false> const&) const
Line
Count
Source
1102
11.4M
    bool operator==(const defusechain_instr_iterator &x) const {
1103
11.4M
      return Op == x.Op;
1104
11.4M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false> const&) const
Line
Count
Source
1102
5.41M
    bool operator==(const defusechain_instr_iterator &x) const {
1103
5.41M
      return Op == x.Op;
1104
5.41M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false> const&) const
Line
Count
Source
1102
46.8M
    bool operator==(const defusechain_instr_iterator &x) const {
1103
46.8M
      return Op == x.Op;
1104
46.8M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false> const&) const
Line
Count
Source
1102
5.21M
    bool operator==(const defusechain_instr_iterator &x) const {
1103
5.21M
      return Op == x.Op;
1104
5.21M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true> const&) const
Line
Count
Source
1102
1.00M
    bool operator==(const defusechain_instr_iterator &x) const {
1103
1.00M
      return Op == x.Op;
1104
1.00M
    }
1105
76.5M
    bool operator!=(const defusechain_instr_iterator &x) const {
1106
76.5M
      return !operator==(x);
1107
76.5M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false> const&) const
Line
Count
Source
1105
6.56M
    bool operator!=(const defusechain_instr_iterator &x) const {
1106
6.56M
      return !operator==(x);
1107
6.56M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false> const&) const
Line
Count
Source
1105
11.4M
    bool operator!=(const defusechain_instr_iterator &x) const {
1106
11.4M
      return !operator==(x);
1107
11.4M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false> const&) const
Line
Count
Source
1105
5.41M
    bool operator!=(const defusechain_instr_iterator &x) const {
1106
5.41M
      return !operator==(x);
1107
5.41M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false> const&) const
Line
Count
Source
1105
46.8M
    bool operator!=(const defusechain_instr_iterator &x) const {
1106
46.8M
      return !operator==(x);
1107
46.8M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false> const&) const
Line
Count
Source
1105
5.21M
    bool operator!=(const defusechain_instr_iterator &x) const {
1106
5.21M
      return !operator==(x);
1107
5.21M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true> const&) const
Line
Count
Source
1105
1.00M
    bool operator!=(const defusechain_instr_iterator &x) const {
1106
1.00M
      return !operator==(x);
1107
1.00M
    }
1108
1109
    /// atEnd - return true if this iterator is equal to reg_end() on the value.
1110
49.2M
    bool atEnd() const { return Op == nullptr; }
1111
1112
    // Iterator traversal: forward iteration only
1113
51.5M
    defusechain_instr_iterator &operator++() {          // Preincrement
1114
51.5M
      assert(Op && "Cannot increment end iterator!");
1115
51.5M
      if (ByOperand)
1116
0
        advance();
1117
51.5M
      else if (ByInstr) {
1118
50.8M
        MachineInstr *P = Op->getParent();
1119
51.3M
        do {
1120
51.3M
          advance();
1121
51.3M
        } while (Op && 
Op->getParent() == P29.1M
);
1122
50.8M
      } else 
if (735k
ByBundle735k
) {
1123
735k
        MachineBasicBlock::instr_iterator P =
1124
735k
            getBundleStart(Op->getParent()->getIterator());
1125
739k
        do {
1126
739k
          advance();
1127
739k
        } while (Op && 
getBundleStart(Op->getParent()->getIterator()) == P465k
);
1128
735k
      }
1129
51.5M
1130
51.5M
      return *this;
1131
51.5M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator++()
Line
Count
Source
1113
3.61M
    defusechain_instr_iterator &operator++() {          // Preincrement
1114
3.61M
      assert(Op && "Cannot increment end iterator!");
1115
3.61M
      if (ByOperand)
1116
0
        advance();
1117
3.61M
      else if (ByInstr) {
1118
3.61M
        MachineInstr *P = Op->getParent();
1119
3.66M
        do {
1120
3.66M
          advance();
1121
3.66M
        } while (Op && 
Op->getParent() == P2.03M
);
1122
3.61M
      } else 
if (0
ByBundle0
) {
1123
0
        MachineBasicBlock::instr_iterator P =
1124
0
            getBundleStart(Op->getParent()->getIterator());
1125
0
        do {
1126
0
          advance();
1127
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1128
0
      }
1129
3.61M
1130
3.61M
      return *this;
1131
3.61M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator++()
Line
Count
Source
1113
5.65M
    defusechain_instr_iterator &operator++() {          // Preincrement
1114
5.65M
      assert(Op && "Cannot increment end iterator!");
1115
5.65M
      if (ByOperand)
1116
0
        advance();
1117
5.65M
      else if (ByInstr) {
1118
5.65M
        MachineInstr *P = Op->getParent();
1119
5.68M
        do {
1120
5.68M
          advance();
1121
5.68M
        } while (Op && 
Op->getParent() == P1.86M
);
1122
5.65M
      } else 
if (0
ByBundle0
) {
1123
0
        MachineBasicBlock::instr_iterator P =
1124
0
            getBundleStart(Op->getParent()->getIterator());
1125
0
        do {
1126
0
          advance();
1127
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1128
0
      }
1129
5.65M
1130
5.65M
      return *this;
1131
5.65M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator++()
Line
Count
Source
1113
3.21M
    defusechain_instr_iterator &operator++() {          // Preincrement
1114
3.21M
      assert(Op && "Cannot increment end iterator!");
1115
3.21M
      if (ByOperand)
1116
0
        advance();
1117
3.21M
      else if (ByInstr) {
1118
3.21M
        MachineInstr *P = Op->getParent();
1119
3.21M
        do {
1120
3.21M
          advance();
1121
3.21M
        } while (Op && 
Op->getParent() == P57.6k
);
1122
3.21M
      } else 
if (0
ByBundle0
) {
1123
0
        MachineBasicBlock::instr_iterator P =
1124
0
            getBundleStart(Op->getParent()->getIterator());
1125
0
        do {
1126
0
          advance();
1127
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1128
0
      }
1129
3.21M
1130
3.21M
      return *this;
1131
3.21M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator++()
Line
Count
Source
1113
34.0M
    defusechain_instr_iterator &operator++() {          // Preincrement
1114
34.0M
      assert(Op && "Cannot increment end iterator!");
1115
34.0M
      if (ByOperand)
1116
0
        advance();
1117
34.0M
      else 
if (34.0M
ByInstr34.0M
) {
1118
34.0M
        MachineInstr *P = Op->getParent();
1119
34.3M
        do {
1120
34.3M
          advance();
1121
34.3M
        } while (Op && 
Op->getParent() == P21.7M
);
1122
18.4E
      } else if (ByBundle) {
1123
0
        MachineBasicBlock::instr_iterator P =
1124
0
            getBundleStart(Op->getParent()->getIterator());
1125
0
        do {
1126
0
          advance();
1127
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1128
0
      }
1129
34.0M
1130
34.0M
      return *this;
1131
34.0M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator++()
Line
Count
Source
1113
4.35M
    defusechain_instr_iterator &operator++() {          // Preincrement
1114
4.35M
      assert(Op && "Cannot increment end iterator!");
1115
4.35M
      if (ByOperand)
1116
0
        advance();
1117
4.35M
      else if (ByInstr) {
1118
4.35M
        MachineInstr *P = Op->getParent();
1119
4.37M
        do {
1120
4.37M
          advance();
1121
4.37M
        } while (Op && 
Op->getParent() == P3.49M
);
1122
4.35M
      } else 
if (0
ByBundle0
) {
1123
0
        MachineBasicBlock::instr_iterator P =
1124
0
            getBundleStart(Op->getParent()->getIterator());
1125
0
        do {
1126
0
          advance();
1127
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1128
0
      }
1129
4.35M
1130
4.35M
      return *this;
1131
4.35M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator++()
Line
Count
Source
1113
735k
    defusechain_instr_iterator &operator++() {          // Preincrement
1114
735k
      assert(Op && "Cannot increment end iterator!");
1115
735k
      if (ByOperand)
1116
0
        advance();
1117
735k
      else if (ByInstr) {
1118
0
        MachineInstr *P = Op->getParent();
1119
0
        do {
1120
0
          advance();
1121
0
        } while (Op && Op->getParent() == P);
1122
735k
      } else if (ByBundle) {
1123
735k
        MachineBasicBlock::instr_iterator P =
1124
735k
            getBundleStart(Op->getParent()->getIterator());
1125
739k
        do {
1126
739k
          advance();
1127
739k
        } while (Op && 
getBundleStart(Op->getParent()->getIterator()) == P465k
);
1128
735k
      }
1129
735k
1130
735k
      return *this;
1131
735k
    }
1132
32.6M
    defusechain_instr_iterator operator++(int) {        // Postincrement
1133
32.6M
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1134
32.6M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator++(int)
Line
Count
Source
1132
31.2M
    defusechain_instr_iterator operator++(int) {        // Postincrement
1133
31.2M
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1134
31.2M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator++(int)
Line
Count
Source
1132
147k
    defusechain_instr_iterator operator++(int) {        // Postincrement
1133
147k
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1134
147k
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator++(int)
Line
Count
Source
1132
735k
    defusechain_instr_iterator operator++(int) {        // Postincrement
1133
735k
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1134
735k
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator++(int)
Line
Count
Source
1132
481k
    defusechain_instr_iterator operator++(int) {        // Postincrement
1133
481k
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1134
481k
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator++(int)
Line
Count
Source
1132
221
    defusechain_instr_iterator operator++(int) {        // Postincrement
1133
221
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1134
221
    }
1135
1136
    // Retrieve a reference to the current operand.
1137
111M
    MachineInstr &operator*() const {
1138
111M
      assert(Op && "Cannot dereference end iterator!");
1139
111M
      if (ByBundle)
1140
735k
        return *getBundleStart(Op->getParent()->getIterator());
1141
110M
      return *Op->getParent();
1142
110M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator*() const
Line
Count
Source
1137
58.8M
    MachineInstr &operator*() const {
1138
58.8M
      assert(Op && "Cannot dereference end iterator!");
1139
58.8M
      if (ByBundle)
1140
0
        return *getBundleStart(Op->getParent()->getIterator());
1141
58.8M
      return *Op->getParent();
1142
58.8M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator*() const
Line
Count
Source
1137
7.34M
    MachineInstr &operator*() const {
1138
7.34M
      assert(Op && "Cannot dereference end iterator!");
1139
7.34M
      if (ByBundle)
1140
0
        return *getBundleStart(Op->getParent()->getIterator());
1141
7.34M
      return *Op->getParent();
1142
7.34M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator*() const
Line
Count
Source
1137
5.75M
    MachineInstr &operator*() const {
1138
5.75M
      assert(Op && "Cannot dereference end iterator!");
1139
5.75M
      if (ByBundle)
1140
0
        return *getBundleStart(Op->getParent()->getIterator());
1141
5.75M
      return *Op->getParent();
1142
5.75M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator*() const
Line
Count
Source
1137
34.0M
    MachineInstr &operator*() const {
1138
34.0M
      assert(Op && "Cannot dereference end iterator!");
1139
34.0M
      if (ByBundle)
1140
0
        return *getBundleStart(Op->getParent()->getIterator());
1141
34.0M
      return *Op->getParent();
1142
34.0M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator*() const
Line
Count
Source
1137
4.35M
    MachineInstr &operator*() const {
1138
4.35M
      assert(Op && "Cannot dereference end iterator!");
1139
4.35M
      if (ByBundle)
1140
0
        return *getBundleStart(Op->getParent()->getIterator());
1141
4.35M
      return *Op->getParent();
1142
4.35M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator*() const
Line
Count
Source
1137
735k
    MachineInstr &operator*() const {
1138
735k
      assert(Op && "Cannot dereference end iterator!");
1139
735k
      if (ByBundle)
1140
735k
        return *getBundleStart(Op->getParent()->getIterator());
1141
0
      return *Op->getParent();
1142
0
    }
1143
1144
2.58k
    MachineInstr *operator->() const { return &operator*(); }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator->() const
Line
Count
Source
1144
595
    MachineInstr *operator->() const { return &operator*(); }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator->() const
Line
Count
Source
1144
60
    MachineInstr *operator->() const { return &operator*(); }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator->() const
Line
Count
Source
1144
1.93k
    MachineInstr *operator->() const { return &operator*(); }
1145
  };
1146
};
1147
1148
/// Iterate over the pressure sets affected by the given physical or virtual
1149
/// register. If Reg is physical, it must be a register unit (from
1150
/// MCRegUnitIterator).
1151
class PSetIterator {
1152
  const int *PSet = nullptr;
1153
  unsigned Weight = 0;
1154
1155
public:
1156
  PSetIterator() = default;
1157
1158
27.9M
  PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
1159
27.9M
    const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1160
27.9M
    if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
1161
25.4M
      const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
1162
25.4M
      PSet = TRI->getRegClassPressureSets(RC);
1163
25.4M
      Weight = TRI->getRegClassWeight(RC).RegWeight;
1164
25.4M
    }
1165
2.44M
    else {
1166
2.44M
      PSet = TRI->getRegUnitPressureSets(RegUnit);
1167
2.44M
      Weight = TRI->getRegUnitWeight(RegUnit);
1168
2.44M
    }
1169
27.9M
    if (*PSet == -1)
1170
434k
      PSet = nullptr;
1171
27.9M
  }
1172
1173
98.8M
  bool isValid() const { return PSet; }
1174
1175
27.9M
  unsigned getWeight() const { return Weight; }
1176
1177
225M
  unsigned operator*() const { return *PSet; }
1178
1179
71.2M
  void operator++() {
1180
71.2M
    assert(isValid() && "Invalid PSetIterator.");
1181
71.2M
    ++PSet;
1182
71.2M
    if (*PSet == -1)
1183
26.9M
      PSet = nullptr;
1184
71.2M
  }
1185
};
1186
1187
inline PSetIterator MachineRegisterInfo::
1188
27.9M
getPressureSets(unsigned RegUnit) const {
1189
27.9M
  return PSetIterator(RegUnit, this);
1190
27.9M
}
1191
1192
} // end namespace llvm
1193
1194
#endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H