Coverage Report

Created: 2018-12-11 17:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
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//===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the MachineRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
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#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/PointerUnion.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringSet.h"
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#include "llvm/ADT/iterator_range.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/LowLevelType.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/MC/LaneBitmask.h"
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#include <cassert>
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#include <cstddef>
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#include <cstdint>
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#include <iterator>
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#include <memory>
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#include <utility>
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#include <vector>
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namespace llvm {
43
44
class PSetIterator;
45
46
/// Convenient type to represent either a register class or a register bank.
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using RegClassOrRegBank =
48
    PointerUnion<const TargetRegisterClass *, const RegisterBank *>;
49
50
/// MachineRegisterInfo - Keep track of information for virtual and physical
51
/// registers, including vreg register classes, use/def chains for registers,
52
/// etc.
53
class MachineRegisterInfo {
54
public:
55
  class Delegate {
56
    virtual void anchor();
57
58
  public:
59
1.53M
    virtual ~Delegate() = default;
60
61
    virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
62
  };
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64
private:
65
  MachineFunction *MF;
66
  Delegate *TheDelegate = nullptr;
67
68
  /// True if subregister liveness is tracked.
69
  const bool TracksSubRegLiveness;
70
71
  /// VRegInfo - Information we keep for each virtual register.
72
  ///
73
  /// Each element in this list contains the register class of the vreg and the
74
  /// start of the use/def list for the register.
75
  IndexedMap<std::pair<RegClassOrRegBank, MachineOperand *>,
76
             VirtReg2IndexFunctor>
77
      VRegInfo;
78
79
  /// Map for recovering vreg name from vreg number.
80
  /// This map is used by the MIR Printer.
81
  IndexedMap<std::string, VirtReg2IndexFunctor> VReg2Name;
82
83
  /// StringSet that is used to unique vreg names.
84
  StringSet<> VRegNames;
85
86
  /// The flag is true upon \p UpdatedCSRs initialization
87
  /// and false otherwise.
88
  bool IsUpdatedCSRsInitialized;
89
90
  /// Contains the updated callee saved register list.
91
  /// As opposed to the static list defined in register info,
92
  /// all registers that were disabled are removed from the list.
93
  SmallVector<MCPhysReg, 16> UpdatedCSRs;
94
95
  /// RegAllocHints - This vector records register allocation hints for
96
  /// virtual registers. For each virtual register, it keeps a pair of hint
97
  /// type and hints vector making up the allocation hints. Only the first
98
  /// hint may be target specific, and in that case this is reflected by the
99
  /// first member of the pair being non-zero. If the hinted register is
100
  /// virtual, it means the allocator should prefer the physical register
101
  /// allocated to it if any.
102
  IndexedMap<std::pair<unsigned, SmallVector<unsigned, 4>>,
103
             VirtReg2IndexFunctor> RegAllocHints;
104
105
  /// PhysRegUseDefLists - This is an array of the head of the use/def list for
106
  /// physical registers.
107
  std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
108
109
  /// getRegUseDefListHead - Return the head pointer for the register use/def
110
  /// list for the specified virtual or physical register.
111
376M
  MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
112
376M
    if (TargetRegisterInfo::isVirtualRegister(RegNo))
113
173M
      return VRegInfo[RegNo].second;
114
202M
    return PhysRegUseDefLists[RegNo];
115
202M
  }
116
117
956M
  MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
118
956M
    if (TargetRegisterInfo::isVirtualRegister(RegNo))
119
475M
      return VRegInfo[RegNo].second;
120
480M
    return PhysRegUseDefLists[RegNo];
121
480M
  }
122
123
  /// Get the next element in the use-def chain.
124
483M
  static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
125
483M
    assert(MO && MO->isReg() && "This is not a register operand!");
126
483M
    return MO->Contents.Reg.Next;
127
483M
  }
128
129
  /// UsedPhysRegMask - Additional used physregs including aliases.
130
  /// This bit vector represents all the registers clobbered by function calls.
131
  BitVector UsedPhysRegMask;
132
133
  /// ReservedRegs - This is a bit vector of reserved registers.  The target
134
  /// may change its mind about which registers should be reserved.  This
135
  /// vector is the frozen set of reserved registers when register allocation
136
  /// started.
137
  BitVector ReservedRegs;
138
139
  using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;
140
  /// Map generic virtual registers to their low-level type.
141
  VRegToTypeMap VRegToType;
142
143
  /// Keep track of the physical registers that are live in to the function.
144
  /// Live in values are typically arguments in registers.  LiveIn values are
145
  /// allowed to have virtual registers associated with them, stored in the
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  /// second element.
147
  std::vector<std::pair<unsigned, unsigned>> LiveIns;
148
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public:
150
  explicit MachineRegisterInfo(MachineFunction *MF);
151
  MachineRegisterInfo(const MachineRegisterInfo &) = delete;
152
  MachineRegisterInfo &operator=(const MachineRegisterInfo &) = delete;
153
154
163M
  const TargetRegisterInfo *getTargetRegisterInfo() const {
155
163M
    return MF->getSubtarget().getRegisterInfo();
156
163M
  }
157
158
1.53M
  void resetDelegate(Delegate *delegate) {
159
1.53M
    // Ensure another delegate does not take over unless the current
160
1.53M
    // delegate first unattaches itself. If we ever need to multicast
161
1.53M
    // notifications, we will need to change to using a list.
162
1.53M
    assert(TheDelegate == delegate &&
163
1.53M
           "Only the current delegate can perform reset!");
164
1.53M
    TheDelegate = nullptr;
165
1.53M
  }
166
167
1.53M
  void setDelegate(Delegate *delegate) {
168
1.53M
    assert(delegate && !TheDelegate &&
169
1.53M
           "Attempted to set delegate to null, or to change it without "
170
1.53M
           "first resetting it!");
171
1.53M
172
1.53M
    TheDelegate = delegate;
173
1.53M
  }
174
175
  //===--------------------------------------------------------------------===//
176
  // Function State
177
  //===--------------------------------------------------------------------===//
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179
  // isSSA - Returns true when the machine function is in SSA form. Early
180
  // passes require the machine function to be in SSA form where every virtual
181
  // register has a single defining instruction.
182
  //
183
  // The TwoAddressInstructionPass and PHIElimination passes take the machine
184
  // function out of SSA form when they introduce multiple defs per virtual
185
  // register.
186
93.6M
  bool isSSA() const {
187
93.6M
    return MF->getProperties().hasProperty(
188
93.6M
        MachineFunctionProperties::Property::IsSSA);
189
93.6M
  }
190
191
  // leaveSSA - Indicates that the machine function is no longer in SSA form.
192
1.04M
  void leaveSSA() {
193
1.04M
    MF->getProperties().reset(MachineFunctionProperties::Property::IsSSA);
194
1.04M
  }
195
196
  /// tracksLiveness - Returns true when tracking register liveness accurately.
197
  /// (see MachineFUnctionProperties::Property description for details)
198
70.8M
  bool tracksLiveness() const {
199
70.8M
    return MF->getProperties().hasProperty(
200
70.8M
        MachineFunctionProperties::Property::TracksLiveness);
201
70.8M
  }
202
203
  /// invalidateLiveness - Indicates that register liveness is no longer being
204
  /// tracked accurately.
205
  ///
206
  /// This should be called by late passes that invalidate the liveness
207
  /// information.
208
70.1k
  void invalidateLiveness() {
209
70.1k
    MF->getProperties().reset(
210
70.1k
        MachineFunctionProperties::Property::TracksLiveness);
211
70.1k
  }
212
213
  /// Returns true if liveness for register class @p RC should be tracked at
214
  /// the subregister level.
215
37.4M
  bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const {
216
37.4M
    return subRegLivenessEnabled() && 
RC.HasDisjunctSubRegs2.35M
;
217
37.4M
  }
218
32.4M
  bool shouldTrackSubRegLiveness(unsigned VReg) const {
219
32.4M
    assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Must pass a VReg");
220
32.4M
    return shouldTrackSubRegLiveness(*getRegClass(VReg));
221
32.4M
  }
222
56.1M
  bool subRegLivenessEnabled() const {
223
56.1M
    return TracksSubRegLiveness;
224
56.1M
  }
225
226
  //===--------------------------------------------------------------------===//
227
  // Register Info
228
  //===--------------------------------------------------------------------===//
229
230
  /// Returns true if the updated CSR list was initialized and false otherwise.
231
4.93k
  bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
232
233
  /// Disables the register from the list of CSRs.
234
  /// I.e. the register will not appear as part of the CSR mask.
235
  /// \see UpdatedCalleeSavedRegs.
236
  void disableCalleeSavedRegister(unsigned Reg);
237
238
  /// Returns list of callee saved registers.
239
  /// The function returns the updated CSR list (after taking into account
240
  /// registers that are disabled from the CSR list).
241
  const MCPhysReg *getCalleeSavedRegs() const;
242
243
  /// Sets the updated Callee Saved Registers list.
244
  /// Notice that it will override ant previously disabled/saved CSRs.
245
  void setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs);
246
247
  // Strictly for use by MachineInstr.cpp.
248
  void addRegOperandToUseList(MachineOperand *MO);
249
250
  // Strictly for use by MachineInstr.cpp.
251
  void removeRegOperandFromUseList(MachineOperand *MO);
252
253
  // Strictly for use by MachineInstr.cpp.
254
  void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
255
256
  /// Verify the sanity of the use list for Reg.
257
  void verifyUseList(unsigned Reg) const;
258
259
  /// Verify the use list of all registers.
260
  void verifyUseLists() const;
261
262
  /// reg_begin/reg_end - Provide iteration support to walk over all definitions
263
  /// and uses of a register within the MachineFunction that corresponds to this
264
  /// MachineRegisterInfo object.
265
  template<bool Uses, bool Defs, bool SkipDebug,
266
           bool ByOperand, bool ByInstr, bool ByBundle>
267
  class defusechain_iterator;
268
  template<bool Uses, bool Defs, bool SkipDebug,
269
           bool ByOperand, bool ByInstr, bool ByBundle>
270
  class defusechain_instr_iterator;
271
272
  // Make it a friend so it can access getNextOperandForReg().
273
  template<bool, bool, bool, bool, bool, bool>
274
    friend class defusechain_iterator;
275
  template<bool, bool, bool, bool, bool, bool>
276
    friend class defusechain_instr_iterator;
277
278
  /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
279
  /// register.
280
  using reg_iterator =
281
      defusechain_iterator<true, true, false, true, false, false>;
282
59.1M
  reg_iterator reg_begin(unsigned RegNo) const {
283
59.1M
    return reg_iterator(getRegUseDefListHead(RegNo));
284
59.1M
  }
285
59.0M
  static reg_iterator reg_end() { return reg_iterator(nullptr); }
286
287
323k
  inline iterator_range<reg_iterator>  reg_operands(unsigned Reg) const {
288
323k
    return make_range(reg_begin(Reg), reg_end());
289
323k
  }
290
291
  /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
292
  /// of the specified register, stepping by MachineInstr.
293
  using reg_instr_iterator =
294
      defusechain_instr_iterator<true, true, false, false, true, false>;
295
14.8M
  reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
296
14.8M
    return reg_instr_iterator(getRegUseDefListHead(RegNo));
297
14.8M
  }
298
14.8M
  static reg_instr_iterator reg_instr_end() {
299
14.8M
    return reg_instr_iterator(nullptr);
300
14.8M
  }
301
302
  inline iterator_range<reg_instr_iterator>
303
764k
  reg_instructions(unsigned Reg) const {
304
764k
    return make_range(reg_instr_begin(Reg), reg_instr_end());
305
764k
  }
306
307
  /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
308
  /// of the specified register, stepping by bundle.
309
  using reg_bundle_iterator =
310
      defusechain_instr_iterator<true, true, false, false, false, true>;
311
316k
  reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
312
316k
    return reg_bundle_iterator(getRegUseDefListHead(RegNo));
313
316k
  }
314
316k
  static reg_bundle_iterator reg_bundle_end() {
315
316k
    return reg_bundle_iterator(nullptr);
316
316k
  }
317
318
0
  inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const {
319
0
    return make_range(reg_bundle_begin(Reg), reg_bundle_end());
320
0
  }
321
322
  /// reg_empty - Return true if there are no instructions using or defining the
323
  /// specified register (it may be live-in).
324
57.2M
  bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
325
326
  /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
327
  /// of the specified register, skipping those marked as Debug.
328
  using reg_nodbg_iterator =
329
      defusechain_iterator<true, true, true, true, false, false>;
330
340M
  reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
331
340M
    return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
332
340M
  }
333
340M
  static reg_nodbg_iterator reg_nodbg_end() {
334
340M
    return reg_nodbg_iterator(nullptr);
335
340M
  }
336
337
  inline iterator_range<reg_nodbg_iterator>
338
31.1M
  reg_nodbg_operands(unsigned Reg) const {
339
31.1M
    return make_range(reg_nodbg_begin(Reg), reg_nodbg_end());
340
31.1M
  }
341
342
  /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
343
  /// all defs and uses of the specified register, stepping by MachineInstr,
344
  /// skipping those marked as Debug.
345
  using reg_instr_nodbg_iterator =
346
      defusechain_instr_iterator<true, true, true, false, true, false>;
347
1.04M
  reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const {
348
1.04M
    return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
349
1.04M
  }
350
1.04M
  static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
351
1.04M
    return reg_instr_nodbg_iterator(nullptr);
352
1.04M
  }
353
354
  inline iterator_range<reg_instr_nodbg_iterator>
355
974k
  reg_nodbg_instructions(unsigned Reg) const {
356
974k
    return make_range(reg_instr_nodbg_begin(Reg), reg_instr_nodbg_end());
357
974k
  }
358
359
  /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
360
  /// all defs and uses of the specified register, stepping by bundle,
361
  /// skipping those marked as Debug.
362
  using reg_bundle_nodbg_iterator =
363
      defusechain_instr_iterator<true, true, true, false, false, true>;
364
0
  reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const {
365
0
    return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
366
0
  }
367
0
  static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
368
0
    return reg_bundle_nodbg_iterator(nullptr);
369
0
  }
370
371
  inline iterator_range<reg_bundle_nodbg_iterator>
372
0
  reg_nodbg_bundles(unsigned Reg) const {
373
0
    return make_range(reg_bundle_nodbg_begin(Reg), reg_bundle_nodbg_end());
374
0
  }
375
376
  /// reg_nodbg_empty - Return true if the only instructions using or defining
377
  /// Reg are Debug instructions.
378
309M
  bool reg_nodbg_empty(unsigned RegNo) const {
379
309M
    return reg_nodbg_begin(RegNo) == reg_nodbg_end();
380
309M
  }
381
382
  /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
383
  using def_iterator =
384
      defusechain_iterator<false, true, false, true, false, false>;
385
285M
  def_iterator def_begin(unsigned RegNo) const {
386
285M
    return def_iterator(getRegUseDefListHead(RegNo));
387
285M
  }
388
278M
  static def_iterator def_end() { return def_iterator(nullptr); }
389
390
2.77M
  inline iterator_range<def_iterator> def_operands(unsigned Reg) const {
391
2.77M
    return make_range(def_begin(Reg), def_end());
392
2.77M
  }
393
394
  /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
395
  /// specified register, stepping by MachineInst.
396
  using def_instr_iterator =
397
      defusechain_instr_iterator<false, true, false, false, true, false>;
398
67.4M
  def_instr_iterator def_instr_begin(unsigned RegNo) const {
399
67.4M
    return def_instr_iterator(getRegUseDefListHead(RegNo));
400
67.4M
  }
401
6.42M
  static def_instr_iterator def_instr_end() {
402
6.42M
    return def_instr_iterator(nullptr);
403
6.42M
  }
404
405
  inline iterator_range<def_instr_iterator>
406
2.75M
  def_instructions(unsigned Reg) const {
407
2.75M
    return make_range(def_instr_begin(Reg), def_instr_end());
408
2.75M
  }
409
410
  /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
411
  /// specified register, stepping by bundle.
412
  using def_bundle_iterator =
413
      defusechain_instr_iterator<false, true, false, false, false, true>;
414
0
  def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
415
0
    return def_bundle_iterator(getRegUseDefListHead(RegNo));
416
0
  }
417
0
  static def_bundle_iterator def_bundle_end() {
418
0
    return def_bundle_iterator(nullptr);
419
0
  }
420
421
0
  inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const {
422
0
    return make_range(def_bundle_begin(Reg), def_bundle_end());
423
0
  }
424
425
  /// def_empty - Return true if there are no instructions defining the
426
  /// specified register (it may be live-in).
427
88.4M
  bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
428
429
95.3k
  StringRef getVRegName(unsigned Reg) const {
430
95.3k
    return VReg2Name.inBounds(Reg) ? 
StringRef(VReg2Name[Reg])339
:
""95.0k
;
431
95.3k
  }
432
433
26.0M
  void insertVRegByName(StringRef Name, unsigned Reg) {
434
26.0M
    assert((Name.empty() || VRegNames.find(Name) == VRegNames.end()) &&
435
26.0M
           "Named VRegs Must be Unique.");
436
26.0M
    if (!Name.empty()) {
437
94
      VRegNames.insert(Name);
438
94
      VReg2Name.grow(Reg);
439
94
      VReg2Name[Reg] = Name.str();
440
94
    }
441
26.0M
  }
442
443
  /// Return true if there is exactly one operand defining the specified
444
  /// register.
445
9.93M
  bool hasOneDef(unsigned RegNo) const {
446
9.93M
    def_iterator DI = def_begin(RegNo);
447
9.93M
    if (DI == def_end())
448
382k
      return false;
449
9.55M
    return ++DI == def_end();
450
9.55M
  }
451
452
  /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
453
  using use_iterator =
454
      defusechain_iterator<true, false, false, true, false, false>;
455
15.4M
  use_iterator use_begin(unsigned RegNo) const {
456
15.4M
    return use_iterator(getRegUseDefListHead(RegNo));
457
15.4M
  }
458
16.1M
  static use_iterator use_end() { return use_iterator(nullptr); }
459
460
11.9M
  inline iterator_range<use_iterator> use_operands(unsigned Reg) const {
461
11.9M
    return make_range(use_begin(Reg), use_end());
462
11.9M
  }
463
464
  /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
465
  /// specified register, stepping by MachineInstr.
466
  using use_instr_iterator =
467
      defusechain_instr_iterator<true, false, false, false, true, false>;
468
7.25M
  use_instr_iterator use_instr_begin(unsigned RegNo) const {
469
7.25M
    return use_instr_iterator(getRegUseDefListHead(RegNo));
470
7.25M
  }
471
7.22M
  static use_instr_iterator use_instr_end() {
472
7.22M
    return use_instr_iterator(nullptr);
473
7.22M
  }
474
475
  inline iterator_range<use_instr_iterator>
476
3.95M
  use_instructions(unsigned Reg) const {
477
3.95M
    return make_range(use_instr_begin(Reg), use_instr_end());
478
3.95M
  }
479
480
  /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
481
  /// specified register, stepping by bundle.
482
  using use_bundle_iterator =
483
      defusechain_instr_iterator<true, false, false, false, false, true>;
484
0
  use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
485
0
    return use_bundle_iterator(getRegUseDefListHead(RegNo));
486
0
  }
487
0
  static use_bundle_iterator use_bundle_end() {
488
0
    return use_bundle_iterator(nullptr);
489
0
  }
490
491
0
  inline iterator_range<use_bundle_iterator> use_bundles(unsigned Reg) const {
492
0
    return make_range(use_bundle_begin(Reg), use_bundle_end());
493
0
  }
494
495
  /// use_empty - Return true if there are no instructions using the specified
496
  /// register.
497
2.18M
  bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
498
499
  /// hasOneUse - Return true if there is exactly one instruction using the
500
  /// specified register.
501
702k
  bool hasOneUse(unsigned RegNo) const {
502
702k
    use_iterator UI = use_begin(RegNo);
503
702k
    if (UI == use_end())
504
33
      return false;
505
702k
    return ++UI == use_end();
506
702k
  }
507
508
  /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
509
  /// specified register, skipping those marked as Debug.
510
  using use_nodbg_iterator =
511
      defusechain_iterator<true, false, true, true, false, false>;
512
158M
  use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
513
158M
    return use_nodbg_iterator(getRegUseDefListHead(RegNo));
514
158M
  }
515
181M
  static use_nodbg_iterator use_nodbg_end() {
516
181M
    return use_nodbg_iterator(nullptr);
517
181M
  }
518
519
  inline iterator_range<use_nodbg_iterator>
520
41.4M
  use_nodbg_operands(unsigned Reg) const {
521
41.4M
    return make_range(use_nodbg_begin(Reg), use_nodbg_end());
522
41.4M
  }
523
524
  /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
525
  /// all uses of the specified register, stepping by MachineInstr, skipping
526
  /// those marked as Debug.
527
  using use_instr_nodbg_iterator =
528
      defusechain_instr_iterator<true, false, true, false, true, false>;
529
6.27M
  use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const {
530
6.27M
    return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
531
6.27M
  }
532
3.45M
  static use_instr_nodbg_iterator use_instr_nodbg_end() {
533
3.45M
    return use_instr_nodbg_iterator(nullptr);
534
3.45M
  }
535
536
  inline iterator_range<use_instr_nodbg_iterator>
537
3.33M
  use_nodbg_instructions(unsigned Reg) const {
538
3.33M
    return make_range(use_instr_nodbg_begin(Reg), use_instr_nodbg_end());
539
3.33M
  }
540
541
  /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
542
  /// all uses of the specified register, stepping by bundle, skipping
543
  /// those marked as Debug.
544
  using use_bundle_nodbg_iterator =
545
      defusechain_instr_iterator<true, false, true, false, false, true>;
546
0
  use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const {
547
0
    return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
548
0
  }
549
0
  static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
550
0
    return use_bundle_nodbg_iterator(nullptr);
551
0
  }
552
553
  inline iterator_range<use_bundle_nodbg_iterator>
554
0
  use_nodbg_bundles(unsigned Reg) const {
555
0
    return make_range(use_bundle_nodbg_begin(Reg), use_bundle_nodbg_end());
556
0
  }
557
558
  /// use_nodbg_empty - Return true if there are no non-Debug instructions
559
  /// using the specified register.
560
94.0M
  bool use_nodbg_empty(unsigned RegNo) const {
561
94.0M
    return use_nodbg_begin(RegNo) == use_nodbg_end();
562
94.0M
  }
563
564
  /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
565
  /// instruction using the specified register.
566
  bool hasOneNonDBGUse(unsigned RegNo) const;
567
568
  /// replaceRegWith - Replace all instances of FromReg with ToReg in the
569
  /// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
570
  /// except that it also changes any definitions of the register as well.
571
  ///
572
  /// Note that it is usually necessary to first constrain ToReg's register
573
  /// class and register bank to match the FromReg constraints using one of the
574
  /// methods:
575
  ///
576
  ///   constrainRegClass(ToReg, getRegClass(FromReg))
577
  ///   constrainRegAttrs(ToReg, FromReg)
578
  ///   RegisterBankInfo::constrainGenericRegister(ToReg,
579
  ///       *MRI.getRegClass(FromReg), MRI)
580
  ///
581
  /// These functions will return a falsy result if the virtual registers have
582
  /// incompatible constraints.
583
  ///
584
  /// Note that if ToReg is a physical register the function will replace and
585
  /// apply sub registers to ToReg in order to obtain a final/proper physical
586
  /// register.
587
  void replaceRegWith(unsigned FromReg, unsigned ToReg);
588
589
  /// getVRegDef - Return the machine instr that defines the specified virtual
590
  /// register or null if none is found.  This assumes that the code is in SSA
591
  /// form, so there should only be one definition.
592
  MachineInstr *getVRegDef(unsigned Reg) const;
593
594
  /// getUniqueVRegDef - Return the unique machine instr that defines the
595
  /// specified virtual register or null if none is found.  If there are
596
  /// multiple definitions or no definition, return null.
597
  MachineInstr *getUniqueVRegDef(unsigned Reg) const;
598
599
  /// clearKillFlags - Iterate over all the uses of the given register and
600
  /// clear the kill flag from the MachineOperand. This function is used by
601
  /// optimization passes which extend register lifetimes and need only
602
  /// preserve conservative kill flag information.
603
  void clearKillFlags(unsigned Reg) const;
604
605
  void dumpUses(unsigned RegNo) const;
606
607
  /// Returns true if PhysReg is unallocatable and constant throughout the
608
  /// function. Writing to a constant register has no effect.
609
  bool isConstantPhysReg(unsigned PhysReg) const;
610
611
  /// Returns true if either isConstantPhysReg or TRI->isCallerPreservedPhysReg
612
  /// returns true. This is a utility member function.
613
  bool isCallerPreservedOrConstPhysReg(unsigned PhysReg) const;
614
615
  /// Get an iterator over the pressure sets affected by the given physical or
616
  /// virtual register. If RegUnit is physical, it must be a register unit (from
617
  /// MCRegUnitIterator).
618
  PSetIterator getPressureSets(unsigned RegUnit) const;
619
620
  //===--------------------------------------------------------------------===//
621
  // Virtual Register Info
622
  //===--------------------------------------------------------------------===//
623
624
  /// Return the register class of the specified virtual register.
625
  /// This shouldn't be used directly unless \p Reg has a register class.
626
  /// \see getRegClassOrNull when this might happen.
627
209M
  const TargetRegisterClass *getRegClass(unsigned Reg) const {
628
209M
    assert(VRegInfo[Reg].first.is<const TargetRegisterClass *>() &&
629
209M
           "Register class not set, wrong accessor");
630
209M
    return VRegInfo[Reg].first.get<const TargetRegisterClass *>();
631
209M
  }
632
633
  /// Return the register class of \p Reg, or null if Reg has not been assigned
634
  /// a register class yet.
635
  ///
636
  /// \note A null register class can only happen when these two
637
  /// conditions are met:
638
  /// 1. Generic virtual registers are created.
639
  /// 2. The machine function has not completely been through the
640
  ///    instruction selection process.
641
  /// None of this condition is possible without GlobalISel for now.
642
  /// In other words, if GlobalISel is not used or if the query happens after
643
  /// the select pass, using getRegClass is safe.
644
31.5M
  const TargetRegisterClass *getRegClassOrNull(unsigned Reg) const {
645
31.5M
    const RegClassOrRegBank &Val = VRegInfo[Reg].first;
646
31.5M
    return Val.dyn_cast<const TargetRegisterClass *>();
647
31.5M
  }
648
649
  /// Return the register bank of \p Reg, or null if Reg has not been assigned
650
  /// a register bank or has been assigned a register class.
651
  /// \note It is possible to get the register bank from the register class via
652
  /// RegisterBankInfo::getRegBankFromRegClass.
653
91.6k
  const RegisterBank *getRegBankOrNull(unsigned Reg) const {
654
91.6k
    const RegClassOrRegBank &Val = VRegInfo[Reg].first;
655
91.6k
    return Val.dyn_cast<const RegisterBank *>();
656
91.6k
  }
657
658
  /// Return the register bank or register class of \p Reg.
659
  /// \note Before the register bank gets assigned (i.e., before the
660
  /// RegBankSelect pass) \p Reg may not have either.
661
43.0M
  const RegClassOrRegBank &getRegClassOrRegBank(unsigned Reg) const {
662
43.0M
    return VRegInfo[Reg].first;
663
43.0M
  }
664
665
  /// setRegClass - Set the register class of the specified virtual register.
666
  void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
667
668
  /// Set the register bank to \p RegBank for \p Reg.
669
  void setRegBank(unsigned Reg, const RegisterBank &RegBank);
670
671
  void setRegClassOrRegBank(unsigned Reg,
672
78
                            const RegClassOrRegBank &RCOrRB){
673
78
    VRegInfo[Reg].first = RCOrRB;
674
78
  }
675
676
  /// constrainRegClass - Constrain the register class of the specified virtual
677
  /// register to be a common subclass of RC and the current register class,
678
  /// but only if the new class has at least MinNumRegs registers.  Return the
679
  /// new register class, or NULL if no such class exists.
680
  /// This should only be used when the constraint is known to be trivial, like
681
  /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
682
  ///
683
  /// \note Assumes that the register has a register class assigned.
684
  /// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's
685
  /// InstructionSelect pass and constrainRegAttrs in every other pass,
686
  /// including non-select passes of GlobalISel, instead.
687
  const TargetRegisterClass *constrainRegClass(unsigned Reg,
688
                                               const TargetRegisterClass *RC,
689
                                               unsigned MinNumRegs = 0);
690
691
  /// Constrain the register class or the register bank of the virtual register
692
  /// \p Reg (and low-level type) to be a common subclass or a common bank of
693
  /// both registers provided respectively (and a common low-level type). Do
694
  /// nothing if any of the attributes (classes, banks, or low-level types) of
695
  /// the registers are deemed incompatible, or if the resulting register will
696
  /// have a class smaller than before and of size less than \p MinNumRegs.
697
  /// Return true if such register attributes exist, false otherwise.
698
  ///
699
  /// \note Use this method instead of constrainRegClass and
700
  /// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG
701
  /// ISel / FastISel and GlobalISel's InstructionSelect pass respectively.
702
  bool constrainRegAttrs(unsigned Reg, unsigned ConstrainingReg,
703
                         unsigned MinNumRegs = 0);
704
705
  /// recomputeRegClass - Try to find a legal super-class of Reg's register
706
  /// class that still satisfies the constraints from the instructions using
707
  /// Reg.  Returns true if Reg was upgraded.
708
  ///
709
  /// This method can be used after constraints have been removed from a
710
  /// virtual register, for example after removing instructions or splitting
711
  /// the live range.
712
  bool recomputeRegClass(unsigned Reg);
713
714
  /// createVirtualRegister - Create and return a new virtual register in the
715
  /// function with the specified register class.
716
  unsigned createVirtualRegister(const TargetRegisterClass *RegClass,
717
                                 StringRef Name = "");
718
719
  /// Create and return a new virtual register in the function with the same
720
  /// attributes as the given register.
721
  unsigned cloneVirtualRegister(unsigned VReg, StringRef Name = "");
722
723
  /// Get the low-level type of \p Reg or LLT{} if Reg is not a generic
724
  /// (target independent) virtual register.
725
81.4M
  LLT getType(unsigned Reg) const {
726
81.4M
    if (TargetRegisterInfo::isVirtualRegister(Reg) && 
VRegToType.inBounds(Reg)77.2M
)
727
67.2M
      return VRegToType[Reg];
728
14.1M
    return LLT{};
729
14.1M
  }
730
731
  /// Set the low-level type of \p VReg to \p Ty.
732
  void setType(unsigned VReg, LLT Ty);
733
734
  /// Create and return a new generic virtual register with low-level
735
  /// type \p Ty.
736
  unsigned createGenericVirtualRegister(LLT Ty, StringRef Name = "");
737
738
  /// Remove all types associated to virtual registers (after instruction
739
  /// selection and constraining of all generic virtual registers).
740
  void clearVirtRegTypes();
741
742
  /// Creates a new virtual register that has no register class, register bank
743
  /// or size assigned yet. This is only allowed to be used
744
  /// temporarily while constructing machine instructions. Most operations are
745
  /// undefined on an incomplete register until one of setRegClass(),
746
  /// setRegBank() or setSize() has been called on it.
747
  unsigned createIncompleteVirtualRegister(StringRef Name = "");
748
749
  /// getNumVirtRegs - Return the number of virtual registers created.
750
39.8M
  unsigned getNumVirtRegs() const { return VRegInfo.size(); }
751
752
  /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
753
  void clearVirtRegs();
754
755
  /// setRegAllocationHint - Specify a register allocation hint for the
756
  /// specified virtual register. This is typically used by target, and in case
757
  /// of an earlier hint it will be overwritten.
758
21.3k
  void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) {
759
21.3k
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
760
21.3k
    RegAllocHints[VReg].first  = Type;
761
21.3k
    RegAllocHints[VReg].second.clear();
762
21.3k
    RegAllocHints[VReg].second.push_back(PrefReg);
763
21.3k
  }
764
765
  /// addRegAllocationHint - Add a register allocation hint to the hints
766
  /// vector for VReg.
767
4.63M
  void addRegAllocationHint(unsigned VReg, unsigned PrefReg) {
768
4.63M
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
769
4.63M
    RegAllocHints[VReg].second.push_back(PrefReg);
770
4.63M
  }
771
772
  /// Specify the preferred (target independent) register allocation hint for
773
  /// the specified virtual register.
774
61
  void setSimpleHint(unsigned VReg, unsigned PrefReg) {
775
61
    setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
776
61
  }
777
778
932
  void clearSimpleHint(unsigned VReg) {
779
932
    assert (RegAllocHints[VReg].first == 0 &&
780
932
            "Expected to clear a non-target hint!");
781
932
    RegAllocHints[VReg].second.clear();
782
932
  }
783
784
  /// getRegAllocationHint - Return the register allocation hint for the
785
  /// specified virtual register. If there are many hints, this returns the
786
  /// one with the greatest weight.
787
  std::pair<unsigned, unsigned>
788
37.2M
  getRegAllocationHint(unsigned VReg) const {
789
37.2M
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
790
37.2M
    unsigned BestHint = (RegAllocHints[VReg].second.size() ?
791
26.0M
                         
RegAllocHints[VReg].second[0]11.1M
: 0);
792
37.2M
    return std::pair<unsigned, unsigned>(RegAllocHints[VReg].first, BestHint);
793
37.2M
  }
794
795
  /// getSimpleHint - same as getRegAllocationHint except it will only return
796
  /// a target independent hint.
797
18.1M
  unsigned getSimpleHint(unsigned VReg) const {
798
18.1M
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
799
18.1M
    std::pair<unsigned, unsigned> Hint = getRegAllocationHint(VReg);
800
18.1M
    return Hint.first ? 
053
:
Hint.second18.1M
;
801
18.1M
  }
802
803
  /// getRegAllocationHints - Return a reference to the vector of all
804
  /// register allocation hints for VReg.
805
  const std::pair<unsigned, SmallVector<unsigned, 4>>
806
12.3M
  &getRegAllocationHints(unsigned VReg) const {
807
12.3M
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
808
12.3M
    return RegAllocHints[VReg];
809
12.3M
  }
810
811
  /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
812
  /// specified register as undefined which causes the DBG_VALUE to be
813
  /// deleted during LiveDebugVariables analysis.
814
  void markUsesInDebugValueAsUndef(unsigned Reg) const;
815
816
  /// Return true if the specified register is modified in this function.
817
  /// This checks that no defining machine operands exist for the register or
818
  /// any of its aliases. Definitions found on functions marked noreturn are
819
  /// ignored, to consider them pass 'true' for optional parameter
820
  /// SkipNoReturnDef. The register is also considered modified when it is set
821
  /// in the UsedPhysRegMask.
822
  bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef = false) const;
823
824
  /// Return true if the specified register is modified or read in this
825
  /// function. This checks that no machine operands exist for the register or
826
  /// any of its aliases. The register is also considered used when it is set
827
  /// in the UsedPhysRegMask.
828
  bool isPhysRegUsed(unsigned PhysReg) const;
829
830
  /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
831
  /// This corresponds to the bit mask attached to register mask operands.
832
1.73M
  void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
833
1.73M
    UsedPhysRegMask.setBitsNotInMask(RegMask);
834
1.73M
  }
835
836
20.2k
  const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
837
838
  //===--------------------------------------------------------------------===//
839
  // Reserved Register Info
840
  //===--------------------------------------------------------------------===//
841
  //
842
  // The set of reserved registers must be invariant during register
843
  // allocation.  For example, the target cannot suddenly decide it needs a
844
  // frame pointer when the register allocator has already used the frame
845
  // pointer register for something else.
846
  //
847
  // These methods can be used by target hooks like hasFP() to avoid changing
848
  // the reserved register set during register allocation.
849
850
  /// freezeReservedRegs - Called by the register allocator to freeze the set
851
  /// of reserved registers before allocation begins.
852
  void freezeReservedRegs(const MachineFunction&);
853
854
  /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
855
  /// to ensure the set of reserved registers stays constant.
856
3.49M
  bool reservedRegsFrozen() const {
857
3.49M
    return !ReservedRegs.empty();
858
3.49M
  }
859
860
  /// canReserveReg - Returns true if PhysReg can be used as a reserved
861
  /// register.  Any register can be reserved before freezeReservedRegs() is
862
  /// called.
863
213k
  bool canReserveReg(unsigned PhysReg) const {
864
213k
    return !reservedRegsFrozen() || 
ReservedRegs.test(PhysReg)208k
;
865
213k
  }
866
867
  /// getReservedRegs - Returns a reference to the frozen set of reserved
868
  /// registers. This method should always be preferred to calling
869
  /// TRI::getReservedRegs() when possible.
870
200M
  const BitVector &getReservedRegs() const {
871
200M
    assert(reservedRegsFrozen() &&
872
200M
           "Reserved registers haven't been frozen yet. "
873
200M
           "Use TRI::getReservedRegs().");
874
200M
    return ReservedRegs;
875
200M
  }
876
877
  /// isReserved - Returns true when PhysReg is a reserved register.
878
  ///
879
  /// Reserved registers may belong to an allocatable register class, but the
880
  /// target has explicitly requested that they are not used.
881
189M
  bool isReserved(unsigned PhysReg) const {
882
189M
    return getReservedRegs().test(PhysReg);
883
189M
  }
884
885
  /// Returns true when the given register unit is considered reserved.
886
  ///
887
  /// Register units are considered reserved when for at least one of their
888
  /// root registers, the root register and all super registers are reserved.
889
  /// This currently iterates the register hierarchy and may be slower than
890
  /// expected.
891
  bool isReservedRegUnit(unsigned Unit) const;
892
893
  /// isAllocatable - Returns true when PhysReg belongs to an allocatable
894
  /// register class and it hasn't been reserved.
895
  ///
896
  /// Allocatable registers may show up in the allocation order of some virtual
897
  /// register, so a register allocator needs to track its liveness and
898
  /// availability.
899
42.7M
  bool isAllocatable(unsigned PhysReg) const {
900
42.7M
    return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
901
42.7M
      
!isReserved(PhysReg)36.6M
;
902
42.7M
  }
903
904
  //===--------------------------------------------------------------------===//
905
  // LiveIn Management
906
  //===--------------------------------------------------------------------===//
907
908
  /// addLiveIn - Add the specified register as a live-in.  Note that it
909
  /// is an error to add the same register to the same set more than once.
910
679k
  void addLiveIn(unsigned Reg, unsigned vreg = 0) {
911
679k
    LiveIns.push_back(std::make_pair(Reg, vreg));
912
679k
  }
913
914
  // Iteration support for the live-ins set.  It's kept in sorted order
915
  // by register number.
916
  using livein_iterator =
917
      std::vector<std::pair<unsigned,unsigned>>::const_iterator;
918
3.08M
  livein_iterator livein_begin() const { return LiveIns.begin(); }
919
3.08M
  livein_iterator livein_end()   const { return LiveIns.end(); }
920
3.53k
  bool            livein_empty() const { return LiveIns.empty(); }
921
922
100k
  ArrayRef<std::pair<unsigned, unsigned>> liveins() const {
923
100k
    return LiveIns;
924
100k
  }
925
926
  bool isLiveIn(unsigned Reg) const;
927
928
  /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
929
  /// corresponding live-in physical register.
930
  unsigned getLiveInPhysReg(unsigned VReg) const;
931
932
  /// getLiveInVirtReg - If PReg is a live-in physical register, return the
933
  /// corresponding live-in physical register.
934
  unsigned getLiveInVirtReg(unsigned PReg) const;
935
936
  /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
937
  /// into the given entry block.
938
  void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
939
                        const TargetRegisterInfo &TRI,
940
                        const TargetInstrInfo &TII);
941
942
  /// Returns a mask covering all bits that can appear in lane masks of
943
  /// subregisters of the virtual register @p Reg.
944
  LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const;
945
946
  /// defusechain_iterator - This class provides iterator support for machine
947
  /// operands in the function that use or define a specific register.  If
948
  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
949
  /// returns defs.  If neither are true then you are silly and it always
950
  /// returns end().  If SkipDebug is true it skips uses marked Debug
951
  /// when incrementing.
952
  template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
953
           bool ByOperand, bool ByInstr, bool ByBundle>
954
  class defusechain_iterator
955
    : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
956
    friend class MachineRegisterInfo;
957
958
    MachineOperand *Op = nullptr;
959
960
1.73G
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
961
1.73G
      // If the first node isn't one we're interested in, advance to one that
962
1.73G
      // we are interested in.
963
1.73G
      if (op) {
964
339M
        if ((!ReturnUses && 
op->isUse()70.6M
) ||
965
339M
            
(171M
!ReturnDefs171M
&&
op->isDef()171M
) ||
966
339M
            
(91.5M
SkipDebug91.5M
&&
op->isDebug()91.5M
))
967
170M
          advance();
968
339M
      }
969
1.73G
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
960
564M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
961
564M
      // If the first node isn't one we're interested in, advance to one that
962
564M
      // we are interested in.
963
564M
      if (op) {
964
70.6M
        if ((!ReturnUses && op->isUse()) ||
965
70.6M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
966
70.6M
            
(0
SkipDebug0
&&
op->isDebug()0
))
967
3.14M
          advance();
968
70.6M
      }
969
564M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
960
339M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
961
339M
      // If the first node isn't one we're interested in, advance to one that
962
339M
      // we are interested in.
963
339M
      if (op) {
964
157M
        if ((!ReturnUses && 
op->isUse()0
) ||
965
157M
            (!ReturnDefs && op->isDef()) ||
966
157M
            
(638k
SkipDebug638k
&&
op->isDebug()638k
))
967
157M
          advance();
968
157M
      }
969
339M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
960
31.6M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
961
31.6M
      // If the first node isn't one we're interested in, advance to one that
962
31.6M
      // we are interested in.
963
31.6M
      if (op) {
964
13.5M
        if ((!ReturnUses && 
op->isUse()0
) ||
965
13.5M
            (!ReturnDefs && op->isDef()) ||
966
13.5M
            
(0
SkipDebug0
&&
op->isDebug()0
))
967
10.3M
          advance();
968
13.5M
      }
969
31.6M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
960
118M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
961
118M
      // If the first node isn't one we're interested in, advance to one that
962
118M
      // we are interested in.
963
118M
      if (op) {
964
6.37M
        if ((!ReturnUses && 
op->isUse()0
) ||
965
6.37M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
966
6.37M
            
(0
SkipDebug0
&&
op->isDebug()0
))
967
0
          advance();
968
6.37M
      }
969
118M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
960
680M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
961
680M
      // If the first node isn't one we're interested in, advance to one that
962
680M
      // we are interested in.
963
680M
      if (op) {
964
90.8M
        if ((!ReturnUses && 
op->isUse()0
) ||
965
90.8M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
966
90.8M
            (SkipDebug && op->isDebug()))
967
5
          advance();
968
90.8M
      }
969
680M
    }
970
971
366M
    void advance() {
972
366M
      assert(Op && "Cannot increment end iterator!");
973
366M
      Op = getNextOperandForReg(Op);
974
366M
975
366M
      // All defs come before the uses, so stop def_iterator early.
976
366M
      if (!ReturnUses) {
977
32.8M
        if (Op) {
978
31.0M
          if (Op->isUse())
979
21.5M
            Op = nullptr;
980
31.0M
          else
981
31.0M
            assert(!Op->isDebug() && "Can't have debug defs");
982
31.0M
        }
983
333M
      } else {
984
333M
        // If this is an operand we don't care about, skip it.
985
373M
        while (Op && 
(304M
(304M
!ReturnDefs304M
&&
Op->isDef()238M
) ||
986
304M
                      
(265M
SkipDebug265M
&&
Op->isDebug()235M
)))
987
39.6M
          Op = getNextOperandForReg(Op);
988
333M
      }
989
366M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::advance()
Line
Count
Source
971
32.8M
    void advance() {
972
32.8M
      assert(Op && "Cannot increment end iterator!");
973
32.8M
      Op = getNextOperandForReg(Op);
974
32.8M
975
32.8M
      // All defs come before the uses, so stop def_iterator early.
976
32.8M
      if (!ReturnUses) {
977
32.8M
        if (Op) {
978
31.0M
          if (Op->isUse())
979
21.5M
            Op = nullptr;
980
31.0M
          else
981
31.0M
            assert(!Op->isDebug() && "Can't have debug defs");
982
31.0M
        }
983
32.8M
      } else {
984
0
        // If this is an operand we don't care about, skip it.
985
0
        while (Op && ((!ReturnDefs && Op->isDef()) ||
986
0
                      (SkipDebug && Op->isDebug())))
987
0
          Op = getNextOperandForReg(Op);
988
0
      }
989
32.8M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::advance()
Line
Count
Source
971
195M
    void advance() {
972
195M
      assert(Op && "Cannot increment end iterator!");
973
195M
      Op = getNextOperandForReg(Op);
974
195M
975
195M
      // All defs come before the uses, so stop def_iterator early.
976
195M
      if (!ReturnUses) {
977
0
        if (Op) {
978
0
          if (Op->isUse())
979
0
            Op = nullptr;
980
0
          else
981
0
            assert(!Op->isDebug() && "Can't have debug defs");
982
0
        }
983
195M
      } else {
984
195M
        // If this is an operand we don't care about, skip it.
985
227M
        while (Op && 
(205M
(205M
!ReturnDefs205M
&&
Op->isDef()205M
) ||
986
205M
                      
(172M
SkipDebug172M
&&
Op->isDebug()172M
)))
987
32.5M
          Op = getNextOperandForReg(Op);
988
195M
      }
989
195M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::advance()
Line
Count
Source
971
38.9M
    void advance() {
972
38.9M
      assert(Op && "Cannot increment end iterator!");
973
38.9M
      Op = getNextOperandForReg(Op);
974
38.9M
975
38.9M
      // All defs come before the uses, so stop def_iterator early.
976
38.9M
      if (!ReturnUses) {
977
0
        if (Op) {
978
0
          if (Op->isUse())
979
0
            Op = nullptr;
980
0
          else
981
0
            assert(!Op->isDebug() && "Can't have debug defs");
982
0
        }
983
38.9M
      } else {
984
38.9M
        // If this is an operand we don't care about, skip it.
985
45.9M
        while (Op && 
(32.8M
(32.8M
!ReturnDefs32.8M
&&
Op->isDef()32.8M
) ||
986
32.8M
                      
(25.7M
SkipDebug25.7M
&&
Op->isDebug()0
)))
987
7.05M
          Op = getNextOperandForReg(Op);
988
38.9M
      }
989
38.9M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::advance()
Line
Count
Source
971
5.71M
    void advance() {
972
5.71M
      assert(Op && "Cannot increment end iterator!");
973
5.71M
      Op = getNextOperandForReg(Op);
974
5.71M
975
5.71M
      // All defs come before the uses, so stop def_iterator early.
976
5.71M
      if (!ReturnUses) {
977
0
        if (Op) {
978
0
          if (Op->isUse())
979
0
            Op = nullptr;
980
0
          else
981
0
            assert(!Op->isDebug() && "Can't have debug defs");
982
0
        }
983
5.71M
      } else {
984
5.71M
        // If this is an operand we don't care about, skip it.
985
5.71M
        while (Op && 
(4.00M
(4.00M
!ReturnDefs4.00M
&&
Op->isDef()0
) ||
986
4.00M
                      (SkipDebug && 
Op->isDebug()0
)))
987
0
          Op = getNextOperandForReg(Op);
988
5.71M
      }
989
5.71M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::advance()
Line
Count
Source
971
93.9M
    void advance() {
972
93.9M
      assert(Op && "Cannot increment end iterator!");
973
93.9M
      Op = getNextOperandForReg(Op);
974
93.9M
975
93.9M
      // All defs come before the uses, so stop def_iterator early.
976
93.9M
      if (!ReturnUses) {
977
0
        if (Op) {
978
0
          if (Op->isUse())
979
0
            Op = nullptr;
980
0
          else
981
0
            assert(!Op->isDebug() && "Can't have debug defs");
982
0
        }
983
93.9M
      } else {
984
93.9M
        // If this is an operand we don't care about, skip it.
985
93.9M
        while (Op && 
(62.8M
(62.8M
!ReturnDefs62.8M
&&
Op->isDef()0
) ||
986
62.8M
                      (SkipDebug && Op->isDebug())))
987
1.49k
          Op = getNextOperandForReg(Op);
988
93.9M
      }
989
93.9M
    }
990
991
  public:
992
    using reference = std::iterator<std::forward_iterator_tag,
993
                                    MachineInstr, ptrdiff_t>::reference;
994
    using pointer = std::iterator<std::forward_iterator_tag,
995
                                  MachineInstr, ptrdiff_t>::pointer;
996
997
106k
    defusechain_iterator() = default;
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::defusechain_iterator()
Line
Count
Source
997
106k
    defusechain_iterator() = default;
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::defusechain_iterator()
Line
Count
Source
997
263
    defusechain_iterator() = default;
998
999
1.02G
    bool operator==(const defusechain_iterator &x) const {
1000
1.02G
      return Op == x.Op;
1001
1.02G
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false> const&) const
Line
Count
Source
999
288M
    bool operator==(const defusechain_iterator &x) const {
1000
288M
      return Op == x.Op;
1001
288M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false> const&) const
Line
Count
Source
999
196M
    bool operator==(const defusechain_iterator &x) const {
1000
196M
      return Op == x.Op;
1001
196M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false> const&) const
Line
Count
Source
999
44.1M
    bool operator==(const defusechain_iterator &x) const {
1000
44.1M
      return Op == x.Op;
1001
44.1M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false> const&) const
Line
Count
Source
999
64.7M
    bool operator==(const defusechain_iterator &x) const {
1000
64.7M
      return Op == x.Op;
1001
64.7M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false> const&) const
Line
Count
Source
999
434M
    bool operator==(const defusechain_iterator &x) const {
1000
434M
      return Op == x.Op;
1001
434M
    }
1002
410M
    bool operator!=(const defusechain_iterator &x) const {
1003
410M
      return !operator==(x);
1004
410M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false> const&) const
Line
Count
Source
1002
7.44M
    bool operator!=(const defusechain_iterator &x) const {
1003
7.44M
      return !operator==(x);
1004
7.44M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false> const&) const
Line
Count
Source
1002
40.5M
    bool operator!=(const defusechain_iterator &x) const {
1003
40.5M
      return !operator==(x);
1004
40.5M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false> const&) const
Line
Count
Source
1002
180M
    bool operator!=(const defusechain_iterator &x) const {
1003
180M
      return !operator==(x);
1004
180M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false> const&) const
Line
Count
Source
1002
125M
    bool operator!=(const defusechain_iterator &x) const {
1003
125M
      return !operator==(x);
1004
125M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false> const&) const
Line
Count
Source
1002
56.5M
    bool operator!=(const defusechain_iterator &x) const {
1003
56.5M
      return !operator==(x);
1004
56.5M
    }
1005
1006
    /// atEnd - return true if this iterator is equal to reg_end() on the value.
1007
    bool atEnd() const { return Op == nullptr; }
1008
1009
    // Iterator traversal: forward iteration only
1010
196M
    defusechain_iterator &operator++() {          // Preincrement
1011
196M
      assert(Op && "Cannot increment end iterator!");
1012
196M
      if (ByOperand)
1013
196M
        advance();
1014
0
      else if (ByInstr) {
1015
0
        MachineInstr *P = Op->getParent();
1016
0
        do {
1017
0
          advance();
1018
0
        } while (Op && Op->getParent() == P);
1019
0
      } else if (ByBundle) {
1020
0
        MachineBasicBlock::instr_iterator P =
1021
0
            getBundleStart(Op->getParent()->getIterator());
1022
0
        do {
1023
0
          advance();
1024
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1025
0
      }
1026
196M
1027
196M
      return *this;
1028
196M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator++()
Line
Count
Source
1010
29.7M
    defusechain_iterator &operator++() {          // Preincrement
1011
29.7M
      assert(Op && "Cannot increment end iterator!");
1012
29.7M
      if (ByOperand)
1013
29.7M
        advance();
1014
0
      else if (ByInstr) {
1015
0
        MachineInstr *P = Op->getParent();
1016
0
        do {
1017
0
          advance();
1018
0
        } while (Op && Op->getParent() == P);
1019
0
      } else if (ByBundle) {
1020
0
        MachineBasicBlock::instr_iterator P =
1021
0
            getBundleStart(Op->getParent()->getIterator());
1022
0
        do {
1023
0
          advance();
1024
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1025
0
      }
1026
29.7M
1027
29.7M
      return *this;
1028
29.7M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator++()
Line
Count
Source
1010
5.71M
    defusechain_iterator &operator++() {          // Preincrement
1011
5.71M
      assert(Op && "Cannot increment end iterator!");
1012
5.71M
      if (ByOperand)
1013
5.71M
        advance();
1014
0
      else if (ByInstr) {
1015
0
        MachineInstr *P = Op->getParent();
1016
0
        do {
1017
0
          advance();
1018
0
        } while (Op && Op->getParent() == P);
1019
0
      } else if (ByBundle) {
1020
0
        MachineBasicBlock::instr_iterator P =
1021
0
            getBundleStart(Op->getParent()->getIterator());
1022
0
        do {
1023
0
          advance();
1024
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1025
0
      }
1026
5.71M
1027
5.71M
      return *this;
1028
5.71M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator++()
Line
Count
Source
1010
28.5M
    defusechain_iterator &operator++() {          // Preincrement
1011
28.5M
      assert(Op && "Cannot increment end iterator!");
1012
28.5M
      if (ByOperand)
1013
28.5M
        advance();
1014
0
      else if (ByInstr) {
1015
0
        MachineInstr *P = Op->getParent();
1016
0
        do {
1017
0
          advance();
1018
0
        } while (Op && Op->getParent() == P);
1019
0
      } else if (ByBundle) {
1020
0
        MachineBasicBlock::instr_iterator P =
1021
0
            getBundleStart(Op->getParent()->getIterator());
1022
0
        do {
1023
0
          advance();
1024
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1025
0
      }
1026
28.5M
1027
28.5M
      return *this;
1028
28.5M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator++()
Line
Count
Source
1010
93.9M
    defusechain_iterator &operator++() {          // Preincrement
1011
93.9M
      assert(Op && "Cannot increment end iterator!");
1012
93.9M
      if (ByOperand)
1013
93.9M
        advance();
1014
0
      else if (ByInstr) {
1015
0
        MachineInstr *P = Op->getParent();
1016
0
        do {
1017
0
          advance();
1018
0
        } while (Op && Op->getParent() == P);
1019
0
      } else if (ByBundle) {
1020
0
        MachineBasicBlock::instr_iterator P =
1021
0
            getBundleStart(Op->getParent()->getIterator());
1022
0
        do {
1023
0
          advance();
1024
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1025
0
      }
1026
93.9M
1027
93.9M
      return *this;
1028
93.9M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator++()
Line
Count
Source
1010
38.0M
    defusechain_iterator &operator++() {          // Preincrement
1011
38.0M
      assert(Op && "Cannot increment end iterator!");
1012
38.0M
      if (ByOperand)
1013
38.0M
        advance();
1014
0
      else if (ByInstr) {
1015
0
        MachineInstr *P = Op->getParent();
1016
0
        do {
1017
0
          advance();
1018
0
        } while (Op && Op->getParent() == P);
1019
0
      } else if (ByBundle) {
1020
0
        MachineBasicBlock::instr_iterator P =
1021
0
            getBundleStart(Op->getParent()->getIterator());
1022
0
        do {
1023
0
          advance();
1024
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1025
0
      }
1026
38.0M
1027
38.0M
      return *this;
1028
38.0M
    }
1029
118k
    defusechain_iterator operator++(int) {        // Postincrement
1030
118k
      defusechain_iterator tmp = *this; ++*this; return tmp;
1031
118k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator++(int)
Line
Count
Source
1029
97.6k
    defusechain_iterator operator++(int) {        // Postincrement
1030
97.6k
      defusechain_iterator tmp = *this; ++*this; return tmp;
1031
97.6k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator++(int)
Line
Count
Source
1029
19.3k
    defusechain_iterator operator++(int) {        // Postincrement
1030
19.3k
      defusechain_iterator tmp = *this; ++*this; return tmp;
1031
19.3k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator++(int)
Line
Count
Source
1029
700
    defusechain_iterator operator++(int) {        // Postincrement
1030
700
      defusechain_iterator tmp = *this; ++*this; return tmp;
1031
700
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator++(int)
Line
Count
Source
1029
340
    defusechain_iterator operator++(int) {        // Postincrement
1030
340
      defusechain_iterator tmp = *this; ++*this; return tmp;
1031
340
    }
1032
1033
    /// getOperandNo - Return the operand # of this MachineOperand in its
1034
    /// MachineInstr.
1035
17.9M
    unsigned getOperandNo() const {
1036
17.9M
      assert(Op && "Cannot dereference end iterator!");
1037
17.9M
      return Op - &Op->getParent()->getOperand(0);
1038
17.9M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::getOperandNo() const
Line
Count
Source
1035
569k
    unsigned getOperandNo() const {
1036
569k
      assert(Op && "Cannot dereference end iterator!");
1037
569k
      return Op - &Op->getParent()->getOperand(0);
1038
569k
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::getOperandNo() const
Line
Count
Source
1035
17.3M
    unsigned getOperandNo() const {
1036
17.3M
      assert(Op && "Cannot dereference end iterator!");
1037
17.3M
      return Op - &Op->getParent()->getOperand(0);
1038
17.3M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::getOperandNo() const
Line
Count
Source
1035
1.81k
    unsigned getOperandNo() const {
1036
1.81k
      assert(Op && "Cannot dereference end iterator!");
1037
1.81k
      return Op - &Op->getParent()->getOperand(0);
1038
1.81k
    }
1039
1040
    // Retrieve a reference to the current operand.
1041
188M
    MachineOperand &operator*() const {
1042
188M
      assert(Op && "Cannot dereference end iterator!");
1043
188M
      return *Op;
1044
188M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator*() const
Line
Count
Source
1041
5.62M
    MachineOperand &operator*() const {
1042
5.62M
      assert(Op && "Cannot dereference end iterator!");
1043
5.62M
      return *Op;
1044
5.62M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator*() const
Line
Count
Source
1041
27.2M
    MachineOperand &operator*() const {
1042
27.2M
      assert(Op && "Cannot dereference end iterator!");
1043
27.2M
      return *Op;
1044
27.2M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator*() const
Line
Count
Source
1041
12.0M
    MachineOperand &operator*() const {
1042
12.0M
      assert(Op && "Cannot dereference end iterator!");
1043
12.0M
      return *Op;
1044
12.0M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator*() const
Line
Count
Source
1041
94.0M
    MachineOperand &operator*() const {
1042
94.0M
      assert(Op && "Cannot dereference end iterator!");
1043
94.0M
      return *Op;
1044
94.0M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator*() const
Line
Count
Source
1041
49.5M
    MachineOperand &operator*() const {
1042
49.5M
      assert(Op && "Cannot dereference end iterator!");
1043
49.5M
      return *Op;
1044
49.5M
    }
1045
1046
14.9M
    MachineOperand *operator->() const {
1047
14.9M
      assert(Op && "Cannot dereference end iterator!");
1048
14.9M
      return Op;
1049
14.9M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator->() const
Line
Count
Source
1046
1.02M
    MachineOperand *operator->() const {
1047
1.02M
      assert(Op && "Cannot dereference end iterator!");
1048
1.02M
      return Op;
1049
1.02M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator->() const
Line
Count
Source
1046
2.46k
    MachineOperand *operator->() const {
1047
2.46k
      assert(Op && "Cannot dereference end iterator!");
1048
2.46k
      return Op;
1049
2.46k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator->() const
Line
Count
Source
1046
492k
    MachineOperand *operator->() const {
1047
492k
      assert(Op && "Cannot dereference end iterator!");
1048
492k
      return Op;
1049
492k
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator->() const
Line
Count
Source
1046
13.4M
    MachineOperand *operator->() const {
1047
13.4M
      assert(Op && "Cannot dereference end iterator!");
1048
13.4M
      return Op;
1049
13.4M
    }
1050
  };
1051
1052
  /// defusechain_iterator - This class provides iterator support for machine
1053
  /// operands in the function that use or define a specific register.  If
1054
  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1055
  /// returns defs.  If neither are true then you are silly and it always
1056
  /// returns end().  If SkipDebug is true it skips uses marked Debug
1057
  /// when incrementing.
1058
  template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
1059
           bool ByOperand, bool ByInstr, bool ByBundle>
1060
  class defusechain_instr_iterator
1061
    : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
1062
    friend class MachineRegisterInfo;
1063
1064
    MachineOperand *Op = nullptr;
1065
1066
130M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1067
130M
      // If the first node isn't one we're interested in, advance to one that
1068
130M
      // we are interested in.
1069
130M
      if (op) {
1070
96.8M
        if ((!ReturnUses && 
op->isUse()67.4M
) ||
1071
96.8M
            
(13.5M
!ReturnDefs13.5M
&&
op->isDef()13.5M
) ||
1072
96.8M
            
(1.04M
SkipDebug1.04M
&&
op->isDebug()1.04M
))
1073
13.5M
          advance();
1074
96.8M
      }
1075
130M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1066
73.9M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1067
73.9M
      // If the first node isn't one we're interested in, advance to one that
1068
73.9M
      // we are interested in.
1069
73.9M
      if (op) {
1070
67.4M
        if ((!ReturnUses && op->isUse()) ||
1071
67.4M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
1072
67.4M
            
(0
SkipDebug0
&&
op->isDebug()0
))
1073
17.5k
          advance();
1074
67.4M
      }
1075
73.9M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1066
9.72M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1067
9.72M
      // If the first node isn't one we're interested in, advance to one that
1068
9.72M
      // we are interested in.
1069
9.72M
      if (op) {
1070
6.27M
        if ((!ReturnUses && 
op->isUse()0
) ||
1071
6.27M
            (!ReturnDefs && op->isDef()) ||
1072
6.27M
            
(0
SkipDebug0
&&
op->isDebug()0
))
1073
6.27M
          advance();
1074
6.27M
      }
1075
9.72M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1066
14.4M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1067
14.4M
      // If the first node isn't one we're interested in, advance to one that
1068
14.4M
      // we are interested in.
1069
14.4M
      if (op) {
1070
7.23M
        if ((!ReturnUses && 
op->isUse()0
) ||
1071
7.23M
            (!ReturnDefs && op->isDef()) ||
1072
7.23M
            
(0
SkipDebug0
&&
op->isDebug()0
))
1073
7.23M
          advance();
1074
7.23M
      }
1075
14.4M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1066
29.6M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1067
29.6M
      // If the first node isn't one we're interested in, advance to one that
1068
29.6M
      // we are interested in.
1069
29.6M
      if (op) {
1070
14.5M
        if ((!ReturnUses && 
op->isUse()0
) ||
1071
14.5M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
1072
14.5M
            
(0
SkipDebug0
&&
op->isDebug()0
))
1073
0
          advance();
1074
14.5M
      }
1075
29.6M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1066
2.09M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1067
2.09M
      // If the first node isn't one we're interested in, advance to one that
1068
2.09M
      // we are interested in.
1069
2.09M
      if (op) {
1070
1.04M
        if ((!ReturnUses && 
op->isUse()0
) ||
1071
1.04M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
1072
1.04M
            (SkipDebug && op->isDebug()))
1073
0
          advance();
1074
1.04M
      }
1075
2.09M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1066
632k
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1067
632k
      // If the first node isn't one we're interested in, advance to one that
1068
632k
      // we are interested in.
1069
632k
      if (op) {
1070
316k
        if ((!ReturnUses && 
op->isUse()0
) ||
1071
316k
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
1072
316k
            
(0
SkipDebug0
&&
op->isDebug()0
))
1073
0
          advance();
1074
316k
      }
1075
632k
    }
1076
1077
75.0M
    void advance() {
1078
75.0M
      assert(Op && "Cannot increment end iterator!");
1079
75.0M
      Op = getNextOperandForReg(Op);
1080
75.0M
1081
75.0M
      // All defs come before the uses, so stop def_iterator early.
1082
75.0M
      if (!ReturnUses) {
1083
4.04M
        if (Op) {
1084
4.02M
          if (Op->isUse())
1085
3.91M
            Op = nullptr;
1086
4.02M
          else
1087
4.02M
            assert(!Op->isDebug() && "Can't have debug defs");
1088
4.02M
        }
1089
70.9M
      } else {
1090
70.9M
        // If this is an operand we don't care about, skip it.
1091
73.3M
        while (Op && 
(48.4M
(48.4M
!ReturnDefs48.4M
&&
Op->isDef()18.7M
) ||
1092
48.4M
                      
(46.0M
SkipDebug46.0M
&&
Op->isDebug()12.7M
)))
1093
2.36M
          Op = getNextOperandForReg(Op);
1094
70.9M
      }
1095
75.0M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::advance()
Line
Count
Source
1077
4.04M
    void advance() {
1078
4.04M
      assert(Op && "Cannot increment end iterator!");
1079
4.04M
      Op = getNextOperandForReg(Op);
1080
4.04M
1081
4.04M
      // All defs come before the uses, so stop def_iterator early.
1082
4.04M
      if (!ReturnUses) {
1083
4.04M
        if (Op) {
1084
4.02M
          if (Op->isUse())
1085
3.91M
            Op = nullptr;
1086
4.02M
          else
1087
4.02M
            assert(!Op->isDebug() && "Can't have debug defs");
1088
4.02M
        }
1089
4.04M
      } else {
1090
0
        // If this is an operand we don't care about, skip it.
1091
0
        while (Op && ((!ReturnDefs && Op->isDef()) ||
1092
0
                      (SkipDebug && Op->isDebug())))
1093
0
          Op = getNextOperandForReg(Op);
1094
0
      }
1095
4.04M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::advance()
Line
Count
Source
1077
10.6M
    void advance() {
1078
10.6M
      assert(Op && "Cannot increment end iterator!");
1079
10.6M
      Op = getNextOperandForReg(Op);
1080
10.6M
1081
10.6M
      // All defs come before the uses, so stop def_iterator early.
1082
10.6M
      if (!ReturnUses) {
1083
0
        if (Op) {
1084
0
          if (Op->isUse())
1085
0
            Op = nullptr;
1086
0
          else
1087
0
            assert(!Op->isDebug() && "Can't have debug defs");
1088
0
        }
1089
10.6M
      } else {
1090
10.6M
        // If this is an operand we don't care about, skip it.
1091
11.8M
        while (Op && 
(9.93M
(9.93M
!ReturnDefs9.93M
&&
Op->isDef()9.93M
) ||
1092
9.93M
                      
(8.70M
SkipDebug8.70M
&&
Op->isDebug()8.70M
)))
1093
1.23M
          Op = getNextOperandForReg(Op);
1094
10.6M
      }
1095
10.6M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::advance()
Line
Count
Source
1077
14.8M
    void advance() {
1078
14.8M
      assert(Op && "Cannot increment end iterator!");
1079
14.8M
      Op = getNextOperandForReg(Op);
1080
14.8M
1081
14.8M
      // All defs come before the uses, so stop def_iterator early.
1082
14.8M
      if (!ReturnUses) {
1083
0
        if (Op) {
1084
0
          if (Op->isUse())
1085
0
            Op = nullptr;
1086
0
          else
1087
0
            assert(!Op->isDebug() && "Can't have debug defs");
1088
0
        }
1089
14.8M
      } else {
1090
14.8M
        // If this is an operand we don't care about, skip it.
1091
15.9M
        while (Op && 
(8.81M
(8.81M
!ReturnDefs8.81M
&&
Op->isDef()8.81M
) ||
1092
8.81M
                      
(7.67M
SkipDebug7.67M
&&
Op->isDebug()0
)))
1093
1.13M
          Op = getNextOperandForReg(Op);
1094
14.8M
      }
1095
14.8M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::advance()
Line
Count
Source
1077
39.5M
    void advance() {
1078
39.5M
      assert(Op && "Cannot increment end iterator!");
1079
39.5M
      Op = getNextOperandForReg(Op);
1080
39.5M
1081
39.5M
      // All defs come before the uses, so stop def_iterator early.
1082
39.5M
      if (!ReturnUses) {
1083
0
        if (Op) {
1084
0
          if (Op->isUse())
1085
0
            Op = nullptr;
1086
0
          else
1087
0
            assert(!Op->isDebug() && "Can't have debug defs");
1088
0
        }
1089
39.5M
      } else {
1090
39.5M
        // If this is an operand we don't care about, skip it.
1091
39.5M
        while (Op && 
(25.0M
(25.0M
!ReturnDefs25.0M
&&
Op->isDef()0
) ||
1092
25.0M
                      (SkipDebug && 
Op->isDebug()0
)))
1093
0
          Op = getNextOperandForReg(Op);
1094
39.5M
      }
1095
39.5M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::advance()
Line
Count
Source
1077
5.08M
    void advance() {
1078
5.08M
      assert(Op && "Cannot increment end iterator!");
1079
5.08M
      Op = getNextOperandForReg(Op);
1080
5.08M
1081
5.08M
      // All defs come before the uses, so stop def_iterator early.
1082
5.08M
      if (!ReturnUses) {
1083
0
        if (Op) {
1084
0
          if (Op->isUse())
1085
0
            Op = nullptr;
1086
0
          else
1087
0
            assert(!Op->isDebug() && "Can't have debug defs");
1088
0
        }
1089
5.08M
      } else {
1090
5.08M
        // If this is an operand we don't care about, skip it.
1091
5.08M
        while (Op && 
(4.08M
(4.08M
!ReturnDefs4.08M
&&
Op->isDef()0
) ||
1092
4.08M
                      (SkipDebug && Op->isDebug())))
1093
0
          Op = getNextOperandForReg(Op);
1094
5.08M
      }
1095
5.08M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::advance()
Line
Count
Source
1077
858k
    void advance() {
1078
858k
      assert(Op && "Cannot increment end iterator!");
1079
858k
      Op = getNextOperandForReg(Op);
1080
858k
1081
858k
      // All defs come before the uses, so stop def_iterator early.
1082
858k
      if (!ReturnUses) {
1083
0
        if (Op) {
1084
0
          if (Op->isUse())
1085
0
            Op = nullptr;
1086
0
          else
1087
0
            assert(!Op->isDebug() && "Can't have debug defs");
1088
0
        }
1089
858k
      } else {
1090
858k
        // If this is an operand we don't care about, skip it.
1091
858k
        while (Op && 
(542k
(542k
!ReturnDefs542k
&&
Op->isDef()0
) ||
1092
542k
                      (SkipDebug && 
Op->isDebug()0
)))
1093
0
          Op = getNextOperandForReg(Op);
1094
858k
      }
1095
858k
    }
1096
1097
  public:
1098
    using reference = std::iterator<std::forward_iterator_tag,
1099
                                    MachineInstr, ptrdiff_t>::reference;
1100
    using pointer = std::iterator<std::forward_iterator_tag,
1101
                                  MachineInstr, ptrdiff_t>::pointer;
1102
1103
3.26M
    defusechain_instr_iterator() = default;
1104
1105
90.3M
    bool operator==(const defusechain_instr_iterator &x) const {
1106
90.3M
      return Op == x.Op;
1107
90.3M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false> const&) const
Line
Count
Source
1105
7.73M
    bool operator==(const defusechain_instr_iterator &x) const {
1106
7.73M
      return Op == x.Op;
1107
7.73M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false> const&) const
Line
Count
Source
1105
14.7M
    bool operator==(const defusechain_instr_iterator &x) const {
1106
14.7M
      return Op == x.Op;
1107
14.7M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false> const&) const
Line
Count
Source
1105
6.84M
    bool operator==(const defusechain_instr_iterator &x) const {
1106
6.84M
      return Op == x.Op;
1107
6.84M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false> const&) const
Line
Count
Source
1105
53.8M
    bool operator==(const defusechain_instr_iterator &x) const {
1106
53.8M
      return Op == x.Op;
1107
53.8M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false> const&) const
Line
Count
Source
1105
6.02M
    bool operator==(const defusechain_instr_iterator &x) const {
1106
6.02M
      return Op == x.Op;
1107
6.02M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true> const&) const
Line
Count
Source
1105
1.17M
    bool operator==(const defusechain_instr_iterator &x) const {
1106
1.17M
      return Op == x.Op;
1107
1.17M
    }
1108
90.3M
    bool operator!=(const defusechain_instr_iterator &x) const {
1109
90.3M
      return !operator==(x);
1110
90.3M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false> const&) const
Line
Count
Source
1108
7.73M
    bool operator!=(const defusechain_instr_iterator &x) const {
1109
7.73M
      return !operator==(x);
1110
7.73M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false> const&) const
Line
Count
Source
1108
14.7M
    bool operator!=(const defusechain_instr_iterator &x) const {
1109
14.7M
      return !operator==(x);
1110
14.7M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false> const&) const
Line
Count
Source
1108
6.84M
    bool operator!=(const defusechain_instr_iterator &x) const {
1109
6.84M
      return !operator==(x);
1110
6.84M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false> const&) const
Line
Count
Source
1108
53.8M
    bool operator!=(const defusechain_instr_iterator &x) const {
1109
53.8M
      return !operator==(x);
1110
53.8M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false> const&) const
Line
Count
Source
1108
6.02M
    bool operator!=(const defusechain_instr_iterator &x) const {
1109
6.02M
      return !operator==(x);
1110
6.02M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true> const&) const
Line
Count
Source
1108
1.17M
    bool operator!=(const defusechain_instr_iterator &x) const {
1109
1.17M
      return !operator==(x);
1110
1.17M
    }
1111
1112
    /// atEnd - return true if this iterator is equal to reg_end() on the value.
1113
56.5M
    bool atEnd() const { return Op == nullptr; }
1114
1115
    // Iterator traversal: forward iteration only
1116
60.7M
    defusechain_instr_iterator &operator++() {          // Preincrement
1117
60.7M
      assert(Op && "Cannot increment end iterator!");
1118
60.7M
      if (ByOperand)
1119
0
        advance();
1120
60.7M
      else if (ByInstr) {
1121
59.9M
        MachineInstr *P = Op->getParent();
1122
60.6M
        do {
1123
60.6M
          advance();
1124
60.6M
        } while (Op && 
Op->getParent() == P34.1M
);
1125
59.9M
      } else 
if (854k
ByBundle854k
) {
1126
854k
        MachineBasicBlock::instr_iterator P =
1127
854k
            getBundleStart(Op->getParent()->getIterator());
1128
858k
        do {
1129
858k
          advance();
1130
858k
        } while (Op && 
getBundleStart(Op->getParent()->getIterator()) == P542k
);
1131
854k
      }
1132
60.7M
1133
60.7M
      return *this;
1134
60.7M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator++()
Line
Count
Source
1116
4.28M
    defusechain_instr_iterator &operator++() {          // Preincrement
1117
4.28M
      assert(Op && "Cannot increment end iterator!");
1118
4.28M
      if (ByOperand)
1119
0
        advance();
1120
4.28M
      else if (ByInstr) {
1121
4.28M
        MachineInstr *P = Op->getParent();
1122
4.35M
        do {
1123
4.35M
          advance();
1124
4.35M
        } while (Op && 
Op->getParent() == P2.45M
);
1125
4.28M
      } else 
if (0
ByBundle0
) {
1126
0
        MachineBasicBlock::instr_iterator P =
1127
0
            getBundleStart(Op->getParent()->getIterator());
1128
0
        do {
1129
0
          advance();
1130
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1131
0
      }
1132
4.28M
1133
4.28M
      return *this;
1134
4.28M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator++()
Line
Count
Source
1116
7.53M
    defusechain_instr_iterator &operator++() {          // Preincrement
1117
7.53M
      assert(Op && "Cannot increment end iterator!");
1118
7.53M
      if (ByOperand)
1119
0
        advance();
1120
7.53M
      else if (ByInstr) {
1121
7.53M
        MachineInstr *P = Op->getParent();
1122
7.57M
        do {
1123
7.57M
          advance();
1124
7.57M
        } while (Op && 
Op->getParent() == P2.45M
);
1125
7.53M
      } else 
if (0
ByBundle0
) {
1126
0
        MachineBasicBlock::instr_iterator P =
1127
0
            getBundleStart(Op->getParent()->getIterator());
1128
0
        do {
1129
0
          advance();
1130
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1131
0
      }
1132
7.53M
1133
7.53M
      return *this;
1134
7.53M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator++()
Line
Count
Source
1116
4.02M
    defusechain_instr_iterator &operator++() {          // Preincrement
1117
4.02M
      assert(Op && "Cannot increment end iterator!");
1118
4.02M
      if (ByOperand)
1119
0
        advance();
1120
4.02M
      else if (ByInstr) {
1121
4.02M
        MachineInstr *P = Op->getParent();
1122
4.02M
        do {
1123
4.02M
          advance();
1124
4.02M
        } while (Op && 
Op->getParent() == P117k
);
1125
4.02M
      } else 
if (0
ByBundle0
) {
1126
0
        MachineBasicBlock::instr_iterator P =
1127
0
            getBundleStart(Op->getParent()->getIterator());
1128
0
        do {
1129
0
          advance();
1130
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1131
0
      }
1132
4.02M
1133
4.02M
      return *this;
1134
4.02M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator++()
Line
Count
Source
1116
39.0M
    defusechain_instr_iterator &operator++() {          // Preincrement
1117
39.0M
      assert(Op && "Cannot increment end iterator!");
1118
39.0M
      if (ByOperand)
1119
0
        advance();
1120
39.0M
      else if (ByInstr) {
1121
39.0M
        MachineInstr *P = Op->getParent();
1122
39.5M
        do {
1123
39.5M
          advance();
1124
39.5M
        } while (Op && 
Op->getParent() == P25.0M
);
1125
39.0M
      } else 
if (0
ByBundle0
) {
1126
0
        MachineBasicBlock::instr_iterator P =
1127
0
            getBundleStart(Op->getParent()->getIterator());
1128
0
        do {
1129
0
          advance();
1130
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1131
0
      }
1132
39.0M
1133
39.0M
      return *this;
1134
39.0M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator++()
Line
Count
Source
1116
5.04M
    defusechain_instr_iterator &operator++() {          // Preincrement
1117
5.04M
      assert(Op && "Cannot increment end iterator!");
1118
5.04M
      if (ByOperand)
1119
0
        advance();
1120
5.04M
      else if (ByInstr) {
1121
5.04M
        MachineInstr *P = Op->getParent();
1122
5.08M
        do {
1123
5.08M
          advance();
1124
5.08M
        } while (Op && 
Op->getParent() == P4.08M
);
1125
5.04M
      } else 
if (0
ByBundle0
) {
1126
0
        MachineBasicBlock::instr_iterator P =
1127
0
            getBundleStart(Op->getParent()->getIterator());
1128
0
        do {
1129
0
          advance();
1130
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1131
0
      }
1132
5.04M
1133
5.04M
      return *this;
1134
5.04M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator++()
Line
Count
Source
1116
854k
    defusechain_instr_iterator &operator++() {          // Preincrement
1117
854k
      assert(Op && "Cannot increment end iterator!");
1118
854k
      if (ByOperand)
1119
0
        advance();
1120
854k
      else if (ByInstr) {
1121
0
        MachineInstr *P = Op->getParent();
1122
0
        do {
1123
0
          advance();
1124
0
        } while (Op && Op->getParent() == P);
1125
854k
      } else if (ByBundle) {
1126
854k
        MachineBasicBlock::instr_iterator P =
1127
854k
            getBundleStart(Op->getParent()->getIterator());
1128
858k
        do {
1129
858k
          advance();
1130
858k
        } while (Op && 
getBundleStart(Op->getParent()->getIterator()) == P542k
);
1131
854k
      }
1132
854k
1133
854k
      return *this;
1134
854k
    }
1135
37.8M
    defusechain_instr_iterator operator++(int) {        // Postincrement
1136
37.8M
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1137
37.8M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator++(int)
Line
Count
Source
1135
36.2M
    defusechain_instr_iterator operator++(int) {        // Postincrement
1136
36.2M
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1137
36.2M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator++(int)
Line
Count
Source
1135
178k
    defusechain_instr_iterator operator++(int) {        // Postincrement
1136
178k
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1137
178k
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator++(int)
Line
Count
Source
1135
854k
    defusechain_instr_iterator operator++(int) {        // Postincrement
1136
854k
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1137
854k
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator++(int)
Line
Count
Source
1135
596k
    defusechain_instr_iterator operator++(int) {        // Postincrement
1136
596k
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1137
596k
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator++(int)
Line
Count
Source
1135
220
    defusechain_instr_iterator operator++(int) {        // Postincrement
1136
220
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1137
220
    }
1138
1139
    // Retrieve a reference to the current operand.
1140
128M
    MachineInstr &operator*() const {
1141
128M
      assert(Op && "Cannot dereference end iterator!");
1142
128M
      if (ByBundle)
1143
854k
        return *getBundleStart(Op->getParent()->getIterator());
1144
127M
      return *Op->getParent();
1145
127M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator*() const
Line
Count
Source
1140
67.5M
    MachineInstr &operator*() const {
1141
67.5M
      assert(Op && "Cannot dereference end iterator!");
1142
67.5M
      if (ByBundle)
1143
0
        return *getBundleStart(Op->getParent()->getIterator());
1144
67.5M
      return *Op->getParent();
1145
67.5M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator*() const
Line
Count
Source
1140
8.63M
    MachineInstr &operator*() const {
1141
8.63M
      assert(Op && "Cannot dereference end iterator!");
1142
8.63M
      if (ByBundle)
1143
0
        return *getBundleStart(Op->getParent()->getIterator());
1144
8.63M
      return *Op->getParent();
1145
8.63M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator*() const
Line
Count
Source
1140
7.64M
    MachineInstr &operator*() const {
1141
7.64M
      assert(Op && "Cannot dereference end iterator!");
1142
7.64M
      if (ByBundle)
1143
0
        return *getBundleStart(Op->getParent()->getIterator());
1144
7.64M
      return *Op->getParent();
1145
7.64M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator*() const
Line
Count
Source
1140
39.0M
    MachineInstr &operator*() const {
1141
39.0M
      assert(Op && "Cannot dereference end iterator!");
1142
39.0M
      if (ByBundle)
1143
0
        return *getBundleStart(Op->getParent()->getIterator());
1144
39.0M
      return *Op->getParent();
1145
39.0M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator*() const
Line
Count
Source
1140
5.04M
    MachineInstr &operator*() const {
1141
5.04M
      assert(Op && "Cannot dereference end iterator!");
1142
5.04M
      if (ByBundle)
1143
0
        return *getBundleStart(Op->getParent()->getIterator());
1144
5.04M
      return *Op->getParent();
1145
5.04M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator*() const
Line
Count
Source
1140
854k
    MachineInstr &operator*() const {
1141
854k
      assert(Op && "Cannot dereference end iterator!");
1142
854k
      if (ByBundle)
1143
854k
        return *getBundleStart(Op->getParent()->getIterator());
1144
0
      return *Op->getParent();
1145
0
    }
1146
1147
3.24k
    MachineInstr *operator->() const { return &operator*(); }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator->() const
Line
Count
Source
1147
905
    MachineInstr *operator->() const { return &operator*(); }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator->() const
Line
Count
Source
1147
60
    MachineInstr *operator->() const { return &operator*(); }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator->() const
Line
Count
Source
1147
2.28k
    MachineInstr *operator->() const { return &operator*(); }
1148
  };
1149
};
1150
1151
/// Iterate over the pressure sets affected by the given physical or virtual
1152
/// register. If Reg is physical, it must be a register unit (from
1153
/// MCRegUnitIterator).
1154
class PSetIterator {
1155
  const int *PSet = nullptr;
1156
  unsigned Weight = 0;
1157
1158
public:
1159
  PSetIterator() = default;
1160
1161
32.6M
  PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
1162
32.6M
    const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1163
32.6M
    if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
1164
29.1M
      const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
1165
29.1M
      PSet = TRI->getRegClassPressureSets(RC);
1166
29.1M
      Weight = TRI->getRegClassWeight(RC).RegWeight;
1167
29.1M
    }
1168
3.49M
    else {
1169
3.49M
      PSet = TRI->getRegUnitPressureSets(RegUnit);
1170
3.49M
      Weight = TRI->getRegUnitWeight(RegUnit);
1171
3.49M
    }
1172
32.6M
    if (*PSet == -1)
1173
729k
      PSet = nullptr;
1174
32.6M
  }
1175
1176
117M
  bool isValid() const { return PSet; }
1177
1178
32.6M
  unsigned getWeight() const { return Weight; }
1179
1180
271M
  unsigned operator*() const { return *PSet; }
1181
1182
84.9M
  void operator++() {
1183
84.9M
    assert(isValid() && "Invalid PSetIterator.");
1184
84.9M
    ++PSet;
1185
84.9M
    if (*PSet == -1)
1186
31.2M
      PSet = nullptr;
1187
84.9M
  }
1188
};
1189
1190
inline PSetIterator MachineRegisterInfo::
1191
32.6M
getPressureSets(unsigned RegUnit) const {
1192
32.6M
  return PSetIterator(RegUnit, this);
1193
32.6M
}
1194
1195
} // end namespace llvm
1196
1197
#endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H