Coverage Report

Created: 2019-03-22 08:08

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
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//===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the MachineRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
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#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/PointerUnion.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringSet.h"
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#include "llvm/ADT/iterator_range.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/LowLevelType.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/MC/LaneBitmask.h"
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#include <cassert>
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#include <cstddef>
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#include <cstdint>
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#include <iterator>
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#include <memory>
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#include <utility>
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#include <vector>
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41
namespace llvm {
42
43
class PSetIterator;
44
45
/// Convenient type to represent either a register class or a register bank.
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using RegClassOrRegBank =
47
    PointerUnion<const TargetRegisterClass *, const RegisterBank *>;
48
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/// MachineRegisterInfo - Keep track of information for virtual and physical
50
/// registers, including vreg register classes, use/def chains for registers,
51
/// etc.
52
class MachineRegisterInfo {
53
public:
54
  class Delegate {
55
    virtual void anchor();
56
57
  public:
58
1.44M
    virtual ~Delegate() = default;
59
60
    virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
61
  };
62
63
private:
64
  MachineFunction *MF;
65
  Delegate *TheDelegate = nullptr;
66
67
  /// True if subregister liveness is tracked.
68
  const bool TracksSubRegLiveness;
69
70
  /// VRegInfo - Information we keep for each virtual register.
71
  ///
72
  /// Each element in this list contains the register class of the vreg and the
73
  /// start of the use/def list for the register.
74
  IndexedMap<std::pair<RegClassOrRegBank, MachineOperand *>,
75
             VirtReg2IndexFunctor>
76
      VRegInfo;
77
78
  /// Map for recovering vreg name from vreg number.
79
  /// This map is used by the MIR Printer.
80
  IndexedMap<std::string, VirtReg2IndexFunctor> VReg2Name;
81
82
  /// StringSet that is used to unique vreg names.
83
  StringSet<> VRegNames;
84
85
  /// The flag is true upon \p UpdatedCSRs initialization
86
  /// and false otherwise.
87
  bool IsUpdatedCSRsInitialized;
88
89
  /// Contains the updated callee saved register list.
90
  /// As opposed to the static list defined in register info,
91
  /// all registers that were disabled are removed from the list.
92
  SmallVector<MCPhysReg, 16> UpdatedCSRs;
93
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  /// RegAllocHints - This vector records register allocation hints for
95
  /// virtual registers. For each virtual register, it keeps a pair of hint
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  /// type and hints vector making up the allocation hints. Only the first
97
  /// hint may be target specific, and in that case this is reflected by the
98
  /// first member of the pair being non-zero. If the hinted register is
99
  /// virtual, it means the allocator should prefer the physical register
100
  /// allocated to it if any.
101
  IndexedMap<std::pair<unsigned, SmallVector<unsigned, 4>>,
102
             VirtReg2IndexFunctor> RegAllocHints;
103
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  /// PhysRegUseDefLists - This is an array of the head of the use/def list for
105
  /// physical registers.
106
  std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
107
108
  /// getRegUseDefListHead - Return the head pointer for the register use/def
109
  /// list for the specified virtual or physical register.
110
351M
  MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
111
351M
    if (TargetRegisterInfo::isVirtualRegister(RegNo))
112
168M
      return VRegInfo[RegNo].second;
113
182M
    return PhysRegUseDefLists[RegNo];
114
182M
  }
115
116
936M
  MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
117
936M
    if (TargetRegisterInfo::isVirtualRegister(RegNo))
118
474M
      return VRegInfo[RegNo].second;
119
461M
    return PhysRegUseDefLists[RegNo];
120
461M
  }
121
122
  /// Get the next element in the use-def chain.
123
488M
  static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
124
488M
    assert(MO && MO->isReg() && "This is not a register operand!");
125
488M
    return MO->Contents.Reg.Next;
126
488M
  }
127
128
  /// UsedPhysRegMask - Additional used physregs including aliases.
129
  /// This bit vector represents all the registers clobbered by function calls.
130
  BitVector UsedPhysRegMask;
131
132
  /// ReservedRegs - This is a bit vector of reserved registers.  The target
133
  /// may change its mind about which registers should be reserved.  This
134
  /// vector is the frozen set of reserved registers when register allocation
135
  /// started.
136
  BitVector ReservedRegs;
137
138
  using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;
139
  /// Map generic virtual registers to their low-level type.
140
  VRegToTypeMap VRegToType;
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  /// Keep track of the physical registers that are live in to the function.
143
  /// Live in values are typically arguments in registers.  LiveIn values are
144
  /// allowed to have virtual registers associated with them, stored in the
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  /// second element.
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  std::vector<std::pair<unsigned, unsigned>> LiveIns;
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public:
149
  explicit MachineRegisterInfo(MachineFunction *MF);
150
  MachineRegisterInfo(const MachineRegisterInfo &) = delete;
151
  MachineRegisterInfo &operator=(const MachineRegisterInfo &) = delete;
152
153
157M
  const TargetRegisterInfo *getTargetRegisterInfo() const {
154
157M
    return MF->getSubtarget().getRegisterInfo();
155
157M
  }
156
157
1.44M
  void resetDelegate(Delegate *delegate) {
158
1.44M
    // Ensure another delegate does not take over unless the current
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1.44M
    // delegate first unattaches itself. If we ever need to multicast
160
1.44M
    // notifications, we will need to change to using a list.
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1.44M
    assert(TheDelegate == delegate &&
162
1.44M
           "Only the current delegate can perform reset!");
163
1.44M
    TheDelegate = nullptr;
164
1.44M
  }
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166
1.44M
  void setDelegate(Delegate *delegate) {
167
1.44M
    assert(delegate && !TheDelegate &&
168
1.44M
           "Attempted to set delegate to null, or to change it without "
169
1.44M
           "first resetting it!");
170
1.44M
171
1.44M
    TheDelegate = delegate;
172
1.44M
  }
173
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  //===--------------------------------------------------------------------===//
175
  // Function State
176
  //===--------------------------------------------------------------------===//
177
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  // isSSA - Returns true when the machine function is in SSA form. Early
179
  // passes require the machine function to be in SSA form where every virtual
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  // register has a single defining instruction.
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  //
182
  // The TwoAddressInstructionPass and PHIElimination passes take the machine
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  // function out of SSA form when they introduce multiple defs per virtual
184
  // register.
185
100M
  bool isSSA() const {
186
100M
    return MF->getProperties().hasProperty(
187
100M
        MachineFunctionProperties::Property::IsSSA);
188
100M
  }
189
190
  // leaveSSA - Indicates that the machine function is no longer in SSA form.
191
972k
  void leaveSSA() {
192
972k
    MF->getProperties().reset(MachineFunctionProperties::Property::IsSSA);
193
972k
  }
194
195
  /// tracksLiveness - Returns true when tracking register liveness accurately.
196
  /// (see MachineFUnctionProperties::Property description for details)
197
76.4M
  bool tracksLiveness() const {
198
76.4M
    return MF->getProperties().hasProperty(
199
76.4M
        MachineFunctionProperties::Property::TracksLiveness);
200
76.4M
  }
201
202
  /// invalidateLiveness - Indicates that register liveness is no longer being
203
  /// tracked accurately.
204
  ///
205
  /// This should be called by late passes that invalidate the liveness
206
  /// information.
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66.0k
  void invalidateLiveness() {
208
66.0k
    MF->getProperties().reset(
209
66.0k
        MachineFunctionProperties::Property::TracksLiveness);
210
66.0k
  }
211
212
  /// Returns true if liveness for register class @p RC should be tracked at
213
  /// the subregister level.
214
34.2M
  bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const {
215
34.2M
    return subRegLivenessEnabled() && 
RC.HasDisjunctSubRegs2.43M
;
216
34.2M
  }
217
29.9M
  bool shouldTrackSubRegLiveness(unsigned VReg) const {
218
29.9M
    assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Must pass a VReg");
219
29.9M
    return shouldTrackSubRegLiveness(*getRegClass(VReg));
220
29.9M
  }
221
52.3M
  bool subRegLivenessEnabled() const {
222
52.3M
    return TracksSubRegLiveness;
223
52.3M
  }
224
225
  //===--------------------------------------------------------------------===//
226
  // Register Info
227
  //===--------------------------------------------------------------------===//
228
229
  /// Returns true if the updated CSR list was initialized and false otherwise.
230
7.99k
  bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
231
232
  /// Disables the register from the list of CSRs.
233
  /// I.e. the register will not appear as part of the CSR mask.
234
  /// \see UpdatedCalleeSavedRegs.
235
  void disableCalleeSavedRegister(unsigned Reg);
236
237
  /// Returns list of callee saved registers.
238
  /// The function returns the updated CSR list (after taking into account
239
  /// registers that are disabled from the CSR list).
240
  const MCPhysReg *getCalleeSavedRegs() const;
241
242
  /// Sets the updated Callee Saved Registers list.
243
  /// Notice that it will override ant previously disabled/saved CSRs.
244
  void setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs);
245
246
  // Strictly for use by MachineInstr.cpp.
247
  void addRegOperandToUseList(MachineOperand *MO);
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249
  // Strictly for use by MachineInstr.cpp.
250
  void removeRegOperandFromUseList(MachineOperand *MO);
251
252
  // Strictly for use by MachineInstr.cpp.
253
  void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
254
255
  /// Verify the sanity of the use list for Reg.
256
  void verifyUseList(unsigned Reg) const;
257
258
  /// Verify the use list of all registers.
259
  void verifyUseLists() const;
260
261
  /// reg_begin/reg_end - Provide iteration support to walk over all definitions
262
  /// and uses of a register within the MachineFunction that corresponds to this
263
  /// MachineRegisterInfo object.
264
  template<bool Uses, bool Defs, bool SkipDebug,
265
           bool ByOperand, bool ByInstr, bool ByBundle>
266
  class defusechain_iterator;
267
  template<bool Uses, bool Defs, bool SkipDebug,
268
           bool ByOperand, bool ByInstr, bool ByBundle>
269
  class defusechain_instr_iterator;
270
271
  // Make it a friend so it can access getNextOperandForReg().
272
  template<bool, bool, bool, bool, bool, bool>
273
    friend class defusechain_iterator;
274
  template<bool, bool, bool, bool, bool, bool>
275
    friend class defusechain_instr_iterator;
276
277
  /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
278
  /// register.
279
  using reg_iterator =
280
      defusechain_iterator<true, true, false, true, false, false>;
281
51.8M
  reg_iterator reg_begin(unsigned RegNo) const {
282
51.8M
    return reg_iterator(getRegUseDefListHead(RegNo));
283
51.8M
  }
284
51.8M
  static reg_iterator reg_end() { return reg_iterator(nullptr); }
285
286
276k
  inline iterator_range<reg_iterator>  reg_operands(unsigned Reg) const {
287
276k
    return make_range(reg_begin(Reg), reg_end());
288
276k
  }
289
290
  /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
291
  /// of the specified register, stepping by MachineInstr.
292
  using reg_instr_iterator =
293
      defusechain_instr_iterator<true, true, false, false, true, false>;
294
13.8M
  reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
295
13.8M
    return reg_instr_iterator(getRegUseDefListHead(RegNo));
296
13.8M
  }
297
13.8M
  static reg_instr_iterator reg_instr_end() {
298
13.8M
    return reg_instr_iterator(nullptr);
299
13.8M
  }
300
301
  inline iterator_range<reg_instr_iterator>
302
780k
  reg_instructions(unsigned Reg) const {
303
780k
    return make_range(reg_instr_begin(Reg), reg_instr_end());
304
780k
  }
305
306
  /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
307
  /// of the specified register, stepping by bundle.
308
  using reg_bundle_iterator =
309
      defusechain_instr_iterator<true, true, false, false, false, true>;
310
328k
  reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
311
328k
    return reg_bundle_iterator(getRegUseDefListHead(RegNo));
312
328k
  }
313
328k
  static reg_bundle_iterator reg_bundle_end() {
314
328k
    return reg_bundle_iterator(nullptr);
315
328k
  }
316
317
0
  inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const {
318
0
    return make_range(reg_bundle_begin(Reg), reg_bundle_end());
319
0
  }
320
321
  /// reg_empty - Return true if there are no instructions using or defining the
322
  /// specified register (it may be live-in).
323
49.4M
  bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
324
325
  /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
326
  /// of the specified register, skipping those marked as Debug.
327
  using reg_nodbg_iterator =
328
      defusechain_iterator<true, true, true, true, false, false>;
329
345M
  reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
330
345M
    return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
331
345M
  }
332
345M
  static reg_nodbg_iterator reg_nodbg_end() {
333
345M
    return reg_nodbg_iterator(nullptr);
334
345M
  }
335
336
  inline iterator_range<reg_nodbg_iterator>
337
28.5M
  reg_nodbg_operands(unsigned Reg) const {
338
28.5M
    return make_range(reg_nodbg_begin(Reg), reg_nodbg_end());
339
28.5M
  }
340
341
  /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
342
  /// all defs and uses of the specified register, stepping by MachineInstr,
343
  /// skipping those marked as Debug.
344
  using reg_instr_nodbg_iterator =
345
      defusechain_instr_iterator<true, true, true, false, true, false>;
346
987k
  reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const {
347
987k
    return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
348
987k
  }
349
987k
  static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
350
987k
    return reg_instr_nodbg_iterator(nullptr);
351
987k
  }
352
353
  inline iterator_range<reg_instr_nodbg_iterator>
354
915k
  reg_nodbg_instructions(unsigned Reg) const {
355
915k
    return make_range(reg_instr_nodbg_begin(Reg), reg_instr_nodbg_end());
356
915k
  }
357
358
  /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
359
  /// all defs and uses of the specified register, stepping by bundle,
360
  /// skipping those marked as Debug.
361
  using reg_bundle_nodbg_iterator =
362
      defusechain_instr_iterator<true, true, true, false, false, true>;
363
0
  reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const {
364
0
    return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
365
0
  }
366
0
  static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
367
0
    return reg_bundle_nodbg_iterator(nullptr);
368
0
  }
369
370
  inline iterator_range<reg_bundle_nodbg_iterator>
371
0
  reg_nodbg_bundles(unsigned Reg) const {
372
0
    return make_range(reg_bundle_nodbg_begin(Reg), reg_bundle_nodbg_end());
373
0
  }
374
375
  /// reg_nodbg_empty - Return true if the only instructions using or defining
376
  /// Reg are Debug instructions.
377
317M
  bool reg_nodbg_empty(unsigned RegNo) const {
378
317M
    return reg_nodbg_begin(RegNo) == reg_nodbg_end();
379
317M
  }
380
381
  /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
382
  using def_iterator =
383
      defusechain_iterator<false, true, false, true, false, false>;
384
261M
  def_iterator def_begin(unsigned RegNo) const {
385
261M
    return def_iterator(getRegUseDefListHead(RegNo));
386
261M
  }
387
254M
  static def_iterator def_end() { return def_iterator(nullptr); }
388
389
2.43M
  inline iterator_range<def_iterator> def_operands(unsigned Reg) const {
390
2.43M
    return make_range(def_begin(Reg), def_end());
391
2.43M
  }
392
393
  /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
394
  /// specified register, stepping by MachineInst.
395
  using def_instr_iterator =
396
      defusechain_instr_iterator<false, true, false, false, true, false>;
397
69.6M
  def_instr_iterator def_instr_begin(unsigned RegNo) const {
398
69.6M
    return def_instr_iterator(getRegUseDefListHead(RegNo));
399
69.6M
  }
400
6.31M
  static def_instr_iterator def_instr_end() {
401
6.31M
    return def_instr_iterator(nullptr);
402
6.31M
  }
403
404
  inline iterator_range<def_instr_iterator>
405
2.47M
  def_instructions(unsigned Reg) const {
406
2.47M
    return make_range(def_instr_begin(Reg), def_instr_end());
407
2.47M
  }
408
409
  /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
410
  /// specified register, stepping by bundle.
411
  using def_bundle_iterator =
412
      defusechain_instr_iterator<false, true, false, false, false, true>;
413
0
  def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
414
0
    return def_bundle_iterator(getRegUseDefListHead(RegNo));
415
0
  }
416
0
  static def_bundle_iterator def_bundle_end() {
417
0
    return def_bundle_iterator(nullptr);
418
0
  }
419
420
0
  inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const {
421
0
    return make_range(def_bundle_begin(Reg), def_bundle_end());
422
0
  }
423
424
  /// def_empty - Return true if there are no instructions defining the
425
  /// specified register (it may be live-in).
426
79.9M
  bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
427
428
161k
  StringRef getVRegName(unsigned Reg) const {
429
161k
    return VReg2Name.inBounds(Reg) ? 
StringRef(VReg2Name[Reg])341
:
""161k
;
430
161k
  }
431
432
22.6M
  void insertVRegByName(StringRef Name, unsigned Reg) {
433
22.6M
    assert((Name.empty() || VRegNames.find(Name) == VRegNames.end()) &&
434
22.6M
           "Named VRegs Must be Unique.");
435
22.6M
    if (!Name.empty()) {
436
97
      VRegNames.insert(Name);
437
97
      VReg2Name.grow(Reg);
438
97
      VReg2Name[Reg] = Name.str();
439
97
    }
440
22.6M
  }
441
442
  /// Return true if there is exactly one operand defining the specified
443
  /// register.
444
9.22M
  bool hasOneDef(unsigned RegNo) const {
445
9.22M
    def_iterator DI = def_begin(RegNo);
446
9.22M
    if (DI == def_end())
447
390k
      return false;
448
8.83M
    return ++DI == def_end();
449
8.83M
  }
450
451
  /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
452
  using use_iterator =
453
      defusechain_iterator<true, false, false, true, false, false>;
454
11.5M
  use_iterator use_begin(unsigned RegNo) const {
455
11.5M
    return use_iterator(getRegUseDefListHead(RegNo));
456
11.5M
  }
457
12.3M
  static use_iterator use_end() { return use_iterator(nullptr); }
458
459
9.83M
  inline iterator_range<use_iterator> use_operands(unsigned Reg) const {
460
9.83M
    return make_range(use_begin(Reg), use_end());
461
9.83M
  }
462
463
  /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
464
  /// specified register, stepping by MachineInstr.
465
  using use_instr_iterator =
466
      defusechain_instr_iterator<true, false, false, false, true, false>;
467
8.90M
  use_instr_iterator use_instr_begin(unsigned RegNo) const {
468
8.90M
    return use_instr_iterator(getRegUseDefListHead(RegNo));
469
8.90M
  }
470
8.87M
  static use_instr_iterator use_instr_end() {
471
8.87M
    return use_instr_iterator(nullptr);
472
8.87M
  }
473
474
  inline iterator_range<use_instr_iterator>
475
4.15M
  use_instructions(unsigned Reg) const {
476
4.15M
    return make_range(use_instr_begin(Reg), use_instr_end());
477
4.15M
  }
478
479
  /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
480
  /// specified register, stepping by bundle.
481
  using use_bundle_iterator =
482
      defusechain_instr_iterator<true, false, false, false, false, true>;
483
0
  use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
484
0
    return use_bundle_iterator(getRegUseDefListHead(RegNo));
485
0
  }
486
0
  static use_bundle_iterator use_bundle_end() {
487
0
    return use_bundle_iterator(nullptr);
488
0
  }
489
490
0
  inline iterator_range<use_bundle_iterator> use_bundles(unsigned Reg) const {
491
0
    return make_range(use_bundle_begin(Reg), use_bundle_end());
492
0
  }
493
494
  /// use_empty - Return true if there are no instructions using the specified
495
  /// register.
496
240k
  bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
497
498
  /// hasOneUse - Return true if there is exactly one instruction using the
499
  /// specified register.
500
792k
  bool hasOneUse(unsigned RegNo) const {
501
792k
    use_iterator UI = use_begin(RegNo);
502
792k
    if (UI == use_end())
503
33
      return false;
504
791k
    return ++UI == use_end();
505
791k
  }
506
507
  /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
508
  /// specified register, skipping those marked as Debug.
509
  using use_nodbg_iterator =
510
      defusechain_iterator<true, false, true, true, false, false>;
511
140M
  use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
512
140M
    return use_nodbg_iterator(getRegUseDefListHead(RegNo));
513
140M
  }
514
162M
  static use_nodbg_iterator use_nodbg_end() {
515
162M
    return use_nodbg_iterator(nullptr);
516
162M
  }
517
518
  inline iterator_range<use_nodbg_iterator>
519
46.5M
  use_nodbg_operands(unsigned Reg) const {
520
46.5M
    return make_range(use_nodbg_begin(Reg), use_nodbg_end());
521
46.5M
  }
522
523
  /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
524
  /// all uses of the specified register, stepping by MachineInstr, skipping
525
  /// those marked as Debug.
526
  using use_instr_nodbg_iterator =
527
      defusechain_instr_iterator<true, false, true, false, true, false>;
528
31.6M
  use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const {
529
31.6M
    return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
530
31.6M
  }
531
29.3M
  static use_instr_nodbg_iterator use_instr_nodbg_end() {
532
29.3M
    return use_instr_nodbg_iterator(nullptr);
533
29.3M
  }
534
535
  inline iterator_range<use_instr_nodbg_iterator>
536
29.2M
  use_nodbg_instructions(unsigned Reg) const {
537
29.2M
    return make_range(use_instr_nodbg_begin(Reg), use_instr_nodbg_end());
538
29.2M
  }
539
540
  /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
541
  /// all uses of the specified register, stepping by bundle, skipping
542
  /// those marked as Debug.
543
  using use_bundle_nodbg_iterator =
544
      defusechain_instr_iterator<true, false, true, false, false, true>;
545
0
  use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const {
546
0
    return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
547
0
  }
548
0
  static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
549
0
    return use_bundle_nodbg_iterator(nullptr);
550
0
  }
551
552
  inline iterator_range<use_bundle_nodbg_iterator>
553
0
  use_nodbg_bundles(unsigned Reg) const {
554
0
    return make_range(use_bundle_nodbg_begin(Reg), use_bundle_nodbg_end());
555
0
  }
556
557
  /// use_nodbg_empty - Return true if there are no non-Debug instructions
558
  /// using the specified register.
559
72.0M
  bool use_nodbg_empty(unsigned RegNo) const {
560
72.0M
    return use_nodbg_begin(RegNo) == use_nodbg_end();
561
72.0M
  }
562
563
  /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
564
  /// instruction using the specified register.
565
  bool hasOneNonDBGUse(unsigned RegNo) const;
566
567
  /// replaceRegWith - Replace all instances of FromReg with ToReg in the
568
  /// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
569
  /// except that it also changes any definitions of the register as well.
570
  ///
571
  /// Note that it is usually necessary to first constrain ToReg's register
572
  /// class and register bank to match the FromReg constraints using one of the
573
  /// methods:
574
  ///
575
  ///   constrainRegClass(ToReg, getRegClass(FromReg))
576
  ///   constrainRegAttrs(ToReg, FromReg)
577
  ///   RegisterBankInfo::constrainGenericRegister(ToReg,
578
  ///       *MRI.getRegClass(FromReg), MRI)
579
  ///
580
  /// These functions will return a falsy result if the virtual registers have
581
  /// incompatible constraints.
582
  ///
583
  /// Note that if ToReg is a physical register the function will replace and
584
  /// apply sub registers to ToReg in order to obtain a final/proper physical
585
  /// register.
586
  void replaceRegWith(unsigned FromReg, unsigned ToReg);
587
588
  /// getVRegDef - Return the machine instr that defines the specified virtual
589
  /// register or null if none is found.  This assumes that the code is in SSA
590
  /// form, so there should only be one definition.
591
  MachineInstr *getVRegDef(unsigned Reg) const;
592
593
  /// getUniqueVRegDef - Return the unique machine instr that defines the
594
  /// specified virtual register or null if none is found.  If there are
595
  /// multiple definitions or no definition, return null.
596
  MachineInstr *getUniqueVRegDef(unsigned Reg) const;
597
598
  /// clearKillFlags - Iterate over all the uses of the given register and
599
  /// clear the kill flag from the MachineOperand. This function is used by
600
  /// optimization passes which extend register lifetimes and need only
601
  /// preserve conservative kill flag information.
602
  void clearKillFlags(unsigned Reg) const;
603
604
  void dumpUses(unsigned RegNo) const;
605
606
  /// Returns true if PhysReg is unallocatable and constant throughout the
607
  /// function. Writing to a constant register has no effect.
608
  bool isConstantPhysReg(unsigned PhysReg) const;
609
610
  /// Returns true if either isConstantPhysReg or TRI->isCallerPreservedPhysReg
611
  /// returns true. This is a utility member function.
612
  bool isCallerPreservedOrConstPhysReg(unsigned PhysReg) const;
613
614
  /// Get an iterator over the pressure sets affected by the given physical or
615
  /// virtual register. If RegUnit is physical, it must be a register unit (from
616
  /// MCRegUnitIterator).
617
  PSetIterator getPressureSets(unsigned RegUnit) const;
618
619
  //===--------------------------------------------------------------------===//
620
  // Virtual Register Info
621
  //===--------------------------------------------------------------------===//
622
623
  /// Return the register class of the specified virtual register.
624
  /// This shouldn't be used directly unless \p Reg has a register class.
625
  /// \see getRegClassOrNull when this might happen.
626
213M
  const TargetRegisterClass *getRegClass(unsigned Reg) const {
627
213M
    assert(VRegInfo[Reg].first.is<const TargetRegisterClass *>() &&
628
213M
           "Register class not set, wrong accessor");
629
213M
    return VRegInfo[Reg].first.get<const TargetRegisterClass *>();
630
213M
  }
631
632
  /// Return the register class of \p Reg, or null if Reg has not been assigned
633
  /// a register class yet.
634
  ///
635
  /// \note A null register class can only happen when these two
636
  /// conditions are met:
637
  /// 1. Generic virtual registers are created.
638
  /// 2. The machine function has not completely been through the
639
  ///    instruction selection process.
640
  /// None of this condition is possible without GlobalISel for now.
641
  /// In other words, if GlobalISel is not used or if the query happens after
642
  /// the select pass, using getRegClass is safe.
643
53.6M
  const TargetRegisterClass *getRegClassOrNull(unsigned Reg) const {
644
53.6M
    const RegClassOrRegBank &Val = VRegInfo[Reg].first;
645
53.6M
    return Val.dyn_cast<const TargetRegisterClass *>();
646
53.6M
  }
647
648
  /// Return the register bank of \p Reg, or null if Reg has not been assigned
649
  /// a register bank or has been assigned a register class.
650
  /// \note It is possible to get the register bank from the register class via
651
  /// RegisterBankInfo::getRegBankFromRegClass.
652
22.8M
  const RegisterBank *getRegBankOrNull(unsigned Reg) const {
653
22.8M
    const RegClassOrRegBank &Val = VRegInfo[Reg].first;
654
22.8M
    return Val.dyn_cast<const RegisterBank *>();
655
22.8M
  }
656
657
  /// Return the register bank or register class of \p Reg.
658
  /// \note Before the register bank gets assigned (i.e., before the
659
  /// RegBankSelect pass) \p Reg may not have either.
660
64.4M
  const RegClassOrRegBank &getRegClassOrRegBank(unsigned Reg) const {
661
64.4M
    return VRegInfo[Reg].first;
662
64.4M
  }
663
664
  /// setRegClass - Set the register class of the specified virtual register.
665
  void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
666
667
  /// Set the register bank to \p RegBank for \p Reg.
668
  void setRegBank(unsigned Reg, const RegisterBank &RegBank);
669
670
  void setRegClassOrRegBank(unsigned Reg,
671
78
                            const RegClassOrRegBank &RCOrRB){
672
78
    VRegInfo[Reg].first = RCOrRB;
673
78
  }
674
675
  /// constrainRegClass - Constrain the register class of the specified virtual
676
  /// register to be a common subclass of RC and the current register class,
677
  /// but only if the new class has at least MinNumRegs registers.  Return the
678
  /// new register class, or NULL if no such class exists.
679
  /// This should only be used when the constraint is known to be trivial, like
680
  /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
681
  ///
682
  /// \note Assumes that the register has a register class assigned.
683
  /// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's
684
  /// InstructionSelect pass and constrainRegAttrs in every other pass,
685
  /// including non-select passes of GlobalISel, instead.
686
  const TargetRegisterClass *constrainRegClass(unsigned Reg,
687
                                               const TargetRegisterClass *RC,
688
                                               unsigned MinNumRegs = 0);
689
690
  /// Constrain the register class or the register bank of the virtual register
691
  /// \p Reg (and low-level type) to be a common subclass or a common bank of
692
  /// both registers provided respectively (and a common low-level type). Do
693
  /// nothing if any of the attributes (classes, banks, or low-level types) of
694
  /// the registers are deemed incompatible, or if the resulting register will
695
  /// have a class smaller than before and of size less than \p MinNumRegs.
696
  /// Return true if such register attributes exist, false otherwise.
697
  ///
698
  /// \note Use this method instead of constrainRegClass and
699
  /// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG
700
  /// ISel / FastISel and GlobalISel's InstructionSelect pass respectively.
701
  bool constrainRegAttrs(unsigned Reg, unsigned ConstrainingReg,
702
                         unsigned MinNumRegs = 0);
703
704
  /// recomputeRegClass - Try to find a legal super-class of Reg's register
705
  /// class that still satisfies the constraints from the instructions using
706
  /// Reg.  Returns true if Reg was upgraded.
707
  ///
708
  /// This method can be used after constraints have been removed from a
709
  /// virtual register, for example after removing instructions or splitting
710
  /// the live range.
711
  bool recomputeRegClass(unsigned Reg);
712
713
  /// createVirtualRegister - Create and return a new virtual register in the
714
  /// function with the specified register class.
715
  unsigned createVirtualRegister(const TargetRegisterClass *RegClass,
716
                                 StringRef Name = "");
717
718
  /// Create and return a new virtual register in the function with the same
719
  /// attributes as the given register.
720
  unsigned cloneVirtualRegister(unsigned VReg, StringRef Name = "");
721
722
  /// Get the low-level type of \p Reg or LLT{} if Reg is not a generic
723
  /// (target independent) virtual register.
724
128M
  LLT getType(unsigned Reg) const {
725
128M
    if (TargetRegisterInfo::isVirtualRegister(Reg) && 
VRegToType.inBounds(Reg)124M
)
726
114M
      return VRegToType[Reg];
727
14.5M
    return LLT{};
728
14.5M
  }
729
730
  /// Set the low-level type of \p VReg to \p Ty.
731
  void setType(unsigned VReg, LLT Ty);
732
733
  /// Create and return a new generic virtual register with low-level
734
  /// type \p Ty.
735
  unsigned createGenericVirtualRegister(LLT Ty, StringRef Name = "");
736
737
  /// Remove all types associated to virtual registers (after instruction
738
  /// selection and constraining of all generic virtual registers).
739
  void clearVirtRegTypes();
740
741
  /// Creates a new virtual register that has no register class, register bank
742
  /// or size assigned yet. This is only allowed to be used
743
  /// temporarily while constructing machine instructions. Most operations are
744
  /// undefined on an incomplete register until one of setRegClass(),
745
  /// setRegBank() or setSize() has been called on it.
746
  unsigned createIncompleteVirtualRegister(StringRef Name = "");
747
748
  /// getNumVirtRegs - Return the number of virtual registers created.
749
35.5M
  unsigned getNumVirtRegs() const { return VRegInfo.size(); }
750
751
  /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
752
  void clearVirtRegs();
753
754
  /// setRegAllocationHint - Specify a register allocation hint for the
755
  /// specified virtual register. This is typically used by target, and in case
756
  /// of an earlier hint it will be overwritten.
757
22.5k
  void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) {
758
22.5k
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
759
22.5k
    RegAllocHints[VReg].first  = Type;
760
22.5k
    RegAllocHints[VReg].second.clear();
761
22.5k
    RegAllocHints[VReg].second.push_back(PrefReg);
762
22.5k
  }
763
764
  /// addRegAllocationHint - Add a register allocation hint to the hints
765
  /// vector for VReg.
766
4.21M
  void addRegAllocationHint(unsigned VReg, unsigned PrefReg) {
767
4.21M
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
768
4.21M
    RegAllocHints[VReg].second.push_back(PrefReg);
769
4.21M
  }
770
771
  /// Specify the preferred (target independent) register allocation hint for
772
  /// the specified virtual register.
773
62
  void setSimpleHint(unsigned VReg, unsigned PrefReg) {
774
62
    setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
775
62
  }
776
777
960
  void clearSimpleHint(unsigned VReg) {
778
960
    assert (RegAllocHints[VReg].first == 0 &&
779
960
            "Expected to clear a non-target hint!");
780
960
    RegAllocHints[VReg].second.clear();
781
960
  }
782
783
  /// getRegAllocationHint - Return the register allocation hint for the
784
  /// specified virtual register. If there are many hints, this returns the
785
  /// one with the greatest weight.
786
  std::pair<unsigned, unsigned>
787
38.5M
  getRegAllocationHint(unsigned VReg) const {
788
38.5M
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
789
38.5M
    unsigned BestHint = (RegAllocHints[VReg].second.size() ?
790
27.7M
                         
RegAllocHints[VReg].second[0]10.8M
: 0);
791
38.5M
    return std::pair<unsigned, unsigned>(RegAllocHints[VReg].first, BestHint);
792
38.5M
  }
793
794
  /// getSimpleHint - same as getRegAllocationHint except it will only return
795
  /// a target independent hint.
796
20.1M
  unsigned getSimpleHint(unsigned VReg) const {
797
20.1M
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
798
20.1M
    std::pair<unsigned, unsigned> Hint = getRegAllocationHint(VReg);
799
20.1M
    return Hint.first ? 
054
:
Hint.second20.1M
;
800
20.1M
  }
801
802
  /// getRegAllocationHints - Return a reference to the vector of all
803
  /// register allocation hints for VReg.
804
  const std::pair<unsigned, SmallVector<unsigned, 4>>
805
12.5M
  &getRegAllocationHints(unsigned VReg) const {
806
12.5M
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
807
12.5M
    return RegAllocHints[VReg];
808
12.5M
  }
809
810
  /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
811
  /// specified register as undefined which causes the DBG_VALUE to be
812
  /// deleted during LiveDebugVariables analysis.
813
  void markUsesInDebugValueAsUndef(unsigned Reg) const;
814
815
  /// Return true if the specified register is modified in this function.
816
  /// This checks that no defining machine operands exist for the register or
817
  /// any of its aliases. Definitions found on functions marked noreturn are
818
  /// ignored, to consider them pass 'true' for optional parameter
819
  /// SkipNoReturnDef. The register is also considered modified when it is set
820
  /// in the UsedPhysRegMask.
821
  bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef = false) const;
822
823
  /// Return true if the specified register is modified or read in this
824
  /// function. This checks that no machine operands exist for the register or
825
  /// any of its aliases. The register is also considered used when it is set
826
  /// in the UsedPhysRegMask.
827
  bool isPhysRegUsed(unsigned PhysReg) const;
828
829
  /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
830
  /// This corresponds to the bit mask attached to register mask operands.
831
1.51M
  void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
832
1.51M
    UsedPhysRegMask.setBitsNotInMask(RegMask);
833
1.51M
  }
834
835
21.3k
  const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
836
837
  //===--------------------------------------------------------------------===//
838
  // Reserved Register Info
839
  //===--------------------------------------------------------------------===//
840
  //
841
  // The set of reserved registers must be invariant during register
842
  // allocation.  For example, the target cannot suddenly decide it needs a
843
  // frame pointer when the register allocator has already used the frame
844
  // pointer register for something else.
845
  //
846
  // These methods can be used by target hooks like hasFP() to avoid changing
847
  // the reserved register set during register allocation.
848
849
  /// freezeReservedRegs - Called by the register allocator to freeze the set
850
  /// of reserved registers before allocation begins.
851
  void freezeReservedRegs(const MachineFunction&);
852
853
  /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
854
  /// to ensure the set of reserved registers stays constant.
855
3.72M
  bool reservedRegsFrozen() const {
856
3.72M
    return !ReservedRegs.empty();
857
3.72M
  }
858
859
  /// canReserveReg - Returns true if PhysReg can be used as a reserved
860
  /// register.  Any register can be reserved before freezeReservedRegs() is
861
  /// called.
862
193k
  bool canReserveReg(unsigned PhysReg) const {
863
193k
    return !reservedRegsFrozen() || 
ReservedRegs.test(PhysReg)188k
;
864
193k
  }
865
866
  /// getReservedRegs - Returns a reference to the frozen set of reserved
867
  /// registers. This method should always be preferred to calling
868
  /// TRI::getReservedRegs() when possible.
869
174M
  const BitVector &getReservedRegs() const {
870
174M
    assert(reservedRegsFrozen() &&
871
174M
           "Reserved registers haven't been frozen yet. "
872
174M
           "Use TRI::getReservedRegs().");
873
174M
    return ReservedRegs;
874
174M
  }
875
876
  /// isReserved - Returns true when PhysReg is a reserved register.
877
  ///
878
  /// Reserved registers may belong to an allocatable register class, but the
879
  /// target has explicitly requested that they are not used.
880
165M
  bool isReserved(unsigned PhysReg) const {
881
165M
    return getReservedRegs().test(PhysReg);
882
165M
  }
883
884
  /// Returns true when the given register unit is considered reserved.
885
  ///
886
  /// Register units are considered reserved when for at least one of their
887
  /// root registers, the root register and all super registers are reserved.
888
  /// This currently iterates the register hierarchy and may be slower than
889
  /// expected.
890
  bool isReservedRegUnit(unsigned Unit) const;
891
892
  /// isAllocatable - Returns true when PhysReg belongs to an allocatable
893
  /// register class and it hasn't been reserved.
894
  ///
895
  /// Allocatable registers may show up in the allocation order of some virtual
896
  /// register, so a register allocator needs to track its liveness and
897
  /// availability.
898
35.2M
  bool isAllocatable(unsigned PhysReg) const {
899
35.2M
    return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
900
35.2M
      
!isReserved(PhysReg)30.9M
;
901
35.2M
  }
902
903
  //===--------------------------------------------------------------------===//
904
  // LiveIn Management
905
  //===--------------------------------------------------------------------===//
906
907
  /// addLiveIn - Add the specified register as a live-in.  Note that it
908
  /// is an error to add the same register to the same set more than once.
909
534k
  void addLiveIn(unsigned Reg, unsigned vreg = 0) {
910
534k
    LiveIns.push_back(std::make_pair(Reg, vreg));
911
534k
  }
912
913
  // Iteration support for the live-ins set.  It's kept in sorted order
914
  // by register number.
915
  using livein_iterator =
916
      std::vector<std::pair<unsigned,unsigned>>::const_iterator;
917
2.54M
  livein_iterator livein_begin() const { return LiveIns.begin(); }
918
2.54M
  livein_iterator livein_end()   const { return LiveIns.end(); }
919
3.57k
  bool            livein_empty() const { return LiveIns.empty(); }
920
921
93.2k
  ArrayRef<std::pair<unsigned, unsigned>> liveins() const {
922
93.2k
    return LiveIns;
923
93.2k
  }
924
925
  bool isLiveIn(unsigned Reg) const;
926
927
  /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
928
  /// corresponding live-in physical register.
929
  unsigned getLiveInPhysReg(unsigned VReg) const;
930
931
  /// getLiveInVirtReg - If PReg is a live-in physical register, return the
932
  /// corresponding live-in physical register.
933
  unsigned getLiveInVirtReg(unsigned PReg) const;
934
935
  /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
936
  /// into the given entry block.
937
  void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
938
                        const TargetRegisterInfo &TRI,
939
                        const TargetInstrInfo &TII);
940
941
  /// Returns a mask covering all bits that can appear in lane masks of
942
  /// subregisters of the virtual register @p Reg.
943
  LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const;
944
945
  /// defusechain_iterator - This class provides iterator support for machine
946
  /// operands in the function that use or define a specific register.  If
947
  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
948
  /// returns defs.  If neither are true then you are silly and it always
949
  /// returns end().  If SkipDebug is true it skips uses marked Debug
950
  /// when incrementing.
951
  template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
952
           bool ByOperand, bool ByInstr, bool ByBundle>
953
  class defusechain_iterator
954
    : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
955
    friend class MachineRegisterInfo;
956
957
    MachineOperand *Op = nullptr;
958
959
1.63G
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
960
1.63G
      // If the first node isn't one we're interested in, advance to one that
961
1.63G
      // we are interested in.
962
1.63G
      if (op) {
963
307M
        if ((!ReturnUses && 
op->isUse()63.7M
) ||
964
307M
            
(151M
!ReturnDefs151M
&&
op->isDef()151M
) ||
965
307M
            
(86.9M
SkipDebug86.9M
&&
op->isDebug()86.9M
))
966
150M
          advance();
967
307M
      }
968
1.63G
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
959
516M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
960
516M
      // If the first node isn't one we're interested in, advance to one that
961
516M
      // we are interested in.
962
516M
      if (op) {
963
63.7M
        if ((!ReturnUses && op->isUse()) ||
964
63.7M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
965
63.7M
            
(0
SkipDebug0
&&
op->isDebug()0
))
966
2.71M
          advance();
967
63.7M
      }
968
516M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
959
303M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
960
303M
      // If the first node isn't one we're interested in, advance to one that
961
303M
      // we are interested in.
962
303M
      if (op) {
963
139M
        if ((!ReturnUses && 
op->isUse()0
) ||
964
139M
            (!ReturnDefs && 
op->isDef()139M
) ||
965
139M
            
(497k
SkipDebug497k
&&
op->isDebug()497k
))
966
139M
          advance();
967
139M
      }
968
303M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
959
23.9M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
960
23.9M
      // If the first node isn't one we're interested in, advance to one that
961
23.9M
      // we are interested in.
962
23.9M
      if (op) {
963
11.4M
        if ((!ReturnUses && 
op->isUse()0
) ||
964
11.4M
            (!ReturnDefs && op->isDef()) ||
965
11.4M
            
(0
SkipDebug0
&&
op->isDebug()0
))
966
8.94M
          advance();
967
11.4M
      }
968
23.9M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
959
103M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
960
103M
      // If the first node isn't one we're interested in, advance to one that
961
103M
      // we are interested in.
962
103M
      if (op) {
963
6.11M
        if ((!ReturnUses && 
op->isUse()0
) ||
964
6.11M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
965
6.11M
            
(0
SkipDebug0
&&
op->isDebug()0
))
966
0
          advance();
967
6.11M
      }
968
103M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
959
691M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
960
691M
      // If the first node isn't one we're interested in, advance to one that
961
691M
      // we are interested in.
962
691M
      if (op) {
963
86.4M
        if ((!ReturnUses && 
op->isUse()0
) ||
964
86.4M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
965
86.4M
            (SkipDebug && op->isDebug()))
966
5
          advance();
967
86.4M
      }
968
691M
    }
969
970
339M
    void advance() {
971
339M
      assert(Op && "Cannot increment end iterator!");
972
339M
      Op = getNextOperandForReg(Op);
973
339M
974
339M
      // All defs come before the uses, so stop def_iterator early.
975
339M
      if (!ReturnUses) {
976
30.9M
        if (Op) {
977
29.2M
          if (Op->isUse())
978
21.1M
            Op = nullptr;
979
29.2M
          else
980
29.2M
            assert(!Op->isDebug() && "Can't have debug defs");
981
29.2M
        }
982
308M
      } else {
983
308M
        // If this is an operand we don't care about, skip it.
984
346M
        while (Op && 
(281M
(281M
!ReturnDefs281M
&&
Op->isDef()220M
) ||
985
281M
                      
(244M
SkipDebug244M
&&
Op->isDebug()216M
)))
986
37.8M
          Op = getNextOperandForReg(Op);
987
308M
      }
988
339M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::advance()
Line
Count
Source
970
30.9M
    void advance() {
971
30.9M
      assert(Op && "Cannot increment end iterator!");
972
30.9M
      Op = getNextOperandForReg(Op);
973
30.9M
974
30.9M
      // All defs come before the uses, so stop def_iterator early.
975
30.9M
      if (!ReturnUses) {
976
30.9M
        if (Op) {
977
29.2M
          if (Op->isUse())
978
21.1M
            Op = nullptr;
979
29.2M
          else
980
29.2M
            assert(!Op->isDebug() && "Can't have debug defs");
981
29.2M
        }
982
30.9M
      } else {
983
0
        // If this is an operand we don't care about, skip it.
984
0
        while (Op && ((!ReturnDefs && Op->isDef()) ||
985
0
                      (SkipDebug && Op->isDebug())))
986
0
          Op = getNextOperandForReg(Op);
987
0
      }
988
30.9M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::advance()
Line
Count
Source
970
182M
    void advance() {
971
182M
      assert(Op && "Cannot increment end iterator!");
972
182M
      Op = getNextOperandForReg(Op);
973
182M
974
182M
      // All defs come before the uses, so stop def_iterator early.
975
182M
      if (!ReturnUses) {
976
0
        if (Op) {
977
0
          if (Op->isUse())
978
0
            Op = nullptr;
979
0
          else
980
0
            assert(!Op->isDebug() && "Can't have debug defs");
981
0
        }
982
182M
      } else {
983
182M
        // If this is an operand we don't care about, skip it.
984
214M
        while (Op && 
(191M
(191M
!ReturnDefs191M
&&
Op->isDef()191M
) ||
985
191M
                      
(159M
SkipDebug159M
&&
Op->isDebug()159M
)))
986
31.8M
          Op = getNextOperandForReg(Op);
987
182M
      }
988
182M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::advance()
Line
Count
Source
970
33.6M
    void advance() {
971
33.6M
      assert(Op && "Cannot increment end iterator!");
972
33.6M
      Op = getNextOperandForReg(Op);
973
33.6M
974
33.6M
      // All defs come before the uses, so stop def_iterator early.
975
33.6M
      if (!ReturnUses) {
976
0
        if (Op) {
977
0
          if (Op->isUse())
978
0
            Op = nullptr;
979
0
          else
980
0
            assert(!Op->isDebug() && "Can't have debug defs");
981
0
        }
982
33.6M
      } else {
983
33.6M
        // If this is an operand we don't care about, skip it.
984
39.6M
        while (Op && 
(28.5M
(28.5M
!ReturnDefs28.5M
&&
Op->isDef()28.5M
) ||
985
28.5M
                      
(22.5M
SkipDebug22.5M
&&
Op->isDebug()0
)))
986
5.98M
          Op = getNextOperandForReg(Op);
987
33.6M
      }
988
33.6M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::advance()
Line
Count
Source
970
6.75M
    void advance() {
971
6.75M
      assert(Op && "Cannot increment end iterator!");
972
6.75M
      Op = getNextOperandForReg(Op);
973
6.75M
974
6.75M
      // All defs come before the uses, so stop def_iterator early.
975
6.75M
      if (!ReturnUses) {
976
0
        if (Op) {
977
0
          if (Op->isUse())
978
0
            Op = nullptr;
979
0
          else
980
0
            assert(!Op->isDebug() && "Can't have debug defs");
981
0
        }
982
6.75M
      } else {
983
6.75M
        // If this is an operand we don't care about, skip it.
984
6.75M
        while (Op && 
(4.60M
(4.60M
!ReturnDefs4.60M
&&
Op->isDef()0
) ||
985
4.60M
                      (SkipDebug && 
Op->isDebug()0
)))
986
0
          Op = getNextOperandForReg(Op);
987
6.75M
      }
988
6.75M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::advance()
Line
Count
Source
970
85.6M
    void advance() {
971
85.6M
      assert(Op && "Cannot increment end iterator!");
972
85.6M
      Op = getNextOperandForReg(Op);
973
85.6M
974
85.6M
      // All defs come before the uses, so stop def_iterator early.
975
85.6M
      if (!ReturnUses) {
976
0
        if (Op) {
977
0
          if (Op->isUse())
978
0
            Op = nullptr;
979
0
          else
980
0
            assert(!Op->isDebug() && "Can't have debug defs");
981
0
        }
982
85.6M
      } else {
983
85.6M
        // If this is an operand we don't care about, skip it.
984
85.6M
        while (Op && 
(57.2M
(57.2M
!ReturnDefs57.2M
&&
Op->isDef()0
) ||
985
57.2M
                      (SkipDebug && Op->isDebug())))
986
1.51k
          Op = getNextOperandForReg(Op);
987
85.6M
      }
988
85.6M
    }
989
990
  public:
991
    using reference = std::iterator<std::forward_iterator_tag,
992
                                    MachineInstr, ptrdiff_t>::reference;
993
    using pointer = std::iterator<std::forward_iterator_tag,
994
                                  MachineInstr, ptrdiff_t>::pointer;
995
996
110k
    defusechain_iterator() = default;
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::defusechain_iterator()
Line
Count
Source
996
110k
    defusechain_iterator() = default;
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::defusechain_iterator()
Line
Count
Source
996
261
    defusechain_iterator() = default;
997
998
972M
    bool operator==(const defusechain_iterator &x) const {
999
972M
      return Op == x.Op;
1000
972M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false> const&) const
Line
Count
Source
998
262M
    bool operator==(const defusechain_iterator &x) const {
999
262M
      return Op == x.Op;
1000
262M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false> const&) const
Line
Count
Source
998
183M
    bool operator==(const defusechain_iterator &x) const {
999
183M
      return Op == x.Op;
1000
183M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false> const&) const
Line
Count
Source
998
36.3M
    bool operator==(const defusechain_iterator &x) const {
999
36.3M
      return Op == x.Op;
1000
36.3M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false> const&) const
Line
Count
Source
998
58.4M
    bool operator==(const defusechain_iterator &x) const {
999
58.4M
      return Op == x.Op;
1000
58.4M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false> const&) const
Line
Count
Source
998
431M
    bool operator==(const defusechain_iterator &x) const {
999
431M
      return Op == x.Op;
1000
431M
    }
1001
389M
    bool operator!=(const defusechain_iterator &x) const {
1002
389M
      return !operator==(x);
1003
389M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false> const&) const
Line
Count
Source
1001
8.90M
    bool operator!=(const defusechain_iterator &x) const {
1002
8.90M
      return !operator==(x);
1003
8.90M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false> const&) const
Line
Count
Source
1001
34.4M
    bool operator!=(const defusechain_iterator &x) const {
1002
34.4M
      return !operator==(x);
1003
34.4M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false> const&) const
Line
Count
Source
1001
164M
    bool operator!=(const defusechain_iterator &x) const {
1002
164M
      return !operator==(x);
1003
164M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false> const&) const
Line
Count
Source
1001
114M
    bool operator!=(const defusechain_iterator &x) const {
1002
114M
      return !operator==(x);
1003
114M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false> const&) const
Line
Count
Source
1001
67.6M
    bool operator!=(const defusechain_iterator &x) const {
1002
67.6M
      return !operator==(x);
1003
67.6M
    }
1004
1005
    /// atEnd - return true if this iterator is equal to reg_end() on the value.
1006
    bool atEnd() const { return Op == nullptr; }
1007
1008
    // Iterator traversal: forward iteration only
1009
188M
    defusechain_iterator &operator++() {          // Preincrement
1010
188M
      assert(Op && "Cannot increment end iterator!");
1011
188M
      if (ByOperand)
1012
188M
        advance();
1013
0
      else if (ByInstr) {
1014
0
        MachineInstr *P = Op->getParent();
1015
0
        do {
1016
0
          advance();
1017
0
        } while (Op && Op->getParent() == P);
1018
0
      } else if (ByBundle) {
1019
0
        MachineBasicBlock::instr_iterator P =
1020
0
            getBundleStart(Op->getParent()->getIterator());
1021
0
        do {
1022
0
          advance();
1023
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1024
0
      }
1025
188M
1026
188M
      return *this;
1027
188M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator++()
Line
Count
Source
1009
28.2M
    defusechain_iterator &operator++() {          // Preincrement
1010
28.2M
      assert(Op && "Cannot increment end iterator!");
1011
28.2M
      if (ByOperand)
1012
28.2M
        advance();
1013
0
      else if (ByInstr) {
1014
0
        MachineInstr *P = Op->getParent();
1015
0
        do {
1016
0
          advance();
1017
0
        } while (Op && Op->getParent() == P);
1018
0
      } else if (ByBundle) {
1019
0
        MachineBasicBlock::instr_iterator P =
1020
0
            getBundleStart(Op->getParent()->getIterator());
1021
0
        do {
1022
0
          advance();
1023
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1024
0
      }
1025
28.2M
1026
28.2M
      return *this;
1027
28.2M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator++()
Line
Count
Source
1009
6.75M
    defusechain_iterator &operator++() {          // Preincrement
1010
6.75M
      assert(Op && "Cannot increment end iterator!");
1011
6.75M
      if (ByOperand)
1012
6.75M
        advance();
1013
0
      else if (ByInstr) {
1014
0
        MachineInstr *P = Op->getParent();
1015
0
        do {
1016
0
          advance();
1017
0
        } while (Op && Op->getParent() == P);
1018
0
      } else if (ByBundle) {
1019
0
        MachineBasicBlock::instr_iterator P =
1020
0
            getBundleStart(Op->getParent()->getIterator());
1021
0
        do {
1022
0
          advance();
1023
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1024
0
      }
1025
6.75M
1026
6.75M
      return *this;
1027
6.75M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator++()
Line
Count
Source
1009
24.6M
    defusechain_iterator &operator++() {          // Preincrement
1010
24.6M
      assert(Op && "Cannot increment end iterator!");
1011
24.6M
      if (ByOperand)
1012
24.6M
        advance();
1013
0
      else if (ByInstr) {
1014
0
        MachineInstr *P = Op->getParent();
1015
0
        do {
1016
0
          advance();
1017
0
        } while (Op && Op->getParent() == P);
1018
0
      } else if (ByBundle) {
1019
0
        MachineBasicBlock::instr_iterator P =
1020
0
            getBundleStart(Op->getParent()->getIterator());
1021
0
        do {
1022
0
          advance();
1023
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1024
0
      }
1025
24.6M
1026
24.6M
      return *this;
1027
24.6M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator++()
Line
Count
Source
1009
85.6M
    defusechain_iterator &operator++() {          // Preincrement
1010
85.6M
      assert(Op && "Cannot increment end iterator!");
1011
85.6M
      if (ByOperand)
1012
85.6M
        advance();
1013
0
      else if (ByInstr) {
1014
0
        MachineInstr *P = Op->getParent();
1015
0
        do {
1016
0
          advance();
1017
0
        } while (Op && Op->getParent() == P);
1018
0
      } else if (ByBundle) {
1019
0
        MachineBasicBlock::instr_iterator P =
1020
0
            getBundleStart(Op->getParent()->getIterator());
1021
0
        do {
1022
0
          advance();
1023
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1024
0
      }
1025
85.6M
1026
85.6M
      return *this;
1027
85.6M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator++()
Line
Count
Source
1009
43.1M
    defusechain_iterator &operator++() {          // Preincrement
1010
43.1M
      assert(Op && "Cannot increment end iterator!");
1011
43.1M
      if (ByOperand)
1012
43.1M
        advance();
1013
0
      else if (ByInstr) {
1014
0
        MachineInstr *P = Op->getParent();
1015
0
        do {
1016
0
          advance();
1017
0
        } while (Op && Op->getParent() == P);
1018
0
      } else if (ByBundle) {
1019
0
        MachineBasicBlock::instr_iterator P =
1020
0
            getBundleStart(Op->getParent()->getIterator());
1021
0
        do {
1022
0
          advance();
1023
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1024
0
      }
1025
43.1M
1026
43.1M
      return *this;
1027
43.1M
    }
1028
123k
    defusechain_iterator operator++(int) {        // Postincrement
1029
123k
      defusechain_iterator tmp = *this; ++*this; return tmp;
1030
123k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator++(int)
Line
Count
Source
1028
107k
    defusechain_iterator operator++(int) {        // Postincrement
1029
107k
      defusechain_iterator tmp = *this; ++*this; return tmp;
1030
107k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator++(int)
Line
Count
Source
1028
15.2k
    defusechain_iterator operator++(int) {        // Postincrement
1029
15.2k
      defusechain_iterator tmp = *this; ++*this; return tmp;
1030
15.2k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator++(int)
Line
Count
Source
1028
577
    defusechain_iterator operator++(int) {        // Postincrement
1029
577
      defusechain_iterator tmp = *this; ++*this; return tmp;
1030
577
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator++(int)
Line
Count
Source
1028
346
    defusechain_iterator operator++(int) {        // Postincrement
1029
346
      defusechain_iterator tmp = *this; ++*this; return tmp;
1030
346
    }
1031
1032
    /// getOperandNo - Return the operand # of this MachineOperand in its
1033
    /// MachineInstr.
1034
17.4M
    unsigned getOperandNo() const {
1035
17.4M
      assert(Op && "Cannot dereference end iterator!");
1036
17.4M
      return Op - &Op->getParent()->getOperand(0);
1037
17.4M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::getOperandNo() const
Line
Count
Source
1034
515k
    unsigned getOperandNo() const {
1035
515k
      assert(Op && "Cannot dereference end iterator!");
1036
515k
      return Op - &Op->getParent()->getOperand(0);
1037
515k
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::getOperandNo() const
Line
Count
Source
1034
16.9M
    unsigned getOperandNo() const {
1035
16.9M
      assert(Op && "Cannot dereference end iterator!");
1036
16.9M
      return Op - &Op->getParent()->getOperand(0);
1037
16.9M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::getOperandNo() const
Line
Count
Source
1034
1.90k
    unsigned getOperandNo() const {
1035
1.90k
      assert(Op && "Cannot dereference end iterator!");
1036
1.90k
      return Op - &Op->getParent()->getOperand(0);
1037
1.90k
    }
1038
1039
    // Retrieve a reference to the current operand.
1040
184M
    MachineOperand &operator*() const {
1041
184M
      assert(Op && "Cannot dereference end iterator!");
1042
184M
      return *Op;
1043
184M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator*() const
Line
Count
Source
1040
6.64M
    MachineOperand &operator*() const {
1041
6.64M
      assert(Op && "Cannot dereference end iterator!");
1042
6.64M
      return *Op;
1043
6.64M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator*() const
Line
Count
Source
1040
23.2M
    MachineOperand &operator*() const {
1041
23.2M
      assert(Op && "Cannot dereference end iterator!");
1042
23.2M
      return *Op;
1043
23.2M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator*() const
Line
Count
Source
1040
10.4M
    MachineOperand &operator*() const {
1041
10.4M
      assert(Op && "Cannot dereference end iterator!");
1042
10.4M
      return *Op;
1043
10.4M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator*() const
Line
Count
Source
1040
85.7M
    MachineOperand &operator*() const {
1041
85.7M
      assert(Op && "Cannot dereference end iterator!");
1042
85.7M
      return *Op;
1043
85.7M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator*() const
Line
Count
Source
1040
58.7M
    MachineOperand &operator*() const {
1041
58.7M
      assert(Op && "Cannot dereference end iterator!");
1042
58.7M
      return *Op;
1043
58.7M
    }
1044
1045
15.2M
    MachineOperand *operator->() const {
1046
15.2M
      assert(Op && "Cannot dereference end iterator!");
1047
15.2M
      return Op;
1048
15.2M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator->() const
Line
Count
Source
1045
1.05M
    MachineOperand *operator->() const {
1046
1.05M
      assert(Op && "Cannot dereference end iterator!");
1047
1.05M
      return Op;
1048
1.05M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator->() const
Line
Count
Source
1045
2.44k
    MachineOperand *operator->() const {
1046
2.44k
      assert(Op && "Cannot dereference end iterator!");
1047
2.44k
      return Op;
1048
2.44k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator->() const
Line
Count
Source
1045
607k
    MachineOperand *operator->() const {
1046
607k
      assert(Op && "Cannot dereference end iterator!");
1047
607k
      return Op;
1048
607k
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator->() const
Line
Count
Source
1045
13.5M
    MachineOperand *operator->() const {
1046
13.5M
      assert(Op && "Cannot dereference end iterator!");
1047
13.5M
      return Op;
1048
13.5M
    }
1049
  };
1050
1051
  /// defusechain_iterator - This class provides iterator support for machine
1052
  /// operands in the function that use or define a specific register.  If
1053
  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1054
  /// returns defs.  If neither are true then you are silly and it always
1055
  /// returns end().  If SkipDebug is true it skips uses marked Debug
1056
  /// when incrementing.
1057
  template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
1058
           bool ByOperand, bool ByInstr, bool ByBundle>
1059
  class defusechain_instr_iterator
1060
    : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
1061
    friend class MachineRegisterInfo;
1062
1063
    MachineOperand *Op = nullptr;
1064
1065
185M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1066
185M
      // If the first node isn't one we're interested in, advance to one that
1067
185M
      // we are interested in.
1068
185M
      if (op) {
1069
125M
        if ((!ReturnUses && 
op->isUse()69.6M
) ||
1070
125M
            
(40.5M
!ReturnDefs40.5M
&&
op->isDef()40.5M
) ||
1071
125M
            
(987k
SkipDebug987k
&&
op->isDebug()987k
))
1072
40.5M
          advance();
1073
125M
      }
1074
185M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1065
75.9M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1066
75.9M
      // If the first node isn't one we're interested in, advance to one that
1067
75.9M
      // we are interested in.
1068
75.9M
      if (op) {
1069
69.6M
        if ((!ReturnUses && op->isUse()) ||
1070
69.6M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
1071
69.6M
            
(0
SkipDebug0
&&
op->isDebug()0
))
1072
16.6k
          advance();
1073
69.6M
      }
1074
75.9M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1065
61.0M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1066
61.0M
      // If the first node isn't one we're interested in, advance to one that
1067
61.0M
      // we are interested in.
1068
61.0M
      if (op) {
1069
31.6M
        if ((!ReturnUses && 
op->isUse()0
) ||
1070
31.6M
            (!ReturnDefs && op->isDef()) ||
1071
31.6M
            
(0
SkipDebug0
&&
op->isDebug()0
))
1072
31.6M
          advance();
1073
31.6M
      }
1074
61.0M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1065
1.97M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1066
1.97M
      // If the first node isn't one we're interested in, advance to one that
1067
1.97M
      // we are interested in.
1068
1.97M
      if (op) {
1069
987k
        if ((!ReturnUses && 
op->isUse()0
) ||
1070
987k
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
1071
987k
            (SkipDebug && op->isDebug()))
1072
0
          advance();
1073
987k
      }
1074
1.97M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1065
17.7M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1066
17.7M
      // If the first node isn't one we're interested in, advance to one that
1067
17.7M
      // we are interested in.
1068
17.7M
      if (op) {
1069
8.89M
        if ((!ReturnUses && 
op->isUse()0
) ||
1070
8.89M
            (!ReturnDefs && op->isDef()) ||
1071
8.89M
            
(0
SkipDebug0
&&
op->isDebug()0
))
1072
8.89M
          advance();
1073
8.89M
      }
1074
17.7M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1065
27.7M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1066
27.7M
      // If the first node isn't one we're interested in, advance to one that
1067
27.7M
      // we are interested in.
1068
27.7M
      if (op) {
1069
13.6M
        if ((!ReturnUses && 
op->isUse()0
) ||
1070
13.6M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
1071
13.6M
            
(0
SkipDebug0
&&
op->isDebug()0
))
1072
0
          advance();
1073
13.6M
      }
1074
27.7M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1065
656k
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1066
656k
      // If the first node isn't one we're interested in, advance to one that
1067
656k
      // we are interested in.
1068
656k
      if (op) {
1069
328k
        if ((!ReturnUses && 
op->isUse()0
) ||
1070
328k
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
1071
328k
            
(0
SkipDebug0
&&
op->isDebug()0
))
1072
0
          advance();
1073
328k
      }
1074
656k
    }
1075
1076
107M
    void advance() {
1077
107M
      assert(Op && "Cannot increment end iterator!");
1078
107M
      Op = getNextOperandForReg(Op);
1079
107M
1080
107M
      // All defs come before the uses, so stop def_iterator early.
1081
107M
      if (!ReturnUses) {
1082
4.18M
        if (Op) {
1083
4.17M
          if (Op->isUse())
1084
4.08M
            Op = nullptr;
1085
4.17M
          else
1086
4.17M
            assert(!Op->isDebug() && "Can't have debug defs");
1087
4.17M
        }
1088
103M
      } else {
1089
103M
        // If this is an operand we don't care about, skip it.
1090
106M
        while (Op && 
(80.0M
(80.0M
!ReturnDefs80.0M
&&
Op->isDef()49.5M
) ||
1091
80.0M
                      
(76.6M
SkipDebug76.6M
&&
Op->isDebug()37.2M
)))
1092
3.43M
          Op = getNextOperandForReg(Op);
1093
103M
      }
1094
107M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::advance()
Line
Count
Source
1076
4.18M
    void advance() {
1077
4.18M
      assert(Op && "Cannot increment end iterator!");
1078
4.18M
      Op = getNextOperandForReg(Op);
1079
4.18M
1080
4.18M
      // All defs come before the uses, so stop def_iterator early.
1081
4.18M
      if (!ReturnUses) {
1082
4.18M
        if (Op) {
1083
4.17M
          if (Op->isUse())
1084
4.08M
            Op = nullptr;
1085
4.17M
          else
1086
4.17M
            assert(!Op->isDebug() && "Can't have debug defs");
1087
4.17M
        }
1088
4.18M
      } else {
1089
0
        // If this is an operand we don't care about, skip it.
1090
0
        while (Op && ((!ReturnDefs && Op->isDef()) ||
1091
0
                      (SkipDebug && Op->isDebug())))
1092
0
          Op = getNextOperandForReg(Op);
1093
0
      }
1094
4.18M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::advance()
Line
Count
Source
1076
36.5M
    void advance() {
1077
36.5M
      assert(Op && "Cannot increment end iterator!");
1078
36.5M
      Op = getNextOperandForReg(Op);
1079
36.5M
1080
36.5M
      // All defs come before the uses, so stop def_iterator early.
1081
36.5M
      if (!ReturnUses) {
1082
0
        if (Op) {
1083
0
          if (Op->isUse())
1084
0
            Op = nullptr;
1085
0
          else
1086
0
            assert(!Op->isDebug() && "Can't have debug defs");
1087
0
        }
1088
36.5M
      } else {
1089
36.5M
        // If this is an operand we don't care about, skip it.
1090
38.2M
        while (Op && 
(35.2M
(35.2M
!ReturnDefs35.2M
&&
Op->isDef()35.2M
) ||
1091
35.2M
                      
(33.5M
SkipDebug33.5M
&&
Op->isDebug()33.5M
)))
1092
1.74M
          Op = getNextOperandForReg(Op);
1093
36.5M
      }
1094
36.5M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::advance()
Line
Count
Source
1076
4.61M
    void advance() {
1077
4.61M
      assert(Op && "Cannot increment end iterator!");
1078
4.61M
      Op = getNextOperandForReg(Op);
1079
4.61M
1080
4.61M
      // All defs come before the uses, so stop def_iterator early.
1081
4.61M
      if (!ReturnUses) {
1082
0
        if (Op) {
1083
0
          if (Op->isUse())
1084
0
            Op = nullptr;
1085
0
          else
1086
0
            assert(!Op->isDebug() && "Can't have debug defs");
1087
0
        }
1088
4.61M
      } else {
1089
4.61M
        // If this is an operand we don't care about, skip it.
1090
4.61M
        while (Op && 
(3.67M
(3.67M
!ReturnDefs3.67M
&&
Op->isDef()0
) ||
1091
3.67M
                      (SkipDebug && Op->isDebug())))
1092
0
          Op = getNextOperandForReg(Op);
1093
4.61M
      }
1094
4.61M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::advance()
Line
Count
Source
1076
21.3M
    void advance() {
1077
21.3M
      assert(Op && "Cannot increment end iterator!");
1078
21.3M
      Op = getNextOperandForReg(Op);
1079
21.3M
1080
21.3M
      // All defs come before the uses, so stop def_iterator early.
1081
21.3M
      if (!ReturnUses) {
1082
0
        if (Op) {
1083
0
          if (Op->isUse())
1084
0
            Op = nullptr;
1085
0
          else
1086
0
            assert(!Op->isDebug() && "Can't have debug defs");
1087
0
        }
1088
21.3M
      } else {
1089
21.3M
        // If this is an operand we don't care about, skip it.
1090
23.0M
        while (Op && 
(14.2M
(14.2M
!ReturnDefs14.2M
&&
Op->isDef()14.2M
) ||
1091
14.2M
                      
(12.5M
SkipDebug12.5M
&&
Op->isDebug()0
)))
1092
1.68M
          Op = getNextOperandForReg(Op);
1093
21.3M
      }
1094
21.3M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::advance()
Line
Count
Source
1076
39.9M
    void advance() {
1077
39.9M
      assert(Op && "Cannot increment end iterator!");
1078
39.9M
      Op = getNextOperandForReg(Op);
1079
39.9M
1080
39.9M
      // All defs come before the uses, so stop def_iterator early.
1081
39.9M
      if (!ReturnUses) {
1082
0
        if (Op) {
1083
0
          if (Op->isUse())
1084
0
            Op = nullptr;
1085
0
          else
1086
0
            assert(!Op->isDebug() && "Can't have debug defs");
1087
0
        }
1088
39.9M
      } else {
1089
39.9M
        // If this is an operand we don't care about, skip it.
1090
39.9M
        while (Op && 
(26.2M
(26.2M
!ReturnDefs26.2M
&&
Op->isDef()0
) ||
1091
26.2M
                      (SkipDebug && 
Op->isDebug()0
)))
1092
0
          Op = getNextOperandForReg(Op);
1093
39.9M
      }
1094
39.9M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::advance()
Line
Count
Source
1076
914k
    void advance() {
1077
914k
      assert(Op && "Cannot increment end iterator!");
1078
914k
      Op = getNextOperandForReg(Op);
1079
914k
1080
914k
      // All defs come before the uses, so stop def_iterator early.
1081
914k
      if (!ReturnUses) {
1082
0
        if (Op) {
1083
0
          if (Op->isUse())
1084
0
            Op = nullptr;
1085
0
          else
1086
0
            assert(!Op->isDebug() && "Can't have debug defs");
1087
0
        }
1088
914k
      } else {
1089
914k
        // If this is an operand we don't care about, skip it.
1090
914k
        while (Op && 
(586k
(586k
!ReturnDefs586k
&&
Op->isDef()0
) ||
1091
586k
                      (SkipDebug && 
Op->isDebug()0
)))
1092
0
          Op = getNextOperandForReg(Op);
1093
914k
      }
1094
914k
    }
1095
1096
  public:
1097
    using reference = std::iterator<std::forward_iterator_tag,
1098
                                    MachineInstr, ptrdiff_t>::reference;
1099
    using pointer = std::iterator<std::forward_iterator_tag,
1100
                                  MachineInstr, ptrdiff_t>::pointer;
1101
1102
4.71M
    defusechain_instr_iterator() = default;
1103
1104
122M
    bool operator==(const defusechain_instr_iterator &x) const {
1105
122M
      return Op == x.Op;
1106
122M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false> const&) const
Line
Count
Source
1104
34.2M
    bool operator==(const defusechain_instr_iterator &x) const {
1105
34.2M
      return Op == x.Op;
1106
34.2M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false> const&) const
Line
Count
Source
1104
5.50M
    bool operator==(const defusechain_instr_iterator &x) const {
1105
5.50M
      return Op == x.Op;
1106
5.50M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false> const&) const
Line
Count
Source
1104
21.3M
    bool operator==(const defusechain_instr_iterator &x) const {
1105
21.3M
      return Op == x.Op;
1106
21.3M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false> const&) const
Line
Count
Source
1104
6.68M
    bool operator==(const defusechain_instr_iterator &x) const {
1105
6.68M
      return Op == x.Op;
1106
6.68M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false> const&) const
Line
Count
Source
1104
53.3M
    bool operator==(const defusechain_instr_iterator &x) const {
1105
53.3M
      return Op == x.Op;
1106
53.3M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true> const&) const
Line
Count
Source
1104
1.24M
    bool operator==(const defusechain_instr_iterator &x) const {
1105
1.24M
      return Op == x.Op;
1106
1.24M
    }
1107
122M
    bool operator!=(const defusechain_instr_iterator &x) const {
1108
122M
      return !operator==(x);
1109
122M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false> const&) const
Line
Count
Source
1107
34.2M
    bool operator!=(const defusechain_instr_iterator &x) const {
1108
34.2M
      return !operator==(x);
1109
34.2M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false> const&) const
Line
Count
Source
1107
5.50M
    bool operator!=(const defusechain_instr_iterator &x) const {
1108
5.50M
      return !operator==(x);
1109
5.50M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false> const&) const
Line
Count
Source
1107
21.3M
    bool operator!=(const defusechain_instr_iterator &x) const {
1108
21.3M
      return !operator==(x);
1109
21.3M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false> const&) const
Line
Count
Source
1107
6.68M
    bool operator!=(const defusechain_instr_iterator &x) const {
1108
6.68M
      return !operator==(x);
1109
6.68M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false> const&) const
Line
Count
Source
1107
53.3M
    bool operator!=(const defusechain_instr_iterator &x) const {
1108
53.3M
      return !operator==(x);
1109
53.3M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true> const&) const
Line
Count
Source
1107
1.24M
    bool operator!=(const defusechain_instr_iterator &x) const {
1108
1.24M
      return !operator==(x);
1109
1.24M
    }
1110
1111
    /// atEnd - return true if this iterator is equal to reg_end() on the value.
1112
62.9M
    bool atEnd() const { return Op == nullptr; }
1113
1114
    // Iterator traversal: forward iteration only
1115
66.4M
    defusechain_instr_iterator &operator++() {          // Preincrement
1116
66.4M
      assert(Op && "Cannot increment end iterator!");
1117
66.4M
      if (ByOperand)
1118
0
        advance();
1119
66.4M
      else if (ByInstr) {
1120
65.5M
        MachineInstr *P = Op->getParent();
1121
66.0M
        do {
1122
66.0M
          advance();
1123
66.0M
        } while (Op && 
Op->getParent() == P39.6M
);
1124
65.5M
      } else 
if (913k
ByBundle913k
) {
1125
913k
        MachineBasicBlock::instr_iterator P =
1126
913k
            getBundleStart(Op->getParent()->getIterator());
1127
914k
        do {
1128
914k
          advance();
1129
914k
        } while (Op && 
getBundleStart(Op->getParent()->getIterator()) == P586k
);
1130
913k
      }
1131
66.4M
1132
66.4M
      return *this;
1133
66.4M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator++()
Line
Count
Source
1115
4.83M
    defusechain_instr_iterator &operator++() {          // Preincrement
1116
4.83M
      assert(Op && "Cannot increment end iterator!");
1117
4.83M
      if (ByOperand)
1118
0
        advance();
1119
4.83M
      else if (ByInstr) {
1120
4.83M
        MachineInstr *P = Op->getParent();
1121
4.90M
        do {
1122
4.90M
          advance();
1123
4.90M
        } while (Op && 
Op->getParent() == P3.03M
);
1124
4.83M
      } else 
if (0
ByBundle0
) {
1125
0
        MachineBasicBlock::instr_iterator P =
1126
0
            getBundleStart(Op->getParent()->getIterator());
1127
0
        do {
1128
0
          advance();
1129
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1130
0
      }
1131
4.83M
1132
4.83M
      return *this;
1133
4.83M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator++()
Line
Count
Source
1115
4.58M
    defusechain_instr_iterator &operator++() {          // Preincrement
1116
4.58M
      assert(Op && "Cannot increment end iterator!");
1117
4.58M
      if (ByOperand)
1118
0
        advance();
1119
4.58M
      else if (ByInstr) {
1120
4.58M
        MachineInstr *P = Op->getParent();
1121
4.61M
        do {
1122
4.61M
          advance();
1123
4.61M
        } while (Op && 
Op->getParent() == P3.67M
);
1124
4.58M
      } else 
if (0
ByBundle0
) {
1125
0
        MachineBasicBlock::instr_iterator P =
1126
0
            getBundleStart(Op->getParent()->getIterator());
1127
0
        do {
1128
0
          advance();
1129
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1130
0
      }
1131
4.58M
1132
4.58M
      return *this;
1133
4.58M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator++()
Line
Count
Source
1115
12.4M
    defusechain_instr_iterator &operator++() {          // Preincrement
1116
12.4M
      assert(Op && "Cannot increment end iterator!");
1117
12.4M
      if (ByOperand)
1118
0
        advance();
1119
12.4M
      else if (ByInstr) {
1120
12.4M
        MachineInstr *P = Op->getParent();
1121
12.4M
        do {
1122
12.4M
          advance();
1123
12.4M
        } while (Op && 
Op->getParent() == P6.58M
);
1124
12.4M
      } else 
if (0
ByBundle0
) {
1125
0
        MachineBasicBlock::instr_iterator P =
1126
0
            getBundleStart(Op->getParent()->getIterator());
1127
0
        do {
1128
0
          advance();
1129
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1130
0
      }
1131
12.4M
1132
12.4M
      return *this;
1133
12.4M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator++()
Line
Count
Source
1115
4.17M
    defusechain_instr_iterator &operator++() {          // Preincrement
1116
4.17M
      assert(Op && "Cannot increment end iterator!");
1117
4.17M
      if (ByOperand)
1118
0
        advance();
1119
4.17M
      else if (ByInstr) {
1120
4.17M
        MachineInstr *P = Op->getParent();
1121
4.17M
        do {
1122
4.17M
          advance();
1123
4.17M
        } while (Op && 
Op->getParent() == P89.0k
);
1124
4.17M
      } else 
if (0
ByBundle0
) {
1125
0
        MachineBasicBlock::instr_iterator P =
1126
0
            getBundleStart(Op->getParent()->getIterator());
1127
0
        do {
1128
0
          advance();
1129
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1130
0
      }
1131
4.17M
1132
4.17M
      return *this;
1133
4.17M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator++()
Line
Count
Source
1115
39.4M
    defusechain_instr_iterator &operator++() {          // Preincrement
1116
39.4M
      assert(Op && "Cannot increment end iterator!");
1117
39.4M
      if (ByOperand)
1118
0
        advance();
1119
39.4M
      else if (ByInstr) {
1120
39.4M
        MachineInstr *P = Op->getParent();
1121
39.9M
        do {
1122
39.9M
          advance();
1123
39.9M
        } while (Op && 
Op->getParent() == P26.2M
);
1124
39.4M
      } else 
if (0
ByBundle0
) {
1125
0
        MachineBasicBlock::instr_iterator P =
1126
0
            getBundleStart(Op->getParent()->getIterator());
1127
0
        do {
1128
0
          advance();
1129
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1130
0
      }
1131
39.4M
1132
39.4M
      return *this;
1133
39.4M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator++()
Line
Count
Source
1115
913k
    defusechain_instr_iterator &operator++() {          // Preincrement
1116
913k
      assert(Op && "Cannot increment end iterator!");
1117
913k
      if (ByOperand)
1118
0
        advance();
1119
913k
      else if (ByInstr) {
1120
0
        MachineInstr *P = Op->getParent();
1121
0
        do {
1122
0
          advance();
1123
0
        } while (Op && Op->getParent() == P);
1124
913k
      } else if (ByBundle) {
1125
913k
        MachineBasicBlock::instr_iterator P =
1126
913k
            getBundleStart(Op->getParent()->getIterator());
1127
914k
        do {
1128
914k
          advance();
1129
914k
        } while (Op && 
getBundleStart(Op->getParent()->getIterator()) == P586k
);
1130
913k
      }
1131
913k
1132
913k
      return *this;
1133
913k
    }
1134
36.7M
    defusechain_instr_iterator operator++(int) {        // Postincrement
1135
36.7M
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1136
36.7M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator++(int)
Line
Count
Source
1134
35.0M
    defusechain_instr_iterator operator++(int) {        // Postincrement
1135
35.0M
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1136
35.0M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator++(int)
Line
Count
Source
1134
174k
    defusechain_instr_iterator operator++(int) {        // Postincrement
1135
174k
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1136
174k
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator++(int)
Line
Count
Source
1134
913k
    defusechain_instr_iterator operator++(int) {        // Postincrement
1135
913k
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1136
913k
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator++(int)
Line
Count
Source
1134
642k
    defusechain_instr_iterator operator++(int) {        // Postincrement
1135
642k
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1136
642k
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator++(int)
Line
Count
Source
1134
246
    defusechain_instr_iterator operator++(int) {        // Postincrement
1135
246
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1136
246
    }
1137
1138
    // Retrieve a reference to the current operand.
1139
160M
    MachineInstr &operator*() const {
1140
160M
      assert(Op && "Cannot dereference end iterator!");
1141
160M
      if (ByBundle)
1142
913k
        return *getBundleStart(Op->getParent()->getIterator());
1143
159M
      return *Op->getParent();
1144
159M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator*() const
Line
Count
Source
1139
69.6M
    MachineInstr &operator*() const {
1140
69.6M
      assert(Op && "Cannot dereference end iterator!");
1141
69.6M
      if (ByBundle)
1142
0
        return *getBundleStart(Op->getParent()->getIterator());
1143
69.6M
      return *Op->getParent();
1144
69.6M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator*() const
Line
Count
Source
1139
33.4M
    MachineInstr &operator*() const {
1140
33.4M
      assert(Op && "Cannot dereference end iterator!");
1141
33.4M
      if (ByBundle)
1142
0
        return *getBundleStart(Op->getParent()->getIterator());
1143
33.4M
      return *Op->getParent();
1144
33.4M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator*() const
Line
Count
Source
1139
4.58M
    MachineInstr &operator*() const {
1140
4.58M
      assert(Op && "Cannot dereference end iterator!");
1141
4.58M
      if (ByBundle)
1142
0
        return *getBundleStart(Op->getParent()->getIterator());
1143
4.58M
      return *Op->getParent();
1144
4.58M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator*() const
Line
Count
Source
1139
12.5M
    MachineInstr &operator*() const {
1140
12.5M
      assert(Op && "Cannot dereference end iterator!");
1141
12.5M
      if (ByBundle)
1142
0
        return *getBundleStart(Op->getParent()->getIterator());
1143
12.5M
      return *Op->getParent();
1144
12.5M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator*() const
Line
Count
Source
1139
39.4M
    MachineInstr &operator*() const {
1140
39.4M
      assert(Op && "Cannot dereference end iterator!");
1141
39.4M
      if (ByBundle)
1142
0
        return *getBundleStart(Op->getParent()->getIterator());
1143
39.4M
      return *Op->getParent();
1144
39.4M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator*() const
Line
Count
Source
1139
913k
    MachineInstr &operator*() const {
1140
913k
      assert(Op && "Cannot dereference end iterator!");
1141
913k
      if (ByBundle)
1142
913k
        return *getBundleStart(Op->getParent()->getIterator());
1143
0
      return *Op->getParent();
1144
0
    }
1145
1146
2.76k
    MachineInstr *operator->() const { return &operator*(); }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator->() const
Line
Count
Source
1146
918
    MachineInstr *operator->() const { return &operator*(); }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator->() const
Line
Count
Source
1146
60
    MachineInstr *operator->() const { return &operator*(); }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator->() const
Line
Count
Source
1146
1.78k
    MachineInstr *operator->() const { return &operator*(); }
1147
  };
1148
};
1149
1150
/// Iterate over the pressure sets affected by the given physical or virtual
1151
/// register. If Reg is physical, it must be a register unit (from
1152
/// MCRegUnitIterator).
1153
class PSetIterator {
1154
  const int *PSet = nullptr;
1155
  unsigned Weight = 0;
1156
1157
public:
1158
  PSetIterator() = default;
1159
1160
41.2M
  PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
1161
41.2M
    const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1162
41.2M
    if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
1163
38.4M
      const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
1164
38.4M
      PSet = TRI->getRegClassPressureSets(RC);
1165
38.4M
      Weight = TRI->getRegClassWeight(RC).RegWeight;
1166
38.4M
    }
1167
2.82M
    else {
1168
2.82M
      PSet = TRI->getRegUnitPressureSets(RegUnit);
1169
2.82M
      Weight = TRI->getRegUnitWeight(RegUnit);
1170
2.82M
    }
1171
41.2M
    if (*PSet == -1)
1172
346k
      PSet = nullptr;
1173
41.2M
  }
1174
1175
141M
  bool isValid() const { return PSet; }
1176
1177
41.2M
  unsigned getWeight() const { return Weight; }
1178
1179
328M
  unsigned operator*() const { return *PSet; }
1180
1181
101M
  void operator++() {
1182
101M
    assert(isValid() && "Invalid PSetIterator.");
1183
101M
    ++PSet;
1184
101M
    if (*PSet == -1)
1185
40.2M
      PSet = nullptr;
1186
101M
  }
1187
};
1188
1189
inline PSetIterator MachineRegisterInfo::
1190
41.2M
getPressureSets(unsigned RegUnit) const {
1191
41.2M
  return PSetIterator(RegUnit, this);
1192
41.2M
}
1193
1194
} // end namespace llvm
1195
1196
#endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H