Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/MachineRegisterInfo.h
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//===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the MachineRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
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#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/PointerUnion.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringSet.h"
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#include "llvm/ADT/iterator_range.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/LowLevelType.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/MC/LaneBitmask.h"
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#include <cassert>
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#include <cstddef>
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#include <cstdint>
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#include <iterator>
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#include <memory>
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#include <utility>
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#include <vector>
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namespace llvm {
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43
class PSetIterator;
44
45
/// Convenient type to represent either a register class or a register bank.
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using RegClassOrRegBank =
47
    PointerUnion<const TargetRegisterClass *, const RegisterBank *>;
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49
/// MachineRegisterInfo - Keep track of information for virtual and physical
50
/// registers, including vreg register classes, use/def chains for registers,
51
/// etc.
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class MachineRegisterInfo {
53
public:
54
  class Delegate {
55
    virtual void anchor();
56
57
  public:
58
1.40M
    virtual ~Delegate() = default;
59
60
    virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
61
  };
62
63
private:
64
  MachineFunction *MF;
65
  Delegate *TheDelegate = nullptr;
66
67
  /// True if subregister liveness is tracked.
68
  const bool TracksSubRegLiveness;
69
70
  /// VRegInfo - Information we keep for each virtual register.
71
  ///
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  /// Each element in this list contains the register class of the vreg and the
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  /// start of the use/def list for the register.
74
  IndexedMap<std::pair<RegClassOrRegBank, MachineOperand *>,
75
             VirtReg2IndexFunctor>
76
      VRegInfo;
77
78
  /// Map for recovering vreg name from vreg number.
79
  /// This map is used by the MIR Printer.
80
  IndexedMap<std::string, VirtReg2IndexFunctor> VReg2Name;
81
82
  /// StringSet that is used to unique vreg names.
83
  StringSet<> VRegNames;
84
85
  /// The flag is true upon \p UpdatedCSRs initialization
86
  /// and false otherwise.
87
  bool IsUpdatedCSRsInitialized;
88
89
  /// Contains the updated callee saved register list.
90
  /// As opposed to the static list defined in register info,
91
  /// all registers that were disabled are removed from the list.
92
  SmallVector<MCPhysReg, 16> UpdatedCSRs;
93
94
  /// RegAllocHints - This vector records register allocation hints for
95
  /// virtual registers. For each virtual register, it keeps a pair of hint
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  /// type and hints vector making up the allocation hints. Only the first
97
  /// hint may be target specific, and in that case this is reflected by the
98
  /// first member of the pair being non-zero. If the hinted register is
99
  /// virtual, it means the allocator should prefer the physical register
100
  /// allocated to it if any.
101
  IndexedMap<std::pair<unsigned, SmallVector<unsigned, 4>>,
102
             VirtReg2IndexFunctor> RegAllocHints;
103
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  /// PhysRegUseDefLists - This is an array of the head of the use/def list for
105
  /// physical registers.
106
  std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
107
108
  /// getRegUseDefListHead - Return the head pointer for the register use/def
109
  /// list for the specified virtual or physical register.
110
331M
  MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
111
331M
    if (TargetRegisterInfo::isVirtualRegister(RegNo))
112
162M
      return VRegInfo[RegNo].second;
113
168M
    return PhysRegUseDefLists[RegNo];
114
168M
  }
115
116
1.51G
  MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
117
1.51G
    if (TargetRegisterInfo::isVirtualRegister(RegNo))
118
466M
      return VRegInfo[RegNo].second;
119
1.05G
    return PhysRegUseDefLists[RegNo];
120
1.05G
  }
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122
  /// Get the next element in the use-def chain.
123
491M
  static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
124
491M
    assert(MO && MO->isReg() && "This is not a register operand!");
125
491M
    return MO->Contents.Reg.Next;
126
491M
  }
127
128
  /// UsedPhysRegMask - Additional used physregs including aliases.
129
  /// This bit vector represents all the registers clobbered by function calls.
130
  BitVector UsedPhysRegMask;
131
132
  /// ReservedRegs - This is a bit vector of reserved registers.  The target
133
  /// may change its mind about which registers should be reserved.  This
134
  /// vector is the frozen set of reserved registers when register allocation
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  /// started.
136
  BitVector ReservedRegs;
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  using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;
139
  /// Map generic virtual registers to their low-level type.
140
  VRegToTypeMap VRegToType;
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  /// Keep track of the physical registers that are live in to the function.
143
  /// Live in values are typically arguments in registers.  LiveIn values are
144
  /// allowed to have virtual registers associated with them, stored in the
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  /// second element.
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  std::vector<std::pair<unsigned, unsigned>> LiveIns;
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public:
149
  explicit MachineRegisterInfo(MachineFunction *MF);
150
  MachineRegisterInfo(const MachineRegisterInfo &) = delete;
151
  MachineRegisterInfo &operator=(const MachineRegisterInfo &) = delete;
152
153
160M
  const TargetRegisterInfo *getTargetRegisterInfo() const {
154
160M
    return MF->getSubtarget().getRegisterInfo();
155
160M
  }
156
157
1.40M
  void resetDelegate(Delegate *delegate) {
158
1.40M
    // Ensure another delegate does not take over unless the current
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1.40M
    // delegate first unattaches itself. If we ever need to multicast
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1.40M
    // notifications, we will need to change to using a list.
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1.40M
    assert(TheDelegate == delegate &&
162
1.40M
           "Only the current delegate can perform reset!");
163
1.40M
    TheDelegate = nullptr;
164
1.40M
  }
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166
1.40M
  void setDelegate(Delegate *delegate) {
167
1.40M
    assert(delegate && !TheDelegate &&
168
1.40M
           "Attempted to set delegate to null, or to change it without "
169
1.40M
           "first resetting it!");
170
1.40M
171
1.40M
    TheDelegate = delegate;
172
1.40M
  }
173
174
  //===--------------------------------------------------------------------===//
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  // Function State
176
  //===--------------------------------------------------------------------===//
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  // isSSA - Returns true when the machine function is in SSA form. Early
179
  // passes require the machine function to be in SSA form where every virtual
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  // register has a single defining instruction.
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  //
182
  // The TwoAddressInstructionPass and PHIElimination passes take the machine
183
  // function out of SSA form when they introduce multiple defs per virtual
184
  // register.
185
117M
  bool isSSA() const {
186
117M
    return MF->getProperties().hasProperty(
187
117M
        MachineFunctionProperties::Property::IsSSA);
188
117M
  }
189
190
  // leaveSSA - Indicates that the machine function is no longer in SSA form.
191
1.01M
  void leaveSSA() {
192
1.01M
    MF->getProperties().reset(MachineFunctionProperties::Property::IsSSA);
193
1.01M
  }
194
195
  /// tracksLiveness - Returns true when tracking register liveness accurately.
196
  /// (see MachineFUnctionProperties::Property description for details)
197
89.0M
  bool tracksLiveness() const {
198
89.0M
    return MF->getProperties().hasProperty(
199
89.0M
        MachineFunctionProperties::Property::TracksLiveness);
200
89.0M
  }
201
202
  /// invalidateLiveness - Indicates that register liveness is no longer being
203
  /// tracked accurately.
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  ///
205
  /// This should be called by late passes that invalidate the liveness
206
  /// information.
207
71.4k
  void invalidateLiveness() {
208
71.4k
    MF->getProperties().reset(
209
71.4k
        MachineFunctionProperties::Property::TracksLiveness);
210
71.4k
  }
211
212
  /// Returns true if liveness for register class @p RC should be tracked at
213
  /// the subregister level.
214
33.8M
  bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const {
215
33.8M
    return subRegLivenessEnabled() && 
RC.HasDisjunctSubRegs3.31M
;
216
33.8M
  }
217
29.8M
  bool shouldTrackSubRegLiveness(unsigned VReg) const {
218
29.8M
    assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Must pass a VReg");
219
29.8M
    return shouldTrackSubRegLiveness(*getRegClass(VReg));
220
29.8M
  }
221
51.4M
  bool subRegLivenessEnabled() const {
222
51.4M
    return TracksSubRegLiveness;
223
51.4M
  }
224
225
  //===--------------------------------------------------------------------===//
226
  // Register Info
227
  //===--------------------------------------------------------------------===//
228
229
  /// Returns true if the updated CSR list was initialized and false otherwise.
230
11.9k
  bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
231
232
  /// Disables the register from the list of CSRs.
233
  /// I.e. the register will not appear as part of the CSR mask.
234
  /// \see UpdatedCalleeSavedRegs.
235
  void disableCalleeSavedRegister(unsigned Reg);
236
237
  /// Returns list of callee saved registers.
238
  /// The function returns the updated CSR list (after taking into account
239
  /// registers that are disabled from the CSR list).
240
  const MCPhysReg *getCalleeSavedRegs() const;
241
242
  /// Sets the updated Callee Saved Registers list.
243
  /// Notice that it will override ant previously disabled/saved CSRs.
244
  void setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs);
245
246
  // Strictly for use by MachineInstr.cpp.
247
  void addRegOperandToUseList(MachineOperand *MO);
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249
  // Strictly for use by MachineInstr.cpp.
250
  void removeRegOperandFromUseList(MachineOperand *MO);
251
252
  // Strictly for use by MachineInstr.cpp.
253
  void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
254
255
  /// Verify the sanity of the use list for Reg.
256
  void verifyUseList(unsigned Reg) const;
257
258
  /// Verify the use list of all registers.
259
  void verifyUseLists() const;
260
261
  /// reg_begin/reg_end - Provide iteration support to walk over all definitions
262
  /// and uses of a register within the MachineFunction that corresponds to this
263
  /// MachineRegisterInfo object.
264
  template<bool Uses, bool Defs, bool SkipDebug,
265
           bool ByOperand, bool ByInstr, bool ByBundle>
266
  class defusechain_iterator;
267
  template<bool Uses, bool Defs, bool SkipDebug,
268
           bool ByOperand, bool ByInstr, bool ByBundle>
269
  class defusechain_instr_iterator;
270
271
  // Make it a friend so it can access getNextOperandForReg().
272
  template<bool, bool, bool, bool, bool, bool>
273
    friend class defusechain_iterator;
274
  template<bool, bool, bool, bool, bool, bool>
275
    friend class defusechain_instr_iterator;
276
277
  /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
278
  /// register.
279
  using reg_iterator =
280
      defusechain_iterator<true, true, false, true, false, false>;
281
58.8M
  reg_iterator reg_begin(unsigned RegNo) const {
282
58.8M
    return reg_iterator(getRegUseDefListHead(RegNo));
283
58.8M
  }
284
58.8M
  static reg_iterator reg_end() { return reg_iterator(nullptr); }
285
286
305k
  inline iterator_range<reg_iterator>  reg_operands(unsigned Reg) const {
287
305k
    return make_range(reg_begin(Reg), reg_end());
288
305k
  }
289
290
  /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
291
  /// of the specified register, stepping by MachineInstr.
292
  using reg_instr_iterator =
293
      defusechain_instr_iterator<true, true, false, false, true, false>;
294
13.1M
  reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
295
13.1M
    return reg_instr_iterator(getRegUseDefListHead(RegNo));
296
13.1M
  }
297
13.1M
  static reg_instr_iterator reg_instr_end() {
298
13.1M
    return reg_instr_iterator(nullptr);
299
13.1M
  }
300
301
  inline iterator_range<reg_instr_iterator>
302
770k
  reg_instructions(unsigned Reg) const {
303
770k
    return make_range(reg_instr_begin(Reg), reg_instr_end());
304
770k
  }
305
306
  /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
307
  /// of the specified register, stepping by bundle.
308
  using reg_bundle_iterator =
309
      defusechain_instr_iterator<true, true, false, false, false, true>;
310
286k
  reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
311
286k
    return reg_bundle_iterator(getRegUseDefListHead(RegNo));
312
286k
  }
313
286k
  static reg_bundle_iterator reg_bundle_end() {
314
286k
    return reg_bundle_iterator(nullptr);
315
286k
  }
316
317
0
  inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const {
318
0
    return make_range(reg_bundle_begin(Reg), reg_bundle_end());
319
0
  }
320
321
  /// reg_empty - Return true if there are no instructions using or defining the
322
  /// specified register (it may be live-in).
323
56.5M
  bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
324
325
  /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
326
  /// of the specified register, skipping those marked as Debug.
327
  using reg_nodbg_iterator =
328
      defusechain_iterator<true, true, true, true, false, false>;
329
927M
  reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
330
927M
    return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
331
927M
  }
332
927M
  static reg_nodbg_iterator reg_nodbg_end() {
333
927M
    return reg_nodbg_iterator(nullptr);
334
927M
  }
335
336
  inline iterator_range<reg_nodbg_iterator>
337
28.5M
  reg_nodbg_operands(unsigned Reg) const {
338
28.5M
    return make_range(reg_nodbg_begin(Reg), reg_nodbg_end());
339
28.5M
  }
340
341
  /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
342
  /// all defs and uses of the specified register, stepping by MachineInstr,
343
  /// skipping those marked as Debug.
344
  using reg_instr_nodbg_iterator =
345
      defusechain_instr_iterator<true, true, true, false, true, false>;
346
1.05M
  reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const {
347
1.05M
    return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
348
1.05M
  }
349
1.05M
  static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
350
1.05M
    return reg_instr_nodbg_iterator(nullptr);
351
1.05M
  }
352
353
  inline iterator_range<reg_instr_nodbg_iterator>
354
988k
  reg_nodbg_instructions(unsigned Reg) const {
355
988k
    return make_range(reg_instr_nodbg_begin(Reg), reg_instr_nodbg_end());
356
988k
  }
357
358
  /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
359
  /// all defs and uses of the specified register, stepping by bundle,
360
  /// skipping those marked as Debug.
361
  using reg_bundle_nodbg_iterator =
362
      defusechain_instr_iterator<true, true, true, false, false, true>;
363
0
  reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const {
364
0
    return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
365
0
  }
366
0
  static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
367
0
    return reg_bundle_nodbg_iterator(nullptr);
368
0
  }
369
370
  inline iterator_range<reg_bundle_nodbg_iterator>
371
0
  reg_nodbg_bundles(unsigned Reg) const {
372
0
    return make_range(reg_bundle_nodbg_begin(Reg), reg_bundle_nodbg_end());
373
0
  }
374
375
  /// reg_nodbg_empty - Return true if the only instructions using or defining
376
  /// Reg are Debug instructions.
377
899M
  bool reg_nodbg_empty(unsigned RegNo) const {
378
899M
    return reg_nodbg_begin(RegNo) == reg_nodbg_end();
379
899M
  }
380
381
  /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
382
  using def_iterator =
383
      defusechain_iterator<false, true, false, true, false, false>;
384
264M
  def_iterator def_begin(unsigned RegNo) const {
385
264M
    return def_iterator(getRegUseDefListHead(RegNo));
386
264M
  }
387
260M
  static def_iterator def_end() { return def_iterator(nullptr); }
388
389
2.92M
  inline iterator_range<def_iterator> def_operands(unsigned Reg) const {
390
2.92M
    return make_range(def_begin(Reg), def_end());
391
2.92M
  }
392
393
  /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
394
  /// specified register, stepping by MachineInst.
395
  using def_instr_iterator =
396
      defusechain_instr_iterator<false, true, false, false, true, false>;
397
71.4M
  def_instr_iterator def_instr_begin(unsigned RegNo) const {
398
71.4M
    return def_instr_iterator(getRegUseDefListHead(RegNo));
399
71.4M
  }
400
5.85M
  static def_instr_iterator def_instr_end() {
401
5.85M
    return def_instr_iterator(nullptr);
402
5.85M
  }
403
404
  inline iterator_range<def_instr_iterator>
405
2.44M
  def_instructions(unsigned Reg) const {
406
2.44M
    return make_range(def_instr_begin(Reg), def_instr_end());
407
2.44M
  }
408
409
  /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
410
  /// specified register, stepping by bundle.
411
  using def_bundle_iterator =
412
      defusechain_instr_iterator<false, true, false, false, false, true>;
413
0
  def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
414
0
    return def_bundle_iterator(getRegUseDefListHead(RegNo));
415
0
  }
416
0
  static def_bundle_iterator def_bundle_end() {
417
0
    return def_bundle_iterator(nullptr);
418
0
  }
419
420
0
  inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const {
421
0
    return make_range(def_bundle_begin(Reg), def_bundle_end());
422
0
  }
423
424
  /// def_empty - Return true if there are no instructions defining the
425
  /// specified register (it may be live-in).
426
39.5M
  bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
427
428
259k
  StringRef getVRegName(unsigned Reg) const {
429
259k
    return VReg2Name.inBounds(Reg) ? 
StringRef(VReg2Name[Reg])370
:
""259k
;
430
259k
  }
431
432
22.7M
  void insertVRegByName(StringRef Name, unsigned Reg) {
433
22.7M
    assert((Name.empty() || VRegNames.find(Name) == VRegNames.end()) &&
434
22.7M
           "Named VRegs Must be Unique.");
435
22.7M
    if (!Name.empty()) {
436
100
      VRegNames.insert(Name);
437
100
      VReg2Name.grow(Reg);
438
100
      VReg2Name[Reg] = Name.str();
439
100
    }
440
22.7M
  }
441
442
  /// Return true if there is exactly one operand defining the specified
443
  /// register.
444
9.16M
  bool hasOneDef(unsigned RegNo) const {
445
9.16M
    def_iterator DI = def_begin(RegNo);
446
9.16M
    if (DI == def_end())
447
447k
      return false;
448
8.71M
    return ++DI == def_end();
449
8.71M
  }
450
451
  /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
452
  using use_iterator =
453
      defusechain_iterator<true, false, false, true, false, false>;
454
11.6M
  use_iterator use_begin(unsigned RegNo) const {
455
11.6M
    return use_iterator(getRegUseDefListHead(RegNo));
456
11.6M
  }
457
13.1M
  static use_iterator use_end() { return use_iterator(nullptr); }
458
459
9.08M
  inline iterator_range<use_iterator> use_operands(unsigned Reg) const {
460
9.08M
    return make_range(use_begin(Reg), use_end());
461
9.08M
  }
462
463
  /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
464
  /// specified register, stepping by MachineInstr.
465
  using use_instr_iterator =
466
      defusechain_instr_iterator<true, false, false, false, true, false>;
467
10.3M
  use_instr_iterator use_instr_begin(unsigned RegNo) const {
468
10.3M
    return use_instr_iterator(getRegUseDefListHead(RegNo));
469
10.3M
  }
470
10.3M
  static use_instr_iterator use_instr_end() {
471
10.3M
    return use_instr_iterator(nullptr);
472
10.3M
  }
473
474
  inline iterator_range<use_instr_iterator>
475
5.08M
  use_instructions(unsigned Reg) const {
476
5.08M
    return make_range(use_instr_begin(Reg), use_instr_end());
477
5.08M
  }
478
479
  /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
480
  /// specified register, stepping by bundle.
481
  using use_bundle_iterator =
482
      defusechain_instr_iterator<true, false, false, false, false, true>;
483
0
  use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
484
0
    return use_bundle_iterator(getRegUseDefListHead(RegNo));
485
0
  }
486
0
  static use_bundle_iterator use_bundle_end() {
487
0
    return use_bundle_iterator(nullptr);
488
0
  }
489
490
0
  inline iterator_range<use_bundle_iterator> use_bundles(unsigned Reg) const {
491
0
    return make_range(use_bundle_begin(Reg), use_bundle_end());
492
0
  }
493
494
  /// use_empty - Return true if there are no instructions using the specified
495
  /// register.
496
304k
  bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
497
498
  /// hasOneUse - Return true if there is exactly one instruction using the
499
  /// specified register.
500
1.51M
  bool hasOneUse(unsigned RegNo) const {
501
1.51M
    use_iterator UI = use_begin(RegNo);
502
1.51M
    if (UI == use_end())
503
41
      return false;
504
1.51M
    return ++UI == use_end();
505
1.51M
  }
506
507
  /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
508
  /// specified register, skipping those marked as Debug.
509
  using use_nodbg_iterator =
510
      defusechain_iterator<true, false, true, true, false, false>;
511
129M
  use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
512
129M
    return use_nodbg_iterator(getRegUseDefListHead(RegNo));
513
129M
  }
514
149M
  static use_nodbg_iterator use_nodbg_end() {
515
149M
    return use_nodbg_iterator(nullptr);
516
149M
  }
517
518
  inline iterator_range<use_nodbg_iterator>
519
37.5M
  use_nodbg_operands(unsigned Reg) const {
520
37.5M
    return make_range(use_nodbg_begin(Reg), use_nodbg_end());
521
37.5M
  }
522
523
  /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
524
  /// all uses of the specified register, stepping by MachineInstr, skipping
525
  /// those marked as Debug.
526
  using use_instr_nodbg_iterator =
527
      defusechain_instr_iterator<true, false, true, false, true, false>;
528
30.3M
  use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const {
529
30.3M
    return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
530
30.3M
  }
531
28.2M
  static use_instr_nodbg_iterator use_instr_nodbg_end() {
532
28.2M
    return use_instr_nodbg_iterator(nullptr);
533
28.2M
  }
534
535
  inline iterator_range<use_instr_nodbg_iterator>
536
27.6M
  use_nodbg_instructions(unsigned Reg) const {
537
27.6M
    return make_range(use_instr_nodbg_begin(Reg), use_instr_nodbg_end());
538
27.6M
  }
539
540
  /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
541
  /// all uses of the specified register, stepping by bundle, skipping
542
  /// those marked as Debug.
543
  using use_bundle_nodbg_iterator =
544
      defusechain_instr_iterator<true, false, true, false, false, true>;
545
0
  use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const {
546
0
    return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
547
0
  }
548
0
  static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
549
0
    return use_bundle_nodbg_iterator(nullptr);
550
0
  }
551
552
  inline iterator_range<use_bundle_nodbg_iterator>
553
0
  use_nodbg_bundles(unsigned Reg) const {
554
0
    return make_range(use_bundle_nodbg_begin(Reg), use_bundle_nodbg_end());
555
0
  }
556
557
  /// use_nodbg_empty - Return true if there are no non-Debug instructions
558
  /// using the specified register.
559
73.0M
  bool use_nodbg_empty(unsigned RegNo) const {
560
73.0M
    return use_nodbg_begin(RegNo) == use_nodbg_end();
561
73.0M
  }
562
563
  /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
564
  /// use of the specified register.
565
  bool hasOneNonDBGUse(unsigned RegNo) const;
566
567
  /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
568
  /// instruction using the specified register. Said instruction may have
569
  /// multiple uses.
570
  bool hasOneNonDBGUser(unsigned RegNo) const;
571
  
572
  /// replaceRegWith - Replace all instances of FromReg with ToReg in the
573
  /// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
574
  /// except that it also changes any definitions of the register as well.
575
  ///
576
  /// Note that it is usually necessary to first constrain ToReg's register
577
  /// class and register bank to match the FromReg constraints using one of the
578
  /// methods:
579
  ///
580
  ///   constrainRegClass(ToReg, getRegClass(FromReg))
581
  ///   constrainRegAttrs(ToReg, FromReg)
582
  ///   RegisterBankInfo::constrainGenericRegister(ToReg,
583
  ///       *MRI.getRegClass(FromReg), MRI)
584
  ///
585
  /// These functions will return a falsy result if the virtual registers have
586
  /// incompatible constraints.
587
  ///
588
  /// Note that if ToReg is a physical register the function will replace and
589
  /// apply sub registers to ToReg in order to obtain a final/proper physical
590
  /// register.
591
  void replaceRegWith(unsigned FromReg, unsigned ToReg);
592
593
  /// getVRegDef - Return the machine instr that defines the specified virtual
594
  /// register or null if none is found.  This assumes that the code is in SSA
595
  /// form, so there should only be one definition.
596
  MachineInstr *getVRegDef(unsigned Reg) const;
597
598
  /// getUniqueVRegDef - Return the unique machine instr that defines the
599
  /// specified virtual register or null if none is found.  If there are
600
  /// multiple definitions or no definition, return null.
601
  MachineInstr *getUniqueVRegDef(unsigned Reg) const;
602
603
  /// clearKillFlags - Iterate over all the uses of the given register and
604
  /// clear the kill flag from the MachineOperand. This function is used by
605
  /// optimization passes which extend register lifetimes and need only
606
  /// preserve conservative kill flag information.
607
  void clearKillFlags(unsigned Reg) const;
608
609
  void dumpUses(unsigned RegNo) const;
610
611
  /// Returns true if PhysReg is unallocatable and constant throughout the
612
  /// function. Writing to a constant register has no effect.
613
  bool isConstantPhysReg(unsigned PhysReg) const;
614
615
  /// Returns true if either isConstantPhysReg or TRI->isCallerPreservedPhysReg
616
  /// returns true. This is a utility member function.
617
  bool isCallerPreservedOrConstPhysReg(unsigned PhysReg) const;
618
619
  /// Get an iterator over the pressure sets affected by the given physical or
620
  /// virtual register. If RegUnit is physical, it must be a register unit (from
621
  /// MCRegUnitIterator).
622
  PSetIterator getPressureSets(unsigned RegUnit) const;
623
624
  //===--------------------------------------------------------------------===//
625
  // Virtual Register Info
626
  //===--------------------------------------------------------------------===//
627
628
  /// Return the register class of the specified virtual register.
629
  /// This shouldn't be used directly unless \p Reg has a register class.
630
  /// \see getRegClassOrNull when this might happen.
631
196M
  const TargetRegisterClass *getRegClass(unsigned Reg) const {
632
196M
    assert(VRegInfo[Reg].first.is<const TargetRegisterClass *>() &&
633
196M
           "Register class not set, wrong accessor");
634
196M
    return VRegInfo[Reg].first.get<const TargetRegisterClass *>();
635
196M
  }
636
637
  /// Return the register class of \p Reg, or null if Reg has not been assigned
638
  /// a register class yet.
639
  ///
640
  /// \note A null register class can only happen when these two
641
  /// conditions are met:
642
  /// 1. Generic virtual registers are created.
643
  /// 2. The machine function has not completely been through the
644
  ///    instruction selection process.
645
  /// None of this condition is possible without GlobalISel for now.
646
  /// In other words, if GlobalISel is not used or if the query happens after
647
  /// the select pass, using getRegClass is safe.
648
60.0M
  const TargetRegisterClass *getRegClassOrNull(unsigned Reg) const {
649
60.0M
    const RegClassOrRegBank &Val = VRegInfo[Reg].first;
650
60.0M
    return Val.dyn_cast<const TargetRegisterClass *>();
651
60.0M
  }
652
653
  /// Return the register bank of \p Reg, or null if Reg has not been assigned
654
  /// a register bank or has been assigned a register class.
655
  /// \note It is possible to get the register bank from the register class via
656
  /// RegisterBankInfo::getRegBankFromRegClass.
657
24.9M
  const RegisterBank *getRegBankOrNull(unsigned Reg) const {
658
24.9M
    const RegClassOrRegBank &Val = VRegInfo[Reg].first;
659
24.9M
    return Val.dyn_cast<const RegisterBank *>();
660
24.9M
  }
661
662
  /// Return the register bank or register class of \p Reg.
663
  /// \note Before the register bank gets assigned (i.e., before the
664
  /// RegBankSelect pass) \p Reg may not have either.
665
66.5M
  const RegClassOrRegBank &getRegClassOrRegBank(unsigned Reg) const {
666
66.5M
    return VRegInfo[Reg].first;
667
66.5M
  }
668
669
  /// setRegClass - Set the register class of the specified virtual register.
670
  void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
671
672
  /// Set the register bank to \p RegBank for \p Reg.
673
  void setRegBank(unsigned Reg, const RegisterBank &RegBank);
674
675
  void setRegClassOrRegBank(unsigned Reg,
676
2.18k
                            const RegClassOrRegBank &RCOrRB){
677
2.18k
    VRegInfo[Reg].first = RCOrRB;
678
2.18k
  }
679
680
  /// constrainRegClass - Constrain the register class of the specified virtual
681
  /// register to be a common subclass of RC and the current register class,
682
  /// but only if the new class has at least MinNumRegs registers.  Return the
683
  /// new register class, or NULL if no such class exists.
684
  /// This should only be used when the constraint is known to be trivial, like
685
  /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
686
  ///
687
  /// \note Assumes that the register has a register class assigned.
688
  /// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's
689
  /// InstructionSelect pass and constrainRegAttrs in every other pass,
690
  /// including non-select passes of GlobalISel, instead.
691
  const TargetRegisterClass *constrainRegClass(unsigned Reg,
692
                                               const TargetRegisterClass *RC,
693
                                               unsigned MinNumRegs = 0);
694
695
  /// Constrain the register class or the register bank of the virtual register
696
  /// \p Reg (and low-level type) to be a common subclass or a common bank of
697
  /// both registers provided respectively (and a common low-level type). Do
698
  /// nothing if any of the attributes (classes, banks, or low-level types) of
699
  /// the registers are deemed incompatible, or if the resulting register will
700
  /// have a class smaller than before and of size less than \p MinNumRegs.
701
  /// Return true if such register attributes exist, false otherwise.
702
  ///
703
  /// \note Use this method instead of constrainRegClass and
704
  /// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG
705
  /// ISel / FastISel and GlobalISel's InstructionSelect pass respectively.
706
  bool constrainRegAttrs(unsigned Reg, unsigned ConstrainingReg,
707
                         unsigned MinNumRegs = 0);
708
709
  /// recomputeRegClass - Try to find a legal super-class of Reg's register
710
  /// class that still satisfies the constraints from the instructions using
711
  /// Reg.  Returns true if Reg was upgraded.
712
  ///
713
  /// This method can be used after constraints have been removed from a
714
  /// virtual register, for example after removing instructions or splitting
715
  /// the live range.
716
  bool recomputeRegClass(unsigned Reg);
717
718
  /// createVirtualRegister - Create and return a new virtual register in the
719
  /// function with the specified register class.
720
  Register createVirtualRegister(const TargetRegisterClass *RegClass,
721
                                 StringRef Name = "");
722
723
  /// Create and return a new virtual register in the function with the same
724
  /// attributes as the given register.
725
  Register cloneVirtualRegister(Register VReg, StringRef Name = "");
726
727
  /// Get the low-level type of \p Reg or LLT{} if Reg is not a generic
728
  /// (target independent) virtual register.
729
155M
  LLT getType(unsigned Reg) const {
730
155M
    if (TargetRegisterInfo::isVirtualRegister(Reg) && 
VRegToType.inBounds(Reg)142M
)
731
131M
      return VRegToType[Reg];
732
24.2M
    return LLT{};
733
24.2M
  }
734
735
  /// Set the low-level type of \p VReg to \p Ty.
736
  void setType(unsigned VReg, LLT Ty);
737
738
  /// Create and return a new generic virtual register with low-level
739
  /// type \p Ty.
740
  Register createGenericVirtualRegister(LLT Ty, StringRef Name = "");
741
742
  /// Remove all types associated to virtual registers (after instruction
743
  /// selection and constraining of all generic virtual registers).
744
  void clearVirtRegTypes();
745
746
  /// Creates a new virtual register that has no register class, register bank
747
  /// or size assigned yet. This is only allowed to be used
748
  /// temporarily while constructing machine instructions. Most operations are
749
  /// undefined on an incomplete register until one of setRegClass(),
750
  /// setRegBank() or setSize() has been called on it.
751
  unsigned createIncompleteVirtualRegister(StringRef Name = "");
752
753
  /// getNumVirtRegs - Return the number of virtual registers created.
754
35.9M
  unsigned getNumVirtRegs() const { return VRegInfo.size(); }
755
756
  /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
757
  void clearVirtRegs();
758
759
  /// setRegAllocationHint - Specify a register allocation hint for the
760
  /// specified virtual register. This is typically used by target, and in case
761
  /// of an earlier hint it will be overwritten.
762
31.7k
  void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) {
763
31.7k
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
764
31.7k
    RegAllocHints[VReg].first  = Type;
765
31.7k
    RegAllocHints[VReg].second.clear();
766
31.7k
    RegAllocHints[VReg].second.push_back(PrefReg);
767
31.7k
  }
768
769
  /// addRegAllocationHint - Add a register allocation hint to the hints
770
  /// vector for VReg.
771
4.25M
  void addRegAllocationHint(unsigned VReg, unsigned PrefReg) {
772
4.25M
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
773
4.25M
    RegAllocHints[VReg].second.push_back(PrefReg);
774
4.25M
  }
775
776
  /// Specify the preferred (target independent) register allocation hint for
777
  /// the specified virtual register.
778
248
  void setSimpleHint(unsigned VReg, unsigned PrefReg) {
779
248
    setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
780
248
  }
781
782
1.20k
  void clearSimpleHint(unsigned VReg) {
783
1.20k
    assert (RegAllocHints[VReg].first == 0 &&
784
1.20k
            "Expected to clear a non-target hint!");
785
1.20k
    RegAllocHints[VReg].second.clear();
786
1.20k
  }
787
788
  /// getRegAllocationHint - Return the register allocation hint for the
789
  /// specified virtual register. If there are many hints, this returns the
790
  /// one with the greatest weight.
791
  std::pair<unsigned, unsigned>
792
35.9M
  getRegAllocationHint(unsigned VReg) const {
793
35.9M
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
794
35.9M
    unsigned BestHint = (RegAllocHints[VReg].second.size() ?
795
25.5M
                         
RegAllocHints[VReg].second[0]10.3M
: 0);
796
35.9M
    return std::pair<unsigned, unsigned>(RegAllocHints[VReg].first, BestHint);
797
35.9M
  }
798
799
  /// getSimpleHint - same as getRegAllocationHint except it will only return
800
  /// a target independent hint.
801
18.2M
  unsigned getSimpleHint(unsigned VReg) const {
802
18.2M
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
803
18.2M
    std::pair<unsigned, unsigned> Hint = getRegAllocationHint(VReg);
804
18.2M
    return Hint.first ? 
052
:
Hint.second18.2M
;
805
18.2M
  }
806
807
  /// getRegAllocationHints - Return a reference to the vector of all
808
  /// register allocation hints for VReg.
809
  const std::pair<unsigned, SmallVector<unsigned, 4>>
810
12.1M
  &getRegAllocationHints(unsigned VReg) const {
811
12.1M
    assert(TargetRegisterInfo::isVirtualRegister(VReg));
812
12.1M
    return RegAllocHints[VReg];
813
12.1M
  }
814
815
  /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
816
  /// specified register as undefined which causes the DBG_VALUE to be
817
  /// deleted during LiveDebugVariables analysis.
818
  void markUsesInDebugValueAsUndef(unsigned Reg) const;
819
820
  /// Return true if the specified register is modified in this function.
821
  /// This checks that no defining machine operands exist for the register or
822
  /// any of its aliases. Definitions found on functions marked noreturn are
823
  /// ignored, to consider them pass 'true' for optional parameter
824
  /// SkipNoReturnDef. The register is also considered modified when it is set
825
  /// in the UsedPhysRegMask.
826
  bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef = false) const;
827
828
  /// Return true if the specified register is modified or read in this
829
  /// function. This checks that no machine operands exist for the register or
830
  /// any of its aliases. The register is also considered used when it is set
831
  /// in the UsedPhysRegMask.
832
  bool isPhysRegUsed(unsigned PhysReg) const;
833
834
  /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
835
  /// This corresponds to the bit mask attached to register mask operands.
836
1.51M
  void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
837
1.51M
    UsedPhysRegMask.setBitsNotInMask(RegMask);
838
1.51M
  }
839
840
63
  const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
841
842
  //===--------------------------------------------------------------------===//
843
  // Reserved Register Info
844
  //===--------------------------------------------------------------------===//
845
  //
846
  // The set of reserved registers must be invariant during register
847
  // allocation.  For example, the target cannot suddenly decide it needs a
848
  // frame pointer when the register allocator has already used the frame
849
  // pointer register for something else.
850
  //
851
  // These methods can be used by target hooks like hasFP() to avoid changing
852
  // the reserved register set during register allocation.
853
854
  /// freezeReservedRegs - Called by the register allocator to freeze the set
855
  /// of reserved registers before allocation begins.
856
  void freezeReservedRegs(const MachineFunction&);
857
858
  /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
859
  /// to ensure the set of reserved registers stays constant.
860
3.05M
  bool reservedRegsFrozen() const {
861
3.05M
    return !ReservedRegs.empty();
862
3.05M
  }
863
864
  /// canReserveReg - Returns true if PhysReg can be used as a reserved
865
  /// register.  Any register can be reserved before freezeReservedRegs() is
866
  /// called.
867
215k
  bool canReserveReg(unsigned PhysReg) const {
868
215k
    return !reservedRegsFrozen() || 
ReservedRegs.test(PhysReg)210k
;
869
215k
  }
870
871
  /// getReservedRegs - Returns a reference to the frozen set of reserved
872
  /// registers. This method should always be preferred to calling
873
  /// TRI::getReservedRegs() when possible.
874
181M
  const BitVector &getReservedRegs() const {
875
181M
    assert(reservedRegsFrozen() &&
876
181M
           "Reserved registers haven't been frozen yet. "
877
181M
           "Use TRI::getReservedRegs().");
878
181M
    return ReservedRegs;
879
181M
  }
880
881
  /// isReserved - Returns true when PhysReg is a reserved register.
882
  ///
883
  /// Reserved registers may belong to an allocatable register class, but the
884
  /// target has explicitly requested that they are not used.
885
170M
  bool isReserved(unsigned PhysReg) const {
886
170M
    return getReservedRegs().test(PhysReg);
887
170M
  }
888
889
  /// Returns true when the given register unit is considered reserved.
890
  ///
891
  /// Register units are considered reserved when for at least one of their
892
  /// root registers, the root register and all super registers are reserved.
893
  /// This currently iterates the register hierarchy and may be slower than
894
  /// expected.
895
  bool isReservedRegUnit(unsigned Unit) const;
896
897
  /// isAllocatable - Returns true when PhysReg belongs to an allocatable
898
  /// register class and it hasn't been reserved.
899
  ///
900
  /// Allocatable registers may show up in the allocation order of some virtual
901
  /// register, so a register allocator needs to track its liveness and
902
  /// availability.
903
35.7M
  bool isAllocatable(unsigned PhysReg) const {
904
35.7M
    return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
905
35.7M
      
!isReserved(PhysReg)31.5M
;
906
35.7M
  }
907
908
  //===--------------------------------------------------------------------===//
909
  // LiveIn Management
910
  //===--------------------------------------------------------------------===//
911
912
  /// addLiveIn - Add the specified register as a live-in.  Note that it
913
  /// is an error to add the same register to the same set more than once.
914
604k
  void addLiveIn(unsigned Reg, unsigned vreg = 0) {
915
604k
    LiveIns.push_back(std::make_pair(Reg, vreg));
916
604k
  }
917
918
  // Iteration support for the live-ins set.  It's kept in sorted order
919
  // by register number.
920
  using livein_iterator =
921
      std::vector<std::pair<unsigned,unsigned>>::const_iterator;
922
2.57M
  livein_iterator livein_begin() const { return LiveIns.begin(); }
923
2.57M
  livein_iterator livein_end()   const { return LiveIns.end(); }
924
5.34k
  bool            livein_empty() const { return LiveIns.empty(); }
925
926
101k
  ArrayRef<std::pair<unsigned, unsigned>> liveins() const {
927
101k
    return LiveIns;
928
101k
  }
929
930
  bool isLiveIn(unsigned Reg) const;
931
932
  /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
933
  /// corresponding live-in physical register.
934
  unsigned getLiveInPhysReg(unsigned VReg) const;
935
936
  /// getLiveInVirtReg - If PReg is a live-in physical register, return the
937
  /// corresponding live-in physical register.
938
  unsigned getLiveInVirtReg(unsigned PReg) const;
939
940
  /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
941
  /// into the given entry block.
942
  void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
943
                        const TargetRegisterInfo &TRI,
944
                        const TargetInstrInfo &TII);
945
946
  /// Returns a mask covering all bits that can appear in lane masks of
947
  /// subregisters of the virtual register @p Reg.
948
  LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const;
949
950
  /// defusechain_iterator - This class provides iterator support for machine
951
  /// operands in the function that use or define a specific register.  If
952
  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
953
  /// returns defs.  If neither are true then you are silly and it always
954
  /// returns end().  If SkipDebug is true it skips uses marked Debug
955
  /// when incrementing.
956
  template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
957
           bool ByOperand, bool ByInstr, bool ByBundle>
958
  class defusechain_iterator
959
    : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
960
    friend class MachineRegisterInfo;
961
962
    MachineOperand *Op = nullptr;
963
964
2.80G
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
965
2.80G
      // If the first node isn't one we're interested in, advance to one that
966
2.80G
      // we are interested in.
967
2.80G
      if (op) {
968
292M
        if ((!ReturnUses && 
op->isUse()60.4M
) ||
969
292M
            
(140M
!ReturnDefs140M
&&
op->isDef()140M
) ||
970
292M
            
(85.7M
SkipDebug85.7M
&&
op->isDebug()85.7M
))
971
140M
          advance();
972
292M
      }
973
2.80G
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
964
524M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
965
524M
      // If the first node isn't one we're interested in, advance to one that
966
524M
      // we are interested in.
967
524M
      if (op) {
968
60.4M
        if ((!ReturnUses && op->isUse()) ||
969
60.4M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
970
60.4M
            
(0
SkipDebug0
&&
op->isDebug()0
))
971
2.89M
          advance();
972
60.4M
      }
973
524M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
964
279M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
965
279M
      // If the first node isn't one we're interested in, advance to one that
966
279M
      // we are interested in.
967
279M
      if (op) {
968
129M
        if ((!ReturnUses && 
op->isUse()0
) ||
969
129M
            (!ReturnDefs && op->isDef()) ||
970
129M
            
(540k
SkipDebug540k
&&
op->isDebug()540k
))
971
128M
          advance();
972
129M
      }
973
279M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
964
24.8M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
965
24.8M
      // If the first node isn't one we're interested in, advance to one that
966
24.8M
      // we are interested in.
967
24.8M
      if (op) {
968
11.5M
        if ((!ReturnUses && 
op->isUse()0
) ||
969
11.5M
            (!ReturnDefs && op->isDef()) ||
970
11.5M
            
(0
SkipDebug0
&&
op->isDebug()0
))
971
9.43M
          advance();
972
11.5M
      }
973
24.8M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
964
117M
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
965
117M
      // If the first node isn't one we're interested in, advance to one that
966
117M
      // we are interested in.
967
117M
      if (op) {
968
6.27M
        if ((!ReturnUses && 
op->isUse()0
) ||
969
6.27M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
970
6.27M
            
(0
SkipDebug0
&&
op->isDebug()0
))
971
0
          advance();
972
6.27M
      }
973
117M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::defusechain_iterator(llvm::MachineOperand*)
Line
Count
Source
964
1.85G
    explicit defusechain_iterator(MachineOperand *op) : Op(op) {
965
1.85G
      // If the first node isn't one we're interested in, advance to one that
966
1.85G
      // we are interested in.
967
1.85G
      if (op) {
968
85.1M
        if ((!ReturnUses && 
op->isUse()0
) ||
969
85.1M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
970
85.1M
            (SkipDebug && op->isDebug()))
971
5
          advance();
972
85.1M
      }
973
1.85G
    }
974
975
330M
    void advance() {
976
330M
      assert(Op && "Cannot increment end iterator!");
977
330M
      Op = getNextOperandForReg(Op);
978
330M
979
330M
      // All defs come before the uses, so stop def_iterator early.
980
330M
      if (!ReturnUses) {
981
32.5M
        if (Op) {
982
30.5M
          if (Op->isUse())
983
22.1M
            Op = nullptr;
984
30.5M
          else
985
30.5M
            assert(!Op->isDebug() && "Can't have debug defs");
986
30.5M
        }
987
297M
      } else {
988
297M
        // If this is an operand we don't care about, skip it.
989
340M
        while (Op && 
(277M
(277M
!ReturnDefs277M
&&
Op->isDef()216M
) ||
990
277M
                      
(235M
SkipDebug235M
&&
Op->isDebug()201M
)))
991
42.3M
          Op = getNextOperandForReg(Op);
992
297M
      }
993
330M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::advance()
Line
Count
Source
975
5.61M
    void advance() {
976
5.61M
      assert(Op && "Cannot increment end iterator!");
977
5.61M
      Op = getNextOperandForReg(Op);
978
5.61M
979
5.61M
      // All defs come before the uses, so stop def_iterator early.
980
5.61M
      if (!ReturnUses) {
981
0
        if (Op) {
982
0
          if (Op->isUse())
983
0
            Op = nullptr;
984
0
          else
985
0
            assert(!Op->isDebug() && "Can't have debug defs");
986
0
        }
987
5.61M
      } else {
988
5.61M
        // If this is an operand we don't care about, skip it.
989
5.61M
        while (Op && 
(3.60M
(3.60M
!ReturnDefs3.60M
&&
Op->isDef()0
) ||
990
3.60M
                      (SkipDebug && 
Op->isDebug()0
)))
991
0
          Op = getNextOperandForReg(Op);
992
5.61M
      }
993
5.61M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::advance()
Line
Count
Source
975
86.1M
    void advance() {
976
86.1M
      assert(Op && "Cannot increment end iterator!");
977
86.1M
      Op = getNextOperandForReg(Op);
978
86.1M
979
86.1M
      // All defs come before the uses, so stop def_iterator early.
980
86.1M
      if (!ReturnUses) {
981
0
        if (Op) {
982
0
          if (Op->isUse())
983
0
            Op = nullptr;
984
0
          else
985
0
            assert(!Op->isDebug() && "Can't have debug defs");
986
0
        }
987
86.1M
      } else {
988
86.1M
        // If this is an operand we don't care about, skip it.
989
86.1M
        while (Op && 
(57.6M
(57.6M
!ReturnDefs57.6M
&&
Op->isDef()0
) ||
990
57.6M
                      (SkipDebug && Op->isDebug())))
991
1.78k
          Op = getNextOperandForReg(Op);
992
86.1M
      }
993
86.1M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::advance()
Line
Count
Source
975
32.5M
    void advance() {
976
32.5M
      assert(Op && "Cannot increment end iterator!");
977
32.5M
      Op = getNextOperandForReg(Op);
978
32.5M
979
32.5M
      // All defs come before the uses, so stop def_iterator early.
980
32.5M
      if (!ReturnUses) {
981
32.5M
        if (Op) {
982
30.5M
          if (Op->isUse())
983
22.1M
            Op = nullptr;
984
30.5M
          else
985
30.5M
            assert(!Op->isDebug() && "Can't have debug defs");
986
30.5M
        }
987
32.5M
      } else {
988
0
        // If this is an operand we don't care about, skip it.
989
0
        while (Op && ((!ReturnDefs && Op->isDef()) ||
990
0
                      (SkipDebug && Op->isDebug())))
991
0
          Op = getNextOperandForReg(Op);
992
0
      }
993
32.5M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::advance()
Line
Count
Source
975
41.3M
    void advance() {
976
41.3M
      assert(Op && "Cannot increment end iterator!");
977
41.3M
      Op = getNextOperandForReg(Op);
978
41.3M
979
41.3M
      // All defs come before the uses, so stop def_iterator early.
980
41.3M
      if (!ReturnUses) {
981
0
        if (Op) {
982
0
          if (Op->isUse())
983
0
            Op = nullptr;
984
0
          else
985
0
            assert(!Op->isDebug() && "Can't have debug defs");
986
0
        }
987
41.3M
      } else {
988
41.3M
        // If this is an operand we don't care about, skip it.
989
48.7M
        while (Op && 
(37.6M
(37.6M
!ReturnDefs37.6M
&&
Op->isDef()37.6M
) ||
990
37.6M
                      
(30.2M
SkipDebug30.2M
&&
Op->isDebug()0
)))
991
7.40M
          Op = getNextOperandForReg(Op);
992
41.3M
      }
993
41.3M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::advance()
Line
Count
Source
975
164M
    void advance() {
976
164M
      assert(Op && "Cannot increment end iterator!");
977
164M
      Op = getNextOperandForReg(Op);
978
164M
979
164M
      // All defs come before the uses, so stop def_iterator early.
980
164M
      if (!ReturnUses) {
981
0
        if (Op) {
982
0
          if (Op->isUse())
983
0
            Op = nullptr;
984
0
          else
985
0
            assert(!Op->isDebug() && "Can't have debug defs");
986
0
        }
987
164M
      } else {
988
164M
        // If this is an operand we don't care about, skip it.
989
199M
        while (Op && 
(178M
(178M
!ReturnDefs178M
&&
Op->isDef()178M
) ||
990
178M
                      
(143M
SkipDebug143M
&&
Op->isDebug()143M
)))
991
34.9M
          Op = getNextOperandForReg(Op);
992
164M
      }
993
164M
    }
994
995
  public:
996
    using reference = std::iterator<std::forward_iterator_tag,
997
                                    MachineInstr, ptrdiff_t>::reference;
998
    using pointer = std::iterator<std::forward_iterator_tag,
999
                                  MachineInstr, ptrdiff_t>::pointer;
1000
1001
253k
    defusechain_iterator() = default;
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::defusechain_iterator()
Line
Count
Source
1001
252k
    defusechain_iterator() = default;
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::defusechain_iterator()
Line
Count
Source
1001
263
    defusechain_iterator() = default;
1002
1003
1.55G
    bool operator==(const defusechain_iterator &x) const {
1004
1.55G
      return Op == x.Op;
1005
1.55G
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false> const&) const
Line
Count
Source
1003
64.4M
    bool operator==(const defusechain_iterator &x) const {
1004
64.4M
      return Op == x.Op;
1005
64.4M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false> const&) const
Line
Count
Source
1003
1.01G
    bool operator==(const defusechain_iterator &x) const {
1004
1.01G
      return Op == x.Op;
1005
1.01G
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false> const&) const
Line
Count
Source
1003
269M
    bool operator==(const defusechain_iterator &x) const {
1004
269M
      return Op == x.Op;
1005
269M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false> const&) const
Line
Count
Source
1003
43.6M
    bool operator==(const defusechain_iterator &x) const {
1004
43.6M
      return Op == x.Op;
1005
43.6M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator==(llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false> const&) const
Line
Count
Source
1003
166M
    bool operator==(const defusechain_iterator &x) const {
1004
166M
      return Op == x.Op;
1005
166M
    }
1006
429M
    bool operator!=(const defusechain_iterator &x) const {
1007
429M
      return !operator==(x);
1008
429M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false> const&) const
Line
Count
Source
1006
7.81M
    bool operator!=(const defusechain_iterator &x) const {
1007
7.81M
      return !operator==(x);
1008
7.81M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false> const&) const
Line
Count
Source
1006
40.3M
    bool operator!=(const defusechain_iterator &x) const {
1007
40.3M
      return !operator==(x);
1008
40.3M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false> const&) const
Line
Count
Source
1006
211M
    bool operator!=(const defusechain_iterator &x) const {
1007
211M
      return !operator==(x);
1008
211M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false> const&) const
Line
Count
Source
1006
114M
    bool operator!=(const defusechain_iterator &x) const {
1007
114M
      return !operator==(x);
1008
114M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator!=(llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false> const&) const
Line
Count
Source
1006
54.7M
    bool operator!=(const defusechain_iterator &x) const {
1007
54.7M
      return !operator==(x);
1008
54.7M
    }
1009
1010
    /// atEnd - return true if this iterator is equal to reg_end() on the value.
1011
    bool atEnd() const { return Op == nullptr; }
1012
1013
    // Iterator traversal: forward iteration only
1014
189M
    defusechain_iterator &operator++() {          // Preincrement
1015
189M
      assert(Op && "Cannot increment end iterator!");
1016
189M
      if (ByOperand)
1017
189M
        advance();
1018
0
      else if (ByInstr) {
1019
0
        MachineInstr *P = Op->getParent();
1020
0
        do {
1021
0
          advance();
1022
0
        } while (Op && Op->getParent() == P);
1023
0
      } else if (ByBundle) {
1024
0
        MachineBasicBlock::instr_iterator P =
1025
0
            getBundleStart(Op->getParent()->getIterator());
1026
0
        do {
1027
0
          advance();
1028
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1029
0
      }
1030
189M
1031
189M
      return *this;
1032
189M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator++()
Line
Count
Source
1014
29.6M
    defusechain_iterator &operator++() {          // Preincrement
1015
29.6M
      assert(Op && "Cannot increment end iterator!");
1016
29.6M
      if (ByOperand)
1017
29.6M
        advance();
1018
0
      else if (ByInstr) {
1019
0
        MachineInstr *P = Op->getParent();
1020
0
        do {
1021
0
          advance();
1022
0
        } while (Op && Op->getParent() == P);
1023
0
      } else if (ByBundle) {
1024
0
        MachineBasicBlock::instr_iterator P =
1025
0
            getBundleStart(Op->getParent()->getIterator());
1026
0
        do {
1027
0
          advance();
1028
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1029
0
      }
1030
29.6M
1031
29.6M
      return *this;
1032
29.6M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator++()
Line
Count
Source
1014
31.9M
    defusechain_iterator &operator++() {          // Preincrement
1015
31.9M
      assert(Op && "Cannot increment end iterator!");
1016
31.9M
      if (ByOperand)
1017
31.9M
        advance();
1018
0
      else if (ByInstr) {
1019
0
        MachineInstr *P = Op->getParent();
1020
0
        do {
1021
0
          advance();
1022
0
        } while (Op && Op->getParent() == P);
1023
0
      } else if (ByBundle) {
1024
0
        MachineBasicBlock::instr_iterator P =
1025
0
            getBundleStart(Op->getParent()->getIterator());
1026
0
        do {
1027
0
          advance();
1028
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1029
0
      }
1030
31.9M
1031
31.9M
      return *this;
1032
31.9M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator++()
Line
Count
Source
1014
5.61M
    defusechain_iterator &operator++() {          // Preincrement
1015
5.61M
      assert(Op && "Cannot increment end iterator!");
1016
5.61M
      if (ByOperand)
1017
5.61M
        advance();
1018
0
      else if (ByInstr) {
1019
0
        MachineInstr *P = Op->getParent();
1020
0
        do {
1021
0
          advance();
1022
0
        } while (Op && Op->getParent() == P);
1023
0
      } else if (ByBundle) {
1024
0
        MachineBasicBlock::instr_iterator P =
1025
0
            getBundleStart(Op->getParent()->getIterator());
1026
0
        do {
1027
0
          advance();
1028
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1029
0
      }
1030
5.61M
1031
5.61M
      return *this;
1032
5.61M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator++()
Line
Count
Source
1014
86.1M
    defusechain_iterator &operator++() {          // Preincrement
1015
86.1M
      assert(Op && "Cannot increment end iterator!");
1016
86.1M
      if (ByOperand)
1017
86.1M
        advance();
1018
0
      else if (ByInstr) {
1019
0
        MachineInstr *P = Op->getParent();
1020
0
        do {
1021
0
          advance();
1022
0
        } while (Op && Op->getParent() == P);
1023
0
      } else if (ByBundle) {
1024
0
        MachineBasicBlock::instr_iterator P =
1025
0
            getBundleStart(Op->getParent()->getIterator());
1026
0
        do {
1027
0
          advance();
1028
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1029
0
      }
1030
86.1M
1031
86.1M
      return *this;
1032
86.1M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator++()
Line
Count
Source
1014
36.3M
    defusechain_iterator &operator++() {          // Preincrement
1015
36.3M
      assert(Op && "Cannot increment end iterator!");
1016
36.3M
      if (ByOperand)
1017
36.3M
        advance();
1018
0
      else if (ByInstr) {
1019
0
        MachineInstr *P = Op->getParent();
1020
0
        do {
1021
0
          advance();
1022
0
        } while (Op && Op->getParent() == P);
1023
0
      } else if (ByBundle) {
1024
0
        MachineBasicBlock::instr_iterator P =
1025
0
            getBundleStart(Op->getParent()->getIterator());
1026
0
        do {
1027
0
          advance();
1028
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1029
0
      }
1030
36.3M
1031
36.3M
      return *this;
1032
36.3M
    }
1033
105k
    defusechain_iterator operator++(int) {        // Postincrement
1034
105k
      defusechain_iterator tmp = *this; ++*this; return tmp;
1035
105k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator++(int)
Line
Count
Source
1033
87.1k
    defusechain_iterator operator++(int) {        // Postincrement
1034
87.1k
      defusechain_iterator tmp = *this; ++*this; return tmp;
1035
87.1k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator++(int)
Line
Count
Source
1033
16.2k
    defusechain_iterator operator++(int) {        // Postincrement
1034
16.2k
      defusechain_iterator tmp = *this; ++*this; return tmp;
1035
16.2k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator++(int)
Line
Count
Source
1033
720
    defusechain_iterator operator++(int) {        // Postincrement
1034
720
      defusechain_iterator tmp = *this; ++*this; return tmp;
1035
720
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator++(int)
Line
Count
Source
1033
939
    defusechain_iterator operator++(int) {        // Postincrement
1034
939
      defusechain_iterator tmp = *this; ++*this; return tmp;
1035
939
    }
1036
1037
    /// getOperandNo - Return the operand # of this MachineOperand in its
1038
    /// MachineInstr.
1039
14.5M
    unsigned getOperandNo() const {
1040
14.5M
      assert(Op && "Cannot dereference end iterator!");
1041
14.5M
      return Op - &Op->getParent()->getOperand(0);
1042
14.5M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::getOperandNo() const
Line
Count
Source
1039
756k
    unsigned getOperandNo() const {
1040
756k
      assert(Op && "Cannot dereference end iterator!");
1041
756k
      return Op - &Op->getParent()->getOperand(0);
1042
756k
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::getOperandNo() const
Line
Count
Source
1039
13.7M
    unsigned getOperandNo() const {
1040
13.7M
      assert(Op && "Cannot dereference end iterator!");
1041
13.7M
      return Op - &Op->getParent()->getOperand(0);
1042
13.7M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::getOperandNo() const
Line
Count
Source
1039
1.97k
    unsigned getOperandNo() const {
1040
1.97k
      assert(Op && "Cannot dereference end iterator!");
1041
1.97k
      return Op - &Op->getParent()->getOperand(0);
1042
1.97k
    }
1043
1044
    // Retrieve a reference to the current operand.
1045
180M
    MachineOperand &operator*() const {
1046
180M
      assert(Op && "Cannot dereference end iterator!");
1047
180M
      return *Op;
1048
180M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator*() const
Line
Count
Source
1045
5.53M
    MachineOperand &operator*() const {
1046
5.53M
      assert(Op && "Cannot dereference end iterator!");
1047
5.53M
      return *Op;
1048
5.53M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator*() const
Line
Count
Source
1045
29.6M
    MachineOperand &operator*() const {
1046
29.6M
      assert(Op && "Cannot dereference end iterator!");
1047
29.6M
      return *Op;
1048
29.6M
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator*() const
Line
Count
Source
1045
11.3M
    MachineOperand &operator*() const {
1046
11.3M
      assert(Op && "Cannot dereference end iterator!");
1047
11.3M
      return *Op;
1048
11.3M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, true, true, false, false>::operator*() const
Line
Count
Source
1045
86.2M
    MachineOperand &operator*() const {
1046
86.2M
      assert(Op && "Cannot dereference end iterator!");
1047
86.2M
      return *Op;
1048
86.2M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator*() const
Line
Count
Source
1045
47.2M
    MachineOperand &operator*() const {
1046
47.2M
      assert(Op && "Cannot dereference end iterator!");
1047
47.2M
      return *Op;
1048
47.2M
    }
1049
1050
12.4M
    MachineOperand *operator->() const {
1051
12.4M
      assert(Op && "Cannot dereference end iterator!");
1052
12.4M
      return Op;
1053
12.4M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, false, true, false, false>::operator->() const
Line
Count
Source
1050
1.15M
    MachineOperand *operator->() const {
1051
1.15M
      assert(Op && "Cannot dereference end iterator!");
1052
1.15M
      return Op;
1053
1.15M
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, false, true, true, false, false>::operator->() const
Line
Count
Source
1050
2.47k
    MachineOperand *operator->() const {
1051
2.47k
      assert(Op && "Cannot dereference end iterator!");
1052
2.47k
      return Op;
1053
2.47k
    }
llvm::MachineRegisterInfo::defusechain_iterator<true, true, false, true, false, false>::operator->() const
Line
Count
Source
1050
540k
    MachineOperand *operator->() const {
1051
540k
      assert(Op && "Cannot dereference end iterator!");
1052
540k
      return Op;
1053
540k
    }
llvm::MachineRegisterInfo::defusechain_iterator<false, true, false, true, false, false>::operator->() const
Line
Count
Source
1050
10.7M
    MachineOperand *operator->() const {
1051
10.7M
      assert(Op && "Cannot dereference end iterator!");
1052
10.7M
      return Op;
1053
10.7M
    }
1054
  };
1055
1056
  /// defusechain_iterator - This class provides iterator support for machine
1057
  /// operands in the function that use or define a specific register.  If
1058
  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1059
  /// returns defs.  If neither are true then you are silly and it always
1060
  /// returns end().  If SkipDebug is true it skips uses marked Debug
1061
  /// when incrementing.
1062
  template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
1063
           bool ByOperand, bool ByInstr, bool ByBundle>
1064
  class defusechain_instr_iterator
1065
    : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
1066
    friend class MachineRegisterInfo;
1067
1068
    MachineOperand *Op = nullptr;
1069
1070
185M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1071
185M
      // If the first node isn't one we're interested in, advance to one that
1072
185M
      // we are interested in.
1073
185M
      if (op) {
1074
126M
        if ((!ReturnUses && 
op->isUse()71.4M
) ||
1075
126M
            
(40.6M
!ReturnDefs40.6M
&&
op->isDef()40.6M
) ||
1076
126M
            
(1.05M
SkipDebug1.05M
&&
op->isDebug()1.05M
))
1077
40.0M
          advance();
1078
126M
      }
1079
185M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1070
77.3M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1071
77.3M
      // If the first node isn't one we're interested in, advance to one that
1072
77.3M
      // we are interested in.
1073
77.3M
      if (op) {
1074
71.4M
        if ((!ReturnUses && 
op->isUse()71.4M
) ||
1075
71.4M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
1076
71.4M
            
(0
SkipDebug0
&&
op->isDebug()0
))
1077
79.4k
          advance();
1078
71.4M
      }
1079
77.3M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1070
58.6M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1071
58.6M
      // If the first node isn't one we're interested in, advance to one that
1072
58.6M
      // we are interested in.
1073
58.6M
      if (op) {
1074
30.3M
        if ((!ReturnUses && 
op->isUse()0
) ||
1075
30.3M
            (!ReturnDefs && op->isDef()) ||
1076
30.3M
            
(0
SkipDebug0
&&
op->isDebug()0
))
1077
30.3M
          advance();
1078
30.3M
      }
1079
58.6M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1070
20.6M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1071
20.6M
      // If the first node isn't one we're interested in, advance to one that
1072
20.6M
      // we are interested in.
1073
20.6M
      if (op) {
1074
10.3M
        if ((!ReturnUses && 
op->isUse()0
) ||
1075
10.3M
            (!ReturnDefs && op->isDef()) ||
1076
10.3M
            
(0
SkipDebug0
&&
op->isDebug()0
))
1077
9.63M
          advance();
1078
10.3M
      }
1079
20.6M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1070
26.2M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1071
26.2M
      // If the first node isn't one we're interested in, advance to one that
1072
26.2M
      // we are interested in.
1073
26.2M
      if (op) {
1074
12.9M
        if ((!ReturnUses && 
op->isUse()0
) ||
1075
12.9M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
1076
12.9M
            
(0
SkipDebug0
&&
op->isDebug()0
))
1077
0
          advance();
1078
12.9M
      }
1079
26.2M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1070
2.11M
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1071
2.11M
      // If the first node isn't one we're interested in, advance to one that
1072
2.11M
      // we are interested in.
1073
2.11M
      if (op) {
1074
1.05M
        if ((!ReturnUses && 
op->isUse()0
) ||
1075
1.05M
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
1076
1.05M
            (SkipDebug && op->isDebug()))
1077
0
          advance();
1078
1.05M
      }
1079
2.11M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::defusechain_instr_iterator(llvm::MachineOperand*)
Line
Count
Source
1070
572k
    explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1071
572k
      // If the first node isn't one we're interested in, advance to one that
1072
572k
      // we are interested in.
1073
572k
      if (op) {
1074
286k
        if ((!ReturnUses && 
op->isUse()0
) ||
1075
286k
            
(0
!ReturnDefs0
&&
op->isDef()0
) ||
1076
286k
            
(0
SkipDebug0
&&
op->isDebug()0
))
1077
0
          advance();
1078
286k
      }
1079
572k
    }
1080
1081
115M
    void advance() {
1082
115M
      assert(Op && "Cannot increment end iterator!");
1083
115M
      Op = getNextOperandForReg(Op);
1084
115M
1085
115M
      // All defs come before the uses, so stop def_iterator early.
1086
115M
      if (!ReturnUses) {
1087
3.66M
        if (Op) {
1088
3.59M
          if (Op->isUse())
1089
3.49M
            Op = nullptr;
1090
3.59M
          else
1091
3.59M
            assert(!Op->isDebug() && "Can't have debug defs");
1092
3.59M
        }
1093
111M
      } else {
1094
111M
        // If this is an operand we don't care about, skip it.
1095
114M
        while (Op && 
(87.3M
(87.3M
!ReturnDefs87.3M
&&
Op->isDef()59.1M
) ||
1096
87.3M
                      
(84.7M
SkipDebug84.7M
&&
Op->isDebug()52.5M
)))
1097
2.61M
          Op = getNextOperandForReg(Op);
1098
111M
      }
1099
115M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::advance()
Line
Count
Source
1081
36.9M
    void advance() {
1082
36.9M
      assert(Op && "Cannot increment end iterator!");
1083
36.9M
      Op = getNextOperandForReg(Op);
1084
36.9M
1085
36.9M
      // All defs come before the uses, so stop def_iterator early.
1086
36.9M
      if (!ReturnUses) {
1087
0
        if (Op) {
1088
0
          if (Op->isUse())
1089
0
            Op = nullptr;
1090
0
          else
1091
0
            assert(!Op->isDebug() && "Can't have debug defs");
1092
0
        }
1093
36.9M
      } else {
1094
36.9M
        // If this is an operand we don't care about, skip it.
1095
36.9M
        while (Op && 
(23.9M
(23.9M
!ReturnDefs23.9M
&&
Op->isDef()0
) ||
1096
23.9M
                      (SkipDebug && 
Op->isDebug()0
)))
1097
0
          Op = getNextOperandForReg(Op);
1098
36.9M
      }
1099
36.9M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::advance()
Line
Count
Source
1081
772k
    void advance() {
1082
772k
      assert(Op && "Cannot increment end iterator!");
1083
772k
      Op = getNextOperandForReg(Op);
1084
772k
1085
772k
      // All defs come before the uses, so stop def_iterator early.
1086
772k
      if (!ReturnUses) {
1087
0
        if (Op) {
1088
0
          if (Op->isUse())
1089
0
            Op = nullptr;
1090
0
          else
1091
0
            assert(!Op->isDebug() && "Can't have debug defs");
1092
0
        }
1093
772k
      } else {
1094
772k
        // If this is an operand we don't care about, skip it.
1095
772k
        while (Op && 
(485k
(485k
!ReturnDefs485k
&&
Op->isDef()0
) ||
1096
485k
                      (SkipDebug && 
Op->isDebug()0
)))
1097
0
          Op = getNextOperandForReg(Op);
1098
772k
      }
1099
772k
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::advance()
Line
Count
Source
1081
4.79M
    void advance() {
1082
4.79M
      assert(Op && "Cannot increment end iterator!");
1083
4.79M
      Op = getNextOperandForReg(Op);
1084
4.79M
1085
4.79M
      // All defs come before the uses, so stop def_iterator early.
1086
4.79M
      if (!ReturnUses) {
1087
0
        if (Op) {
1088
0
          if (Op->isUse())
1089
0
            Op = nullptr;
1090
0
          else
1091
0
            assert(!Op->isDebug() && "Can't have debug defs");
1092
0
        }
1093
4.79M
      } else {
1094
4.79M
        // If this is an operand we don't care about, skip it.
1095
4.79M
        while (Op && 
(3.78M
(3.78M
!ReturnDefs3.78M
&&
Op->isDef()0
) ||
1096
3.78M
                      (SkipDebug && Op->isDebug())))
1097
0
          Op = getNextOperandForReg(Op);
1098
4.79M
      }
1099
4.79M
    }
Unexecuted instantiation: llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, false, true>::advance()
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::advance()
Line
Count
Source
1081
3.66M
    void advance() {
1082
3.66M
      assert(Op && "Cannot increment end iterator!");
1083
3.66M
      Op = getNextOperandForReg(Op);
1084
3.66M
1085
3.66M
      // All defs come before the uses, so stop def_iterator early.
1086
3.66M
      if (!ReturnUses) {
1087
3.66M
        if (Op) {
1088
3.59M
          if (Op->isUse())
1089
3.49M
            Op = nullptr;
1090
3.59M
          else
1091
3.59M
            assert(!Op->isDebug() && "Can't have debug defs");
1092
3.59M
        }
1093
3.66M
      } else {
1094
0
        // If this is an operand we don't care about, skip it.
1095
0
        while (Op && ((!ReturnDefs && Op->isDef()) ||
1096
0
                      (SkipDebug && Op->isDebug())))
1097
0
          Op = getNextOperandForReg(Op);
1098
0
      }
1099
3.66M
    }
Unexecuted instantiation: llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, false, true>::advance()
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::advance()
Line
Count
Source
1081
18.0M
    void advance() {
1082
18.0M
      assert(Op && "Cannot increment end iterator!");
1083
18.0M
      Op = getNextOperandForReg(Op);
1084
18.0M
1085
18.0M
      // All defs come before the uses, so stop def_iterator early.
1086
18.0M
      if (!ReturnUses) {
1087
0
        if (Op) {
1088
0
          if (Op->isUse())
1089
0
            Op = nullptr;
1090
0
          else
1091
0
            assert(!Op->isDebug() && "Can't have debug defs");
1092
0
        }
1093
18.0M
      } else {
1094
18.0M
        // If this is an operand we don't care about, skip it.
1095
18.9M
        while (Op && 
(8.71M
(8.71M
!ReturnDefs8.71M
&&
Op->isDef()8.71M
) ||
1096
8.71M
                      
(7.78M
SkipDebug7.78M
&&
Op->isDebug()0
)))
1097
922k
          Op = getNextOperandForReg(Op);
1098
18.0M
      }
1099
18.0M
    }
Unexecuted instantiation: llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, false, true>::advance()
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::advance()
Line
Count
Source
1081
51.3M
    void advance() {
1082
51.3M
      assert(Op && "Cannot increment end iterator!");
1083
51.3M
      Op = getNextOperandForReg(Op);
1084
51.3M
1085
51.3M
      // All defs come before the uses, so stop def_iterator early.
1086
51.3M
      if (!ReturnUses) {
1087
0
        if (Op) {
1088
0
          if (Op->isUse())
1089
0
            Op = nullptr;
1090
0
          else
1091
0
            assert(!Op->isDebug() && "Can't have debug defs");
1092
0
        }
1093
51.3M
      } else {
1094
51.3M
        // If this is an operand we don't care about, skip it.
1095
53.0M
        while (Op && 
(50.4M
(50.4M
!ReturnDefs50.4M
&&
Op->isDef()50.4M
) ||
1096
50.4M
                      
(48.7M
SkipDebug48.7M
&&
Op->isDebug()48.7M
)))
1097
1.68M
          Op = getNextOperandForReg(Op);
1098
51.3M
      }
1099
51.3M
    }
Unexecuted instantiation: llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, false, true>::advance()
1100
1101
  public:
1102
    using reference = std::iterator<std::forward_iterator_tag,
1103
                                    MachineInstr, ptrdiff_t>::reference;
1104
    using pointer = std::iterator<std::forward_iterator_tag,
1105
                                  MachineInstr, ptrdiff_t>::pointer;
1106
1107
5.22M
    defusechain_instr_iterator() = default;
1108
1109
130M
    bool operator==(const defusechain_instr_iterator &x) const {
1110
130M
      return Op == x.Op;
1111
130M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false> const&) const
Line
Count
Source
1109
48.8M
    bool operator==(const defusechain_instr_iterator &x) const {
1110
48.8M
      return Op == x.Op;
1111
48.8M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false> const&) const
Line
Count
Source
1109
18.6M
    bool operator==(const defusechain_instr_iterator &x) const {
1110
18.6M
      return Op == x.Op;
1111
18.6M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false> const&) const
Line
Count
Source
1109
6.05M
    bool operator==(const defusechain_instr_iterator &x) const {
1110
6.05M
      return Op == x.Op;
1111
6.05M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false> const&) const
Line
Count
Source
1109
49.6M
    bool operator==(const defusechain_instr_iterator &x) const {
1110
49.6M
      return Op == x.Op;
1111
49.6M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false> const&) const
Line
Count
Source
1109
5.75M
    bool operator==(const defusechain_instr_iterator &x) const {
1110
5.75M
      return Op == x.Op;
1111
5.75M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator==(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true> const&) const
Line
Count
Source
1109
1.05M
    bool operator==(const defusechain_instr_iterator &x) const {
1110
1.05M
      return Op == x.Op;
1111
1.05M
    }
1112
129M
    bool operator!=(const defusechain_instr_iterator &x) const {
1113
129M
      return !operator==(x);
1114
129M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false> const&) const
Line
Count
Source
1112
48.3M
    bool operator!=(const defusechain_instr_iterator &x) const {
1113
48.3M
      return !operator==(x);
1114
48.3M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false> const&) const
Line
Count
Source
1112
18.6M
    bool operator!=(const defusechain_instr_iterator &x) const {
1113
18.6M
      return !operator==(x);
1114
18.6M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false> const&) const
Line
Count
Source
1112
6.05M
    bool operator!=(const defusechain_instr_iterator &x) const {
1113
6.05M
      return !operator==(x);
1114
6.05M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false> const&) const
Line
Count
Source
1112
49.6M
    bool operator!=(const defusechain_instr_iterator &x) const {
1113
49.6M
      return !operator==(x);
1114
49.6M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false> const&) const
Line
Count
Source
1112
5.75M
    bool operator!=(const defusechain_instr_iterator &x) const {
1113
5.75M
      return !operator==(x);
1114
5.75M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator!=(llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true> const&) const
Line
Count
Source
1112
1.05M
    bool operator!=(const defusechain_instr_iterator &x) const {
1113
1.05M
      return !operator==(x);
1114
1.05M
    }
1115
1116
    /// atEnd - return true if this iterator is equal to reg_end() on the value.
1117
65.2M
    bool atEnd() const { return Op == nullptr; }
1118
1119
    // Iterator traversal: forward iteration only
1120
74.7M
    defusechain_instr_iterator &operator++() {          // Preincrement
1121
74.7M
      assert(Op && "Cannot increment end iterator!");
1122
74.7M
      if (ByOperand)
1123
0
        advance();
1124
74.7M
      else if (ByInstr) {
1125
74.0M
        MachineInstr *P = Op->getParent();
1126
74.6M
        do {
1127
74.6M
          advance();
1128
74.6M
        } while (Op && 
Op->getParent() == P49.3M
);
1129
74.0M
      } else 
if (770k
ByBundle770k
) {
1130
770k
        MachineBasicBlock::instr_iterator P =
1131
770k
            getBundleStart(Op->getParent()->getIterator());
1132
772k
        do {
1133
772k
          advance();
1134
772k
        } while (Op && 
getBundleStart(Op->getParent()->getIterator()) == P485k
);
1135
770k
      }
1136
74.7M
1137
74.7M
      return *this;
1138
74.7M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator++()
Line
Count
Source
1120
20.8M
    defusechain_instr_iterator &operator++() {          // Preincrement
1121
20.8M
      assert(Op && "Cannot increment end iterator!");
1122
20.8M
      if (ByOperand)
1123
0
        advance();
1124
20.8M
      else if (ByInstr) {
1125
20.8M
        MachineInstr *P = Op->getParent();
1126
20.9M
        do {
1127
20.9M
          advance();
1128
20.9M
        } while (Op && 
Op->getParent() == P19.1M
);
1129
20.8M
      } else 
if (0
ByBundle0
) {
1130
0
        MachineBasicBlock::instr_iterator P =
1131
0
            getBundleStart(Op->getParent()->getIterator());
1132
0
        do {
1133
0
          advance();
1134
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1135
0
      }
1136
20.8M
1137
20.8M
      return *this;
1138
20.8M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator++()
Line
Count
Source
1120
8.35M
    defusechain_instr_iterator &operator++() {          // Preincrement
1121
8.35M
      assert(Op && "Cannot increment end iterator!");
1122
8.35M
      if (ByOperand)
1123
0
        advance();
1124
8.35M
      else if (ByInstr) {
1125
8.35M
        MachineInstr *P = Op->getParent();
1126
8.38M
        do {
1127
8.38M
          advance();
1128
8.38M
        } while (Op && 
Op->getParent() == P2.36M
);
1129
8.35M
      } else 
if (0
ByBundle0
) {
1130
0
        MachineBasicBlock::instr_iterator P =
1131
0
            getBundleStart(Op->getParent()->getIterator());
1132
0
        do {
1133
0
          advance();
1134
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1135
0
      }
1136
8.35M
1137
8.35M
      return *this;
1138
8.35M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator++()
Line
Count
Source
1120
3.58M
    defusechain_instr_iterator &operator++() {          // Preincrement
1121
3.58M
      assert(Op && "Cannot increment end iterator!");
1122
3.58M
      if (ByOperand)
1123
0
        advance();
1124
3.58M
      else 
if (3.58M
ByInstr3.58M
) {
1125
3.58M
        MachineInstr *P = Op->getParent();
1126
3.58M
        do {
1127
3.58M
          advance();
1128
3.58M
        } while (Op && 
Op->getParent() == P98.8k
);
1129
18.4E
      } else if (ByBundle) {
1130
0
        MachineBasicBlock::instr_iterator P =
1131
0
            getBundleStart(Op->getParent()->getIterator());
1132
0
        do {
1133
0
          advance();
1134
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1135
0
      }
1136
3.58M
1137
3.58M
      return *this;
1138
3.58M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator++()
Line
Count
Source
1120
36.4M
    defusechain_instr_iterator &operator++() {          // Preincrement
1121
36.4M
      assert(Op && "Cannot increment end iterator!");
1122
36.4M
      if (ByOperand)
1123
0
        advance();
1124
36.4M
      else if (ByInstr) {
1125
36.4M
        MachineInstr *P = Op->getParent();
1126
36.9M
        do {
1127
36.9M
          advance();
1128
36.9M
        } while (Op && 
Op->getParent() == P23.9M
);
1129
36.4M
      } else 
if (0
ByBundle0
) {
1130
0
        MachineBasicBlock::instr_iterator P =
1131
0
            getBundleStart(Op->getParent()->getIterator());
1132
0
        do {
1133
0
          advance();
1134
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1135
0
      }
1136
36.4M
1137
36.4M
      return *this;
1138
36.4M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator++()
Line
Count
Source
1120
4.76M
    defusechain_instr_iterator &operator++() {          // Preincrement
1121
4.76M
      assert(Op && "Cannot increment end iterator!");
1122
4.76M
      if (ByOperand)
1123
0
        advance();
1124
4.76M
      else if (ByInstr) {
1125
4.76M
        MachineInstr *P = Op->getParent();
1126
4.79M
        do {
1127
4.79M
          advance();
1128
4.79M
        } while (Op && 
Op->getParent() == P3.78M
);
1129
4.76M
      } else 
if (0
ByBundle0
) {
1130
0
        MachineBasicBlock::instr_iterator P =
1131
0
            getBundleStart(Op->getParent()->getIterator());
1132
0
        do {
1133
0
          advance();
1134
0
        } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1135
0
      }
1136
4.76M
1137
4.76M
      return *this;
1138
4.76M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator++()
Line
Count
Source
1120
770k
    defusechain_instr_iterator &operator++() {          // Preincrement
1121
770k
      assert(Op && "Cannot increment end iterator!");
1122
770k
      if (ByOperand)
1123
0
        advance();
1124
770k
      else if (ByInstr) {
1125
0
        MachineInstr *P = Op->getParent();
1126
0
        do {
1127
0
          advance();
1128
0
        } while (Op && Op->getParent() == P);
1129
770k
      } else if (ByBundle) {
1130
770k
        MachineBasicBlock::instr_iterator P =
1131
770k
            getBundleStart(Op->getParent()->getIterator());
1132
772k
        do {
1133
772k
          advance();
1134
772k
        } while (Op && 
getBundleStart(Op->getParent()->getIterator()) == P485k
);
1135
770k
      }
1136
770k
1137
770k
      return *this;
1138
770k
    }
1139
34.8M
    defusechain_instr_iterator operator++(int) {        // Postincrement
1140
34.8M
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1141
34.8M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator++(int)
Line
Count
Source
1139
33.2M
    defusechain_instr_iterator operator++(int) {        // Postincrement
1140
33.2M
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1141
33.2M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator++(int)
Line
Count
Source
1139
165k
    defusechain_instr_iterator operator++(int) {        // Postincrement
1140
165k
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1141
165k
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator++(int)
Line
Count
Source
1139
770k
    defusechain_instr_iterator operator++(int) {        // Postincrement
1140
770k
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1141
770k
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator++(int)
Line
Count
Source
1139
601k
    defusechain_instr_iterator operator++(int) {        // Postincrement
1140
601k
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1141
601k
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator++(int)
Line
Count
Source
1139
254
    defusechain_instr_iterator operator++(int) {        // Postincrement
1140
254
      defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1141
254
    }
1142
1143
    // Retrieve a reference to the current operand.
1144
170M
    MachineInstr &operator*() const {
1145
170M
      assert(Op && "Cannot dereference end iterator!");
1146
170M
      if (ByBundle)
1147
770k
        return *getBundleStart(Op->getParent()->getIterator());
1148
169M
      return *Op->getParent();
1149
169M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator*() const
Line
Count
Source
1144
71.4M
    MachineInstr &operator*() const {
1145
71.4M
      assert(Op && "Cannot dereference end iterator!");
1146
71.4M
      if (ByBundle)
1147
0
        return *getBundleStart(Op->getParent()->getIterator());
1148
71.4M
      return *Op->getParent();
1149
71.4M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator*() const
Line
Count
Source
1144
48.2M
    MachineInstr &operator*() const {
1145
48.2M
      assert(Op && "Cannot dereference end iterator!");
1146
48.2M
      if (ByBundle)
1147
0
        return *getBundleStart(Op->getParent()->getIterator());
1148
48.2M
      return *Op->getParent();
1149
48.2M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator*() const
Line
Count
Source
1144
8.45M
    MachineInstr &operator*() const {
1145
8.45M
      assert(Op && "Cannot dereference end iterator!");
1146
8.45M
      if (ByBundle)
1147
0
        return *getBundleStart(Op->getParent()->getIterator());
1148
8.45M
      return *Op->getParent();
1149
8.45M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, true, false>::operator*() const
Line
Count
Source
1144
36.4M
    MachineInstr &operator*() const {
1145
36.4M
      assert(Op && "Cannot dereference end iterator!");
1146
36.4M
      if (ByBundle)
1147
0
        return *getBundleStart(Op->getParent()->getIterator());
1148
36.4M
      return *Op->getParent();
1149
36.4M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, true, false, true, false>::operator*() const
Line
Count
Source
1144
4.76M
    MachineInstr &operator*() const {
1145
4.76M
      assert(Op && "Cannot dereference end iterator!");
1146
4.76M
      if (ByBundle)
1147
0
        return *getBundleStart(Op->getParent()->getIterator());
1148
4.76M
      return *Op->getParent();
1149
4.76M
    }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, true, false, false, false, true>::operator*() const
Line
Count
Source
1144
770k
    MachineInstr &operator*() const {
1145
770k
      assert(Op && "Cannot dereference end iterator!");
1146
770k
      if (ByBundle)
1147
770k
        return *getBundleStart(Op->getParent()->getIterator());
1148
0
      return *Op->getParent();
1149
0
    }
1150
1151
2.97k
    MachineInstr *operator->() const { return &operator*(); }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, true, false, true, false>::operator->() const
Line
Count
Source
1151
1.15k
    MachineInstr *operator->() const { return &operator*(); }
llvm::MachineRegisterInfo::defusechain_instr_iterator<false, true, false, false, true, false>::operator->() const
Line
Count
Source
1151
60
    MachineInstr *operator->() const { return &operator*(); }
llvm::MachineRegisterInfo::defusechain_instr_iterator<true, false, false, false, true, false>::operator->() const
Line
Count
Source
1151
1.76k
    MachineInstr *operator->() const { return &operator*(); }
1152
  };
1153
};
1154
1155
/// Iterate over the pressure sets affected by the given physical or virtual
1156
/// register. If Reg is physical, it must be a register unit (from
1157
/// MCRegUnitIterator).
1158
class PSetIterator {
1159
  const int *PSet = nullptr;
1160
  unsigned Weight = 0;
1161
1162
public:
1163
  PSetIterator() = default;
1164
1165
35.7M
  PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
1166
35.7M
    const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1167
35.7M
    if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
1168
32.9M
      const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
1169
32.9M
      PSet = TRI->getRegClassPressureSets(RC);
1170
32.9M
      Weight = TRI->getRegClassWeight(RC).RegWeight;
1171
32.9M
    }
1172
2.82M
    else {
1173
2.82M
      PSet = TRI->getRegUnitPressureSets(RegUnit);
1174
2.82M
      Weight = TRI->getRegUnitWeight(RegUnit);
1175
2.82M
    }
1176
35.7M
    if (*PSet == -1)
1177
362k
      PSet = nullptr;
1178
35.7M
  }
1179
1180
198M
  bool isValid() const { return PSet; }
1181
1182
35.7M
  unsigned getWeight() const { return Weight; }
1183
1184
468M
  unsigned operator*() const { return *PSet; }
1185
1186
163M
  void operator++() {
1187
163M
    assert(isValid() && "Invalid PSetIterator.");
1188
163M
    ++PSet;
1189
163M
    if (*PSet == -1)
1190
34.6M
      PSet = nullptr;
1191
163M
  }
1192
};
1193
1194
inline PSetIterator MachineRegisterInfo::
1195
35.7M
getPressureSets(unsigned RegUnit) const {
1196
35.7M
  return PSetIterator(RegUnit, this);
1197
35.7M
}
1198
1199
} // end namespace llvm
1200
1201
#endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H