Coverage Report

Created: 2019-02-21 13:17

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/RegisterClassInfo.h
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//===- RegisterClassInfo.h - Dynamic Register Class Info --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the RegisterClassInfo class which provides dynamic
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// information about target register classes. Callee saved and reserved
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// registers depends on calling conventions and other dynamic information, so
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// some things cannot be determined statically.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_REGISTERCLASSINFO_H
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#define LLVM_CODEGEN_REGISTERCLASSINFO_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include <cassert>
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#include <cstdint>
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#include <memory>
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namespace llvm {
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class RegisterClassInfo {
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  struct RCInfo {
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    unsigned Tag = 0;
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    unsigned NumRegs = 0;
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    bool ProperSubClass = false;
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    uint8_t MinCost = 0;
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    uint16_t LastCostChange = 0;
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    std::unique_ptr<MCPhysReg[]> Order;
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    RCInfo() = default;
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12.3M
    operator ArrayRef<MCPhysReg>() const {
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12.3M
      return makeArrayRef(Order.get(), NumRegs);
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    }
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  };
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  // Brief cached information for each register class.
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  std::unique_ptr<RCInfo[]> RegClass;
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  // Tag changes whenever cached information needs to be recomputed. An RCInfo
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  // entry is valid when its tag matches.
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  unsigned Tag = 0;
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  const MachineFunction *MF = nullptr;
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  const TargetRegisterInfo *TRI = nullptr;
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  // Callee saved registers of last MF. Assumed to be valid until the next
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  // runOnFunction() call.
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  // Used only to determine if an update was made to CalleeSavedAliases.
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  const MCPhysReg *CalleeSavedRegs = nullptr;
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  // Map register alias to the callee saved Register.
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  SmallVector<MCPhysReg, 4> CalleeSavedAliases;
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  // Reserved registers in the current MF.
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  BitVector Reserved;
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  std::unique_ptr<unsigned[]> PSetLimits;
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  // Compute all information about RC.
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  void compute(const TargetRegisterClass *RC) const;
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  // Return an up-to-date RCInfo for RC.
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27.3M
  const RCInfo &get(const TargetRegisterClass *RC) const {
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    const RCInfo &RCI = RegClass[RC->getID()];
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    if (Tag != RCI.Tag)
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      compute(RC);
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    return RCI;
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  }
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public:
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  RegisterClassInfo();
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  /// runOnFunction - Prepare to answer questions about MF. This must be called
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  /// before any other methods are used.
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  void runOnMachineFunction(const MachineFunction &MF);
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  /// getNumAllocatableRegs - Returns the number of actually allocatable
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  /// registers in RC in the current function.
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  unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
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    return get(RC).NumRegs;
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  }
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  /// getOrder - Returns the preferred allocation order for RC. The order
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  /// contains no reserved registers, and registers that alias callee saved
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  /// registers come last.
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  ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const {
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    return get(RC);
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  }
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  /// isProperSubClass - Returns true if RC has a legal super-class with more
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  /// allocatable registers.
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  ///
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  /// Register classes like GR32_NOSP are not proper sub-classes because %esp
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  /// is not allocatable.  Similarly, tGPR is not a proper sub-class in Thumb
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  /// mode because the GPR super-class is not legal.
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  bool isProperSubClass(const TargetRegisterClass *RC) const {
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    return get(RC).ProperSubClass;
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  }
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  /// getLastCalleeSavedAlias - Returns the last callee saved register that
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  /// overlaps PhysReg, or 0 if Reg doesn't overlap a CalleeSavedAliases.
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  unsigned getLastCalleeSavedAlias(unsigned PhysReg) const {
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    assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
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    if (PhysReg < CalleeSavedAliases.size())
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      return CalleeSavedAliases[PhysReg];
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    return 0;
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  }
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  /// Get the minimum register cost in RC's allocation order.
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  /// This is the smallest value returned by TRI->getCostPerUse(Reg) for all
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  /// the registers in getOrder(RC).
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  unsigned getMinCost(const TargetRegisterClass *RC) {
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    return get(RC).MinCost;
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  }
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  /// Get the position of the last cost change in getOrder(RC).
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  ///
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  /// All registers in getOrder(RC).slice(getLastCostChange(RC)) will have the
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  /// same cost according to TRI->getCostPerUse().
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  unsigned getLastCostChange(const TargetRegisterClass *RC) {
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    return get(RC).LastCostChange;
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  }
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  /// Get the register unit limit for the given pressure set index.
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  ///
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  /// RegisterClassInfo adjusts this limit for reserved registers.
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113M
  unsigned getRegPressureSetLimit(unsigned Idx) const {
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    if (!PSetLimits[Idx])
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      PSetLimits[Idx] = computePSetLimit(Idx);
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    return PSetLimits[Idx];
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  }
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protected:
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  unsigned computePSetLimit(unsigned Idx) const;
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};
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} // end namespace llvm
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#endif // LLVM_CODEGEN_REGISTERCLASSINFO_H