Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/RegisterPressure.h
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//===- RegisterPressure.h - Dynamic Register Pressure -----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the RegisterPressure class which can be used to track
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// MachineInstr level register pressure.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_REGISTERPRESSURE_H
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#define LLVM_CODEGEN_REGISTERPRESSURE_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/SparseSet.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/MC/LaneBitmask.h"
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#include <cassert>
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#include <cstddef>
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#include <cstdint>
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#include <cstdlib>
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#include <limits>
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#include <vector>
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namespace llvm {
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class LiveIntervals;
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class MachineFunction;
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class MachineInstr;
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class MachineRegisterInfo;
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class RegisterClassInfo;
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struct RegisterMaskPair {
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  unsigned RegUnit; ///< Virtual register or register unit.
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  LaneBitmask LaneMask;
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43
  RegisterMaskPair(unsigned RegUnit, LaneBitmask LaneMask)
44
45.8M
      : RegUnit(RegUnit), LaneMask(LaneMask) {}
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};
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47
/// Base class for register pressure results.
48
struct RegisterPressure {
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  /// Map of max reg pressure indexed by pressure set ID, not class ID.
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  std::vector<unsigned> MaxSetPressure;
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  /// List of live in virtual registers or physical register units.
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  SmallVector<RegisterMaskPair,8> LiveInRegs;
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  SmallVector<RegisterMaskPair,8> LiveOutRegs;
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56
  void dump(const TargetRegisterInfo *TRI) const;
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};
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/// RegisterPressure computed within a region of instructions delimited by
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/// TopIdx and BottomIdx.  During pressure computation, the maximum pressure per
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/// register pressure set is increased. Once pressure within a region is fully
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/// computed, the live-in and live-out sets are recorded.
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///
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/// This is preferable to RegionPressure when LiveIntervals are available,
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/// because delimiting regions by SlotIndex is more robust and convenient than
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/// holding block iterators. The block contents can change without invalidating
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/// the pressure result.
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struct IntervalPressure : RegisterPressure {
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  /// Record the boundary of the region being tracked.
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  SlotIndex TopIdx;
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  SlotIndex BottomIdx;
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  void reset();
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  void openTop(SlotIndex NextTop);
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  void openBottom(SlotIndex PrevBottom);
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};
79
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/// RegisterPressure computed within a region of instructions delimited by
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/// TopPos and BottomPos. This is a less precise version of IntervalPressure for
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/// use when LiveIntervals are unavailable.
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struct RegionPressure : RegisterPressure {
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  /// Record the boundary of the region being tracked.
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  MachineBasicBlock::const_iterator TopPos;
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  MachineBasicBlock::const_iterator BottomPos;
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88
  void reset();
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90
  void openTop(MachineBasicBlock::const_iterator PrevTop);
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  void openBottom(MachineBasicBlock::const_iterator PrevBottom);
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};
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/// Capture a change in pressure for a single pressure set. UnitInc may be
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/// expressed in terms of upward or downward pressure depending on the client
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/// and will be dynamically adjusted for current liveness.
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///
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/// Pressure increments are tiny, typically 1-2 units, and this is only for
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/// heuristics, so we don't check UnitInc overflow. Instead, we may have a
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/// higher level assert that pressure is consistent within a region. We also
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/// effectively ignore dead defs which don't affect heuristics much.
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class PressureChange {
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  uint16_t PSetID = 0; // ID+1. 0=Invalid.
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  int16_t UnitInc = 0;
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public:
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482M
  PressureChange() = default;
109
33.9M
  PressureChange(unsigned id): PSetID(id + 1) {
110
33.9M
    assert(id < std::numeric_limits<uint16_t>::max() && "PSetID overflow.");
111
33.9M
  }
112
113
544M
  bool isValid() const { return PSetID > 0; }
114
115
236M
  unsigned getPSet() const {
116
236M
    assert(isValid() && "invalid PressureChange");
117
236M
    return PSetID - 1;
118
236M
  }
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120
  // If PSetID is invalid, return UINT16_MAX to give it lowest priority.
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222M
  unsigned getPSetOrMax() const {
122
222M
    return (PSetID - 1) & std::numeric_limits<uint16_t>::max();
123
222M
  }
124
125
588M
  int getUnitInc() const { return UnitInc; }
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127
35.7M
  void setUnitInc(int Inc) { UnitInc = Inc; }
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129
0
  bool operator==(const PressureChange &RHS) const {
130
0
    return PSetID == RHS.PSetID && UnitInc == RHS.UnitInc;
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0
  }
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};
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/// List of PressureChanges in order of increasing, unique PSetID.
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///
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/// Use a small fixed number, because we can fit more PressureChanges in an
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/// empty SmallVector than ever need to be tracked per register class. If more
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/// PSets are affected, then we only track the most constrained.
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class PressureDiff {
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  // The initial design was for MaxPSets=4, but that requires PSet partitions,
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  // which are not yet implemented. (PSet partitions are equivalent PSets given
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  // the register classes actually in use within the scheduling region.)
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  enum { MaxPSets = 16 };
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  PressureChange PressureChanges[MaxPSets];
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  using iterator = PressureChange *;
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149
30.3M
  iterator nonconst_begin() { return &PressureChanges[0]; }
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30.3M
  iterator nonconst_end() { return &PressureChanges[MaxPSets]; }
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public:
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  using const_iterator = const PressureChange *;
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32.2M
  const_iterator begin() const { return &PressureChanges[0]; }
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32.2M
  const_iterator end() const { return &PressureChanges[MaxPSets]; }
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  void addPressureChange(unsigned RegUnit, bool IsDec,
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                         const MachineRegisterInfo *MRI);
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  void dump(const TargetRegisterInfo &TRI) const;
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};
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/// List of registers defined and used by a machine instruction.
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class RegisterOperands {
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public:
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  /// List of virtual registers and register units read by the instruction.
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  SmallVector<RegisterMaskPair, 8> Uses;
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  /// List of virtual registers and register units defined by the
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  /// instruction which are not dead.
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  SmallVector<RegisterMaskPair, 8> Defs;
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  /// List of virtual registers and register units defined by the
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  /// instruction but dead.
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  SmallVector<RegisterMaskPair, 8> DeadDefs;
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  /// Analyze the given instruction \p MI and fill in the Uses, Defs and
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  /// DeadDefs list based on the MachineOperand flags.
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  void collect(const MachineInstr &MI, const TargetRegisterInfo &TRI,
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               const MachineRegisterInfo &MRI, bool TrackLaneMasks,
180
               bool IgnoreDead);
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  /// Use liveness information to find dead defs not marked with a dead flag
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  /// and move them to the DeadDefs vector.
184
  void detectDeadDefs(const MachineInstr &MI, const LiveIntervals &LIS);
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  /// Use liveness information to find out which uses/defs are partially
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  /// undefined/dead and adjust the RegisterMaskPairs accordingly.
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  /// If \p AddFlagsMI is given then missing read-undef and dead flags will be
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  /// added to the instruction.
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  void adjustLaneLiveness(const LiveIntervals &LIS,
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                          const MachineRegisterInfo &MRI, SlotIndex Pos,
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                          MachineInstr *AddFlagsMI = nullptr);
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};
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/// Array of PressureDiffs.
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class PressureDiffs {
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  PressureDiff *PDiffArray = nullptr;
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  unsigned Size = 0;
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  unsigned Max = 0;
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public:
202
445k
  PressureDiffs() = default;
203
445k
  ~PressureDiffs() { free(PDiffArray); }
204
205
4.64M
  void clear() { Size = 0; }
206
207
  void init(unsigned N);
208
209
38.8M
  PressureDiff &operator[](unsigned Idx) {
210
38.8M
    assert(Idx < Size && "PressureDiff index out of bounds");
211
38.8M
    return PDiffArray[Idx];
212
38.8M
  }
213
0
  const PressureDiff &operator[](unsigned Idx) const {
214
0
    return const_cast<PressureDiffs*>(this)->operator[](Idx);
215
0
  }
216
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  /// Record pressure difference induced by the given operand list to
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  /// node with index \p Idx.
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  void addInstruction(unsigned Idx, const RegisterOperands &RegOpers,
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                      const MachineRegisterInfo &MRI);
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};
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/// Store the effects of a change in pressure on things that MI scheduler cares
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/// about.
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///
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/// Excess records the value of the largest difference in register units beyond
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/// the target's pressure limits across the affected pressure sets, where
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/// largest is defined as the absolute value of the difference. Negative
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/// ExcessUnits indicates a reduction in pressure that had already exceeded the
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/// target's limits.
231
///
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/// CriticalMax records the largest increase in the tracker's max pressure that
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/// exceeds the critical limit for some pressure set determined by the client.
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///
235
/// CurrentMax records the largest increase in the tracker's max pressure that
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/// exceeds the current limit for some pressure set determined by the client.
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struct RegPressureDelta {
238
  PressureChange Excess;
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  PressureChange CriticalMax;
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  PressureChange CurrentMax;
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144M
  RegPressureDelta() = default;
243
244
0
  bool operator==(const RegPressureDelta &RHS) const {
245
0
    return Excess == RHS.Excess && CriticalMax == RHS.CriticalMax
246
0
      && CurrentMax == RHS.CurrentMax;
247
0
  }
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0
  bool operator!=(const RegPressureDelta &RHS) const {
249
0
    return !operator==(RHS);
250
0
  }
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};
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/// A set of live virtual registers and physical register units.
254
///
255
/// This is a wrapper around a SparseSet which deals with mapping register unit
256
/// and virtual register indexes to an index usable by the sparse set.
257
class LiveRegSet {
258
private:
259
  struct IndexMaskPair {
260
    unsigned Index;
261
    LaneBitmask LaneMask;
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263
    IndexMaskPair(unsigned Index, LaneBitmask LaneMask)
264
9.24M
        : Index(Index), LaneMask(LaneMask) {}
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42.7M
    unsigned getSparseSetIndex() const {
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42.7M
      return Index;
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42.7M
    }
269
  };
270
271
  using RegSet = SparseSet<IndexMaskPair>;
272
  RegSet Regs;
273
  unsigned NumRegUnits;
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32.1M
  unsigned getSparseIndexFromReg(unsigned Reg) const {
276
32.1M
    if (TargetRegisterInfo::isVirtualRegister(Reg))
277
29.6M
      return TargetRegisterInfo::virtReg2Index(Reg) + NumRegUnits;
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2.44M
    assert(Reg < NumRegUnits);
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2.44M
    return Reg;
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2.44M
  }
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282
3.52M
  unsigned getRegFromSparseIndex(unsigned SparseIndex) const {
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3.52M
    if (SparseIndex >= NumRegUnits)
284
2.86M
      return TargetRegisterInfo::index2VirtReg(SparseIndex-NumRegUnits);
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657k
    return SparseIndex;
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657k
  }
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public:
289
  void clear();
290
  void init(const MachineRegisterInfo &MRI);
291
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17.9M
  LaneBitmask contains(unsigned Reg) const {
293
17.9M
    unsigned SparseIndex = getSparseIndexFromReg(Reg);
294
17.9M
    RegSet::const_iterator I = Regs.find(SparseIndex);
295
17.9M
    if (I == Regs.end())
296
10.7M
      return LaneBitmask::getNone();
297
7.27M
    return I->LaneMask;
298
7.27M
  }
299
300
  /// Mark the \p Pair.LaneMask lanes of \p Pair.Reg as live.
301
  /// Returns the previously live lanes of \p Pair.Reg.
302
9.24M
  LaneBitmask insert(RegisterMaskPair Pair) {
303
9.24M
    unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
304
9.24M
    auto InsertRes = Regs.insert(IndexMaskPair(SparseIndex, Pair.LaneMask));
305
9.24M
    if (!InsertRes.second) {
306
3.66M
      LaneBitmask PrevMask = InsertRes.first->LaneMask;
307
3.66M
      InsertRes.first->LaneMask |= Pair.LaneMask;
308
3.66M
      return PrevMask;
309
3.66M
    }
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5.58M
    return LaneBitmask::getNone();
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5.58M
  }
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313
  /// Clears the \p Pair.LaneMask lanes of \p Pair.Reg (mark them as dead).
314
  /// Returns the previously live lanes of \p Pair.Reg.
315
4.91M
  LaneBitmask erase(RegisterMaskPair Pair) {
316
4.91M
    unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
317
4.91M
    RegSet::iterator I = Regs.find(SparseIndex);
318
4.91M
    if (I == Regs.end())
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323k
      return LaneBitmask::getNone();
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4.59M
    LaneBitmask PrevMask = I->LaneMask;
321
4.59M
    I->LaneMask &= ~Pair.LaneMask;
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4.59M
    return PrevMask;
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4.59M
  }
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632k
  size_t size() const {
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632k
    return Regs.size();
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632k
  }
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329
  template<typename ContainerT>
330
632k
  void appendTo(ContainerT &To) const {
331
3.52M
    for (const IndexMaskPair &P : Regs) {
332
3.52M
      unsigned Reg = getRegFromSparseIndex(P.Index);
333
3.52M
      if (P.LaneMask.any())
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1.76M
        To.push_back(RegisterMaskPair(Reg, P.LaneMask));
335
3.52M
    }
336
632k
  }
337
};
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339
/// Track the current register pressure at some position in the instruction
340
/// stream, and remember the high water mark within the region traversed. This
341
/// does not automatically consider live-through ranges. The client may
342
/// independently adjust for global liveness.
343
///
344
/// Each RegPressureTracker only works within a MachineBasicBlock. Pressure can
345
/// be tracked across a larger region by storing a RegisterPressure result at
346
/// each block boundary and explicitly adjusting pressure to account for block
347
/// live-in and live-out register sets.
348
///
349
/// RegPressureTracker holds a reference to a RegisterPressure result that it
350
/// computes incrementally. During downward tracking, P.BottomIdx or P.BottomPos
351
/// is invalid until it reaches the end of the block or closeRegion() is
352
/// explicitly called. Similarly, P.TopIdx is invalid during upward
353
/// tracking. Changing direction has the side effect of closing region, and
354
/// traversing past TopIdx or BottomIdx reopens it.
355
class RegPressureTracker {
356
  const MachineFunction *MF = nullptr;
357
  const TargetRegisterInfo *TRI = nullptr;
358
  const RegisterClassInfo *RCI = nullptr;
359
  const MachineRegisterInfo *MRI;
360
  const LiveIntervals *LIS = nullptr;
361
362
  /// We currently only allow pressure tracking within a block.
363
  const MachineBasicBlock *MBB = nullptr;
364
365
  /// Track the max pressure within the region traversed so far.
366
  RegisterPressure &P;
367
368
  /// Run in two modes dependending on whether constructed with IntervalPressure
369
  /// or RegisterPressure. If requireIntervals is false, LIS are ignored.
370
  bool RequireIntervals;
371
372
  /// True if UntiedDefs will be populated.
373
  bool TrackUntiedDefs = false;
374
375
  /// True if lanemasks should be tracked.
376
  bool TrackLaneMasks = false;
377
378
  /// Register pressure corresponds to liveness before this instruction
379
  /// iterator. It may point to the end of the block or a DebugValue rather than
380
  /// an instruction.
381
  MachineBasicBlock::const_iterator CurrPos;
382
383
  /// Pressure map indexed by pressure set ID, not class ID.
384
  std::vector<unsigned> CurrSetPressure;
385
386
  /// Set of live registers.
387
  LiveRegSet LiveRegs;
388
389
  /// Set of vreg defs that start a live range.
390
  SparseSet<unsigned, VirtReg2IndexFunctor> UntiedDefs;
391
  /// Live-through pressure.
392
  std::vector<unsigned> LiveThruPressure;
393
394
public:
395
1.33M
  RegPressureTracker(IntervalPressure &rp) : P(rp), RequireIntervals(true) {}
396
0
  RegPressureTracker(RegionPressure &rp) : P(rp), RequireIntervals(false) {}
397
398
  void reset();
399
400
  void init(const MachineFunction *mf, const RegisterClassInfo *rci,
401
            const LiveIntervals *lis, const MachineBasicBlock *mbb,
402
            MachineBasicBlock::const_iterator pos,
403
            bool TrackLaneMasks, bool TrackUntiedDefs);
404
405
  /// Force liveness of virtual registers or physical register
406
  /// units. Particularly useful to initialize the livein/out state of the
407
  /// tracker before the first call to advance/recede.
408
  void addLiveRegs(ArrayRef<RegisterMaskPair> Regs);
409
410
  /// Get the MI position corresponding to this register pressure.
411
10.9M
  MachineBasicBlock::const_iterator getPos() const { return CurrPos; }
412
413
  // Reset the MI position corresponding to the register pressure. This allows
414
  // schedulers to move instructions above the RegPressureTracker's
415
  // CurrPos. Since the pressure is computed before CurrPos, the iterator
416
  // position changes while pressure does not.
417
1.07M
  void setPos(MachineBasicBlock::const_iterator Pos) { CurrPos = Pos; }
418
419
  /// Recede across the previous instruction.
420
  void recede(SmallVectorImpl<RegisterMaskPair> *LiveUses = nullptr);
421
422
  /// Recede across the previous instruction.
423
  /// This "low-level" variant assumes that recedeSkipDebugValues() was
424
  /// called previously and takes precomputed RegisterOperands for the
425
  /// instruction.
426
  void recede(const RegisterOperands &RegOpers,
427
              SmallVectorImpl<RegisterMaskPair> *LiveUses = nullptr);
428
429
  /// Recede until we find an instruction which is not a DebugValue.
430
  void recedeSkipDebugValues();
431
432
  /// Advance across the current instruction.
433
  void advance();
434
435
  /// Advance across the current instruction.
436
  /// This is a "low-level" variant of advance() which takes precomputed
437
  /// RegisterOperands of the instruction.
438
  void advance(const RegisterOperands &RegOpers);
439
440
  /// Finalize the region boundaries and recored live ins and live outs.
441
  void closeRegion();
442
443
  /// Initialize the LiveThru pressure set based on the untied defs found in
444
  /// RPTracker.
445
  void initLiveThru(const RegPressureTracker &RPTracker);
446
447
  /// Copy an existing live thru pressure result.
448
158k
  void initLiveThru(ArrayRef<unsigned> PressureSet) {
449
158k
    LiveThruPressure.assign(PressureSet.begin(), PressureSet.end());
450
158k
  }
451
452
316k
  ArrayRef<unsigned> getLiveThru() const { return LiveThruPressure; }
453
454
  /// Get the resulting register pressure over the traversed region.
455
  /// This result is complete if closeRegion() was explicitly invoked.
456
3.82M
  RegisterPressure &getPressure() { return P; }
457
0
  const RegisterPressure &getPressure() const { return P; }
458
459
  /// Get the register set pressure at the current position, which may be less
460
  /// than the pressure across the traversed region.
461
370k
  const std::vector<unsigned> &getRegSetPressureAtPos() const {
462
370k
    return CurrSetPressure;
463
370k
  }
464
465
  bool isTopClosed() const;
466
  bool isBottomClosed() const;
467
468
  void closeTop();
469
  void closeBottom();
470
471
  /// Consider the pressure increase caused by traversing this instruction
472
  /// bottom-up. Find the pressure set with the most change beyond its pressure
473
  /// limit based on the tracker's current pressure, and record the number of
474
  /// excess register units of that pressure set introduced by this instruction.
475
  void getMaxUpwardPressureDelta(const MachineInstr *MI,
476
                                 PressureDiff *PDiff,
477
                                 RegPressureDelta &Delta,
478
                                 ArrayRef<PressureChange> CriticalPSets,
479
                                 ArrayRef<unsigned> MaxPressureLimit);
480
481
  void getUpwardPressureDelta(const MachineInstr *MI,
482
                              /*const*/ PressureDiff &PDiff,
483
                              RegPressureDelta &Delta,
484
                              ArrayRef<PressureChange> CriticalPSets,
485
                              ArrayRef<unsigned> MaxPressureLimit) const;
486
487
  /// Consider the pressure increase caused by traversing this instruction
488
  /// top-down. Find the pressure set with the most change beyond its pressure
489
  /// limit based on the tracker's current pressure, and record the number of
490
  /// excess register units of that pressure set introduced by this instruction.
491
  void getMaxDownwardPressureDelta(const MachineInstr *MI,
492
                                   RegPressureDelta &Delta,
493
                                   ArrayRef<PressureChange> CriticalPSets,
494
                                   ArrayRef<unsigned> MaxPressureLimit);
495
496
  /// Find the pressure set with the most change beyond its pressure limit after
497
  /// traversing this instruction either upward or downward depending on the
498
  /// closed end of the current region.
499
  void getMaxPressureDelta(const MachineInstr *MI,
500
                           RegPressureDelta &Delta,
501
                           ArrayRef<PressureChange> CriticalPSets,
502
102k
                           ArrayRef<unsigned> MaxPressureLimit) {
503
102k
    if (isTopClosed())
504
54.7k
      return getMaxDownwardPressureDelta(MI, Delta, CriticalPSets,
505
54.7k
                                         MaxPressureLimit);
506
47.9k
507
47.9k
    assert(isBottomClosed() && "Uninitialized pressure tracker");
508
47.9k
    return getMaxUpwardPressureDelta(MI, nullptr, Delta, CriticalPSets,
509
47.9k
                                     MaxPressureLimit);
510
47.9k
  }
511
512
  /// Get the pressure of each PSet after traversing this instruction bottom-up.
513
  void getUpwardPressure(const MachineInstr *MI,
514
                         std::vector<unsigned> &PressureResult,
515
                         std::vector<unsigned> &MaxPressureResult);
516
517
  /// Get the pressure of each PSet after traversing this instruction top-down.
518
  void getDownwardPressure(const MachineInstr *MI,
519
                           std::vector<unsigned> &PressureResult,
520
                           std::vector<unsigned> &MaxPressureResult);
521
522
  void getPressureAfterInst(const MachineInstr *MI,
523
                            std::vector<unsigned> &PressureResult,
524
0
                            std::vector<unsigned> &MaxPressureResult) {
525
0
    if (isTopClosed())
526
0
      return getUpwardPressure(MI, PressureResult, MaxPressureResult);
527
0
528
0
    assert(isBottomClosed() && "Uninitialized pressure tracker");
529
0
    return getDownwardPressure(MI, PressureResult, MaxPressureResult);
530
0
  }
531
532
556k
  bool hasUntiedDef(unsigned VirtReg) const {
533
556k
    return UntiedDefs.count(VirtReg);
534
556k
  }
535
536
  void dump() const;
537
538
protected:
539
  /// Add Reg to the live out set and increase max pressure.
540
  void discoverLiveOut(RegisterMaskPair Pair);
541
  /// Add Reg to the live in set and increase max pressure.
542
  void discoverLiveIn(RegisterMaskPair Pair);
543
544
  /// Get the SlotIndex for the first nondebug instruction including or
545
  /// after the current position.
546
  SlotIndex getCurrSlot() const;
547
548
  void increaseRegPressure(unsigned RegUnit, LaneBitmask PreviousMask,
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                           LaneBitmask NewMask);
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  void decreaseRegPressure(unsigned RegUnit, LaneBitmask PreviousMask,
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                           LaneBitmask NewMask);
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  void bumpDeadDefs(ArrayRef<RegisterMaskPair> DeadDefs);
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  void bumpUpwardPressure(const MachineInstr *MI);
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  void bumpDownwardPressure(const MachineInstr *MI);
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  void discoverLiveInOrOut(RegisterMaskPair Pair,
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                           SmallVectorImpl<RegisterMaskPair> &LiveInOrOut);
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  LaneBitmask getLastUsedLanes(unsigned RegUnit, SlotIndex Pos) const;
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  LaneBitmask getLiveLanesAt(unsigned RegUnit, SlotIndex Pos) const;
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  LaneBitmask getLiveThroughAt(unsigned RegUnit, SlotIndex Pos) const;
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};
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void dumpRegSetPressure(ArrayRef<unsigned> SetPressure,
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                        const TargetRegisterInfo *TRI);
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569
} // end namespace llvm
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#endif // LLVM_CODEGEN_REGISTERPRESSURE_H