Coverage Report

Created: 2019-06-16 23:17

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
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//===- ScheduleDAGInstrs.h - MachineInstr Scheduling ------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file Implements the ScheduleDAGInstrs class, which implements scheduling
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/// for a MachineInstr-based dependency graph.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
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#define LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/PointerIntPair.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/SparseMultiSet.h"
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#include "llvm/ADT/SparseSet.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSchedule.h"
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#include "llvm/MC/LaneBitmask.h"
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#include <cassert>
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#include <cstdint>
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#include <list>
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#include <utility>
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#include <vector>
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namespace llvm {
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  class LiveIntervals;
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  class MachineFrameInfo;
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  class MachineFunction;
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  class MachineInstr;
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  class MachineLoopInfo;
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  class MachineOperand;
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  struct MCSchedClassDesc;
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  class PressureDiffs;
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  class PseudoSourceValue;
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  class RegPressureTracker;
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  class UndefValue;
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  class Value;
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  /// An individual mapping from virtual register number to SUnit.
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  struct VReg2SUnit {
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    unsigned VirtReg;
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    LaneBitmask LaneMask;
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    SUnit *SU;
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    VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU)
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17.6M
      : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
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    unsigned getSparseSetIndex() const {
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59.5M
      return TargetRegisterInfo::virtReg2Index(VirtReg);
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    }
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  };
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  /// Mapping from virtual register to SUnit including an operand index.
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  struct VReg2SUnitOperIdx : public VReg2SUnit {
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    unsigned OperandIndex;
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    VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask,
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                      unsigned OperandIndex, SUnit *SU)
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12.4M
      : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {}
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  };
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  /// Record a physical register access.
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  /// For non-data-dependent uses, OpIdx == -1.
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  struct PhysRegSUOper {
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    SUnit *SU;
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    int OpIdx;
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    unsigned Reg;
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13.7M
    PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
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    unsigned getSparseSetIndex() const { return Reg; }
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  };
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  /// Use a SparseMultiSet to track physical registers. Storage is only
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  /// allocated once for the pass. It can be cleared in constant time and reused
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  /// without any frees.
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  using Reg2SUnitsMap =
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      SparseMultiSet<PhysRegSUOper, identity<unsigned>, uint16_t>;
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  /// Use SparseSet as a SparseMap by relying on the fact that it never
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  /// compares ValueT's, only unsigned keys. This allows the set to be cleared
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  /// between scheduling regions in constant time as long as ValueT does not
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  /// require a destructor.
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  using VReg2SUnitMap = SparseSet<VReg2SUnit, VirtReg2IndexFunctor>;
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  /// Track local uses of virtual registers. These uses are gathered by the DAG
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  /// builder and may be consulted by the scheduler to avoid iterating an entire
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  /// vreg use list.
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  using VReg2SUnitMultiMap = SparseMultiSet<VReg2SUnit, VirtReg2IndexFunctor>;
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  using VReg2SUnitOperIdxMultiMap =
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      SparseMultiSet<VReg2SUnitOperIdx, VirtReg2IndexFunctor>;
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  using ValueType = PointerUnion<const Value *, const PseudoSourceValue *>;
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  struct UnderlyingObject : PointerIntPair<ValueType, 1, bool> {
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    UnderlyingObject(ValueType V, bool MayAlias)
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1.11M
        : PointerIntPair<ValueType, 1, bool>(V, MayAlias) {}
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    ValueType getValue() const { return getPointer(); }
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    bool mayAlias() const { return getInt(); }
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  };
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  using UnderlyingObjectsVector = SmallVector<UnderlyingObject, 4>;
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  /// A ScheduleDAG for scheduling lists of MachineInstr.
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  class ScheduleDAGInstrs : public ScheduleDAG {
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  protected:
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    const MachineLoopInfo *MLI;
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    const MachineFrameInfo &MFI;
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    /// TargetSchedModel provides an interface to the machine model.
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    TargetSchedModel SchedModel;
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    /// True if the DAG builder should remove kill flags (in preparation for
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    /// rescheduling).
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    bool RemoveKillFlags;
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    /// The standard DAG builder does not normally include terminators as DAG
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    /// nodes because it does not create the necessary dependencies to prevent
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    /// reordering. A specialized scheduler can override
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    /// TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate
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    /// it has taken responsibility for scheduling the terminator correctly.
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    bool CanHandleTerminators = false;
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    /// Whether lane masks should get tracked.
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    bool TrackLaneMasks = false;
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    // State specific to the current scheduling region.
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    // ------------------------------------------------
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    /// The block in which to insert instructions
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    MachineBasicBlock *BB;
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    /// The beginning of the range to be scheduled.
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    MachineBasicBlock::iterator RegionBegin;
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    /// The end of the range to be scheduled.
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    MachineBasicBlock::iterator RegionEnd;
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    /// Instructions in this region (distance(RegionBegin, RegionEnd)).
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    unsigned NumRegionInstrs;
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    /// After calling BuildSchedGraph, each machine instruction in the current
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    /// scheduling region is mapped to an SUnit.
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    DenseMap<MachineInstr*, SUnit*> MISUnitMap;
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    // State internal to DAG building.
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    // -------------------------------
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    /// Defs, Uses - Remember where defs and uses of each register are as we
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    /// iterate upward through the instructions. This is allocated here instead
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    /// of inside BuildSchedGraph to avoid the need for it to be initialized and
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    /// destructed for each block.
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    Reg2SUnitsMap Defs;
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    Reg2SUnitsMap Uses;
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    /// Tracks the last instruction(s) in this region defining each virtual
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    /// register. There may be multiple current definitions for a register with
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    /// disjunct lanemasks.
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    VReg2SUnitMultiMap CurrentVRegDefs;
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    /// Tracks the last instructions in this region using each virtual register.
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    VReg2SUnitOperIdxMultiMap CurrentVRegUses;
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    AliasAnalysis *AAForDep = nullptr;
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    /// Remember a generic side-effecting instruction as we proceed.
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    /// No other SU ever gets scheduled around it (except in the special
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    /// case of a huge region that gets reduced).
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    SUnit *BarrierChain = nullptr;
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  public:
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    /// A list of SUnits, used in Value2SUsMap, during DAG construction.
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    /// Note: to gain speed it might be worth investigating an optimized
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    /// implementation of this data structure, such as a singly linked list
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    /// with a memory pool (SmallVector was tried but slow and SparseSet is not
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    /// applicable).
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    using SUList = std::list<SUnit *>;
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  protected:
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    /// A map from ValueType to SUList, used during DAG construction, as
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    /// a means of remembering which SUs depend on which memory locations.
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    class Value2SUsMap;
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    /// Reduces maps in FIFO order, by N SUs. This is better than turning
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    /// every Nth memory SU into BarrierChain in buildSchedGraph(), since
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    /// it avoids unnecessary edges between seen SUs above the new BarrierChain,
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    /// and those below it.
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    void reduceHugeMemNodeMaps(Value2SUsMap &stores,
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                               Value2SUsMap &loads, unsigned N);
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    /// Adds a chain edge between SUa and SUb, but only if both
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    /// AliasAnalysis and Target fail to deny the dependency.
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    void addChainDependency(SUnit *SUa, SUnit *SUb,
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                            unsigned Latency = 0);
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    /// Adds dependencies as needed from all SUs in list to SU.
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    void addChainDependencies(SUnit *SU, SUList &SUs, unsigned Latency) {
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      for (SUnit *Entry : SUs)
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        addChainDependency(SU, Entry, Latency);
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    }
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    /// Adds dependencies as needed from all SUs in map, to SU.
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    void addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap);
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    /// Adds dependencies as needed to SU, from all SUs mapped to V.
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    void addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap,
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                              ValueType V);
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    /// Adds barrier chain edges from all SUs in map, and then clear the map.
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    /// This is equivalent to insertBarrierChain(), but optimized for the common
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    /// case where the new BarrierChain (a global memory object) has a higher
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    /// NodeNum than all SUs in map. It is assumed BarrierChain has been set
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    /// before calling this.
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    void addBarrierChain(Value2SUsMap &map);
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    /// Inserts a barrier chain in a huge region, far below current SU.
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    /// Adds barrier chain edges from all SUs in map with higher NodeNums than
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    /// this new BarrierChain, and remove them from map. It is assumed
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    /// BarrierChain has been set before calling this.
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    void insertBarrierChain(Value2SUsMap &map);
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    /// For an unanalyzable memory access, this Value is used in maps.
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    UndefValue *UnknownValue;
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    /// Topo - A topological ordering for SUnits which permits fast IsReachable
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    /// and similar queries.
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    ScheduleDAGTopologicalSort Topo;
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    using DbgValueVector =
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        std::vector<std::pair<MachineInstr *, MachineInstr *>>;
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    /// Remember instruction that precedes DBG_VALUE.
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    /// These are generated by buildSchedGraph but persist so they can be
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    /// referenced when emitting the final schedule.
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    DbgValueVector DbgValues;
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    MachineInstr *FirstDbgValue = nullptr;
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    /// Set of live physical registers for updating kill flags.
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    LivePhysRegs LiveRegs;
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  public:
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    explicit ScheduleDAGInstrs(MachineFunction &mf,
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                               const MachineLoopInfo *mli,
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                               bool RemoveKillFlags = false);
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    ~ScheduleDAGInstrs() override = default;
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    /// Gets the machine model for instruction scheduling.
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    const TargetSchedModel *getSchedModel() const { return &SchedModel; }
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    /// Resolves and cache a resolved scheduling class for an SUnit.
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    const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
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      if (!SU->SchedClass && 
SchedModel.hasInstrSchedModel()12.7M
)
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        SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
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      return SU->SchedClass;
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    }
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    /// Returns an iterator to the top of the current scheduling region.
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    MachineBasicBlock::iterator begin() const { return RegionBegin; }
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    /// Returns an iterator to the bottom of the current scheduling region.
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    MachineBasicBlock::iterator end() const { return RegionEnd; }
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    /// Creates a new SUnit and return a ptr to it.
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    SUnit *newSUnit(MachineInstr *MI);
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    /// Returns an existing SUnit for this MI, or nullptr.
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    SUnit *getSUnit(MachineInstr *MI) const;
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    /// If this method returns true, handling of the scheduling regions
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    /// themselves (in case of a scheduling boundary in MBB) will be done
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    /// beginning with the topmost region of MBB.
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    virtual bool doMBBSchedRegionsTopDown() const { return false; }
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    /// Prepares to perform scheduling in the given block.
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    virtual void startBlock(MachineBasicBlock *BB);
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    /// Cleans up after scheduling in the given block.
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    virtual void finishBlock();
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    /// Initialize the DAG and common scheduler state for a new
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    /// scheduling region. This does not actually create the DAG, only clears
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    /// it. The scheduling driver may call BuildSchedGraph multiple times per
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    /// scheduling region.
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    virtual void enterRegion(MachineBasicBlock *bb,
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                             MachineBasicBlock::iterator begin,
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                             MachineBasicBlock::iterator end,
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                             unsigned regioninstrs);
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    /// Called when the scheduler has finished scheduling the current region.
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    virtual void exitRegion();
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    /// Builds SUnits for the current region.
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    /// If \p RPTracker is non-null, compute register pressure as a side effect.
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    /// The DAG builder is an efficient place to do it because it already visits
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    /// operands.
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    void buildSchedGraph(AliasAnalysis *AA,
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                         RegPressureTracker *RPTracker = nullptr,
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                         PressureDiffs *PDiffs = nullptr,
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                         LiveIntervals *LIS = nullptr,
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                         bool TrackLaneMasks = false);
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    /// Adds dependencies from instructions in the current list of
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    /// instructions being scheduled to scheduling barrier. We want to make sure
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    /// instructions which define registers that are either used by the
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    /// terminator or are live-out are properly scheduled. This is especially
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    /// important when the definition latency of the return value(s) are too
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    /// high to be hidden by the branch or when the liveout registers used by
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    /// instructions in the fallthrough block.
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    void addSchedBarrierDeps();
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    /// Orders nodes according to selected style.
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    ///
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    /// Typically, a scheduling algorithm will implement schedule() without
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    /// overriding enterRegion() or exitRegion().
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    virtual void schedule() = 0;
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    /// Allow targets to perform final scheduling actions at the level of the
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    /// whole MachineFunction. By default does nothing.
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    virtual void finalizeSchedule() {}
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    void dumpNode(const SUnit &SU) const override;
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    void dump() const override;
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    /// Returns a label for a DAG node that points to an instruction.
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    std::string getGraphNodeLabel(const SUnit *SU) const override;
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    /// Returns a label for the region of code covered by the DAG.
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    std::string getDAGName() const override;
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    /// Fixes register kill flags that scheduling has made invalid.
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    void fixupKills(MachineBasicBlock &MBB);
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    /// True if an edge can be added from PredSU to SuccSU without creating
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    /// a cycle.
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    bool canAddEdge(SUnit *SuccSU, SUnit *PredSU);
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    /// Add a DAG edge to the given SU with the given predecessor
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    /// dependence data.
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    ///
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    /// \returns true if the edge may be added without creating a cycle OR if an
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    /// equivalent edge already existed (false indicates failure).
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    bool addEdge(SUnit *SuccSU, const SDep &PredDep);
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  protected:
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    void initSUnits();
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    void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx);
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    void addPhysRegDeps(SUnit *SU, unsigned OperIdx);
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    void addVRegDefDeps(SUnit *SU, unsigned OperIdx);
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    void addVRegUseDeps(SUnit *SU, unsigned OperIdx);
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    /// Initializes register live-range state for updating kills.
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    /// PostRA helper for rewriting kill flags.
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    void startBlockForKills(MachineBasicBlock *BB);
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    /// Toggles a register operand kill flag.
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    ///
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    /// Other adjustments may be made to the instruction if necessary. Return
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    /// true if the operand has been deleted, false if not.
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    void toggleKillFlag(MachineInstr &MI, MachineOperand &MO);
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    /// Returns a mask for which lanes get read/written by the given (register)
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    /// machine operand.
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    LaneBitmask getLaneMaskForMO(const MachineOperand &MO) const;
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  };
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  /// Creates a new SUnit and return a ptr to it.
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  inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) {
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#ifndef NDEBUG
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    const SUnit *Addr = SUnits.empty() ? nullptr : &SUnits[0];
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#endif
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    SUnits.emplace_back(MI, (unsigned)SUnits.size());
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    assert((Addr == nullptr || Addr == &SUnits[0]) &&
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           "SUnits std::vector reallocated on the fly!");
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    return &SUnits.back();
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  }
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  /// Returns an existing SUnit for this MI, or nullptr.
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376k
  inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const {
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376k
    DenseMap<MachineInstr*, SUnit*>::const_iterator I = MISUnitMap.find(MI);
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    if (I == MISUnitMap.end())
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      return nullptr;
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    return I->second;
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  }
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} // end namespace llvm
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#endif // LLVM_CODEGEN_SCHEDULEDAGINSTRS_H