Coverage Report

Created: 2018-11-16 02:38

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/SelectionDAGISel.h
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//===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SelectionDAGISel class, which is used as the common
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// base class for SelectionDAG-based instruction selectors.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H
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#define LLVM_CODEGEN_SELECTIONDAGISEL_H
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/Pass.h"
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#include <memory>
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namespace llvm {
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  class FastISel;
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  class SelectionDAGBuilder;
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  class SDValue;
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  class MachineRegisterInfo;
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  class MachineBasicBlock;
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  class MachineFunction;
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  class MachineInstr;
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  class OptimizationRemarkEmitter;
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  class TargetLowering;
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  class TargetLibraryInfo;
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  class FunctionLoweringInfo;
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  class ScheduleHazardRecognizer;
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  class GCFunctionInfo;
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  class ScheduleDAGSDNodes;
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  class LoadInst;
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/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
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/// pattern-matching instruction selectors.
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class SelectionDAGISel : public MachineFunctionPass {
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public:
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  TargetMachine &TM;
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  const TargetLibraryInfo *LibInfo;
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  FunctionLoweringInfo *FuncInfo;
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  MachineFunction *MF;
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  MachineRegisterInfo *RegInfo;
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  SelectionDAG *CurDAG;
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  SelectionDAGBuilder *SDB;
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  AliasAnalysis *AA;
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  GCFunctionInfo *GFI;
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  CodeGenOpt::Level OptLevel;
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  const TargetInstrInfo *TII;
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  const TargetLowering *TLI;
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  bool FastISelFailed;
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  SmallPtrSet<const Instruction *, 4> ElidedArgCopyInstrs;
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  /// Current optimization remark emitter.
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  /// Used to report things like combines and FastISel failures.
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  std::unique_ptr<OptimizationRemarkEmitter> ORE;
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  static char ID;
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  explicit SelectionDAGISel(TargetMachine &tm,
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                            CodeGenOpt::Level OL = CodeGenOpt::Default);
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  ~SelectionDAGISel() override;
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1.62M
  const TargetLowering *getTargetLowering() const { return TLI; }
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  void getAnalysisUsage(AnalysisUsage &AU) const override;
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  bool runOnMachineFunction(MachineFunction &MF) override;
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  virtual void EmitFunctionEntryCode() {}
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  /// PreprocessISelDAG - This hook allows targets to hack on the graph before
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  /// instruction selection starts.
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1.26M
  virtual void PreprocessISelDAG() {}
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  /// PostprocessISelDAG() - This hook allows the target to hack on the graph
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  /// right after selection.
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1.36M
  virtual void PostprocessISelDAG() {}
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  /// Main hook for targets to transform nodes into machine nodes.
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  virtual void Select(SDNode *N) = 0;
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  /// SelectInlineAsmMemoryOperand - Select the specified address as a target
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  /// addressing mode, according to the specified constraint.  If this does
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  /// not match or is not implemented, return true.  The resultant operands
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  /// (which will appear in the machine instruction) should be added to the
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  /// OutOps vector.
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  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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                                            unsigned ConstraintID,
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                                            std::vector<SDValue> &OutOps) {
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    return true;
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  }
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  /// IsProfitableToFold - Returns true if it's profitable to fold the specific
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  /// operand node N of U during instruction selection that starts at Root.
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  virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
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  /// IsLegalToFold - Returns true if the specific operand node N of
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  /// U can be folded during instruction selection that starts at Root.
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  /// FIXME: This is a static member function because the MSP430/X86
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  /// targets, which uses it during isel.  This could become a proper member.
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  static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
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                            CodeGenOpt::Level OptLevel,
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                            bool IgnoreChains = false);
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  static void InvalidateNodeId(SDNode *N);
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  static int getUninvalidatedNodeId(SDNode *N);
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  static void EnforceNodeIdInvariant(SDNode *N);
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  // Opcodes used by the DAG state machine:
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  enum BuiltinOpcodes {
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    OPC_Scope,
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    OPC_RecordNode,
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    OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
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    OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
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    OPC_RecordMemRef,
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    OPC_CaptureGlueInput,
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    OPC_MoveChild,
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    OPC_MoveChild0, OPC_MoveChild1, OPC_MoveChild2, OPC_MoveChild3,
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    OPC_MoveChild4, OPC_MoveChild5, OPC_MoveChild6, OPC_MoveChild7,
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    OPC_MoveParent,
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    OPC_CheckSame,
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    OPC_CheckChild0Same, OPC_CheckChild1Same,
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    OPC_CheckChild2Same, OPC_CheckChild3Same,
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    OPC_CheckPatternPredicate,
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    OPC_CheckPredicate,
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    OPC_CheckOpcode,
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    OPC_SwitchOpcode,
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    OPC_CheckType,
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    OPC_CheckTypeRes,
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    OPC_SwitchType,
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    OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
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    OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
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    OPC_CheckChild6Type, OPC_CheckChild7Type,
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    OPC_CheckInteger,
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    OPC_CheckChild0Integer, OPC_CheckChild1Integer, OPC_CheckChild2Integer,
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    OPC_CheckChild3Integer, OPC_CheckChild4Integer,
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    OPC_CheckCondCode,
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    OPC_CheckValueType,
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    OPC_CheckComplexPat,
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    OPC_CheckAndImm, OPC_CheckOrImm,
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    OPC_CheckFoldableChainNode,
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    OPC_EmitInteger,
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    OPC_EmitRegister,
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    OPC_EmitRegister2,
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    OPC_EmitConvertToTarget,
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    OPC_EmitMergeInputChains,
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    OPC_EmitMergeInputChains1_0,
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    OPC_EmitMergeInputChains1_1,
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    OPC_EmitMergeInputChains1_2,
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    OPC_EmitCopyToReg,
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    OPC_EmitNodeXForm,
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    OPC_EmitNode,
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    // Space-optimized forms that implicitly encode number of result VTs.
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    OPC_EmitNode0, OPC_EmitNode1, OPC_EmitNode2,
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    OPC_MorphNodeTo,
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    // Space-optimized forms that implicitly encode number of result VTs.
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    OPC_MorphNodeTo0, OPC_MorphNodeTo1, OPC_MorphNodeTo2,
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    OPC_CompleteMatch,
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    // Contains offset in table for pattern being selected
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    OPC_Coverage
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  };
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  enum {
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    OPFL_None       = 0,  // Node has no chain or glue input and isn't variadic.
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    OPFL_Chain      = 1,     // Node has a chain input.
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    OPFL_GlueInput  = 2,     // Node has a glue input.
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    OPFL_GlueOutput = 4,     // Node has a glue output.
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    OPFL_MemRefs    = 8,     // Node gets accumulated MemRefs.
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    OPFL_Variadic0  = 1<<4,  // Node is variadic, root has 0 fixed inputs.
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    OPFL_Variadic1  = 2<<4,  // Node is variadic, root has 1 fixed inputs.
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    OPFL_Variadic2  = 3<<4,  // Node is variadic, root has 2 fixed inputs.
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    OPFL_Variadic3  = 4<<4,  // Node is variadic, root has 3 fixed inputs.
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    OPFL_Variadic4  = 5<<4,  // Node is variadic, root has 4 fixed inputs.
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    OPFL_Variadic5  = 6<<4,  // Node is variadic, root has 5 fixed inputs.
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    OPFL_Variadic6  = 7<<4,  // Node is variadic, root has 6 fixed inputs.
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    OPFL_VariadicInfo = OPFL_Variadic6
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  };
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  /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
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  /// number of fixed arity values that should be skipped when copying from the
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  /// root.
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1.02M
  static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
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1.02M
    return ((Flags&OPFL_VariadicInfo) >> 4)-1;
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1.02M
  }
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protected:
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  /// DAGSize - Size of DAG being instruction selected.
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  ///
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  unsigned DAGSize;
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  /// ReplaceUses - replace all uses of the old node F with the use
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  /// of the new node T.
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4.63M
  void ReplaceUses(SDValue F, SDValue T) {
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4.63M
    CurDAG->ReplaceAllUsesOfValueWith(F, T);
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4.63M
    EnforceNodeIdInvariant(T.getNode());
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  }
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  /// ReplaceUses - replace all uses of the old nodes F with the use
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  /// of the new nodes T.
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  void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
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    CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num);
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    for (unsigned i = 0; i < Num; 
++i838
)
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      EnforceNodeIdInvariant(T[i].getNode());
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  }
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  /// ReplaceUses - replace all uses of the old node F with the use
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  /// of the new node T.
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59.3k
  void ReplaceUses(SDNode *F, SDNode *T) {
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59.3k
    CurDAG->ReplaceAllUsesWith(F, T);
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59.3k
    EnforceNodeIdInvariant(T);
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  }
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  /// Replace all uses of \c F with \c T, then remove \c F from the DAG.
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332k
  void ReplaceNode(SDNode *F, SDNode *T) {
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    CurDAG->ReplaceAllUsesWith(F, T);
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    EnforceNodeIdInvariant(T);
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    CurDAG->RemoveDeadNode(F);
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  }
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  /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
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  /// by tblgen.  Others should not call it.
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  void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
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                                     const SDLoc &DL);
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  /// getPatternForIndex - Patterns selected by tablegen during ISEL
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  virtual StringRef getPatternForIndex(unsigned index) {
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    llvm_unreachable("Tblgen should generate the implementation of this!");
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  }
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  /// getIncludePathForIndex - get the td source location of pattern instantiation
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  virtual StringRef getIncludePathForIndex(unsigned index) {
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    llvm_unreachable("Tblgen should generate the implementation of this!");
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  }
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public:
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  // Calls to these predicates are generated by tblgen.
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  bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
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                    int64_t DesiredMaskS) const;
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  bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
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                    int64_t DesiredMaskS) const;
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  /// CheckPatternPredicate - This function is generated by tblgen in the
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  /// target.  It runs the specified pattern predicate and returns true if it
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  /// succeeds or false if it fails.  The number is a private implementation
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  /// detail to the code tblgen produces.
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  virtual bool CheckPatternPredicate(unsigned PredNo) const {
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    llvm_unreachable("Tblgen should generate the implementation of this!");
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  }
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  /// CheckNodePredicate - This function is generated by tblgen in the target.
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  /// It runs node predicate number PredNo and returns true if it succeeds or
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  /// false if it fails.  The number is a private implementation
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  /// detail to the code tblgen produces.
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  virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
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    llvm_unreachable("Tblgen should generate the implementation of this!");
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  }
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  virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
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                                   unsigned PatternNo,
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                        SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
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    llvm_unreachable("Tblgen should generate the implementation of this!");
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  }
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  virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
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    llvm_unreachable("Tblgen should generate this!");
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  }
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  void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
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                        unsigned TableSize);
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  /// Return true if complex patterns for this target can mutate the
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  /// DAG.
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8.50M
  virtual bool ComplexPatternFuncMutatesDAG() const {
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8.50M
    return false;
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8.50M
  }
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  bool isOrEquivalentToAdd(const SDNode *N) const;
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private:
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  // Calls to these functions are generated by tblgen.
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  void Select_INLINEASM(SDNode *N);
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  void Select_READ_REGISTER(SDNode *Op);
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  void Select_WRITE_REGISTER(SDNode *Op);
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  void Select_UNDEF(SDNode *N);
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  void CannotYetSelect(SDNode *N);
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private:
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  void DoInstructionSelection();
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  SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
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                    ArrayRef<SDValue> Ops, unsigned EmitNodeInfo);
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  SDNode *MutateStrictFPToFP(SDNode *Node, unsigned NewOpc);
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  /// Prepares the landing pad to take incoming values or do other EH
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  /// personality specific tasks. Returns true if the block should be
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  /// instruction selected, false if no code should be emitted for it.
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  bool PrepareEHLandingPad();
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  /// Perform instruction selection on all basic blocks in the function.
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  void SelectAllBasicBlocks(const Function &Fn);
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  /// Perform instruction selection on a single basic block, for
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  /// instructions between \p Begin and \p End.  \p HadTailCall will be set
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  /// to true if a call in the block was translated as a tail call.
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  void SelectBasicBlock(BasicBlock::const_iterator Begin,
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                        BasicBlock::const_iterator End,
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                        bool &HadTailCall);
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  void FinishBasicBlock();
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  void CodeGenAndEmitDAG();
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  /// Generate instructions for lowering the incoming arguments of the
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  /// given function.
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  void LowerArguments(const Function &F);
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  void ComputeLiveOutVRegInfo();
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  /// Create the scheduler. If a specific scheduler was specified
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  /// via the SchedulerRegistry, use it, otherwise select the
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  /// one preferred by the target.
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  ///
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  ScheduleDAGSDNodes *CreateScheduler();
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  /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
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  /// state machines that start with a OPC_SwitchOpcode node.
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  std::vector<unsigned> OpcodeOffset;
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  void UpdateChains(SDNode *NodeToMatch, SDValue InputChain,
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                    SmallVectorImpl<SDNode *> &ChainNodesMatched,
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                    bool isMorphNodeTo);
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};
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}
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#endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */