Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/TargetInstrInfo.h
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//===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the target machine instruction set to the code generator.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETINSTRINFO_H
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#define LLVM_TARGET_TARGETINSTRINFO_H
15
16
#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/DenseMapInfo.h"
19
#include "llvm/ADT/None.h"
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#include "llvm/CodeGen/LiveRegUnits.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
22
#include "llvm/CodeGen/MachineCombinerPattern.h"
23
#include "llvm/CodeGen/MachineFunction.h"
24
#include "llvm/CodeGen/MachineInstr.h"
25
#include "llvm/CodeGen/MachineLoopInfo.h"
26
#include "llvm/CodeGen/MachineOperand.h"
27
#include "llvm/CodeGen/MachineOutliner.h"
28
#include "llvm/CodeGen/PseudoSourceValue.h"
29
#include "llvm/CodeGen/VirtRegMap.h"
30
#include "llvm/MC/MCInstrInfo.h"
31
#include "llvm/Support/BranchProbability.h"
32
#include "llvm/Support/ErrorHandling.h"
33
#include <cassert>
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#include <cstddef>
35
#include <cstdint>
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#include <utility>
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#include <vector>
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39
namespace llvm {
40
41
class DFAPacketizer;
42
class InstrItineraryData;
43
class LiveIntervals;
44
class LiveVariables;
45
class MachineMemOperand;
46
class MachineRegisterInfo;
47
class MCAsmInfo;
48
class MCInst;
49
struct MCSchedModel;
50
class Module;
51
class ScheduleDAG;
52
class ScheduleHazardRecognizer;
53
class SDNode;
54
class SelectionDAG;
55
class RegScavenger;
56
class TargetRegisterClass;
57
class TargetRegisterInfo;
58
class TargetSchedModel;
59
class TargetSubtargetInfo;
60
61
template <class T> class SmallVectorImpl;
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63
//---------------------------------------------------------------------------
64
///
65
/// TargetInstrInfo - Interface to description of machine instruction set
66
///
67
class TargetInstrInfo : public MCInstrInfo {
68
public:
69
  TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
70
                  unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
71
      : CallFrameSetupOpcode(CFSetupOpcode),
72
        CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
73
53.2k
        ReturnOpcode(ReturnOpcode) {}
74
  TargetInstrInfo(const TargetInstrInfo &) = delete;
75
  TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
76
  virtual ~TargetInstrInfo();
77
78
31.5M
  static bool isGenericOpcode(unsigned Opc) {
79
31.5M
    return Opc <= TargetOpcode::GENERIC_OP_END;
80
31.5M
  }
81
82
  /// Given a machine instruction descriptor, returns the register
83
  /// class constraint for OpNum, or NULL.
84
  virtual
85
  const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
86
                                         const TargetRegisterInfo *TRI,
87
                                         const MachineFunction &MF) const;
88
89
  /// Return true if the instruction is trivially rematerializable, meaning it
90
  /// has no side effects and requires no operands that aren't always available.
91
  /// This means the only allowed uses are constants and unallocatable physical
92
  /// registers so that the instructions result is independent of the place
93
  /// in the function.
94
  bool isTriviallyReMaterializable(const MachineInstr &MI,
95
6.61M
                                   AliasAnalysis *AA = nullptr) const {
96
6.61M
    return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
97
6.61M
           
(6.61M
MI.getDesc().isRematerializable()6.61M
&&
98
6.61M
            
(4.07M
isReallyTriviallyReMaterializable(MI, AA)4.07M
||
99
4.07M
             
isReallyTriviallyReMaterializableGeneric(MI, AA)3.87M
));
100
6.61M
  }
101
102
protected:
103
  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
104
  /// set, this hook lets the target specify whether the instruction is actually
105
  /// trivially rematerializable, taking into consideration its operands. This
106
  /// predicate must return false if the instruction has any side effects other
107
  /// than producing a value, or if it requres any address registers that are
108
  /// not always available.
109
  /// Requirements must be check as stated in isTriviallyReMaterializable() .
110
  virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
111
3.66M
                                                 AliasAnalysis *AA) const {
112
3.66M
    return false;
113
3.66M
  }
114
115
  /// This method commutes the operands of the given machine instruction MI.
116
  /// The operands to be commuted are specified by their indices OpIdx1 and
117
  /// OpIdx2.
118
  ///
119
  /// If a target has any instructions that are commutable but require
120
  /// converting to different instructions or making non-trivial changes
121
  /// to commute them, this method can be overloaded to do that.
122
  /// The default implementation simply swaps the commutable operands.
123
  ///
124
  /// If NewMI is false, MI is modified in place and returned; otherwise, a
125
  /// new machine instruction is created and returned.
126
  ///
127
  /// Do not call this method for a non-commutable instruction.
128
  /// Even though the instruction is commutable, the method may still
129
  /// fail to commute the operands, null pointer is returned in such cases.
130
  virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
131
                                               unsigned OpIdx1,
132
                                               unsigned OpIdx2) const;
133
134
  /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
135
  /// operand indices to (ResultIdx1, ResultIdx2).
136
  /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
137
  /// predefined to some indices or be undefined (designated by the special
138
  /// value 'CommuteAnyOperandIndex').
139
  /// The predefined result indices cannot be re-defined.
140
  /// The function returns true iff after the result pair redefinition
141
  /// the fixed result pair is equal to or equivalent to the source pair of
142
  /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
143
  /// the pairs (x,y) and (y,x) are equivalent.
144
  static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
145
                                   unsigned CommutableOpIdx1,
146
                                   unsigned CommutableOpIdx2);
147
148
private:
149
  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
150
  /// set and the target hook isReallyTriviallyReMaterializable returns false,
151
  /// this function does target-independent tests to determine if the
152
  /// instruction is really trivially rematerializable.
153
  bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
154
                                                AliasAnalysis *AA) const;
155
156
public:
157
  /// These methods return the opcode of the frame setup/destroy instructions
158
  /// if they exist (-1 otherwise).  Some targets use pseudo instructions in
159
  /// order to abstract away the difference between operating with a frame
160
  /// pointer and operating without, through the use of these two instructions.
161
  ///
162
44.1M
  unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
163
53.0M
  unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
164
165
  /// Returns true if the argument is a frame pseudo instruction.
166
38.2M
  bool isFrameInstr(const MachineInstr &I) const {
167
38.2M
    return I.getOpcode() == getCallFrameSetupOpcode() ||
168
38.2M
           
I.getOpcode() == getCallFrameDestroyOpcode()36.7M
;
169
38.2M
  }
170
171
  /// Returns true if the argument is a frame setup pseudo instruction.
172
505k
  bool isFrameSetup(const MachineInstr &I) const {
173
505k
    return I.getOpcode() == getCallFrameSetupOpcode();
174
505k
  }
175
176
  /// Returns size of the frame associated with the given frame instruction.
177
  /// For frame setup instruction this is frame that is set up space set up
178
  /// after the instruction. For frame destroy instruction this is the frame
179
  /// freed by the caller.
180
  /// Note, in some cases a call frame (or a part of it) may be prepared prior
181
  /// to the frame setup instruction. It occurs in the calls that involve
182
  /// inalloca arguments. This function reports only the size of the frame part
183
  /// that is set up between the frame setup and destroy pseudo instructions.
184
8.65M
  int64_t getFrameSize(const MachineInstr &I) const {
185
8.65M
    assert(isFrameInstr(I) && "Not a frame instruction");
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8.65M
    assert(I.getOperand(0).getImm() >= 0);
187
8.65M
    return I.getOperand(0).getImm();
188
8.65M
  }
189
190
  /// Returns the total frame size, which is made up of the space set up inside
191
  /// the pair of frame start-stop instructions and the space that is set up
192
  /// prior to the pair.
193
332k
  int64_t getFrameTotalSize(const MachineInstr &I) const {
194
332k
    if (isFrameSetup(I)) {
195
166k
      assert(I.getOperand(1).getImm() >= 0 &&
196
166k
             "Frame size must not be negative");
197
166k
      return getFrameSize(I) + I.getOperand(1).getImm();
198
166k
    }
199
166k
    return getFrameSize(I);
200
166k
  }
201
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1.89k
  unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
203
30
  unsigned getReturnOpcode() const { return ReturnOpcode; }
204
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  /// Returns the actual stack pointer adjustment made by an instruction
206
  /// as part of a call sequence. By default, only call frame setup/destroy
207
  /// instructions adjust the stack, but targets may want to override this
208
  /// to enable more fine-grained adjustment, or adjust by a different value.
209
  virtual int getSPAdjust(const MachineInstr &MI) const;
210
211
  /// Return true if the instruction is a "coalescable" extension instruction.
212
  /// That is, it's like a copy where it's legal for the source to overlap the
213
  /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
214
  /// expected the pre-extension value is available as a subreg of the result
215
  /// register. This also returns the sub-register index in SubIdx.
216
  virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
217
2.04M
                                     unsigned &DstReg, unsigned &SubIdx) const {
218
2.04M
    return false;
219
2.04M
  }
220
221
  /// If the specified machine instruction is a direct
222
  /// load from a stack slot, return the virtual or physical register number of
223
  /// the destination along with the FrameIndex of the loaded stack slot.  If
224
  /// not, return 0.  This predicate must return 0 if the instruction has
225
  /// any side effects other than loading from the stack slot.
226
  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
227
1.84k
                                       int &FrameIndex) const {
228
1.84k
    return 0;
229
1.84k
  }
230
231
  /// Optional extension of isLoadFromStackSlot that returns the number of
232
  /// bytes loaded from the stack. This must be implemented if a backend
233
  /// supports partial stack slot spills/loads to further disambiguate
234
  /// what the load does.
235
  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
236
                                       int &FrameIndex,
237
3.42M
                                       unsigned &MemBytes) const {
238
3.42M
    MemBytes = 0;
239
3.42M
    return isLoadFromStackSlot(MI, FrameIndex);
240
3.42M
  }
241
242
  /// Check for post-frame ptr elimination stack locations as well.
243
  /// This uses a heuristic so it isn't reliable for correctness.
244
  virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
245
1.00M
                                             int &FrameIndex) const {
246
1.00M
    return 0;
247
1.00M
  }
248
249
  /// If the specified machine instruction has a load from a stack slot,
250
  /// return true along with the FrameIndices of the loaded stack slot and the
251
  /// machine mem operands containing the reference.
252
  /// If not, return false.  Unlike isLoadFromStackSlot, this returns true for
253
  /// any instructions that loads from the stack.  This is just a hint, as some
254
  /// cases may be missed.
255
  virtual bool hasLoadFromStackSlot(
256
      const MachineInstr &MI,
257
      SmallVectorImpl<const MachineMemOperand *> &Accesses) const;
258
259
  /// If the specified machine instruction is a direct
260
  /// store to a stack slot, return the virtual or physical register number of
261
  /// the source reg along with the FrameIndex of the loaded stack slot.  If
262
  /// not, return 0.  This predicate must return 0 if the instruction has
263
  /// any side effects other than storing to the stack slot.
264
  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
265
1.07k
                                      int &FrameIndex) const {
266
1.07k
    return 0;
267
1.07k
  }
268
269
  /// Optional extension of isStoreToStackSlot that returns the number of
270
  /// bytes stored to the stack. This must be implemented if a backend
271
  /// supports partial stack slot spills/loads to further disambiguate
272
  /// what the store does.
273
  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
274
                                      int &FrameIndex,
275
143k
                                      unsigned &MemBytes) const {
276
143k
    MemBytes = 0;
277
143k
    return isStoreToStackSlot(MI, FrameIndex);
278
143k
  }
279
280
  /// Check for post-frame ptr elimination stack locations as well.
281
  /// This uses a heuristic, so it isn't reliable for correctness.
282
  virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
283
981k
                                            int &FrameIndex) const {
284
981k
    return 0;
285
981k
  }
286
287
  /// If the specified machine instruction has a store to a stack slot,
288
  /// return true along with the FrameIndices of the loaded stack slot and the
289
  /// machine mem operands containing the reference.
290
  /// If not, return false.  Unlike isStoreToStackSlot,
291
  /// this returns true for any instructions that stores to the
292
  /// stack.  This is just a hint, as some cases may be missed.
293
  virtual bool hasStoreToStackSlot(
294
      const MachineInstr &MI,
295
      SmallVectorImpl<const MachineMemOperand *> &Accesses) const;
296
297
  /// Return true if the specified machine instruction
298
  /// is a copy of one stack slot to another and has no other effect.
299
  /// Provide the identity of the two frame indices.
300
  virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
301
3.93M
                               int &SrcFrameIndex) const {
302
3.93M
    return false;
303
3.93M
  }
304
305
  /// Compute the size in bytes and offset within a stack slot of a spilled
306
  /// register or subregister.
307
  ///
308
  /// \param [out] Size in bytes of the spilled value.
309
  /// \param [out] Offset in bytes within the stack slot.
310
  /// \returns true if both Size and Offset are successfully computed.
311
  ///
312
  /// Not all subregisters have computable spill slots. For example,
313
  /// subregisters registers may not be byte-sized, and a pair of discontiguous
314
  /// subregisters has no single offset.
315
  ///
316
  /// Targets with nontrivial bigendian implementations may need to override
317
  /// this, particularly to support spilled vector registers.
318
  virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
319
                                 unsigned &Size, unsigned &Offset,
320
                                 const MachineFunction &MF) const;
321
322
  /// Returns the size in bytes of the specified MachineInstr, or ~0U
323
  /// when this function is not implemented by a target.
324
0
  virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
325
0
    return ~0U;
326
0
  }
327
328
  /// Return true if the instruction is as cheap as a move instruction.
329
  ///
330
  /// Targets for different archs need to override this, and different
331
  /// micro-architectures can also be finely tuned inside.
332
709k
  virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
333
709k
    return MI.isAsCheapAsAMove();
334
709k
  }
335
336
  /// Return true if the instruction should be sunk by MachineSink.
337
  ///
338
  /// MachineSink determines on its own whether the instruction is safe to sink;
339
  /// this gives the target a hook to override the default behavior with regards
340
  /// to which instructions should be sunk.
341
26.8M
  virtual bool shouldSink(const MachineInstr &MI) const { return true; }
342
343
  /// Re-issue the specified 'original' instruction at the
344
  /// specific location targeting a new destination register.
345
  /// The register in Orig->getOperand(0).getReg() will be substituted by
346
  /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
347
  /// SubIdx.
348
  virtual void reMaterialize(MachineBasicBlock &MBB,
349
                             MachineBasicBlock::iterator MI, unsigned DestReg,
350
                             unsigned SubIdx, const MachineInstr &Orig,
351
                             const TargetRegisterInfo &TRI) const;
352
353
  /// Clones instruction or the whole instruction bundle \p Orig and
354
  /// insert into \p MBB before \p InsertBefore. The target may update operands
355
  /// that are required to be unique.
356
  ///
357
  /// \p Orig must not return true for MachineInstr::isNotDuplicable().
358
  virtual MachineInstr &duplicate(MachineBasicBlock &MBB,
359
                                  MachineBasicBlock::iterator InsertBefore,
360
                                  const MachineInstr &Orig) const;
361
362
  /// This method must be implemented by targets that
363
  /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
364
  /// may be able to convert a two-address instruction into one or more true
365
  /// three-address instructions on demand.  This allows the X86 target (for
366
  /// example) to convert ADD and SHL instructions into LEA instructions if they
367
  /// would require register copies due to two-addressness.
368
  ///
369
  /// This method returns a null pointer if the transformation cannot be
370
  /// performed, otherwise it returns the last new instruction.
371
  ///
372
  virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
373
                                              MachineInstr &MI,
374
0
                                              LiveVariables *LV) const {
375
0
    return nullptr;
376
0
  }
377
378
  // This constant can be used as an input value of operand index passed to
379
  // the method findCommutedOpIndices() to tell the method that the
380
  // corresponding operand index is not pre-defined and that the method
381
  // can pick any commutable operand.
382
  static const unsigned CommuteAnyOperandIndex = ~0U;
383
384
  /// This method commutes the operands of the given machine instruction MI.
385
  ///
386
  /// The operands to be commuted are specified by their indices OpIdx1 and
387
  /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
388
  /// 'CommuteAnyOperandIndex', which means that the method is free to choose
389
  /// any arbitrarily chosen commutable operand. If both arguments are set to
390
  /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
391
  /// operands; then commutes them if such operands could be found.
392
  ///
393
  /// If NewMI is false, MI is modified in place and returned; otherwise, a
394
  /// new machine instruction is created and returned.
395
  ///
396
  /// Do not call this method for a non-commutable instruction or
397
  /// for non-commuable operands.
398
  /// Even though the instruction is commutable, the method may still
399
  /// fail to commute the operands, null pointer is returned in such cases.
400
  MachineInstr *
401
  commuteInstruction(MachineInstr &MI, bool NewMI = false,
402
                     unsigned OpIdx1 = CommuteAnyOperandIndex,
403
                     unsigned OpIdx2 = CommuteAnyOperandIndex) const;
404
405
  /// Returns true iff the routine could find two commutable operands in the
406
  /// given machine instruction.
407
  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
408
  /// If any of the INPUT values is set to the special value
409
  /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
410
  /// operand, then returns its index in the corresponding argument.
411
  /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
412
  /// looks for 2 commutable operands.
413
  /// If INPUT values refer to some operands of MI, then the method simply
414
  /// returns true if the corresponding operands are commutable and returns
415
  /// false otherwise.
416
  ///
417
  /// For example, calling this method this way:
418
  ///     unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
419
  ///     findCommutedOpIndices(MI, Op1, Op2);
420
  /// can be interpreted as a query asking to find an operand that would be
421
  /// commutable with the operand#1.
422
  virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
423
                                     unsigned &SrcOpIdx2) const;
424
425
  /// A pair composed of a register and a sub-register index.
426
  /// Used to give some type checking when modeling Reg:SubReg.
427
  struct RegSubRegPair {
428
    unsigned Reg;
429
    unsigned SubReg;
430
431
    RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
432
53.4M
        : Reg(Reg), SubReg(SubReg) {}
433
434
0
    bool operator==(const RegSubRegPair& P) const {
435
0
      return Reg == P.Reg && SubReg == P.SubReg;
436
0
    }
437
0
    bool operator!=(const RegSubRegPair& P) const {
438
0
      return !(*this == P);
439
0
    }
440
  };
441
442
  /// A pair composed of a pair of a register and a sub-register index,
443
  /// and another sub-register index.
444
  /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
445
  struct RegSubRegPairAndIdx : RegSubRegPair {
446
    unsigned SubIdx;
447
448
    RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
449
                        unsigned SubIdx = 0)
450
993k
        : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
451
  };
452
453
  /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
454
  /// and \p DefIdx.
455
  /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
456
  /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef
457
  /// flag are not added to this list.
458
  /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
459
  /// two elements:
460
  /// - %1:sub1, sub0
461
  /// - %2<:0>, sub1
462
  ///
463
  /// \returns true if it is possible to build such an input sequence
464
  /// with the pair \p MI, \p DefIdx. False otherwise.
465
  ///
466
  /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
467
  ///
468
  /// \note The generic implementation does not provide any support for
469
  /// MI.isRegSequenceLike(). In other words, one has to override
470
  /// getRegSequenceLikeInputs for target specific instructions.
471
  bool
472
  getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
473
                       SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
474
475
  /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
476
  /// and \p DefIdx.
477
  /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
478
  /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
479
  /// - %1:sub1, sub0
480
  ///
481
  /// \returns true if it is possible to build such an input sequence
482
  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
483
  /// False otherwise.
484
  ///
485
  /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
486
  ///
487
  /// \note The generic implementation does not provide any support for
488
  /// MI.isExtractSubregLike(). In other words, one has to override
489
  /// getExtractSubregLikeInputs for target specific instructions.
490
  bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
491
                              RegSubRegPairAndIdx &InputReg) const;
492
493
  /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
494
  /// and \p DefIdx.
495
  /// \p [out] BaseReg and \p [out] InsertedReg contain
496
  /// the equivalent inputs of INSERT_SUBREG.
497
  /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
498
  /// - BaseReg: %0:sub0
499
  /// - InsertedReg: %1:sub1, sub3
500
  ///
501
  /// \returns true if it is possible to build such an input sequence
502
  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
503
  /// False otherwise.
504
  ///
505
  /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
506
  ///
507
  /// \note The generic implementation does not provide any support for
508
  /// MI.isInsertSubregLike(). In other words, one has to override
509
  /// getInsertSubregLikeInputs for target specific instructions.
510
  bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
511
                             RegSubRegPair &BaseReg,
512
                             RegSubRegPairAndIdx &InsertedReg) const;
513
514
  /// Return true if two machine instructions would produce identical values.
515
  /// By default, this is only true when the two instructions
516
  /// are deemed identical except for defs. If this function is called when the
517
  /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
518
  /// aggressive checks.
519
  virtual bool produceSameValue(const MachineInstr &MI0,
520
                                const MachineInstr &MI1,
521
                                const MachineRegisterInfo *MRI = nullptr) const;
522
523
  /// \returns true if a branch from an instruction with opcode \p BranchOpc
524
  ///  bytes is capable of jumping to a position \p BrOffset bytes away.
525
  virtual bool isBranchOffsetInRange(unsigned BranchOpc,
526
0
                                     int64_t BrOffset) const {
527
0
    llvm_unreachable("target did not implement");
528
0
  }
529
530
  /// \returns The block that branch instruction \p MI jumps to.
531
0
  virtual MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const {
532
0
    llvm_unreachable("target did not implement");
533
0
  }
534
535
  /// Insert an unconditional indirect branch at the end of \p MBB to \p
536
  /// NewDestBB.  \p BrOffset indicates the offset of \p NewDestBB relative to
537
  /// the offset of the position to insert the new branch.
538
  ///
539
  /// \returns The number of bytes added to the block.
540
  virtual unsigned insertIndirectBranch(MachineBasicBlock &MBB,
541
                                        MachineBasicBlock &NewDestBB,
542
                                        const DebugLoc &DL,
543
                                        int64_t BrOffset = 0,
544
0
                                        RegScavenger *RS = nullptr) const {
545
0
    llvm_unreachable("target did not implement");
546
0
  }
547
548
  /// Analyze the branching code at the end of MBB, returning
549
  /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
550
  /// implemented for a target).  Upon success, this returns false and returns
551
  /// with the following information in various cases:
552
  ///
553
  /// 1. If this block ends with no branches (it just falls through to its succ)
554
  ///    just return false, leaving TBB/FBB null.
555
  /// 2. If this block ends with only an unconditional branch, it sets TBB to be
556
  ///    the destination block.
557
  /// 3. If this block ends with a conditional branch and it falls through to a
558
  ///    successor block, it sets TBB to be the branch destination block and a
559
  ///    list of operands that evaluate the condition. These operands can be
560
  ///    passed to other TargetInstrInfo methods to create new branches.
561
  /// 4. If this block ends with a conditional branch followed by an
562
  ///    unconditional branch, it returns the 'true' destination in TBB, the
563
  ///    'false' destination in FBB, and a list of operands that evaluate the
564
  ///    condition.  These operands can be passed to other TargetInstrInfo
565
  ///    methods to create new branches.
566
  ///
567
  /// Note that removeBranch and insertBranch must be implemented to support
568
  /// cases where this method returns success.
569
  ///
570
  /// If AllowModify is true, then this routine is allowed to modify the basic
571
  /// block (e.g. delete instructions after the unconditional branch).
572
  ///
573
  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
574
  /// before calling this function.
575
  virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
576
                             MachineBasicBlock *&FBB,
577
                             SmallVectorImpl<MachineOperand> &Cond,
578
0
                             bool AllowModify = false) const {
579
0
    return true;
580
0
  }
581
582
  /// Represents a predicate at the MachineFunction level.  The control flow a
583
  /// MachineBranchPredicate represents is:
584
  ///
585
  ///  Reg = LHS `Predicate` RHS         == ConditionDef
586
  ///  if Reg then goto TrueDest else goto FalseDest
587
  ///
588
  struct MachineBranchPredicate {
589
    enum ComparePredicate {
590
      PRED_EQ,     // True if two values are equal
591
      PRED_NE,     // True if two values are not equal
592
      PRED_INVALID // Sentinel value
593
    };
594
595
    ComparePredicate Predicate = PRED_INVALID;
596
    MachineOperand LHS = MachineOperand::CreateImm(0);
597
    MachineOperand RHS = MachineOperand::CreateImm(0);
598
    MachineBasicBlock *TrueDest = nullptr;
599
    MachineBasicBlock *FalseDest = nullptr;
600
    MachineInstr *ConditionDef = nullptr;
601
602
    /// SingleUseCondition is true if ConditionDef is dead except for the
603
    /// branch(es) at the end of the basic block.
604
    ///
605
    bool SingleUseCondition = false;
606
607
60
    explicit MachineBranchPredicate() = default;
608
  };
609
610
  /// Analyze the branching code at the end of MBB and parse it into the
611
  /// MachineBranchPredicate structure if possible.  Returns false on success
612
  /// and true on failure.
613
  ///
614
  /// If AllowModify is true, then this routine is allowed to modify the basic
615
  /// block (e.g. delete instructions after the unconditional branch).
616
  ///
617
  virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB,
618
                                      MachineBranchPredicate &MBP,
619
0
                                      bool AllowModify = false) const {
620
0
    return true;
621
0
  }
622
623
  /// Remove the branching code at the end of the specific MBB.
624
  /// This is only invoked in cases where AnalyzeBranch returns success. It
625
  /// returns the number of instructions that were removed.
626
  /// If \p BytesRemoved is non-null, report the change in code size from the
627
  /// removed instructions.
628
  virtual unsigned removeBranch(MachineBasicBlock &MBB,
629
0
                                int *BytesRemoved = nullptr) const {
630
0
    llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
631
0
  }
632
633
  /// Insert branch code into the end of the specified MachineBasicBlock. The
634
  /// operands to this method are the same as those returned by AnalyzeBranch.
635
  /// This is only invoked in cases where AnalyzeBranch returns success. It
636
  /// returns the number of instructions inserted. If \p BytesAdded is non-null,
637
  /// report the change in code size from the added instructions.
638
  ///
639
  /// It is also invoked by tail merging to add unconditional branches in
640
  /// cases where AnalyzeBranch doesn't apply because there was no original
641
  /// branch to analyze.  At least this much must be implemented, else tail
642
  /// merging needs to be disabled.
643
  ///
644
  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
645
  /// before calling this function.
646
  virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
647
                                MachineBasicBlock *FBB,
648
                                ArrayRef<MachineOperand> Cond,
649
                                const DebugLoc &DL,
650
0
                                int *BytesAdded = nullptr) const {
651
0
    llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
652
0
  }
653
654
  unsigned insertUnconditionalBranch(MachineBasicBlock &MBB,
655
                                     MachineBasicBlock *DestBB,
656
                                     const DebugLoc &DL,
657
3
                                     int *BytesAdded = nullptr) const {
658
3
    return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL,
659
3
                        BytesAdded);
660
3
  }
661
662
  /// Analyze the loop code, return true if it cannot be understoo. Upon
663
  /// success, this function returns false and returns information about the
664
  /// induction variable and compare instruction used at the end.
665
  virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
666
0
                           MachineInstr *&CmpInst) const {
667
0
    return true;
668
0
  }
669
670
  /// Generate code to reduce the loop iteration by one and check if the loop
671
  /// is finished.  Return the value/register of the new loop count.  We need
672
  /// this function when peeling off one or more iterations of a loop. This
673
  /// function assumes the nth iteration is peeled first.
674
  virtual unsigned reduceLoopCount(MachineBasicBlock &MBB,
675
                                   MachineBasicBlock &PreHeader,
676
                                   MachineInstr *IndVar, MachineInstr &Cmp,
677
                                   SmallVectorImpl<MachineOperand> &Cond,
678
                                   SmallVectorImpl<MachineInstr *> &PrevInsts,
679
0
                                   unsigned Iter, unsigned MaxIter) const {
680
0
    llvm_unreachable("Target didn't implement ReduceLoopCount");
681
0
  }
682
683
  /// Delete the instruction OldInst and everything after it, replacing it with
684
  /// an unconditional branch to NewDest. This is used by the tail merging pass.
685
  virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
686
                                       MachineBasicBlock *NewDest) const;
687
688
  /// Return true if it's legal to split the given basic
689
  /// block at the specified instruction (i.e. instruction would be the start
690
  /// of a new basic block).
691
  virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
692
64.4k
                                   MachineBasicBlock::iterator MBBI) const {
693
64.4k
    return true;
694
64.4k
  }
695
696
  /// Return true if it's profitable to predicate
697
  /// instructions with accumulated instruction latency of "NumCycles"
698
  /// of the specified basic block, where the probability of the instructions
699
  /// being executed is given by Probability, and Confidence is a measure
700
  /// of our confidence that it will be properly predicted.
701
  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
702
                                   unsigned ExtraPredCycles,
703
0
                                   BranchProbability Probability) const {
704
0
    return false;
705
0
  }
706
707
  /// Second variant of isProfitableToIfCvt. This one
708
  /// checks for the case where two basic blocks from true and false path
709
  /// of a if-then-else (diamond) are predicated on mutally exclusive
710
  /// predicates, where the probability of the true path being taken is given
711
  /// by Probability, and Confidence is a measure of our confidence that it
712
  /// will be properly predicted.
713
  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,
714
                                   unsigned ExtraTCycles,
715
                                   MachineBasicBlock &FMBB, unsigned NumFCycles,
716
                                   unsigned ExtraFCycles,
717
0
                                   BranchProbability Probability) const {
718
0
    return false;
719
0
  }
720
721
  /// Return true if it's profitable for if-converter to duplicate instructions
722
  /// of specified accumulated instruction latencies in the specified MBB to
723
  /// enable if-conversion.
724
  /// The probability of the instructions being executed is given by
725
  /// Probability, and Confidence is a measure of our confidence that it
726
  /// will be properly predicted.
727
  virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
728
                                         unsigned NumCycles,
729
0
                                         BranchProbability Probability) const {
730
0
    return false;
731
0
  }
732
733
  /// Return true if it's profitable to unpredicate
734
  /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
735
  /// exclusive predicates.
736
  /// e.g.
737
  ///   subeq  r0, r1, #1
738
  ///   addne  r0, r1, #1
739
  /// =>
740
  ///   sub    r0, r1, #1
741
  ///   addne  r0, r1, #1
742
  ///
743
  /// This may be profitable is conditional instructions are always executed.
744
  virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
745
15
                                         MachineBasicBlock &FMBB) const {
746
15
    return false;
747
15
  }
748
749
  /// Return true if it is possible to insert a select
750
  /// instruction that chooses between TrueReg and FalseReg based on the
751
  /// condition code in Cond.
752
  ///
753
  /// When successful, also return the latency in cycles from TrueReg,
754
  /// FalseReg, and Cond to the destination register. In most cases, a select
755
  /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
756
  ///
757
  /// Some x86 implementations have 2-cycle cmov instructions.
758
  ///
759
  /// @param MBB         Block where select instruction would be inserted.
760
  /// @param Cond        Condition returned by AnalyzeBranch.
761
  /// @param TrueReg     Virtual register to select when Cond is true.
762
  /// @param FalseReg    Virtual register to select when Cond is false.
763
  /// @param CondCycles  Latency from Cond+Branch to select output.
764
  /// @param TrueCycles  Latency from TrueReg to select output.
765
  /// @param FalseCycles Latency from FalseReg to select output.
766
  virtual bool canInsertSelect(const MachineBasicBlock &MBB,
767
                               ArrayRef<MachineOperand> Cond, unsigned TrueReg,
768
                               unsigned FalseReg, int &CondCycles,
769
0
                               int &TrueCycles, int &FalseCycles) const {
770
0
    return false;
771
0
  }
772
773
  /// Insert a select instruction into MBB before I that will copy TrueReg to
774
  /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
775
  ///
776
  /// This function can only be called after canInsertSelect() returned true.
777
  /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
778
  /// that the same flags or registers required by Cond are available at the
779
  /// insertion point.
780
  ///
781
  /// @param MBB      Block where select instruction should be inserted.
782
  /// @param I        Insertion point.
783
  /// @param DL       Source location for debugging.
784
  /// @param DstReg   Virtual register to be defined by select instruction.
785
  /// @param Cond     Condition as computed by AnalyzeBranch.
786
  /// @param TrueReg  Virtual register to copy when Cond is true.
787
  /// @param FalseReg Virtual register to copy when Cons is false.
788
  virtual void insertSelect(MachineBasicBlock &MBB,
789
                            MachineBasicBlock::iterator I, const DebugLoc &DL,
790
                            unsigned DstReg, ArrayRef<MachineOperand> Cond,
791
0
                            unsigned TrueReg, unsigned FalseReg) const {
792
0
    llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
793
0
  }
794
795
  /// Analyze the given select instruction, returning true if
796
  /// it cannot be understood. It is assumed that MI->isSelect() is true.
797
  ///
798
  /// When successful, return the controlling condition and the operands that
799
  /// determine the true and false result values.
800
  ///
801
  ///   Result = SELECT Cond, TrueOp, FalseOp
802
  ///
803
  /// Some targets can optimize select instructions, for example by predicating
804
  /// the instruction defining one of the operands. Such targets should set
805
  /// Optimizable.
806
  ///
807
  /// @param         MI Select instruction to analyze.
808
  /// @param Cond    Condition controlling the select.
809
  /// @param TrueOp  Operand number of the value selected when Cond is true.
810
  /// @param FalseOp Operand number of the value selected when Cond is false.
811
  /// @param Optimizable Returned as true if MI is optimizable.
812
  /// @returns False on success.
813
  virtual bool analyzeSelect(const MachineInstr &MI,
814
                             SmallVectorImpl<MachineOperand> &Cond,
815
                             unsigned &TrueOp, unsigned &FalseOp,
816
519
                             bool &Optimizable) const {
817
519
    assert(MI.getDesc().isSelect() && "MI must be a select instruction");
818
519
    return true;
819
519
  }
820
821
  /// Given a select instruction that was understood by
822
  /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
823
  /// merging it with one of its operands. Returns NULL on failure.
824
  ///
825
  /// When successful, returns the new select instruction. The client is
826
  /// responsible for deleting MI.
827
  ///
828
  /// If both sides of the select can be optimized, PreferFalse is used to pick
829
  /// a side.
830
  ///
831
  /// @param MI          Optimizable select instruction.
832
  /// @param NewMIs     Set that record all MIs in the basic block up to \p
833
  /// MI. Has to be updated with any newly created MI or deleted ones.
834
  /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
835
  /// @returns Optimized instruction or NULL.
836
  virtual MachineInstr *optimizeSelect(MachineInstr &MI,
837
                                       SmallPtrSetImpl<MachineInstr *> &NewMIs,
838
0
                                       bool PreferFalse = false) const {
839
0
    // This function must be implemented if Optimizable is ever set.
840
0
    llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
841
0
  }
842
843
  /// Emit instructions to copy a pair of physical registers.
844
  ///
845
  /// This function should support copies within any legal register class as
846
  /// well as any cross-class copies created during instruction selection.
847
  ///
848
  /// The source and destination registers may overlap, which may require a
849
  /// careful implementation when multiple copy instructions are required for
850
  /// large registers. See for example the ARM target.
851
  virtual void copyPhysReg(MachineBasicBlock &MBB,
852
                           MachineBasicBlock::iterator MI, const DebugLoc &DL,
853
                           unsigned DestReg, unsigned SrcReg,
854
0
                           bool KillSrc) const {
855
0
    llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
856
0
  }
857
858
protected:
859
  /// Target-dependent implemenation for IsCopyInstr.
860
  /// If the specific machine instruction is a instruction that moves/copies
861
  /// value from one register to another register return true along with
862
  /// @Source machine operand and @Destination machine operand.
863
  virtual bool isCopyInstrImpl(const MachineInstr &MI,
864
                               const MachineOperand *&Source,
865
155
                               const MachineOperand *&Destination) const {
866
155
    return false;
867
155
  }
868
869
public:
870
  /// If the specific machine instruction is a instruction that moves/copies
871
  /// value from one register to another register return true along with
872
  /// @Source machine operand and @Destination machine operand.
873
  /// For COPY-instruction the method naturally returns true, for all other
874
  /// instructions the method calls target-dependent implementation.
875
  bool isCopyInstr(const MachineInstr &MI, const MachineOperand *&Source,
876
2.94k
                   const MachineOperand *&Destination) const {
877
2.94k
    if (MI.isCopy()) {
878
0
      Destination = &MI.getOperand(0);
879
0
      Source = &MI.getOperand(1);
880
0
      return true;
881
0
    }
882
2.94k
    return isCopyInstrImpl(MI, Source, Destination);
883
2.94k
  }
884
885
  /// Store the specified register of the given register class to the specified
886
  /// stack frame index. The store instruction is to be added to the given
887
  /// machine basic block before the specified machine instruction. If isKill
888
  /// is true, the register operand is the last use and must be marked kill.
889
  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
890
                                   MachineBasicBlock::iterator MI,
891
                                   unsigned SrcReg, bool isKill, int FrameIndex,
892
                                   const TargetRegisterClass *RC,
893
0
                                   const TargetRegisterInfo *TRI) const {
894
0
    llvm_unreachable("Target didn't implement "
895
0
                     "TargetInstrInfo::storeRegToStackSlot!");
896
0
  }
897
898
  /// Load the specified register of the given register class from the specified
899
  /// stack frame index. The load instruction is to be added to the given
900
  /// machine basic block before the specified machine instruction.
901
  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
902
                                    MachineBasicBlock::iterator MI,
903
                                    unsigned DestReg, int FrameIndex,
904
                                    const TargetRegisterClass *RC,
905
0
                                    const TargetRegisterInfo *TRI) const {
906
0
    llvm_unreachable("Target didn't implement "
907
0
                     "TargetInstrInfo::loadRegFromStackSlot!");
908
0
  }
909
910
  /// This function is called for all pseudo instructions
911
  /// that remain after register allocation. Many pseudo instructions are
912
  /// created to help register allocation. This is the place to convert them
913
  /// into real instructions. The target can edit MI in place, or it can insert
914
  /// new instructions and erase MI. The function should return true if
915
  /// anything was changed.
916
354k
  virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
917
918
  /// Check whether the target can fold a load that feeds a subreg operand
919
  /// (or a subreg operand that feeds a store).
920
  /// For example, X86 may want to return true if it can fold
921
  /// movl (%esp), %eax
922
  /// subb, %al, ...
923
  /// Into:
924
  /// subb (%esp), ...
925
  ///
926
  /// Ideally, we'd like the target implementation of foldMemoryOperand() to
927
  /// reject subregs - but since this behavior used to be enforced in the
928
  /// target-independent code, moving this responsibility to the targets
929
  /// has the potential of causing nasty silent breakage in out-of-tree targets.
930
21.9k
  virtual bool isSubregFoldable() const { return false; }
931
932
  /// Attempt to fold a load or store of the specified stack
933
  /// slot into the specified machine instruction for the specified operand(s).
934
  /// If this is possible, a new instruction is returned with the specified
935
  /// operand folded, otherwise NULL is returned.
936
  /// The new instruction is inserted before MI, and the client is responsible
937
  /// for removing the old instruction.
938
  /// If VRM is passed, the assigned physregs can be inspected by target to
939
  /// decide on using an opcode (note that those assignments can still change).
940
  MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
941
                                  int FI,
942
                                  LiveIntervals *LIS = nullptr,
943
                                  VirtRegMap *VRM = nullptr) const;
944
945
  /// Same as the previous version except it allows folding of any load and
946
  /// store from / to any address, not just from a specific stack slot.
947
  MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
948
                                  MachineInstr &LoadMI,
949
                                  LiveIntervals *LIS = nullptr) const;
950
951
  /// Return true when there is potentially a faster code sequence
952
  /// for an instruction chain ending in \p Root. All potential patterns are
953
  /// returned in the \p Pattern vector. Pattern should be sorted in priority
954
  /// order since the pattern evaluator stops checking as soon as it finds a
955
  /// faster sequence.
956
  /// \param Root - Instruction that could be combined with one of its operands
957
  /// \param Patterns - Vector of possible combination patterns
958
  virtual bool getMachineCombinerPatterns(
959
      MachineInstr &Root,
960
      SmallVectorImpl<MachineCombinerPattern> &Patterns) const;
961
962
  /// Return true when a code sequence can improve throughput. It
963
  /// should be called only for instructions in loops.
964
  /// \param Pattern - combiner pattern
965
  virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const;
966
967
  /// Return true if the input \P Inst is part of a chain of dependent ops
968
  /// that are suitable for reassociation, otherwise return false.
969
  /// If the instruction's operands must be commuted to have a previous
970
  /// instruction of the same type define the first source operand, \P Commuted
971
  /// will be set to true.
972
  bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
973
974
  /// Return true when \P Inst is both associative and commutative.
975
0
  virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
976
0
    return false;
977
0
  }
978
979
  /// Return true when \P Inst has reassociable operands in the same \P MBB.
980
  virtual bool hasReassociableOperands(const MachineInstr &Inst,
981
                                       const MachineBasicBlock *MBB) const;
982
983
  /// Return true when \P Inst has reassociable sibling.
984
  bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
985
986
  /// When getMachineCombinerPatterns() finds patterns, this function generates
987
  /// the instructions that could replace the original code sequence. The client
988
  /// has to decide whether the actual replacement is beneficial or not.
989
  /// \param Root - Instruction that could be combined with one of its operands
990
  /// \param Pattern - Combination pattern for Root
991
  /// \param InsInstrs - Vector of new instructions that implement P
992
  /// \param DelInstrs - Old instructions, including Root, that could be
993
  /// replaced by InsInstr
994
  /// \param InstIdxForVirtReg - map of virtual register to instruction in
995
  /// InsInstr that defines it
996
  virtual void genAlternativeCodeSequence(
997
      MachineInstr &Root, MachineCombinerPattern Pattern,
998
      SmallVectorImpl<MachineInstr *> &InsInstrs,
999
      SmallVectorImpl<MachineInstr *> &DelInstrs,
1000
      DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const;
1001
1002
  /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
1003
  /// reduce critical path length.
1004
  void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
1005
                      MachineCombinerPattern Pattern,
1006
                      SmallVectorImpl<MachineInstr *> &InsInstrs,
1007
                      SmallVectorImpl<MachineInstr *> &DelInstrs,
1008
                      DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
1009
1010
  /// This is an architecture-specific helper function of reassociateOps.
1011
  /// Set special operand attributes for new instructions after reassociation.
1012
  virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
1013
                                     MachineInstr &NewMI1,
1014
330
                                     MachineInstr &NewMI2) const {}
1015
1016
  /// Return true when a target supports MachineCombiner.
1017
0
  virtual bool useMachineCombiner() const { return false; }
1018
1019
  /// Return true if the given SDNode can be copied during scheduling
1020
  /// even if it has glue.
1021
45
  virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; }
1022
1023
protected:
1024
  /// Target-dependent implementation for foldMemoryOperand.
1025
  /// Target-independent code in foldMemoryOperand will
1026
  /// take care of adding a MachineMemOperand to the newly created instruction.
1027
  /// The instruction and any auxiliary instructions necessary will be inserted
1028
  /// at InsertPt.
1029
  virtual MachineInstr *
1030
  foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
1031
                        ArrayRef<unsigned> Ops,
1032
                        MachineBasicBlock::iterator InsertPt, int FrameIndex,
1033
                        LiveIntervals *LIS = nullptr,
1034
19.6k
                        VirtRegMap *VRM = nullptr) const {
1035
19.6k
    return nullptr;
1036
19.6k
  }
1037
1038
  /// Target-dependent implementation for foldMemoryOperand.
1039
  /// Target-independent code in foldMemoryOperand will
1040
  /// take care of adding a MachineMemOperand to the newly created instruction.
1041
  /// The instruction and any auxiliary instructions necessary will be inserted
1042
  /// at InsertPt.
1043
  virtual MachineInstr *foldMemoryOperandImpl(
1044
      MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
1045
      MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1046
898
      LiveIntervals *LIS = nullptr) const {
1047
898
    return nullptr;
1048
898
  }
1049
1050
  /// Target-dependent implementation of getRegSequenceInputs.
1051
  ///
1052
  /// \returns true if it is possible to build the equivalent
1053
  /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
1054
  ///
1055
  /// \pre MI.isRegSequenceLike().
1056
  ///
1057
  /// \see TargetInstrInfo::getRegSequenceInputs.
1058
  virtual bool getRegSequenceLikeInputs(
1059
      const MachineInstr &MI, unsigned DefIdx,
1060
0
      SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
1061
0
    return false;
1062
0
  }
1063
1064
  /// Target-dependent implementation of getExtractSubregInputs.
1065
  ///
1066
  /// \returns true if it is possible to build the equivalent
1067
  /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1068
  ///
1069
  /// \pre MI.isExtractSubregLike().
1070
  ///
1071
  /// \see TargetInstrInfo::getExtractSubregInputs.
1072
  virtual bool getExtractSubregLikeInputs(const MachineInstr &MI,
1073
                                          unsigned DefIdx,
1074
0
                                          RegSubRegPairAndIdx &InputReg) const {
1075
0
    return false;
1076
0
  }
1077
1078
  /// Target-dependent implementation of getInsertSubregInputs.
1079
  ///
1080
  /// \returns true if it is possible to build the equivalent
1081
  /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1082
  ///
1083
  /// \pre MI.isInsertSubregLike().
1084
  ///
1085
  /// \see TargetInstrInfo::getInsertSubregInputs.
1086
  virtual bool
1087
  getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
1088
                            RegSubRegPair &BaseReg,
1089
0
                            RegSubRegPairAndIdx &InsertedReg) const {
1090
0
    return false;
1091
0
  }
1092
1093
public:
1094
  /// getAddressSpaceForPseudoSourceKind - Given the kind of memory
1095
  /// (e.g. stack) the target returns the corresponding address space.
1096
  virtual unsigned
1097
3.44M
  getAddressSpaceForPseudoSourceKind(unsigned Kind) const {
1098
3.44M
    return 0;
1099
3.44M
  }
1100
1101
  /// unfoldMemoryOperand - Separate a single instruction which folded a load or
1102
  /// a store or a load and a store into two or more instruction. If this is
1103
  /// possible, returns true as well as the new instructions by reference.
1104
  virtual bool
1105
  unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
1106
                      bool UnfoldLoad, bool UnfoldStore,
1107
0
                      SmallVectorImpl<MachineInstr *> &NewMIs) const {
1108
0
    return false;
1109
0
  }
1110
1111
  virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
1112
0
                                   SmallVectorImpl<SDNode *> &NewNodes) const {
1113
0
    return false;
1114
0
  }
1115
1116
  /// Returns the opcode of the would be new
1117
  /// instruction after load / store are unfolded from an instruction of the
1118
  /// specified opcode. It returns zero if the specified unfolding is not
1119
  /// possible. If LoadRegIndex is non-null, it is filled in with the operand
1120
  /// index of the operand which will hold the register holding the loaded
1121
  /// value.
1122
  virtual unsigned
1123
  getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
1124
5.12k
                             unsigned *LoadRegIndex = nullptr) const {
1125
5.12k
    return 0;
1126
5.12k
  }
1127
1128
  /// This is used by the pre-regalloc scheduler to determine if two loads are
1129
  /// loading from the same base address. It should only return true if the base
1130
  /// pointers are the same and the only differences between the two addresses
1131
  /// are the offset. It also returns the offsets by reference.
1132
  virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1133
                                       int64_t &Offset1,
1134
2.96M
                                       int64_t &Offset2) const {
1135
2.96M
    return false;
1136
2.96M
  }
1137
1138
  /// This is a used by the pre-regalloc scheduler to determine (in conjunction
1139
  /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
1140
  /// On some targets if two loads are loading from
1141
  /// addresses in the same cache line, it's better if they are scheduled
1142
  /// together. This function takes two integers that represent the load offsets
1143
  /// from the common base address. It returns true if it decides it's desirable
1144
  /// to schedule the two loads together. "NumLoads" is the number of loads that
1145
  /// have already been scheduled after Load1.
1146
  virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1147
                                       int64_t Offset1, int64_t Offset2,
1148
0
                                       unsigned NumLoads) const {
1149
0
    return false;
1150
0
  }
1151
1152
  /// Get the base operand and byte offset of an instruction that reads/writes
1153
  /// memory.
1154
  virtual bool getMemOperandWithOffset(const MachineInstr &MI,
1155
                                       const MachineOperand *&BaseOp,
1156
                                       int64_t &Offset,
1157
4
                                       const TargetRegisterInfo *TRI) const {
1158
4
    return false;
1159
4
  }
1160
1161
  /// Return true if the instruction contains a base register and offset. If
1162
  /// true, the function also sets the operand position in the instruction
1163
  /// for the base register and offset.
1164
  virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
1165
                                        unsigned &BasePos,
1166
43
                                        unsigned &OffsetPos) const {
1167
43
    return false;
1168
43
  }
1169
1170
  /// If the instruction is an increment of a constant value, return the amount.
1171
0
  virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
1172
0
    return false;
1173
0
  }
1174
1175
  /// Returns true if the two given memory operations should be scheduled
1176
  /// adjacent. Note that you have to add:
1177
  ///   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1178
  /// or
1179
  ///   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1180
  /// to TargetPassConfig::createMachineScheduler() to have an effect.
1181
  virtual bool shouldClusterMemOps(const MachineOperand &BaseOp1,
1182
                                   const MachineOperand &BaseOp2,
1183
0
                                   unsigned NumLoads) const {
1184
0
    llvm_unreachable("target did not implement shouldClusterMemOps()");
1185
0
  }
1186
1187
  /// Reverses the branch condition of the specified condition list,
1188
  /// returning false on success and true if it cannot be reversed.
1189
  virtual bool
1190
19
  reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1191
19
    return true;
1192
19
  }
1193
1194
  /// Insert a noop into the instruction stream at the specified point.
1195
  virtual void insertNoop(MachineBasicBlock &MBB,
1196
                          MachineBasicBlock::iterator MI) const;
1197
1198
  /// Return the noop instruction to use for a noop.
1199
  virtual void getNoop(MCInst &NopInst) const;
1200
1201
  /// Return true for post-incremented instructions.
1202
24
  virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
1203
1204
  /// Returns true if the instruction is already predicated.
1205
3.05M
  virtual bool isPredicated(const MachineInstr &MI) const { return false; }
1206
1207
  /// Returns true if the instruction is a
1208
  /// terminator instruction that has not been predicated.
1209
  virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
1210
1211
  /// Returns true if MI is an unconditional tail call.
1212
23.8k
  virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
1213
23.8k
    return false;
1214
23.8k
  }
1215
1216
  /// Returns true if the tail call can be made conditional on BranchCond.
1217
  virtual bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
1218
0
                                          const MachineInstr &TailCall) const {
1219
0
    return false;
1220
0
  }
1221
1222
  /// Replace the conditional branch in MBB with a conditional tail call.
1223
  virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB,
1224
                                         SmallVectorImpl<MachineOperand> &Cond,
1225
0
                                         const MachineInstr &TailCall) const {
1226
0
    llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
1227
0
  }
1228
1229
  /// Convert the instruction into a predicated instruction.
1230
  /// It returns true if the operation was successful.
1231
  virtual bool PredicateInstruction(MachineInstr &MI,
1232
                                    ArrayRef<MachineOperand> Pred) const;
1233
1234
  /// Returns true if the first specified predicate
1235
  /// subsumes the second, e.g. GE subsumes GT.
1236
  virtual bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1237
0
                                 ArrayRef<MachineOperand> Pred2) const {
1238
0
    return false;
1239
0
  }
1240
1241
  /// If the specified instruction defines any predicate
1242
  /// or condition code register(s) used for predication, returns true as well
1243
  /// as the definition predicate(s) by reference.
1244
  virtual bool DefinesPredicate(MachineInstr &MI,
1245
12.1k
                                std::vector<MachineOperand> &Pred) const {
1246
12.1k
    return false;
1247
12.1k
  }
1248
1249
  /// Return true if the specified instruction can be predicated.
1250
  /// By default, this returns true for every instruction with a
1251
  /// PredicateOperand.
1252
1.07k
  virtual bool isPredicable(const MachineInstr &MI) const {
1253
1.07k
    return MI.getDesc().isPredicable();
1254
1.07k
  }
1255
1256
  /// Return true if it's safe to move a machine
1257
  /// instruction that defines the specified register class.
1258
11.9M
  virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1259
11.9M
    return true;
1260
11.9M
  }
1261
1262
  /// Test if the given instruction should be considered a scheduling boundary.
1263
  /// This primarily includes labels and terminators.
1264
  virtual bool isSchedulingBoundary(const MachineInstr &MI,
1265
                                    const MachineBasicBlock *MBB,
1266
                                    const MachineFunction &MF) const;
1267
1268
  /// Measure the specified inline asm to determine an approximation of its
1269
  /// length.
1270
  virtual unsigned getInlineAsmLength(
1271
    const char *Str, const MCAsmInfo &MAI,
1272
    const TargetSubtargetInfo *STI = nullptr) const;
1273
1274
  /// Allocate and return a hazard recognizer to use for this target when
1275
  /// scheduling the machine instructions before register allocation.
1276
  virtual ScheduleHazardRecognizer *
1277
  CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
1278
                               const ScheduleDAG *DAG) const;
1279
1280
  /// Allocate and return a hazard recognizer to use for this target when
1281
  /// scheduling the machine instructions before register allocation.
1282
  virtual ScheduleHazardRecognizer *
1283
  CreateTargetMIHazardRecognizer(const InstrItineraryData *,
1284
                                 const ScheduleDAG *DAG) const;
1285
1286
  /// Allocate and return a hazard recognizer to use for this target when
1287
  /// scheduling the machine instructions after register allocation.
1288
  virtual ScheduleHazardRecognizer *
1289
  CreateTargetPostRAHazardRecognizer(const InstrItineraryData *,
1290
                                     const ScheduleDAG *DAG) const;
1291
1292
  /// Allocate and return a hazard recognizer to use for by non-scheduling
1293
  /// passes.
1294
  virtual ScheduleHazardRecognizer *
1295
0
  CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {
1296
0
    return nullptr;
1297
0
  }
1298
1299
  /// Provide a global flag for disabling the PreRA hazard recognizer that
1300
  /// targets may choose to honor.
1301
  bool usePreRAHazardRecognizer() const;
1302
1303
  /// For a comparison instruction, return the source registers
1304
  /// in SrcReg and SrcReg2 if having two register operands, and the value it
1305
  /// compares against in CmpValue. Return true if the comparison instruction
1306
  /// can be analyzed.
1307
  virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1308
6.22k
                              unsigned &SrcReg2, int &Mask, int &Value) const {
1309
6.22k
    return false;
1310
6.22k
  }
1311
1312
  /// See if the comparison instruction can be converted
1313
  /// into something more efficient. E.g., on ARM most instructions can set the
1314
  /// flags register, obviating the need for a separate CMP.
1315
  virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1316
                                    unsigned SrcReg2, int Mask, int Value,
1317
1.59k
                                    const MachineRegisterInfo *MRI) const {
1318
1.59k
    return false;
1319
1.59k
  }
1320
205k
  virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
1321
1322
  /// Try to remove the load by folding it to a register operand at the use.
1323
  /// We fold the load instructions if and only if the
1324
  /// def and use are in the same BB. We only look at one load and see
1325
  /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
1326
  /// defined by the load we are trying to fold. DefMI returns the machine
1327
  /// instruction that defines FoldAsLoadDefReg, and the function returns
1328
  /// the machine instruction generated due to folding.
1329
  virtual MachineInstr *optimizeLoadInstr(MachineInstr &MI,
1330
                                          const MachineRegisterInfo *MRI,
1331
                                          unsigned &FoldAsLoadDefReg,
1332
27.8k
                                          MachineInstr *&DefMI) const {
1333
27.8k
    return nullptr;
1334
27.8k
  }
1335
1336
  /// 'Reg' is known to be defined by a move immediate instruction,
1337
  /// try to fold the immediate into the use instruction.
1338
  /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1339
  /// then the caller may assume that DefMI has been erased from its parent
1340
  /// block. The caller may assume that it will not be erased by this
1341
  /// function otherwise.
1342
  virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
1343
900k
                             unsigned Reg, MachineRegisterInfo *MRI) const {
1344
900k
    return false;
1345
900k
  }
1346
1347
  /// Return the number of u-operations the given machine
1348
  /// instruction will be decoded to on the target cpu. The itinerary's
1349
  /// IssueWidth is the number of microops that can be dispatched each
1350
  /// cycle. An instruction with zero microops takes no dispatch resources.
1351
  virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1352
                                  const MachineInstr &MI) const;
1353
1354
  /// Return true for pseudo instructions that don't consume any
1355
  /// machine resources in their current form. These are common cases that the
1356
  /// scheduler should consider free, rather than conservatively handling them
1357
  /// as instructions with no itinerary.
1358
1.11M
  bool isZeroCost(unsigned Opcode) const {
1359
1.11M
    return Opcode <= TargetOpcode::COPY;
1360
1.11M
  }
1361
1362
  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1363
                                SDNode *DefNode, unsigned DefIdx,
1364
                                SDNode *UseNode, unsigned UseIdx) const;
1365
1366
  /// Compute and return the use operand latency of a given pair of def and use.
1367
  /// In most cases, the static scheduling itinerary was enough to determine the
1368
  /// operand latency. But it may not be possible for instructions with variable
1369
  /// number of defs / uses.
1370
  ///
1371
  /// This is a raw interface to the itinerary that may be directly overridden
1372
  /// by a target. Use computeOperandLatency to get the best estimate of
1373
  /// latency.
1374
  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1375
                                const MachineInstr &DefMI, unsigned DefIdx,
1376
                                const MachineInstr &UseMI,
1377
                                unsigned UseIdx) const;
1378
1379
  /// Compute the instruction latency of a given instruction.
1380
  /// If the instruction has higher cost when predicated, it's returned via
1381
  /// PredCost.
1382
  virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1383
                                   const MachineInstr &MI,
1384
                                   unsigned *PredCost = nullptr) const;
1385
1386
  virtual unsigned getPredicationCost(const MachineInstr &MI) const;
1387
1388
  virtual int getInstrLatency(const InstrItineraryData *ItinData,
1389
                              SDNode *Node) const;
1390
1391
  /// Return the default expected latency for a def based on its opcode.
1392
  unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1393
                             const MachineInstr &DefMI) const;
1394
1395
  int computeDefOperandLatency(const InstrItineraryData *ItinData,
1396
                               const MachineInstr &DefMI) const;
1397
1398
  /// Return true if this opcode has high latency to its result.
1399
1.96M
  virtual bool isHighLatencyDef(int opc) const { return false; }
1400
1401
  /// Compute operand latency between a def of 'Reg'
1402
  /// and a use in the current loop. Return true if the target considered
1403
  /// it 'high'. This is used by optimization passes such as machine LICM to
1404
  /// determine whether it makes sense to hoist an instruction out even in a
1405
  /// high register pressure situation.
1406
  virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1407
                                     const MachineRegisterInfo *MRI,
1408
                                     const MachineInstr &DefMI, unsigned DefIdx,
1409
                                     const MachineInstr &UseMI,
1410
72.7k
                                     unsigned UseIdx) const {
1411
72.7k
    return false;
1412
72.7k
  }
1413
1414
  /// Compute operand latency of a def of 'Reg'. Return true
1415
  /// if the target considered it 'low'.
1416
  virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1417
                                const MachineInstr &DefMI,
1418
                                unsigned DefIdx) const;
1419
1420
  /// Perform target-specific instruction verification.
1421
  virtual bool verifyInstruction(const MachineInstr &MI,
1422
9.39M
                                 StringRef &ErrInfo) const {
1423
9.39M
    return true;
1424
9.39M
  }
1425
1426
  /// Return the current execution domain and bit mask of
1427
  /// possible domains for instruction.
1428
  ///
1429
  /// Some micro-architectures have multiple execution domains, and multiple
1430
  /// opcodes that perform the same operation in different domains.  For
1431
  /// example, the x86 architecture provides the por, orps, and orpd
1432
  /// instructions that all do the same thing.  There is a latency penalty if a
1433
  /// register is written in one domain and read in another.
1434
  ///
1435
  /// This function returns a pair (domain, mask) containing the execution
1436
  /// domain of MI, and a bit mask of possible domains.  The setExecutionDomain
1437
  /// function can be used to change the opcode to one of the domains in the
1438
  /// bit mask.  Instructions whose execution domain can't be changed should
1439
  /// return a 0 mask.
1440
  ///
1441
  /// The execution domain numbers don't have any special meaning except domain
1442
  /// 0 is used for instructions that are not associated with any interesting
1443
  /// execution domain.
1444
  ///
1445
  virtual std::pair<uint16_t, uint16_t>
1446
0
  getExecutionDomain(const MachineInstr &MI) const {
1447
0
    return std::make_pair(0, 0);
1448
0
  }
1449
1450
  /// Change the opcode of MI to execute in Domain.
1451
  ///
1452
  /// The bit (1 << Domain) must be set in the mask returned from
1453
  /// getExecutionDomain(MI).
1454
0
  virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
1455
1456
  /// Returns the preferred minimum clearance
1457
  /// before an instruction with an unwanted partial register update.
1458
  ///
1459
  /// Some instructions only write part of a register, and implicitly need to
1460
  /// read the other parts of the register.  This may cause unwanted stalls
1461
  /// preventing otherwise unrelated instructions from executing in parallel in
1462
  /// an out-of-order CPU.
1463
  ///
1464
  /// For example, the x86 instruction cvtsi2ss writes its result to bits
1465
  /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1466
  /// the instruction needs to wait for the old value of the register to become
1467
  /// available:
1468
  ///
1469
  ///   addps %xmm1, %xmm0
1470
  ///   movaps %xmm0, (%rax)
1471
  ///   cvtsi2ss %rbx, %xmm0
1472
  ///
1473
  /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1474
  /// instruction before it can issue, even though the high bits of %xmm0
1475
  /// probably aren't needed.
1476
  ///
1477
  /// This hook returns the preferred clearance before MI, measured in
1478
  /// instructions.  Other defs of MI's operand OpNum are avoided in the last N
1479
  /// instructions before MI.  It should only return a positive value for
1480
  /// unwanted dependencies.  If the old bits of the defined register have
1481
  /// useful values, or if MI is determined to otherwise read the dependency,
1482
  /// the hook should return 0.
1483
  ///
1484
  /// The unwanted dependency may be handled by:
1485
  ///
1486
  /// 1. Allocating the same register for an MI def and use.  That makes the
1487
  ///    unwanted dependency identical to a required dependency.
1488
  ///
1489
  /// 2. Allocating a register for the def that has no defs in the previous N
1490
  ///    instructions.
1491
  ///
1492
  /// 3. Calling breakPartialRegDependency() with the same arguments.  This
1493
  ///    allows the target to insert a dependency breaking instruction.
1494
  ///
1495
  virtual unsigned
1496
  getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
1497
0
                               const TargetRegisterInfo *TRI) const {
1498
0
    // The default implementation returns 0 for no partial register dependency.
1499
0
    return 0;
1500
0
  }
1501
1502
  /// Return the minimum clearance before an instruction that reads an
1503
  /// unused register.
1504
  ///
1505
  /// For example, AVX instructions may copy part of a register operand into
1506
  /// the unused high bits of the destination register.
1507
  ///
1508
  /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
1509
  ///
1510
  /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1511
  /// false dependence on any previous write to %xmm0.
1512
  ///
1513
  /// This hook works similarly to getPartialRegUpdateClearance, except that it
1514
  /// does not take an operand index. Instead sets \p OpNum to the index of the
1515
  /// unused register.
1516
  virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
1517
728k
                                        const TargetRegisterInfo *TRI) const {
1518
728k
    // The default implementation returns 0 for no undef register dependency.
1519
728k
    return 0;
1520
728k
  }
1521
1522
  /// Insert a dependency-breaking instruction
1523
  /// before MI to eliminate an unwanted dependency on OpNum.
1524
  ///
1525
  /// If it wasn't possible to avoid a def in the last N instructions before MI
1526
  /// (see getPartialRegUpdateClearance), this hook will be called to break the
1527
  /// unwanted dependency.
1528
  ///
1529
  /// On x86, an xorps instruction can be used as a dependency breaker:
1530
  ///
1531
  ///   addps %xmm1, %xmm0
1532
  ///   movaps %xmm0, (%rax)
1533
  ///   xorps %xmm0, %xmm0
1534
  ///   cvtsi2ss %rbx, %xmm0
1535
  ///
1536
  /// An <imp-kill> operand should be added to MI if an instruction was
1537
  /// inserted.  This ties the instructions together in the post-ra scheduler.
1538
  ///
1539
  virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
1540
0
                                         const TargetRegisterInfo *TRI) const {}
1541
1542
  /// Create machine specific model for scheduling.
1543
  virtual DFAPacketizer *
1544
0
  CreateTargetScheduleState(const TargetSubtargetInfo &) const {
1545
0
    return nullptr;
1546
0
  }
1547
1548
  /// Sometimes, it is possible for the target
1549
  /// to tell, even without aliasing information, that two MIs access different
1550
  /// memory addresses. This function returns true if two MIs access different
1551
  /// memory addresses and false otherwise.
1552
  ///
1553
  /// Assumes any physical registers used to compute addresses have the same
1554
  /// value for both instructions. (This is the most useful assumption for
1555
  /// post-RA scheduling.)
1556
  ///
1557
  /// See also MachineInstr::mayAlias, which is implemented on top of this
1558
  /// function.
1559
  virtual bool
1560
  areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
1561
                                  const MachineInstr &MIb,
1562
1.85M
                                  AliasAnalysis *AA = nullptr) const {
1563
1.85M
    assert((MIa.mayLoad() || MIa.mayStore()) &&
1564
1.85M
           "MIa must load from or modify a memory location");
1565
1.85M
    assert((MIb.mayLoad() || MIb.mayStore()) &&
1566
1.85M
           "MIb must load from or modify a memory location");
1567
1.85M
    return false;
1568
1.85M
  }
1569
1570
  /// Return the value to use for the MachineCSE's LookAheadLimit,
1571
  /// which is a heuristic used for CSE'ing phys reg defs.
1572
464k
  virtual unsigned getMachineCSELookAheadLimit() const {
1573
464k
    // The default lookahead is small to prevent unprofitable quadratic
1574
464k
    // behavior.
1575
464k
    return 5;
1576
464k
  }
1577
1578
  /// Return an array that contains the ids of the target indices (used for the
1579
  /// TargetIndex machine operand) and their names.
1580
  ///
1581
  /// MIR Serialization is able to serialize only the target indices that are
1582
  /// defined by this method.
1583
  virtual ArrayRef<std::pair<int, const char *>>
1584
0
  getSerializableTargetIndices() const {
1585
0
    return None;
1586
0
  }
1587
1588
  /// Decompose the machine operand's target flags into two values - the direct
1589
  /// target flag value and any of bit flags that are applied.
1590
  virtual std::pair<unsigned, unsigned>
1591
0
  decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
1592
0
    return std::make_pair(0u, 0u);
1593
0
  }
1594
1595
  /// Return an array that contains the direct target flag values and their
1596
  /// names.
1597
  ///
1598
  /// MIR Serialization is able to serialize only the target flags that are
1599
  /// defined by this method.
1600
  virtual ArrayRef<std::pair<unsigned, const char *>>
1601
0
  getSerializableDirectMachineOperandTargetFlags() const {
1602
0
    return None;
1603
0
  }
1604
1605
  /// Return an array that contains the bitmask target flag values and their
1606
  /// names.
1607
  ///
1608
  /// MIR Serialization is able to serialize only the target flags that are
1609
  /// defined by this method.
1610
  virtual ArrayRef<std::pair<unsigned, const char *>>
1611
1
  getSerializableBitmaskMachineOperandTargetFlags() const {
1612
1
    return None;
1613
1
  }
1614
1615
  /// Return an array that contains the MMO target flag values and their
1616
  /// names.
1617
  ///
1618
  /// MIR Serialization is able to serialize only the MMO target flags that are
1619
  /// defined by this method.
1620
  virtual ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
1621
0
  getSerializableMachineMemOperandTargetFlags() const {
1622
0
    return None;
1623
0
  }
1624
1625
  /// Determines whether \p Inst is a tail call instruction. Override this
1626
  /// method on targets that do not properly set MCID::Return and MCID::Call on
1627
  /// tail call instructions."
1628
362
  virtual bool isTailCall(const MachineInstr &Inst) const {
1629
362
    return Inst.isReturn() && 
Inst.isCall()100
;
1630
362
  }
1631
1632
  /// True if the instruction is bound to the top of its basic block and no
1633
  /// other instructions shall be inserted before it. This can be implemented
1634
  /// to prevent register allocator to insert spills before such instructions.
1635
28.1M
  virtual bool isBasicBlockPrologue(const MachineInstr &MI) const {
1636
28.1M
    return false;
1637
28.1M
  }
1638
1639
  /// Returns a \p outliner::OutlinedFunction struct containing target-specific
1640
  /// information for a set of outlining candidates.
1641
  virtual outliner::OutlinedFunction getOutliningCandidateInfo(
1642
0
      std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
1643
0
    llvm_unreachable(
1644
0
        "Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!");
1645
0
  }
1646
1647
  /// Returns how or if \p MI should be outlined.
1648
  virtual outliner::InstrType
1649
0
  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
1650
0
    llvm_unreachable(
1651
0
        "Target didn't implement TargetInstrInfo::getOutliningType!");
1652
0
  }
1653
1654
  /// Optional target hook that returns true if \p MBB is safe to outline from,
1655
  /// and returns any target-specific information in \p Flags.
1656
  virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
1657
24
                                      unsigned &Flags) const {
1658
24
    return true;
1659
24
  }
1660
1661
  /// Insert a custom frame for outlined functions.
1662
  virtual void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
1663
0
                                  const outliner::OutlinedFunction &OF) const {
1664
0
    llvm_unreachable(
1665
0
        "Target didn't implement TargetInstrInfo::buildOutlinedFrame!");
1666
0
  }
1667
1668
  /// Insert a call to an outlined function into the program.
1669
  /// Returns an iterator to the spot where we inserted the call. This must be
1670
  /// implemented by the target.
1671
  virtual MachineBasicBlock::iterator
1672
  insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
1673
                     MachineBasicBlock::iterator &It, MachineFunction &MF,
1674
0
                     const outliner::Candidate &C) const {
1675
0
    llvm_unreachable(
1676
0
        "Target didn't implement TargetInstrInfo::insertOutlinedCall!");
1677
0
  }
1678
1679
  /// Return true if the function can safely be outlined from.
1680
  /// A function \p MF is considered safe for outlining if an outlined function
1681
  /// produced from instructions in F will produce a program which produces the
1682
  /// same output for any set of given inputs.
1683
  virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
1684
0
                                           bool OutlineFromLinkOnceODRs) const {
1685
0
    llvm_unreachable("Target didn't implement "
1686
0
                     "TargetInstrInfo::isFunctionSafeToOutlineFrom!");
1687
0
  }
1688
1689
  /// Return true if the function should be outlined from by default.
1690
0
  virtual bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const {
1691
0
    return false;
1692
0
  }
1693
1694
private:
1695
  unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
1696
  unsigned CatchRetOpcode;
1697
  unsigned ReturnOpcode;
1698
};
1699
1700
/// Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
1701
template <> struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> {
1702
  using RegInfo = DenseMapInfo<unsigned>;
1703
1704
20.8M
  static inline TargetInstrInfo::RegSubRegPair getEmptyKey() {
1705
20.8M
    return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
1706
20.8M
                                          RegInfo::getEmptyKey());
1707
20.8M
  }
1708
1709
13.5M
  static inline TargetInstrInfo::RegSubRegPair getTombstoneKey() {
1710
13.5M
    return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
1711
13.5M
                                          RegInfo::getTombstoneKey());
1712
13.5M
  }
1713
1714
  /// Reuse getHashValue implementation from
1715
  /// std::pair<unsigned, unsigned>.
1716
9.98M
  static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
1717
9.98M
    std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
1718
9.98M
    return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
1719
9.98M
  }
1720
1721
  static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
1722
43.8M
                      const TargetInstrInfo::RegSubRegPair &RHS) {
1723
43.8M
    return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
1724
43.8M
           
RegInfo::isEqual(LHS.SubReg, RHS.SubReg)25.8M
;
1725
43.8M
  }
1726
};
1727
1728
} // end namespace llvm
1729
1730
#endif // LLVM_TARGET_TARGETINSTRINFO_H