Coverage Report

Created: 2018-12-11 17:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/TargetLowering.h
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//===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file describes how to lower LLVM code to machine code.  This has two
12
/// main components:
13
///
14
///  1. Which ValueTypes are natively supported by the target.
15
///  2. Which operations are supported for supported ValueTypes.
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///  3. Cost thresholds for alternative implementations of certain operations.
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///
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/// In addition it has a few other components, like information about FP
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/// immediates.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_TARGETLOWERING_H
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#define LLVM_CODEGEN_TARGETLOWERING_H
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26
#include "llvm/ADT/APInt.h"
27
#include "llvm/ADT/ArrayRef.h"
28
#include "llvm/ADT/DenseMap.h"
29
#include "llvm/ADT/STLExtras.h"
30
#include "llvm/ADT/SmallVector.h"
31
#include "llvm/ADT/StringRef.h"
32
#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
33
#include "llvm/CodeGen/DAGCombine.h"
34
#include "llvm/CodeGen/ISDOpcodes.h"
35
#include "llvm/CodeGen/RuntimeLibcalls.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/CodeGen/TargetCallingConv.h"
39
#include "llvm/CodeGen/ValueTypes.h"
40
#include "llvm/IR/Attributes.h"
41
#include "llvm/IR/CallSite.h"
42
#include "llvm/IR/CallingConv.h"
43
#include "llvm/IR/DataLayout.h"
44
#include "llvm/IR/DerivedTypes.h"
45
#include "llvm/IR/Function.h"
46
#include "llvm/IR/IRBuilder.h"
47
#include "llvm/IR/InlineAsm.h"
48
#include "llvm/IR/Instruction.h"
49
#include "llvm/IR/Instructions.h"
50
#include "llvm/IR/Type.h"
51
#include "llvm/MC/MCRegisterInfo.h"
52
#include "llvm/Support/AtomicOrdering.h"
53
#include "llvm/Support/Casting.h"
54
#include "llvm/Support/ErrorHandling.h"
55
#include "llvm/Support/MachineValueType.h"
56
#include "llvm/Target/TargetMachine.h"
57
#include <algorithm>
58
#include <cassert>
59
#include <climits>
60
#include <cstdint>
61
#include <iterator>
62
#include <map>
63
#include <string>
64
#include <utility>
65
#include <vector>
66
67
namespace llvm {
68
69
class BranchProbability;
70
class CCState;
71
class CCValAssign;
72
class Constant;
73
class FastISel;
74
class FunctionLoweringInfo;
75
class GlobalValue;
76
class IntrinsicInst;
77
struct KnownBits;
78
class LLVMContext;
79
class MachineBasicBlock;
80
class MachineFunction;
81
class MachineInstr;
82
class MachineJumpTableInfo;
83
class MachineLoop;
84
class MachineRegisterInfo;
85
class MCContext;
86
class MCExpr;
87
class Module;
88
class TargetRegisterClass;
89
class TargetLibraryInfo;
90
class TargetRegisterInfo;
91
class Value;
92
93
namespace Sched {
94
95
  enum Preference {
96
    None,             // No preference
97
    Source,           // Follow source order.
98
    RegPressure,      // Scheduling for lowest register pressure.
99
    Hybrid,           // Scheduling for both latency and register pressure.
100
    ILP,              // Scheduling for ILP in low register pressure mode.
101
    VLIW              // Scheduling for VLIW targets.
102
  };
103
104
} // end namespace Sched
105
106
/// This base class for TargetLowering contains the SelectionDAG-independent
107
/// parts that can be used from the rest of CodeGen.
108
class TargetLoweringBase {
109
public:
110
  /// This enum indicates whether operations are valid for a target, and if not,
111
  /// what action should be used to make them valid.
112
  enum LegalizeAction : uint8_t {
113
    Legal,      // The target natively supports this operation.
114
    Promote,    // This operation should be executed in a larger type.
115
    Expand,     // Try to expand this to other ops, otherwise use a libcall.
116
    LibCall,    // Don't try to expand this to other ops, always use a libcall.
117
    Custom      // Use the LowerOperation hook to implement custom lowering.
118
  };
119
120
  /// This enum indicates whether a types are legal for a target, and if not,
121
  /// what action should be used to make them valid.
122
  enum LegalizeTypeAction : uint8_t {
123
    TypeLegal,           // The target natively supports this type.
124
    TypePromoteInteger,  // Replace this integer with a larger one.
125
    TypeExpandInteger,   // Split this integer into two of half the size.
126
    TypeSoftenFloat,     // Convert this float to a same size integer type,
127
                         // if an operation is not supported in target HW.
128
    TypeExpandFloat,     // Split this float into two of half the size.
129
    TypeScalarizeVector, // Replace this one-element vector with its element.
130
    TypeSplitVector,     // Split this vector into two of half the size.
131
    TypeWidenVector,     // This vector should be widened into a larger vector.
132
    TypePromoteFloat     // Replace this float with a larger one.
133
  };
134
135
  /// LegalizeKind holds the legalization kind that needs to happen to EVT
136
  /// in order to type-legalize it.
137
  using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
138
139
  /// Enum that describes how the target represents true/false values.
140
  enum BooleanContent {
141
    UndefinedBooleanContent,    // Only bit 0 counts, the rest can hold garbage.
142
    ZeroOrOneBooleanContent,        // All bits zero except for bit 0.
143
    ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
144
  };
145
146
  /// Enum that describes what type of support for selects the target has.
147
  enum SelectSupportKind {
148
    ScalarValSelect,      // The target supports scalar selects (ex: cmov).
149
    ScalarCondVectorVal,  // The target supports selects with a scalar condition
150
                          // and vector values (ex: cmov).
151
    VectorMaskSelect      // The target supports vector selects with a vector
152
                          // mask (ex: x86 blends).
153
  };
154
155
  /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
156
  /// to, if at all. Exists because different targets have different levels of
157
  /// support for these atomic instructions, and also have different options
158
  /// w.r.t. what they should expand to.
159
  enum class AtomicExpansionKind {
160
    None,    // Don't expand the instruction.
161
    LLSC,    // Expand the instruction into loadlinked/storeconditional; used
162
             // by ARM/AArch64.
163
    LLOnly,  // Expand the (load) instruction into just a load-linked, which has
164
             // greater atomic guarantees than a normal load.
165
    CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
166
    MaskedIntrinsic, // Use a target-specific intrinsic for the LL/SC loop.
167
  };
168
169
  /// Enum that specifies when a multiplication should be expanded.
170
  enum class MulExpansionKind {
171
    Always,            // Always expand the instruction.
172
    OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
173
                       // or custom.
174
  };
175
176
  class ArgListEntry {
177
  public:
178
    Value *Val = nullptr;
179
    SDValue Node = SDValue();
180
    Type *Ty = nullptr;
181
    bool IsSExt : 1;
182
    bool IsZExt : 1;
183
    bool IsInReg : 1;
184
    bool IsSRet : 1;
185
    bool IsNest : 1;
186
    bool IsByVal : 1;
187
    bool IsInAlloca : 1;
188
    bool IsReturned : 1;
189
    bool IsSwiftSelf : 1;
190
    bool IsSwiftError : 1;
191
    uint16_t Alignment = 0;
192
193
    ArgListEntry()
194
        : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
195
          IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
196
2.29M
          IsSwiftSelf(false), IsSwiftError(false) {}
197
198
    void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx);
199
  };
200
  using ArgListTy = std::vector<ArgListEntry>;
201
202
  virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
203
18.7k
                                     ArgListTy &Args) const {};
204
205
448k
  static ISD::NodeType getExtendForContent(BooleanContent Content) {
206
448k
    switch (Content) {
207
448k
    case UndefinedBooleanContent:
208
103
      // Extend by adding rubbish bits.
209
103
      return ISD::ANY_EXTEND;
210
448k
    case ZeroOrOneBooleanContent:
211
446k
      // Extend by adding zero bits.
212
446k
      return ISD::ZERO_EXTEND;
213
448k
    case ZeroOrNegativeOneBooleanContent:
214
2.04k
      // Extend by copying the sign bit.
215
2.04k
      return ISD::SIGN_EXTEND;
216
0
    }
217
0
    llvm_unreachable("Invalid content kind");
218
0
  }
219
220
  /// NOTE: The TargetMachine owns TLOF.
221
  explicit TargetLoweringBase(const TargetMachine &TM);
222
  TargetLoweringBase(const TargetLoweringBase &) = delete;
223
  TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
224
35.7k
  virtual ~TargetLoweringBase() = default;
225
226
protected:
227
  /// Initialize all of the actions to default values.
228
  void initActions();
229
230
public:
231
19.3M
  const TargetMachine &getTargetMachine() const { return TM; }
232
233
3.21M
  virtual bool useSoftFloat() const { return false; }
234
235
  /// Return the pointer type for the given address space, defaults to
236
  /// the pointer type from the data layout.
237
  /// FIXME: The default needs to be removed once all the code is updated.
238
35.1M
  MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
239
35.1M
    return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
240
35.1M
  }
241
242
  /// Return the type for frame index, which is determined by
243
  /// the alloca address space specified through the data layout.
244
670k
  MVT getFrameIndexTy(const DataLayout &DL) const {
245
670k
    return getPointerTy(DL, DL.getAllocaAddrSpace());
246
670k
  }
247
248
  /// Return the type for operands of fence.
249
  /// TODO: Let fence operands be of i32 type and remove this.
250
12.3k
  virtual MVT getFenceOperandTy(const DataLayout &DL) const {
251
12.3k
    return getPointerTy(DL);
252
12.3k
  }
253
254
  /// EVT is not used in-tree, but is used by out-of-tree target.
255
  /// A documentation for this function would be nice...
256
  virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
257
258
  EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
259
                       bool LegalTypes = true) const;
260
261
  /// Returns the type to be used for the index operand of:
262
  /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
263
  /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
264
267k
  virtual MVT getVectorIdxTy(const DataLayout &DL) const {
265
267k
    return getPointerTy(DL);
266
267k
  }
267
268
269k
  virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
269
269k
    return true;
270
269k
  }
271
272
  /// Return true if it is profitable to convert a select of FP constants into
273
  /// a constant pool load whose address depends on the select condition. The
274
  /// parameter may be used to differentiate a select with FP compare from
275
  /// integer compare.
276
159k
  virtual bool reduceSelectOfFPConstantLoads(bool IsFPSetCC) const {
277
159k
    return true;
278
159k
  }
279
280
  /// Return true if multiple condition registers are available.
281
4.08M
  bool hasMultipleConditionRegisters() const {
282
4.08M
    return HasMultipleConditionRegisters;
283
4.08M
  }
284
285
  /// Return true if the target has BitExtract instructions.
286
231k
  bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
287
288
  /// Return the preferred vector type legalization action.
289
  virtual TargetLoweringBase::LegalizeTypeAction
290
4.05M
  getPreferredVectorAction(MVT VT) const {
291
4.05M
    // The default action for one element vectors is to scalarize
292
4.05M
    if (VT.getVectorNumElements() == 1)
293
659k
      return TypeScalarizeVector;
294
3.39M
    // The default action for other vectors is to promote
295
3.39M
    return TypePromoteInteger;
296
3.39M
  }
297
298
  // There are two general methods for expanding a BUILD_VECTOR node:
299
  //  1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
300
  //     them together.
301
  //  2. Build the vector on the stack and then load it.
302
  // If this function returns true, then method (1) will be used, subject to
303
  // the constraint that all of the necessary shuffles are legal (as determined
304
  // by isShuffleMaskLegal). If this function returns false, then method (2) is
305
  // always used. The vector type, and the number of defined values, are
306
  // provided.
307
  virtual bool
308
  shouldExpandBuildVectorWithShuffles(EVT /* VT */,
309
2.73k
                                      unsigned DefinedValues) const {
310
2.73k
    return DefinedValues < 3;
311
2.73k
  }
312
313
  /// Return true if integer divide is usually cheaper than a sequence of
314
  /// several shifts, adds, and multiplies for this target.
315
  /// The definition of "cheaper" may depend on whether we're optimizing
316
  /// for speed or for size.
317
1.28k
  virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
318
319
  /// Return true if the target can handle a standalone remainder operation.
320
0
  virtual bool hasStandaloneRem(EVT VT) const {
321
0
    return true;
322
0
  }
323
324
  /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
325
130
  virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
326
130
    // Default behavior is to replace SQRT(X) with X*RSQRT(X).
327
130
    return false;
328
130
  }
329
330
  /// Reciprocal estimate status values used by the functions below.
331
  enum ReciprocalEstimate : int {
332
    Unspecified = -1,
333
    Disabled = 0,
334
    Enabled = 1
335
  };
336
337
  /// Return a ReciprocalEstimate enum value for a square root of the given type
338
  /// based on the function's attributes. If the operation is not overridden by
339
  /// the function's attributes, "Unspecified" is returned and target defaults
340
  /// are expected to be used for instruction selection.
341
  int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
342
343
  /// Return a ReciprocalEstimate enum value for a division of the given type
344
  /// based on the function's attributes. If the operation is not overridden by
345
  /// the function's attributes, "Unspecified" is returned and target defaults
346
  /// are expected to be used for instruction selection.
347
  int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
348
349
  /// Return the refinement step count for a square root of the given type based
350
  /// on the function's attributes. If the operation is not overridden by
351
  /// the function's attributes, "Unspecified" is returned and target defaults
352
  /// are expected to be used for instruction selection.
353
  int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
354
355
  /// Return the refinement step count for a division of the given type based
356
  /// on the function's attributes. If the operation is not overridden by
357
  /// the function's attributes, "Unspecified" is returned and target defaults
358
  /// are expected to be used for instruction selection.
359
  int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
360
361
  /// Returns true if target has indicated at least one type should be bypassed.
362
501k
  bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
363
364
  /// Returns map of slow types for division or remainder with corresponding
365
  /// fast types
366
23.8k
  const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
367
23.8k
    return BypassSlowDivWidths;
368
23.8k
  }
369
370
  /// Return true if Flow Control is an expensive operation that should be
371
  /// avoided.
372
74.7k
  bool isJumpExpensive() const { return JumpIsExpensive; }
373
374
  /// Return true if selects are only cheaper than branches if the branch is
375
  /// unlikely to be predicted right.
376
283k
  bool isPredictableSelectExpensive() const {
377
283k
    return PredictableSelectIsExpensive;
378
283k
  }
379
380
  /// If a branch or a select condition is skewed in one direction by more than
381
  /// this factor, it is very likely to be predicted correctly.
382
  virtual BranchProbability getPredictableBranchThreshold() const;
383
384
  /// Return true if the following transform is beneficial:
385
  /// fold (conv (load x)) -> (load (conv*)x)
386
  /// On architectures that don't natively support some vector loads
387
  /// efficiently, casting the load to a smaller vector of larger types and
388
  /// loading is more efficient, however, this can be undone by optimizations in
389
  /// dag combiner.
390
  virtual bool isLoadBitCastBeneficial(EVT LoadVT,
391
19.1k
                                       EVT BitcastVT) const {
392
19.1k
    // Don't do if we could do an indexed load on the original type, but not on
393
19.1k
    // the new one.
394
19.1k
    if (!LoadVT.isSimple() || 
!BitcastVT.isSimple()19.1k
)
395
89
      return true;
396
19.0k
397
19.0k
    MVT LoadMVT = LoadVT.getSimpleVT();
398
19.0k
399
19.0k
    // Don't bother doing this if it's just going to be promoted again later, as
400
19.0k
    // doing so might interfere with other combines.
401
19.0k
    if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
402
19.0k
        
getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT()388
)
403
251
      return false;
404
18.8k
405
18.8k
    return true;
406
18.8k
  }
407
408
  /// Return true if the following transform is beneficial:
409
  /// (store (y (conv x)), y*)) -> (store x, (x*))
410
22.9k
  virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {
411
22.9k
    // Default to the same logic as loads.
412
22.9k
    return isLoadBitCastBeneficial(StoreVT, BitcastVT);
413
22.9k
  }
414
415
  /// Return true if it is expected to be cheaper to do a store of a non-zero
416
  /// vector constant with the given size and type for the address space than to
417
  /// store the individual scalar element constants.
418
  virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
419
                                            unsigned NumElem,
420
231k
                                            unsigned AddrSpace) const {
421
231k
    return false;
422
231k
  }
423
424
  /// Allow store merging after legalization in addition to before legalization.
425
  /// This may catch stores that do not exist earlier (eg, stores created from
426
  /// intrinsics).
427
1.49M
  virtual bool mergeStoresAfterLegalization() const { return true; }
428
429
  /// Returns if it's reasonable to merge stores to MemVT size.
430
  virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
431
6.45k
                                const SelectionDAG &DAG) const {
432
6.45k
    return true;
433
6.45k
  }
434
435
  /// Return true if it is cheap to speculate a call to intrinsic cttz.
436
8
  virtual bool isCheapToSpeculateCttz() const {
437
8
    return false;
438
8
  }
439
440
  /// Return true if it is cheap to speculate a call to intrinsic ctlz.
441
5
  virtual bool isCheapToSpeculateCtlz() const {
442
5
    return false;
443
5
  }
444
445
  /// Return true if ctlz instruction is fast.
446
0
  virtual bool isCtlzFast() const {
447
0
    return false;
448
0
  }
449
450
  /// Return true if it is safe to transform an integer-domain bitwise operation
451
  /// into the equivalent floating-point operation. This should be set to true
452
  /// if the target has IEEE-754-compliant fabs/fneg operations for the input
453
  /// type.
454
24.3k
  virtual bool hasBitPreservingFPLogic(EVT VT) const {
455
24.3k
    return false;
456
24.3k
  }
457
458
  /// Return true if it is cheaper to split the store of a merged int val
459
  /// from a pair of smaller values into multiple stores.
460
574
  virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
461
574
    return false;
462
574
  }
463
464
  /// Return if the target supports combining a
465
  /// chain like:
466
  /// \code
467
  ///   %andResult = and %val1, #mask
468
  ///   %icmpResult = icmp %andResult, 0
469
  /// \endcode
470
  /// into a single machine instruction of a form like:
471
  /// \code
472
  ///   cc = test %register, #mask
473
  /// \endcode
474
97
  virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
475
97
    return false;
476
97
  }
477
478
  /// Use bitwise logic to make pairs of compares more efficient. For example:
479
  /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
480
  /// This should be true when it takes more than one instruction to lower
481
  /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
482
  /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
483
7.27k
  virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
484
7.27k
    return false;
485
7.27k
  }
486
487
  /// Return the preferred operand type if the target has a quick way to compare
488
  /// integer values of the given size. Assume that any legal integer type can
489
  /// be compared efficiently. Targets may override this to allow illegal wide
490
  /// types to return a vector type if there is support to compare that type.
491
44
  virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
492
44
    MVT VT = MVT::getIntegerVT(NumBits);
493
44
    return isTypeLegal(VT) ? 
VT22
:
MVT::INVALID_SIMPLE_VALUE_TYPE22
;
494
44
  }
495
496
  /// Return true if the target should transform:
497
  /// (X & Y) == Y ---> (~X & Y) == 0
498
  /// (X & Y) != Y ---> (~X & Y) != 0
499
  ///
500
  /// This may be profitable if the target has a bitwise and-not operation that
501
  /// sets comparison flags. A target may want to limit the transformation based
502
  /// on the type of Y or if Y is a constant.
503
  ///
504
  /// Note that the transform will not occur if Y is known to be a power-of-2
505
  /// because a mask and compare of a single bit can be handled by inverting the
506
  /// predicate, for example:
507
  /// (X & 8) == 8 ---> (X & 8) != 0
508
714
  virtual bool hasAndNotCompare(SDValue Y) const {
509
714
    return false;
510
714
  }
511
512
  /// Return true if the target has a bitwise and-not operation:
513
  /// X = ~A & B
514
  /// This can be used to simplify select or other instructions.
515
771
  virtual bool hasAndNot(SDValue X) const {
516
771
    // If the target has the more complex version of this operation, assume that
517
771
    // it has this operation too.
518
771
    return hasAndNotCompare(X);
519
771
  }
520
521
  /// There are two ways to clear extreme bits (either low or high):
522
  /// Mask:    x &  (-1 << y)  (the instcombine canonical form)
523
  /// Shifts:  x >> y << y
524
  /// Return true if the variant with 2 shifts is preferred.
525
  /// Return false if there is no preference.
526
333k
  virtual bool preferShiftsToClearExtremeBits(SDValue X) const {
527
333k
    // By default, let's assume that no one prefers shifts.
528
333k
    return false;
529
333k
  }
530
531
  /// Should we tranform the IR-optimal check for whether given truncation
532
  /// down into KeptBits would be truncating or not:
533
  ///   (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
534
  /// Into it's more traditional form:
535
  ///   ((%x << C) a>> C) dstcond %x
536
  /// Return true if we should transform.
537
  /// Return false if there is no preference.
538
  virtual bool shouldTransformSignedTruncationCheck(EVT XVT,
539
59
                                                    unsigned KeptBits) const {
540
59
    // By default, let's assume that no one prefers shifts.
541
59
    return false;
542
59
  }
543
544
  /// Return true if the target wants to use the optimization that
545
  /// turns ext(promotableInst1(...(promotableInstN(load)))) into
546
  /// promotedInst1(...(promotedInstN(ext(load)))).
547
540k
  bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
548
549
  /// Return true if the target can combine store(extractelement VectorTy,
550
  /// Idx).
551
  /// \p Cost[out] gives the cost of that transformation when this is true.
552
  virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
553
46.1k
                                         unsigned &Cost) const {
554
46.1k
    return false;
555
46.1k
  }
556
557
  /// Return true if inserting a scalar into a variable element of an undef
558
  /// vector is more efficiently handled by splatting the scalar instead.
559
29
  virtual bool shouldSplatInsEltVarIndex(EVT) const {
560
29
    return false;
561
29
  }
562
563
  /// Return true if target supports floating point exceptions.
564
12.7M
  bool hasFloatingPointExceptions() const {
565
12.7M
    return HasFloatingPointExceptions;
566
12.7M
  }
567
568
  /// Return true if target always beneficiates from combining into FMA for a
569
  /// given value type. This must typically return false on targets where FMA
570
  /// takes more cycles to execute than FADD.
571
4.60k
  virtual bool enableAggressiveFMAFusion(EVT VT) const {
572
4.60k
    return false;
573
4.60k
  }
574
575
  /// Return the ValueType of the result of SETCC operations.
576
  virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
577
                                 EVT VT) const;
578
579
  /// Return the ValueType for comparison libcalls. Comparions libcalls include
580
  /// floating point comparion calls, and Ordered/Unordered check calls on
581
  /// floating point numbers.
582
  virtual
583
  MVT::SimpleValueType getCmpLibcallReturnType() const;
584
585
  /// For targets without i1 registers, this gives the nature of the high-bits
586
  /// of boolean values held in types wider than i1.
587
  ///
588
  /// "Boolean values" are special true/false values produced by nodes like
589
  /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
590
  /// Not to be confused with general values promoted from i1.  Some cpus
591
  /// distinguish between vectors of boolean and scalars; the isVec parameter
592
  /// selects between the two kinds.  For example on X86 a scalar boolean should
593
  /// be zero extended from i1, while the elements of a vector of booleans
594
  /// should be sign extended from i1.
595
  ///
596
  /// Some cpus also treat floating point types the same way as they treat
597
  /// vectors instead of the way they treat scalars.
598
2.41M
  BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
599
2.41M
    if (isVec)
600
287k
      return BooleanVectorContents;
601
2.12M
    return isFloat ? 
BooleanFloatContents47.5k
:
BooleanContents2.08M
;
602
2.12M
  }
603
604
2.39M
  BooleanContent getBooleanContents(EVT Type) const {
605
2.39M
    return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
606
2.39M
  }
607
608
  /// Return target scheduling preference.
609
513k
  Sched::Preference getSchedulingPreference() const {
610
513k
    return SchedPreferenceInfo;
611
513k
  }
612
613
  /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
614
  /// for different nodes. This function returns the preference (or none) for
615
  /// the given node.
616
17.8M
  virtual Sched::Preference getSchedulingPreference(SDNode *) const {
617
17.8M
    return Sched::None;
618
17.8M
  }
619
620
  /// Return the register class that should be used for the specified value
621
  /// type.
622
29.6M
  virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
623
29.6M
    const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
624
29.6M
    assert(RC && "This value type is not natively supported!");
625
29.6M
    return RC;
626
29.6M
  }
627
628
  /// Return the 'representative' register class for the specified value
629
  /// type.
630
  ///
631
  /// The 'representative' register class is the largest legal super-reg
632
  /// register class for the register class of the value type.  For example, on
633
  /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
634
  /// register class is GR64 on x86_64.
635
3.29M
  virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
636
3.29M
    const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
637
3.29M
    return RC;
638
3.29M
  }
639
640
  /// Return the cost of the 'representative' register class for the specified
641
  /// value type.
642
2.95M
  virtual uint8_t getRepRegClassCostFor(MVT VT) const {
643
2.95M
    return RepRegClassCostForVT[VT.SimpleTy];
644
2.95M
  }
645
646
  /// Return true if the target has native support for the specified value type.
647
  /// This means that it has a register that directly holds it without
648
  /// promotions or expansions.
649
724M
  bool isTypeLegal(EVT VT) const {
650
724M
    assert(!VT.isSimple() ||
651
724M
           (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
652
724M
    return VT.isSimple() && 
RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr723M
;
653
724M
  }
654
655
  class ValueTypeActionImpl {
656
    /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
657
    /// that indicates how instruction selection should deal with the type.
658
    LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
659
660
  public:
661
51.3k
    ValueTypeActionImpl() {
662
51.3k
      std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
663
51.3k
                TypeLegal);
664
51.3k
    }
665
666
139M
    LegalizeTypeAction getTypeAction(MVT VT) const {
667
139M
      return ValueTypeActions[VT.SimpleTy];
668
139M
    }
669
670
4.85M
    void setTypeAction(MVT VT, LegalizeTypeAction Action) {
671
4.85M
      ValueTypeActions[VT.SimpleTy] = Action;
672
4.85M
    }
673
  };
674
675
2.21M
  const ValueTypeActionImpl &getValueTypeActions() const {
676
2.21M
    return ValueTypeActions;
677
2.21M
  }
678
679
  /// Return how we should legalize values of this type, either it is already
680
  /// legal (return 'Legal') or we need to promote it to a larger type (return
681
  /// 'Promote'), or we need to expand it into multiple registers of smaller
682
  /// integer type (return 'Expand').  'Custom' is not an option.
683
130M
  LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
684
130M
    return getTypeConversion(Context, VT).first;
685
130M
  }
686
37.9k
  LegalizeTypeAction getTypeAction(MVT VT) const {
687
37.9k
    return ValueTypeActions.getTypeAction(VT);
688
37.9k
  }
689
690
  /// For types supported by the target, this is an identity function.  For
691
  /// types that must be promoted to larger types, this returns the larger type
692
  /// to promote to.  For integer types that are larger than the largest integer
693
  /// register, this contains one step in the expansion to get to the smaller
694
  /// register. For illegal floating point types, this returns the integer type
695
  /// to transform to.
696
1.90M
  EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
697
1.90M
    return getTypeConversion(Context, VT).second;
698
1.90M
  }
699
700
  /// For types supported by the target, this is an identity function.  For
701
  /// types that must be expanded (i.e. integer types that are larger than the
702
  /// largest integer register or illegal floating point types), this returns
703
  /// the largest legal type it will be expanded to.
704
19.7k
  EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
705
19.7k
    assert(!VT.isVector());
706
21.2k
    while (true) {
707
21.2k
      switch (getTypeAction(Context, VT)) {
708
21.2k
      case TypeLegal:
709
19.7k
        return VT;
710
21.2k
      case TypeExpandInteger:
711
1.45k
        VT = getTypeToTransformTo(Context, VT);
712
1.45k
        break;
713
21.2k
      default:
714
0
        llvm_unreachable("Type is not legal nor is it to be expanded!");
715
21.2k
      }
716
21.2k
    }
717
19.7k
  }
718
719
  /// Vector types are broken down into some number of legal first class types.
720
  /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
721
  /// promoted EVT::f64 values with the X86 FP stack.  Similarly, EVT::v2i64
722
  /// turns into 4 EVT::i32 values with both PPC and X86.
723
  ///
724
  /// This method returns the number of registers needed, and the VT for each
725
  /// register.  It also returns the VT and quantity of the intermediate values
726
  /// before they are promoted/expanded.
727
  unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
728
                                  EVT &IntermediateVT,
729
                                  unsigned &NumIntermediates,
730
                                  MVT &RegisterVT) const;
731
732
  /// Certain targets such as MIPS require that some types such as vectors are
733
  /// always broken down into scalars in some contexts. This occurs even if the
734
  /// vector type is legal.
735
  virtual unsigned getVectorTypeBreakdownForCallingConv(
736
      LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
737
15.4k
      unsigned &NumIntermediates, MVT &RegisterVT) const {
738
15.4k
    return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
739
15.4k
                                  RegisterVT);
740
15.4k
  }
741
742
  struct IntrinsicInfo {
743
    unsigned     opc = 0;          // target opcode
744
    EVT          memVT;            // memory VT
745
746
    // value representing memory location
747
    PointerUnion<const Value *, const PseudoSourceValue *> ptrVal;
748
749
    int          offset = 0;       // offset off of ptrVal
750
    unsigned     size = 0;         // the size of the memory location
751
                                   // (taken from memVT if zero)
752
    unsigned     align = 1;        // alignment
753
754
    MachineMemOperand::Flags flags = MachineMemOperand::MONone;
755
311k
    IntrinsicInfo() = default;
756
  };
757
758
  /// Given an intrinsic, checks if on the target the intrinsic will need to map
759
  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
760
  /// true and store the intrinsic information into the IntrinsicInfo that was
761
  /// passed to the function.
762
  virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
763
                                  MachineFunction &,
764
3.91k
                                  unsigned /*Intrinsic*/) const {
765
3.91k
    return false;
766
3.91k
  }
767
768
  /// Returns true if the target can instruction select the specified FP
769
  /// immediate natively. If false, the legalizer will materialize the FP
770
  /// immediate as a load from a constant pool.
771
75
  virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
772
75
    return false;
773
75
  }
774
775
  /// Targets can use this to indicate that they only support *some*
776
  /// VECTOR_SHUFFLE operations, those with specific masks.  By default, if a
777
  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
778
  /// legal.
779
1.33k
  virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
780
1.33k
    return true;
781
1.33k
  }
782
783
  /// Returns true if the operation can trap for the value type.
784
  ///
785
  /// VT must be a legal type. By default, we optimistically assume most
786
  /// operations don't trap except for integer divide and remainder.
787
  virtual bool canOpTrap(unsigned Op, EVT VT) const;
788
789
  /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
790
  /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
791
  /// constant pool entry.
792
  virtual bool isVectorClearMaskLegal(ArrayRef<int> /*Mask*/,
793
12.1k
                                      EVT /*VT*/) const {
794
12.1k
    return false;
795
12.1k
  }
796
797
  /// Return how this operation should be treated: either it is legal, needs to
798
  /// be promoted to a larger size, needs to be expanded to some other code
799
  /// sequence, or the target has a custom expander for it.
800
146M
  LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
801
146M
    if (VT.isExtended()) 
return Expand188k
;
802
145M
    // If a target-specific SDNode requires legalization, require the target
803
145M
    // to provide custom legalization for it.
804
145M
    if (Op >= array_lengthof(OpActions[0])) 
return Custom197
;
805
145M
    return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
806
145M
  }
807
808
502
  LegalizeAction getStrictFPOperationAction(unsigned Op, EVT VT) const {
809
502
    unsigned EqOpc;
810
502
    switch (Op) {
811
502
      
default: 0
llvm_unreachable0
("Unexpected FP pseudo-opcode");
812
502
      
case ISD::STRICT_FADD: EqOpc = ISD::FADD; break30
;
813
502
      
case ISD::STRICT_FSUB: EqOpc = ISD::FSUB; break38
;
814
502
      
case ISD::STRICT_FMUL: EqOpc = ISD::FMUL; break30
;
815
502
      
case ISD::STRICT_FDIV: EqOpc = ISD::FDIV; break30
;
816
502
      
case ISD::STRICT_FREM: EqOpc = ISD::FREM; break19
;
817
502
      
case ISD::STRICT_FSQRT: EqOpc = ISD::FSQRT; break30
;
818
502
      
case ISD::STRICT_FPOW: EqOpc = ISD::FPOW; break19
;
819
502
      
case ISD::STRICT_FPOWI: EqOpc = ISD::FPOWI; break19
;
820
502
      
case ISD::STRICT_FMA: EqOpc = ISD::FMA; break36
;
821
502
      
case ISD::STRICT_FSIN: EqOpc = ISD::FSIN; break19
;
822
502
      
case ISD::STRICT_FCOS: EqOpc = ISD::FCOS; break19
;
823
502
      
case ISD::STRICT_FEXP: EqOpc = ISD::FEXP; break19
;
824
502
      
case ISD::STRICT_FEXP2: EqOpc = ISD::FEXP2; break19
;
825
502
      
case ISD::STRICT_FLOG: EqOpc = ISD::FLOG; break19
;
826
502
      
case ISD::STRICT_FLOG10: EqOpc = ISD::FLOG10; break19
;
827
502
      
case ISD::STRICT_FLOG2: EqOpc = ISD::FLOG2; break19
;
828
502
      
case ISD::STRICT_FRINT: EqOpc = ISD::FRINT; break20
;
829
502
      
case ISD::STRICT_FNEARBYINT: EqOpc = ISD::FNEARBYINT; break20
;
830
502
      
case ISD::STRICT_FMAXNUM: EqOpc = ISD::FMAXNUM; break17
;
831
502
      
case ISD::STRICT_FMINNUM: EqOpc = ISD::FMINNUM; break17
;
832
502
      
case ISD::STRICT_FCEIL: EqOpc = ISD::FCEIL; break11
;
833
502
      
case ISD::STRICT_FFLOOR: EqOpc = ISD::FFLOOR; break11
;
834
502
      
case ISD::STRICT_FROUND: EqOpc = ISD::FROUND; break11
;
835
502
      
case ISD::STRICT_FTRUNC: EqOpc = ISD::FTRUNC; break11
;
836
502
    }
837
502
838
502
    auto Action = getOperationAction(EqOpc, VT);
839
502
840
502
    // We don't currently handle Custom or Promote for strict FP pseudo-ops.
841
502
    // For now, we just expand for those cases.
842
502
    if (Action != Legal)
843
306
      Action = Expand;
844
502
845
502
    return Action;
846
502
  }
847
848
  /// Return true if the specified operation is legal on this target or can be
849
  /// made legal with custom lowering. This is used to help guide high-level
850
  /// lowering decisions.
851
31.2M
  bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
852
31.2M
    return (VT == MVT::Other || 
isTypeLegal(VT)31.1M
) &&
853
31.2M
      
(25.5M
getOperationAction(Op, VT) == Legal25.5M
||
854
25.5M
       
getOperationAction(Op, VT) == Custom16.3M
);
855
31.2M
  }
856
857
  /// Return true if the specified operation is legal on this target or can be
858
  /// made legal using promotion. This is used to help guide high-level lowering
859
  /// decisions.
860
677k
  bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
861
677k
    return (VT == MVT::Other || isTypeLegal(VT)) &&
862
677k
      
(677k
getOperationAction(Op, VT) == Legal677k
||
863
677k
       
getOperationAction(Op, VT) == Promote72.1k
);
864
677k
  }
865
866
  /// Return true if the specified operation is legal on this target or can be
867
  /// made legal with custom lowering or using promotion. This is used to help
868
  /// guide high-level lowering decisions.
869
744k
  bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
870
744k
    return (VT == MVT::Other || isTypeLegal(VT)) &&
871
744k
      
(734k
getOperationAction(Op, VT) == Legal734k
||
872
734k
       
getOperationAction(Op, VT) == Custom32.8k
||
873
734k
       
getOperationAction(Op, VT) == Promote19.3k
);
874
744k
  }
875
876
  /// Return true if the operation uses custom lowering, regardless of whether
877
  /// the type is legal or not.
878
1.07k
  bool isOperationCustom(unsigned Op, EVT VT) const {
879
1.07k
    return getOperationAction(Op, VT) == Custom;
880
1.07k
  }
881
882
  /// Return true if lowering to a jump table is allowed.
883
69.6k
  virtual bool areJTsAllowed(const Function *Fn) const {
884
69.6k
    if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
885
2
      return false;
886
69.6k
887
69.6k
    return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
888
69.6k
           
isOperationLegalOrCustom(ISD::BRIND, MVT::Other)20.9k
;
889
69.6k
  }
890
891
  /// Check whether the range [Low,High] fits in a machine word.
892
  bool rangeFitsInWord(const APInt &Low, const APInt &High,
893
85.6k
                       const DataLayout &DL) const {
894
85.6k
    // FIXME: Using the pointer type doesn't seem ideal.
895
85.6k
    uint64_t BW = DL.getIndexSizeInBits(0u);
896
85.6k
    uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
897
85.6k
    return Range <= BW;
898
85.6k
  }
899
900
  /// Return true if lowering to a jump table is suitable for a set of case
901
  /// clusters which may contain \p NumCases cases, \p Range range of values.
902
  /// FIXME: This function check the maximum table size and density, but the
903
  /// minimum size is not checked. It would be nice if the minimum size is
904
  /// also combined within this function. Currently, the minimum size check is
905
  /// performed in findJumpTable() in SelectionDAGBuiler and
906
  /// getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
907
  virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
908
35.3k
                                      uint64_t Range) const {
909
35.3k
    const bool OptForSize = SI->getParent()->getParent()->optForSize();
910
35.3k
    const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
911
35.3k
    const unsigned MaxJumpTableSize =
912
35.3k
        OptForSize || 
getMaximumJumpTableSize() == 035.1k
913
35.3k
            ? UINT_MAX
914
35.3k
            : 
getMaximumJumpTableSize()464
;
915
35.3k
    // Check whether a range of clusters is dense enough for a jump table.
916
35.3k
    if (Range <= MaxJumpTableSize &&
917
35.3k
        
(NumCases * 100 >= Range * MinDensity)35.0k
) {
918
26.1k
      return true;
919
26.1k
    }
920
9.18k
    return false;
921
9.18k
  }
922
923
  /// Return true if lowering to a bit test is suitable for a set of case
924
  /// clusters which contains \p NumDests unique destinations, \p Low and
925
  /// \p High as its lowest and highest case values, and expects \p NumCmps
926
  /// case value comparisons. Check if the number of destinations, comparison
927
  /// metric, and range are all suitable.
928
  bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
929
                             const APInt &Low, const APInt &High,
930
68.1k
                             const DataLayout &DL) const {
931
68.1k
    // FIXME: I don't think NumCmps is the correct metric: a single case and a
932
68.1k
    // range of cases both require only one branch to lower. Just looking at the
933
68.1k
    // number of clusters and destinations should be enough to decide whether to
934
68.1k
    // build bit tests.
935
68.1k
936
68.1k
    // To lower a range with bit tests, the range must fit the bitwidth of a
937
68.1k
    // machine word.
938
68.1k
    if (!rangeFitsInWord(Low, High, DL))
939
9.62k
      return false;
940
58.5k
941
58.5k
    // Decide whether it's profitable to lower this range with bit tests. Each
942
58.5k
    // destination requires a bit test and branch, and there is an overall range
943
58.5k
    // check branch. For a small number of clusters, separate comparisons might
944
58.5k
    // be cheaper, and for many destinations, splitting the range might be
945
58.5k
    // better.
946
58.5k
    return (NumDests == 1 && 
NumCmps >= 313.3k
) ||
(50.8k
NumDests == 250.8k
&&
NumCmps >= 527.7k
) ||
947
58.5k
           
(49.7k
NumDests == 349.7k
&&
NumCmps >= 65.16k
);
948
58.5k
  }
949
950
  /// Return true if the specified operation is illegal on this target or
951
  /// unlikely to be made legal with custom lowering. This is used to help guide
952
  /// high-level lowering decisions.
953
278k
  bool isOperationExpand(unsigned Op, EVT VT) const {
954
278k
    return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
955
278k
  }
956
957
  /// Return true if the specified operation is legal on this target.
958
4.31M
  bool isOperationLegal(unsigned Op, EVT VT) const {
959
4.31M
    return 
(4.31M
VT == MVT::Other4.31M
|| isTypeLegal(VT)) &&
960
4.31M
           
getOperationAction(Op, VT) == Legal4.26M
;
961
4.31M
  }
962
963
  /// Return how this load with extension should be treated: either it is legal,
964
  /// needs to be promoted to a larger size, needs to be expanded to some other
965
  /// code sequence, or the target has a custom expander for it.
966
  LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
967
1.67M
                                  EVT MemVT) const {
968
1.67M
    if (ValVT.isExtended() || 
MemVT.isExtended()1.67M
)
return Expand4.70k
;
969
1.66M
    unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
970
1.66M
    unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
971
1.66M
    assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
972
1.66M
           MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
973
1.66M
    unsigned Shift = 4 * ExtType;
974
1.66M
    return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
975
1.66M
  }
976
977
  /// Return true if the specified load with extension is legal on this target.
978
1.10M
  bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
979
1.10M
    return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
980
1.10M
  }
981
982
  /// Return true if the specified load with extension is legal or custom
983
  /// on this target.
984
3.99k
  bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
985
3.99k
    return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
986
3.99k
           
getLoadExtAction(ExtType, ValVT, MemVT) == Custom3.55k
;
987
3.99k
  }
988
989
  /// Return how this store with truncation should be treated: either it is
990
  /// legal, needs to be promoted to a larger size, needs to be expanded to some
991
  /// other code sequence, or the target has a custom expander for it.
992
644k
  LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
993
644k
    if (ValVT.isExtended() || MemVT.isExtended()) 
return Expand217k
;
994
427k
    unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
995
427k
    unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
996
427k
    assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
997
427k
           "Table isn't big enough!");
998
427k
    return TruncStoreActions[ValI][MemI];
999
427k
  }
1000
1001
  /// Return true if the specified store with truncation is legal on this
1002
  /// target.
1003
324k
  bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
1004
324k
    return isTypeLegal(ValVT) && 
getTruncStoreAction(ValVT, MemVT) == Legal289k
;
1005
324k
  }
1006
1007
  /// Return true if the specified store with truncation has solution on this
1008
  /// target.
1009
2.27k
  bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
1010
2.27k
    return isTypeLegal(ValVT) &&
1011
2.27k
      (getTruncStoreAction(ValVT, MemVT) == Legal ||
1012
2.27k
       
getTruncStoreAction(ValVT, MemVT) == Custom1.05k
);
1013
2.27k
  }
1014
1015
  /// Return how the indexed load should be treated: either it is legal, needs
1016
  /// to be promoted to a larger size, needs to be expanded to some other code
1017
  /// sequence, or the target has a custom expander for it.
1018
  LegalizeAction
1019
6.92M
  getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
1020
6.92M
    assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1021
6.92M
           "Table isn't big enough!");
1022
6.92M
    unsigned Ty = (unsigned)VT.SimpleTy;
1023
6.92M
    return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
1024
6.92M
  }
1025
1026
  /// Return true if the specified indexed load is legal on this target.
1027
4.39M
  bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
1028
4.39M
    return VT.isSimple() &&
1029
4.39M
      (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
1030
4.39M
       
getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom2.53M
);
1031
4.39M
  }
1032
1033
  /// Return how the indexed store should be treated: either it is legal, needs
1034
  /// to be promoted to a larger size, needs to be expanded to some other code
1035
  /// sequence, or the target has a custom expander for it.
1036
  LegalizeAction
1037
7.05M
  getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
1038
7.05M
    assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1039
7.05M
           "Table isn't big enough!");
1040
7.05M
    unsigned Ty = (unsigned)VT.SimpleTy;
1041
7.05M
    return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
1042
7.05M
  }
1043
1044
  /// Return true if the specified indexed load is legal on this target.
1045
4.44M
  bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
1046
4.44M
    return VT.isSimple() &&
1047
4.44M
      (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
1048
4.44M
       
getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom2.61M
);
1049
4.44M
  }
1050
1051
  /// Return how the condition code should be treated: either it is legal, needs
1052
  /// to be expanded to some other code sequence, or the target has a custom
1053
  /// expander for it.
1054
  LegalizeAction
1055
1.01M
  getCondCodeAction(ISD::CondCode CC, MVT VT) const {
1056
1.01M
    assert((unsigned)CC < array_lengthof(CondCodeActions) &&
1057
1.01M
           ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
1058
1.01M
           "Table isn't big enough!");
1059
1.01M
    // See setCondCodeAction for how this is encoded.
1060
1.01M
    uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1061
1.01M
    uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
1062
1.01M
    LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
1063
1.01M
    assert(Action != Promote && "Can't promote condition code!");
1064
1.01M
    return Action;
1065
1.01M
  }
1066
1067
  /// Return true if the specified condition code is legal on this target.
1068
31.6k
  bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
1069
31.6k
    return getCondCodeAction(CC, VT) == Legal;
1070
31.6k
  }
1071
1072
  /// Return true if the specified condition code is legal or custom on this
1073
  /// target.
1074
4.09k
  bool isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) const {
1075
4.09k
    return getCondCodeAction(CC, VT) == Legal ||
1076
4.09k
           
getCondCodeAction(CC, VT) == Custom1.45k
;
1077
4.09k
  }
1078
1079
  /// If the action for this operation is to promote, this method returns the
1080
  /// ValueType to promote to.
1081
221k
  MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
1082
221k
    assert(getOperationAction(Op, VT) == Promote &&
1083
221k
           "This operation isn't promoted!");
1084
221k
1085
221k
    // See if this has an explicit type specified.
1086
221k
    std::map<std::pair<unsigned, MVT::SimpleValueType>,
1087
221k
             MVT::SimpleValueType>::const_iterator PTTI =
1088
221k
      PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1089
221k
    if (PTTI != PromoteToType.end()) 
return PTTI->second220k
;
1090
1.32k
1091
1.32k
    assert((VT.isInteger() || VT.isFloatingPoint()) &&
1092
1.32k
           "Cannot autopromote this type, add it with AddPromotedToType.");
1093
1.32k
1094
1.32k
    MVT NVT = VT;
1095
1.73k
    do {
1096
1.73k
      NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1097
1.73k
      assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1098
1.73k
             "Didn't find type to promote to!");
1099
1.73k
    } while (!isTypeLegal(NVT) ||
1100
1.73k
              
getOperationAction(Op, NVT) == Promote1.47k
);
1101
1.32k
    return NVT;
1102
1.32k
  }
1103
1104
  /// Return the EVT corresponding to this LLVM type.  This is fixed by the LLVM
1105
  /// operations except for the pointer size.  If AllowUnknown is true, this
1106
  /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1107
  /// otherwise it will assert.
1108
  EVT getValueType(const DataLayout &DL, Type *Ty,
1109
74.4M
                   bool AllowUnknown = false) const {
1110
74.4M
    // Lower scalar pointers to native pointer types.
1111
74.4M
    if (PointerType *PTy = dyn_cast<PointerType>(Ty))
1112
24.5M
      return getPointerTy(DL, PTy->getAddressSpace());
1113
49.8M
1114
49.8M
    if (Ty->isVectorTy()) {
1115
6.75M
      VectorType *VTy = cast<VectorType>(Ty);
1116
6.75M
      Type *Elm = VTy->getElementType();
1117
6.75M
      // Lower vectors of pointers to native pointer types.
1118
6.75M
      if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
1119
359k
        EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
1120
359k
        Elm = PointerTy.getTypeForEVT(Ty->getContext());
1121
359k
      }
1122
6.75M
1123
6.75M
      return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1124
6.75M
                       VTy->getNumElements());
1125
6.75M
    }
1126
43.1M
    return EVT::getEVT(Ty, AllowUnknown);
1127
43.1M
  }
1128
1129
  /// Return the MVT corresponding to this LLVM type. See getValueType.
1130
  MVT getSimpleValueType(const DataLayout &DL, Type *Ty,
1131
22.6k
                         bool AllowUnknown = false) const {
1132
22.6k
    return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1133
22.6k
  }
1134
1135
  /// Return the desired alignment for ByVal or InAlloca aggregate function
1136
  /// arguments in the caller parameter area.  This is the actual alignment, not
1137
  /// its logarithm.
1138
  virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1139
1140
  /// Return the type of registers that this ValueType will eventually require.
1141
4.20M
  MVT getRegisterType(MVT VT) const {
1142
4.20M
    assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
1143
4.20M
    return RegisterTypeForVT[VT.SimpleTy];
1144
4.20M
  }
1145
1146
  /// Return the type of registers that this ValueType will eventually require.
1147
13.3M
  MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1148
13.3M
    if (VT.isSimple()) {
1149
13.3M
      assert((unsigned)VT.getSimpleVT().SimpleTy <
1150
13.3M
                array_lengthof(RegisterTypeForVT));
1151
13.3M
      return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1152
13.3M
    }
1153
17.6k
    if (VT.isVector()) {
1154
3.62k
      EVT VT1;
1155
3.62k
      MVT RegisterVT;
1156
3.62k
      unsigned NumIntermediates;
1157
3.62k
      (void)getVectorTypeBreakdown(Context, VT, VT1,
1158
3.62k
                                   NumIntermediates, RegisterVT);
1159
3.62k
      return RegisterVT;
1160
3.62k
    }
1161
13.9k
    if (VT.isInteger()) {
1162
13.9k
      return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1163
13.9k
    }
1164
0
    llvm_unreachable("Unsupported extended type!");
1165
0
  }
1166
1167
  /// Return the number of registers that this ValueType will eventually
1168
  /// require.
1169
  ///
1170
  /// This is one for any types promoted to live in larger registers, but may be
1171
  /// more than one for types (like i64) that are split into pieces.  For types
1172
  /// like i140, which are first promoted then expanded, it is the number of
1173
  /// registers needed to hold all the bits of the original type.  For an i140
1174
  /// on a 32 bit machine this means 5 registers.
1175
15.1M
  unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1176
15.1M
    if (VT.isSimple()) {
1177
15.1M
      assert((unsigned)VT.getSimpleVT().SimpleTy <
1178
15.1M
                array_lengthof(NumRegistersForVT));
1179
15.1M
      return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1180
15.1M
    }
1181
9.68k
    if (VT.isVector()) {
1182
3.73k
      EVT VT1;
1183
3.73k
      MVT VT2;
1184
3.73k
      unsigned NumIntermediates;
1185
3.73k
      return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1186
3.73k
    }
1187
5.95k
    if (VT.isInteger()) {
1188
5.95k
      unsigned BitWidth = VT.getSizeInBits();
1189
5.95k
      unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1190
5.95k
      return (BitWidth + RegWidth - 1) / RegWidth;
1191
5.95k
    }
1192
0
    llvm_unreachable("Unsupported extended type!");
1193
0
  }
1194
1195
  /// Certain combinations of ABIs, Targets and features require that types
1196
  /// are legal for some operations and not for other operations.
1197
  /// For MIPS all vector types must be passed through the integer register set.
1198
  virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context,
1199
5.71M
                                            CallingConv::ID CC, EVT VT) const {
1200
5.71M
    return getRegisterType(Context, VT);
1201
5.71M
  }
1202
1203
  /// Certain targets require unusual breakdowns of certain types. For MIPS,
1204
  /// this occurs when a vector type is used, as vector are passed through the
1205
  /// integer register set.
1206
  virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1207
                                                 CallingConv::ID CC,
1208
5.71M
                                                 EVT VT) const {
1209
5.71M
    return getNumRegisters(Context, VT);
1210
5.71M
  }
1211
1212
  /// Certain targets have context senstive alignment requirements, where one
1213
  /// type has the alignment requirement of another type.
1214
  virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
1215
2.59M
                                                 DataLayout DL) const {
1216
2.59M
    return DL.getABITypeAlignment(ArgTy);
1217
2.59M
  }
1218
1219
  /// If true, then instruction selection should seek to shrink the FP constant
1220
  /// of the specified type to a smaller type in order to save space and / or
1221
  /// reduce runtime.
1222
292
  virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1223
1224
  /// Return true if it is profitable to reduce a load to a smaller type.
1225
  /// Example: (i16 (trunc (i32 (load x))) -> i16 load x
1226
  virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
1227
28.0k
                                     EVT NewVT) const {
1228
28.0k
    // By default, assume that it is cheaper to extract a subvector from a wide
1229
28.0k
    // vector load rather than creating multiple narrow vector loads.
1230
28.0k
    if (NewVT.isVector() && 
!Load->hasOneUse()9.49k
)
1231
9.41k
      return false;
1232
18.6k
1233
18.6k
    return true;
1234
18.6k
  }
1235
1236
  /// When splitting a value of the specified type into parts, does the Lo
1237
  /// or Hi part come first?  This usually follows the endianness, except
1238
  /// for ppcf128, where the Hi part always comes first.
1239
151k
  bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1240
151k
    return DL.isBigEndian() || 
VT == MVT::ppcf128146k
;
1241
151k
  }
1242
1243
  /// If true, the target has custom DAG combine transformations that it can
1244
  /// perform for the specified node.
1245
110M
  bool hasTargetDAGCombine(ISD::NodeType NT) const {
1246
110M
    assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1247
110M
    return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1248
110M
  }
1249
1250
16.3M
  unsigned getGatherAllAliasesMaxDepth() const {
1251
16.3M
    return GatherAllAliasesMaxDepth;
1252
16.3M
  }
1253
1254
  /// Returns the size of the platform's va_list object.
1255
0
  virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1256
0
    return getPointerTy(DL).getSizeInBits();
1257
0
  }
1258
1259
  /// Get maximum # of store operations permitted for llvm.memset
1260
  ///
1261
  /// This function returns the maximum number of store operations permitted
1262
  /// to replace a call to llvm.memset. The value is set by the target at the
1263
  /// performance threshold for such a replacement. If OptSize is true,
1264
  /// return the limit for functions that have OptSize attribute.
1265
14.6k
  unsigned getMaxStoresPerMemset(bool OptSize) const {
1266
14.6k
    return OptSize ? 
MaxStoresPerMemsetOptSize21
:
MaxStoresPerMemset14.6k
;
1267
14.6k
  }
1268
1269
  /// Get maximum # of store operations permitted for llvm.memcpy
1270
  ///
1271
  /// This function returns the maximum number of store operations permitted
1272
  /// to replace a call to llvm.memcpy. The value is set by the target at the
1273
  /// performance threshold for such a replacement. If OptSize is true,
1274
  /// return the limit for functions that have OptSize attribute.
1275
16.1k
  unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1276
16.1k
    return OptSize ? 
MaxStoresPerMemcpyOptSize46
:
MaxStoresPerMemcpy16.1k
;
1277
16.1k
  }
1278
1279
  /// \brief Get maximum # of store operations to be glued together
1280
  ///
1281
  /// This function returns the maximum number of store operations permitted
1282
  /// to glue together during lowering of llvm.memcpy. The value is set by
1283
  //  the target at the performance threshold for such a replacement.
1284
14.3k
  virtual unsigned getMaxGluedStoresPerMemcpy() const {
1285
14.3k
    return MaxGluedStoresPerMemcpy;
1286
14.3k
  }
1287
1288
  /// Get maximum # of load operations permitted for memcmp
1289
  ///
1290
  /// This function returns the maximum number of load operations permitted
1291
  /// to replace a call to memcmp. The value is set by the target at the
1292
  /// performance threshold for such a replacement. If OptSize is true,
1293
  /// return the limit for functions that have OptSize attribute.
1294
433
  unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1295
433
    return OptSize ? 
MaxLoadsPerMemcmpOptSize108
:
MaxLoadsPerMemcmp325
;
1296
433
  }
1297
1298
  /// For memcmp expansion when the memcmp result is only compared equal or
1299
  /// not-equal to 0, allow up to this number of load pairs per block. As an
1300
  /// example, this may allow 'memcmp(a, b, 3) == 0' in a single block:
1301
  ///   a0 = load2bytes &a[0]
1302
  ///   b0 = load2bytes &b[0]
1303
  ///   a2 = load1byte  &a[2]
1304
  ///   b2 = load1byte  &b[2]
1305
  ///   r  = cmp eq (a0 ^ b0 | a2 ^ b2), 0
1306
22
  virtual unsigned getMemcmpEqZeroLoadsPerBlock() const {
1307
22
    return 1;
1308
22
  }
1309
1310
  /// Get maximum # of store operations permitted for llvm.memmove
1311
  ///
1312
  /// This function returns the maximum number of store operations permitted
1313
  /// to replace a call to llvm.memmove. The value is set by the target at the
1314
  /// performance threshold for such a replacement. If OptSize is true,
1315
  /// return the limit for functions that have OptSize attribute.
1316
103
  unsigned getMaxStoresPerMemmove(bool OptSize) const {
1317
103
    return OptSize ? 
MaxStoresPerMemmoveOptSize0
: MaxStoresPerMemmove;
1318
103
  }
1319
1320
  /// Determine if the target supports unaligned memory accesses.
1321
  ///
1322
  /// This function returns true if the target allows unaligned memory accesses
1323
  /// of the specified type in the given address space. If true, it also returns
1324
  /// whether the unaligned memory access is "fast" in the last argument by
1325
  /// reference. This is used, for example, in situations where an array
1326
  /// copy/move/set is converted to a sequence of store operations. Its use
1327
  /// helps to ensure that such replacements don't generate code that causes an
1328
  /// alignment error (trap) on the target machine.
1329
  virtual bool allowsMisalignedMemoryAccesses(EVT,
1330
                                              unsigned AddrSpace = 0,
1331
                                              unsigned Align = 1,
1332
1.17k
                                              bool * /*Fast*/ = nullptr) const {
1333
1.17k
    return false;
1334
1.17k
  }
1335
1336
  /// Return true if the target supports a memory access of this type for the
1337
  /// given address space and alignment. If the access is allowed, the optional
1338
  /// final parameter returns if the access is also fast (as defined by the
1339
  /// target).
1340
  bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1341
                          unsigned AddrSpace = 0, unsigned Alignment = 1,
1342
                          bool *Fast = nullptr) const;
1343
1344
  /// Returns the target specific optimal type for load and store operations as
1345
  /// a result of memset, memcpy, and memmove lowering.
1346
  ///
1347
  /// If DstAlign is zero that means it's safe to destination alignment can
1348
  /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1349
  /// a need to check it against alignment requirement, probably because the
1350
  /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1351
  /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1352
  /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1353
  /// does not need to be loaded.  It returns EVT::Other if the type should be
1354
  /// determined using generic target-independent logic.
1355
  virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
1356
                                  unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
1357
                                  bool /*IsMemset*/,
1358
                                  bool /*ZeroMemset*/,
1359
                                  bool /*MemcpyStrSrc*/,
1360
144
                                  MachineFunction &/*MF*/) const {
1361
144
    return MVT::Other;
1362
144
  }
1363
1364
  /// Returns true if it's safe to use load / store of the specified type to
1365
  /// expand memcpy / memset inline.
1366
  ///
1367
  /// This is mostly true for all types except for some special cases. For
1368
  /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1369
  /// fstpl which also does type conversion. Note the specified type doesn't
1370
  /// have to be legal as the hook is used before type legalization.
1371
9.18k
  virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1372
1373
  /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1374
0
  bool usesUnderscoreSetJmp() const {
1375
0
    return UseUnderscoreSetJmp;
1376
0
  }
1377
1378
  /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1379
0
  bool usesUnderscoreLongJmp() const {
1380
0
    return UseUnderscoreLongJmp;
1381
0
  }
1382
1383
  /// Return lower limit for number of blocks in a jump table.
1384
  virtual unsigned getMinimumJumpTableEntries() const;
1385
1386
  /// Return lower limit of the density in a jump table.
1387
  unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1388
1389
  /// Return upper limit for number of entries in a jump table.
1390
  /// Zero if no limit.
1391
  unsigned getMaximumJumpTableSize() const;
1392
1393
525
  virtual bool isJumpTableRelative() const {
1394
525
    return TM.isPositionIndependent();
1395
525
  }
1396
1397
  /// If a physical register, this specifies the register that
1398
  /// llvm.savestack/llvm.restorestack should save and restore.
1399
24.6M
  unsigned getStackPointerRegisterToSaveRestore() const {
1400
24.6M
    return StackPointerRegisterToSaveRestore;
1401
24.6M
  }
1402
1403
  /// If a physical register, this returns the register that receives the
1404
  /// exception address on entry to an EH pad.
1405
  virtual unsigned
1406
0
  getExceptionPointerRegister(const Constant *PersonalityFn) const {
1407
0
    // 0 is guaranteed to be the NoRegister value on all targets
1408
0
    return 0;
1409
0
  }
1410
1411
  /// If a physical register, this returns the register that receives the
1412
  /// exception typeid on entry to a landing pad.
1413
  virtual unsigned
1414
0
  getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1415
0
    // 0 is guaranteed to be the NoRegister value on all targets
1416
0
    return 0;
1417
0
  }
1418
1419
0
  virtual bool needsFixedCatchObjects() const {
1420
0
    report_fatal_error("Funclet EH is not implemented for this target");
1421
0
  }
1422
1423
  /// Returns the target's jmp_buf size in bytes (if never set, the default is
1424
  /// 200)
1425
0
  unsigned getJumpBufSize() const {
1426
0
    return JumpBufSize;
1427
0
  }
1428
1429
  /// Returns the target's jmp_buf alignment in bytes (if never set, the default
1430
  /// is 0)
1431
0
  unsigned getJumpBufAlignment() const {
1432
0
    return JumpBufAlignment;
1433
0
  }
1434
1435
  /// Return the minimum stack alignment of an argument.
1436
174
  unsigned getMinStackArgumentAlignment() const {
1437
174
    return MinStackArgumentAlignment;
1438
174
  }
1439
1440
  /// Return the minimum function alignment.
1441
565k
  unsigned getMinFunctionAlignment() const {
1442
565k
    return MinFunctionAlignment;
1443
565k
  }
1444
1445
  /// Return the preferred function alignment.
1446
556k
  unsigned getPrefFunctionAlignment() const {
1447
556k
    return PrefFunctionAlignment;
1448
556k
  }
1449
1450
  /// Return the preferred loop alignment.
1451
702k
  virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1452
702k
    return PrefLoopAlignment;
1453
702k
  }
1454
1455
  /// Should loops be aligned even when the function is marked OptSize (but not
1456
  /// MinSize).
1457
147
  virtual bool alignLoopsWithOptSize() const {
1458
147
    return false;
1459
147
  }
1460
1461
  /// If the target has a standard location for the stack protector guard,
1462
  /// returns the address of that location. Otherwise, returns nullptr.
1463
  /// DEPRECATED: please override useLoadStackGuardNode and customize
1464
  ///             LOAD_STACK_GUARD, or customize \@llvm.stackguard().
1465
  virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1466
1467
  /// Inserts necessary declarations for SSP (stack protection) purpose.
1468
  /// Should be used only when getIRStackGuard returns nullptr.
1469
  virtual void insertSSPDeclarations(Module &M) const;
1470
1471
  /// Return the variable that's previously inserted by insertSSPDeclarations,
1472
  /// if any, otherwise return nullptr. Should be used only when
1473
  /// getIRStackGuard returns nullptr.
1474
  virtual Value *getSDagStackGuard(const Module &M) const;
1475
1476
  /// If this function returns true, stack protection checks should XOR the
1477
  /// frame pointer (or whichever pointer is used to address locals) into the
1478
  /// stack guard value before checking it. getIRStackGuard must return nullptr
1479
  /// if this returns true.
1480
6.16k
  virtual bool useStackGuardXorFP() const { return false; }
1481
1482
  /// If the target has a standard stack protection check function that
1483
  /// performs validation and error handling, returns the function. Otherwise,
1484
  /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1485
  /// Should be used only when getIRStackGuard returns nullptr.
1486
  virtual Value *getSSPStackGuardCheck(const Module &M) const;
1487
1488
protected:
1489
  Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1490
                                            bool UseTLS) const;
1491
1492
public:
1493
  /// Returns the target-specific address of the unsafe stack pointer.
1494
  virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1495
1496
  /// Returns the name of the symbol used to emit stack probes or the empty
1497
  /// string if not applicable.
1498
0
  virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const {
1499
0
    return "";
1500
0
  }
1501
1502
  /// Returns true if a cast between SrcAS and DestAS is a noop.
1503
468
  virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1504
468
    return false;
1505
468
  }
1506
1507
  /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1508
  /// are happy to sink it into basic blocks.
1509
201
  virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1510
201
    return isNoopAddrSpaceCast(SrcAS, DestAS);
1511
201
  }
1512
1513
  /// Return true if the pointer arguments to CI should be aligned by aligning
1514
  /// the object whose address is being passed. If so then MinSize is set to the
1515
  /// minimum size the object must be to be aligned and PrefAlign is set to the
1516
  /// preferred alignment.
1517
  virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1518
4.26M
                                      unsigned & /*PrefAlign*/) const {
1519
4.26M
    return false;
1520
4.26M
  }
1521
1522
  //===--------------------------------------------------------------------===//
1523
  /// \name Helpers for TargetTransformInfo implementations
1524
  /// @{
1525
1526
  /// Get the ISD node that corresponds to the Instruction class opcode.
1527
  int InstructionOpcodeToISD(unsigned Opcode) const;
1528
1529
  /// Estimate the cost of type-legalization and the legalized type.
1530
  std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1531
                                              Type *Ty) const;
1532
1533
  /// @}
1534
1535
  //===--------------------------------------------------------------------===//
1536
  /// \name Helpers for atomic expansion.
1537
  /// @{
1538
1539
  /// Returns the maximum atomic operation size (in bits) supported by
1540
  /// the backend. Atomic operations greater than this size (as well
1541
  /// as ones that are not naturally aligned), will be expanded by
1542
  /// AtomicExpandPass into an __atomic_* library call.
1543
44.6k
  unsigned getMaxAtomicSizeInBitsSupported() const {
1544
44.6k
    return MaxAtomicSizeInBitsSupported;
1545
44.6k
  }
1546
1547
  /// Returns the size of the smallest cmpxchg or ll/sc instruction
1548
  /// the backend supports.  Any smaller operations are widened in
1549
  /// AtomicExpandPass.
1550
  ///
1551
  /// Note that *unlike* operations above the maximum size, atomic ops
1552
  /// are still natively supported below the minimum; they just
1553
  /// require a more complex expansion.
1554
59.2k
  unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1555
1556
  /// Whether the target supports unaligned atomic operations.
1557
1.14k
  bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
1558
1559
  /// Whether AtomicExpandPass should automatically insert fences and reduce
1560
  /// ordering for this atomic. This should be true for most architectures with
1561
  /// weak memory ordering. Defaults to false.
1562
45.9k
  virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1563
45.9k
    return false;
1564
45.9k
  }
1565
1566
  /// Perform a load-linked operation on Addr, returning a "Value *" with the
1567
  /// corresponding pointee type. This may entail some non-trivial operations to
1568
  /// truncate or reconstruct types that will be illegal in the backend. See
1569
  /// ARMISelLowering for an example implementation.
1570
  virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1571
0
                                AtomicOrdering Ord) const {
1572
0
    llvm_unreachable("Load linked unimplemented on this target");
1573
0
  }
1574
1575
  /// Perform a store-conditional operation to Addr. Return the status of the
1576
  /// store. This should be 0 if the store succeeded, non-zero otherwise.
1577
  virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1578
0
                                      Value *Addr, AtomicOrdering Ord) const {
1579
0
    llvm_unreachable("Store conditional unimplemented on this target");
1580
0
  }
1581
1582
  /// Perform a masked atomicrmw using a target-specific intrinsic. This
1583
  /// represents the core LL/SC loop which will be lowered at a late stage by
1584
  /// the backend.
1585
  virtual Value *emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder,
1586
                                              AtomicRMWInst *AI,
1587
                                              Value *AlignedAddr, Value *Incr,
1588
                                              Value *Mask, Value *ShiftAmt,
1589
0
                                              AtomicOrdering Ord) const {
1590
0
    llvm_unreachable("Masked atomicrmw expansion unimplemented on this target");
1591
0
  }
1592
1593
  /// Perform a masked cmpxchg using a target-specific intrinsic. This
1594
  /// represents the core LL/SC loop which will be lowered at a late stage by
1595
  /// the backend.
1596
  virtual Value *emitMaskedAtomicCmpXchgIntrinsic(
1597
      IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
1598
0
      Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
1599
0
    llvm_unreachable("Masked cmpxchg expansion unimplemented on this target");
1600
0
  }
1601
1602
  /// Inserts in the IR a target-specific intrinsic specifying a fence.
1603
  /// It is called by AtomicExpandPass before expanding an
1604
  ///   AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1605
  ///   if shouldInsertFencesForAtomic returns true.
1606
  ///
1607
  /// Inst is the original atomic instruction, prior to other expansions that
1608
  /// may be performed.
1609
  ///
1610
  /// This function should either return a nullptr, or a pointer to an IR-level
1611
  ///   Instruction*. Even complex fence sequences can be represented by a
1612
  ///   single Instruction* through an intrinsic to be lowered later.
1613
  /// Backends should override this method to produce target-specific intrinsic
1614
  ///   for their fences.
1615
  /// FIXME: Please note that the default implementation here in terms of
1616
  ///   IR-level fences exists for historical/compatibility reasons and is
1617
  ///   *unsound* ! Fences cannot, in general, be used to restore sequential
1618
  ///   consistency. For example, consider the following example:
1619
  /// atomic<int> x = y = 0;
1620
  /// int r1, r2, r3, r4;
1621
  /// Thread 0:
1622
  ///   x.store(1);
1623
  /// Thread 1:
1624
  ///   y.store(1);
1625
  /// Thread 2:
1626
  ///   r1 = x.load();
1627
  ///   r2 = y.load();
1628
  /// Thread 3:
1629
  ///   r3 = y.load();
1630
  ///   r4 = x.load();
1631
  ///  r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1632
  ///  seq_cst. But if they are lowered to monotonic accesses, no amount of
1633
  ///  IR-level fences can prevent it.
1634
  /// @{
1635
  virtual Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
1636
127
                                        AtomicOrdering Ord) const {
1637
127
    if (isReleaseOrStronger(Ord) && 
Inst->hasAtomicStore()97
)
1638
94
      return Builder.CreateFence(Ord);
1639
33
    else
1640
33
      return nullptr;
1641
127
  }
1642
1643
  virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
1644
                                         Instruction *Inst,
1645
127
                                         AtomicOrdering Ord) const {
1646
127
    if (isAcquireOrStronger(Ord))
1647
104
      return Builder.CreateFence(Ord);
1648
23
    else
1649
23
      return nullptr;
1650
127
  }
1651
  /// @}
1652
1653
  // Emits code that executes when the comparison result in the ll/sc
1654
  // expansion of a cmpxchg instruction is such that the store-conditional will
1655
  // not execute.  This makes it possible to balance out the load-linked with
1656
  // a dedicated instruction, if desired.
1657
  // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1658
  // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1659
3
  virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1660
1661
  /// Returns true if the given (atomic) store should be expanded by the
1662
  /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1663
271
  virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1664
271
    return false;
1665
271
  }
1666
1667
  /// Returns true if arguments should be sign-extended in lib calls.
1668
45.4k
  virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1669
45.4k
    return IsSigned;
1670
45.4k
  }
1671
1672
  /// Returns how the given (atomic) load should be expanded by the
1673
  /// IR-level AtomicExpand pass.
1674
301
  virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const {
1675
301
    return AtomicExpansionKind::None;
1676
301
  }
1677
1678
  /// Returns how the given atomic cmpxchg should be expanded by the IR-level
1679
  /// AtomicExpand pass.
1680
  virtual AtomicExpansionKind
1681
1.82k
  shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
1682
1.82k
    return AtomicExpansionKind::None;
1683
1.82k
  }
1684
1685
  /// Returns how the IR-level AtomicExpand pass should expand the given
1686
  /// AtomicRMW, if at all. Default is to never expand.
1687
786
  virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
1688
786
    return AtomicExpansionKind::None;
1689
786
  }
1690
1691
  /// On some platforms, an AtomicRMW that never actually modifies the value
1692
  /// (such as fetch_add of 0) can be turned into a fence followed by an
1693
  /// atomic load. This may sound useless, but it makes it possible for the
1694
  /// processor to keep the cacheline shared, dramatically improving
1695
  /// performance. And such idempotent RMWs are useful for implementing some
1696
  /// kinds of locks, see for example (justification + benchmarks):
1697
  /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1698
  /// This method tries doing that transformation, returning the atomic load if
1699
  /// it succeeds, and nullptr otherwise.
1700
  /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1701
  /// another round of expansion.
1702
  virtual LoadInst *
1703
0
  lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1704
0
    return nullptr;
1705
0
  }
1706
1707
  /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1708
  /// SIGN_EXTEND, or ANY_EXTEND).
1709
2.15k
  virtual ISD::NodeType getExtendForAtomicOps() const {
1710
2.15k
    return ISD::ZERO_EXTEND;
1711
2.15k
  }
1712
1713
  /// @}
1714
1715
  /// Returns true if we should normalize
1716
  /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1717
  /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1718
  /// that it saves us from materializing N0 and N1 in an integer register.
1719
  /// Targets that are able to perform and/or on flags should return false here.
1720
  virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
1721
47.7k
                                               EVT VT) const {
1722
47.7k
    // If a target has multiple condition registers, then it likely has logical
1723
47.7k
    // operations on those registers.
1724
47.7k
    if (hasMultipleConditionRegisters())
1725
14.7k
      return false;
1726
33.0k
    // Only do the transform if the value won't be split into multiple
1727
33.0k
    // registers.
1728
33.0k
    LegalizeTypeAction Action = getTypeAction(Context, VT);
1729
33.0k
    return Action != TypeExpandInteger && 
Action != TypeExpandFloat32.3k
&&
1730
33.0k
      
Action != TypeSplitVector32.3k
;
1731
33.0k
  }
1732
1733
  /// Return true if a select of constants (select Cond, C1, C2) should be
1734
  /// transformed into simple math ops with the condition value. For example:
1735
  /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1736
8.64k
  virtual bool convertSelectOfConstantsToMath(EVT VT) const {
1737
8.64k
    return false;
1738
8.64k
  }
1739
1740
  /// Return true if it is profitable to transform an integer
1741
  /// multiplication-by-constant into simpler operations like shifts and adds.
1742
  /// This may be true if the target does not directly support the
1743
  /// multiplication operation for the specified type or the sequence of simpler
1744
  /// ops is faster than the multiply.
1745
107k
  virtual bool decomposeMulByConstant(EVT VT, SDValue C) const {
1746
107k
    return false;
1747
107k
  }
1748
1749
  /// Return true if it is more correct/profitable to use strict FP_TO_INT
1750
  /// conversion operations - canonicalizing the FP source value instead of
1751
  /// converting all cases and then selecting based on value.
1752
  /// This may be true if the target throws exceptions for out of bounds
1753
  /// conversions or has fast FP CMOV.
1754
  virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT,
1755
49
                                        bool IsSigned) const {
1756
49
    return false;
1757
49
  }
1758
1759
  //===--------------------------------------------------------------------===//
1760
  // TargetLowering Configuration Methods - These methods should be invoked by
1761
  // the derived class constructor to configure this object for the target.
1762
  //
1763
protected:
1764
  /// Specify how the target extends the result of integer and floating point
1765
  /// boolean values from i1 to a wider type.  See getBooleanContents.
1766
51.3k
  void setBooleanContents(BooleanContent Ty) {
1767
51.3k
    BooleanContents = Ty;
1768
51.3k
    BooleanFloatContents = Ty;
1769
51.3k
  }
1770
1771
  /// Specify how the target extends the result of integer and floating point
1772
  /// boolean values from i1 to a wider type.  See getBooleanContents.
1773
1.34k
  void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1774
1.34k
    BooleanContents = IntTy;
1775
1.34k
    BooleanFloatContents = FloatTy;
1776
1.34k
  }
1777
1778
  /// Specify how the target extends the result of a vector boolean value from a
1779
  /// vector of i1 to a wider type.  See getBooleanContents.
1780
50.6k
  void setBooleanVectorContents(BooleanContent Ty) {
1781
50.6k
    BooleanVectorContents = Ty;
1782
50.6k
  }
1783
1784
  /// Specify the target scheduling preference.
1785
43.3k
  void setSchedulingPreference(Sched::Preference Pref) {
1786
43.3k
    SchedPreferenceInfo = Pref;
1787
43.3k
  }
1788
1789
  /// Indicate whether this target prefers to use _setjmp to implement
1790
  /// llvm.setjmp or the version without _.  Defaults to false.
1791
16.7k
  void setUseUnderscoreSetJmp(bool Val) {
1792
16.7k
    UseUnderscoreSetJmp = Val;
1793
16.7k
  }
1794
1795
  /// Indicate whether this target prefers to use _longjmp to implement
1796
  /// llvm.longjmp or the version without _.  Defaults to false.
1797
16.7k
  void setUseUnderscoreLongJmp(bool Val) {
1798
16.7k
    UseUnderscoreLongJmp = Val;
1799
16.7k
  }
1800
1801
  /// Indicate the minimum number of blocks to generate jump tables.
1802
  void setMinimumJumpTableEntries(unsigned Val);
1803
1804
  /// Indicate the maximum number of entries in jump tables.
1805
  /// Set to zero to generate unlimited jump tables.
1806
  void setMaximumJumpTableSize(unsigned);
1807
1808
  /// If set to a physical register, this specifies the register that
1809
  /// llvm.savestack/llvm.restorestack should save and restore.
1810
47.8k
  void setStackPointerRegisterToSaveRestore(unsigned R) {
1811
47.8k
    StackPointerRegisterToSaveRestore = R;
1812
47.8k
  }
1813
1814
  /// Tells the code generator that the target has multiple (allocatable)
1815
  /// condition registers that can be used to store the results of comparisons
1816
  /// for use by selects and conditional branches. With multiple condition
1817
  /// registers, the code generator will not aggressively sink comparisons into
1818
  /// the blocks of their users.
1819
4.39k
  void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1820
4.39k
    HasMultipleConditionRegisters = hasManyRegs;
1821
4.39k
  }
1822
1823
  /// Tells the code generator that the target has BitExtract instructions.
1824
  /// The code generator will aggressively sink "shift"s into the blocks of
1825
  /// their users if the users will generate "and" instructions which can be
1826
  /// combined with "shift" to BitExtract instructions.
1827
12.0k
  void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1828
12.0k
    HasExtractBitsInsn = hasExtractInsn;
1829
12.0k
  }
1830
1831
  /// Tells the code generator not to expand logic operations on comparison
1832
  /// predicates into separate sequences that increase the amount of flow
1833
  /// control.
1834
  void setJumpIsExpensive(bool isExpensive = true);
1835
1836
  /// Tells the code generator that this target supports floating point
1837
  /// exceptions and cares about preserving floating point exception behavior.
1838
2.92k
  void setHasFloatingPointExceptions(bool FPExceptions = true) {
1839
2.92k
    HasFloatingPointExceptions = FPExceptions;
1840
2.92k
  }
1841
1842
  /// Tells the code generator which bitwidths to bypass.
1843
2.27k
  void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1844
2.27k
    BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1845
2.27k
  }
1846
1847
  /// Add the specified register class as an available regclass for the
1848
  /// specified value type. This indicates the selector can handle values of
1849
  /// that class natively.
1850
639k
  void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1851
639k
    assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1852
639k
    RegClassForVT[VT.SimpleTy] = RC;
1853
639k
  }
1854
1855
  /// Return the largest legal super-reg register class of the register class
1856
  /// for the specified type and its associated "cost".
1857
  virtual std::pair<const TargetRegisterClass *, uint8_t>
1858
  findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1859
1860
  /// Once all of the register classes are added, this allows us to compute
1861
  /// derived properties we expose.
1862
  void computeRegisterProperties(const TargetRegisterInfo *TRI);
1863
1864
  /// Indicate that the specified operation does not work with the specified
1865
  /// type and indicate what to do about it. Note that VT may refer to either
1866
  /// the type of a result or that of an operand of Op.
1867
  void setOperationAction(unsigned Op, MVT VT,
1868
385M
                          LegalizeAction Action) {
1869
385M
    assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1870
385M
    OpActions[(unsigned)VT.SimpleTy][Op] = Action;
1871
385M
  }
1872
1873
  /// Indicate that the specified load with extension does not work with the
1874
  /// specified type and indicate what to do about it.
1875
  void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1876
923M
                        LegalizeAction Action) {
1877
923M
    assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1878
923M
           MemVT.isValid() && "Table isn't big enough!");
1879
923M
    assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1880
923M
    unsigned Shift = 4 * ExtType;
1881
923M
    LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
1882
923M
    LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
1883
923M
  }
1884
1885
  /// Indicate that the specified truncating store does not work with the
1886
  /// specified type and indicate what to do about it.
1887
  void setTruncStoreAction(MVT ValVT, MVT MemVT,
1888
331M
                           LegalizeAction Action) {
1889
331M
    assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1890
331M
    TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
1891
331M
  }
1892
1893
  /// Indicate that the specified indexed load does or does not work with the
1894
  /// specified type and indicate what to do abort it.
1895
  ///
1896
  /// NOTE: All indexed mode loads are initialized to Expand in
1897
  /// TargetLowering.cpp
1898
  void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1899
24.1M
                            LegalizeAction Action) {
1900
24.1M
    assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1901
24.1M
           (unsigned)Action < 0xf && "Table isn't big enough!");
1902
24.1M
    // Load action are kept in the upper half.
1903
24.1M
    IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1904
24.1M
    IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1905
24.1M
  }
1906
1907
  /// Indicate that the specified indexed store does or does not work with the
1908
  /// specified type and indicate what to do about it.
1909
  ///
1910
  /// NOTE: All indexed mode stores are initialized to Expand in
1911
  /// TargetLowering.cpp
1912
  void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1913
24.1M
                             LegalizeAction Action) {
1914
24.1M
    assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1915
24.1M
           (unsigned)Action < 0xf && "Table isn't big enough!");
1916
24.1M
    // Store action are kept in the lower half.
1917
24.1M
    IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1918
24.1M
    IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1919
24.1M
  }
1920
1921
  /// Indicate that the specified condition code is or isn't supported on the
1922
  /// target and indicate what to do about it.
1923
  void setCondCodeAction(ISD::CondCode CC, MVT VT,
1924
341k
                         LegalizeAction Action) {
1925
341k
    assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1926
341k
           "Table isn't big enough!");
1927
341k
    assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1928
341k
    /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
1929
341k
    /// value and the upper 29 bits index into the second dimension of the array
1930
341k
    /// to select what 32-bit value to use.
1931
341k
    uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1932
341k
    CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
1933
341k
    CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
1934
341k
  }
1935
1936
  /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1937
  /// to trying a larger integer/fp until it can find one that works. If that
1938
  /// default is insufficient, this method can be used by the target to override
1939
  /// the default.
1940
1.52M
  void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1941
1.52M
    PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1942
1.52M
  }
1943
1944
  /// Convenience method to set an operation to Promote and specify the type
1945
  /// in a single call.
1946
242k
  void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1947
242k
    setOperationAction(Opc, OrigVT, Promote);
1948
242k
    AddPromotedToType(Opc, OrigVT, DestVT);
1949
242k
  }
1950
1951
  /// Targets should invoke this method for each target independent node that
1952
  /// they want to provide a custom DAG combiner for by implementing the
1953
  /// PerformDAGCombine virtual method.
1954
1.23M
  void setTargetDAGCombine(ISD::NodeType NT) {
1955
1.23M
    assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1956
1.23M
    TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1957
1.23M
  }
1958
1959
  /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1960
0
  void setJumpBufSize(unsigned Size) {
1961
0
    JumpBufSize = Size;
1962
0
  }
1963
1964
  /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1965
  /// 0
1966
0
  void setJumpBufAlignment(unsigned Align) {
1967
0
    JumpBufAlignment = Align;
1968
0
  }
1969
1970
  /// Set the target's minimum function alignment (in log2(bytes))
1971
32.4k
  void setMinFunctionAlignment(unsigned Align) {
1972
32.4k
    MinFunctionAlignment = Align;
1973
32.4k
  }
1974
1975
  /// Set the target's preferred function alignment.  This should be set if
1976
  /// there is a performance benefit to higher-than-minimum alignment (in
1977
  /// log2(bytes))
1978
27.5k
  void setPrefFunctionAlignment(unsigned Align) {
1979
27.5k
    PrefFunctionAlignment = Align;
1980
27.5k
  }
1981
1982
  /// Set the target's preferred loop alignment. Default alignment is zero, it
1983
  /// means the target does not care about loop alignment.  The alignment is
1984
  /// specified in log2(bytes). The target may also override
1985
  /// getPrefLoopAlignment to provide per-loop values.
1986
34.9k
  void setPrefLoopAlignment(unsigned Align) {
1987
34.9k
    PrefLoopAlignment = Align;
1988
34.9k
  }
1989
1990
  /// Set the minimum stack alignment of an argument (in log2(bytes)).
1991
20.6k
  void setMinStackArgumentAlignment(unsigned Align) {
1992
20.6k
    MinStackArgumentAlignment = Align;
1993
20.6k
  }
1994
1995
  /// Set the maximum atomic operation size supported by the
1996
  /// backend. Atomic operations greater than this size (as well as
1997
  /// ones that are not naturally aligned), will be expanded by
1998
  /// AtomicExpandPass into an __atomic_* library call.
1999
1.73k
  void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
2000
1.73k
    MaxAtomicSizeInBitsSupported = SizeInBits;
2001
1.73k
  }
2002
2003
  /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
2004
1.42k
  void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
2005
1.42k
    MinCmpXchgSizeInBits = SizeInBits;
2006
1.42k
  }
2007
2008
  /// Sets whether unaligned atomic operations are supported.
2009
0
  void setSupportsUnalignedAtomics(bool UnalignedSupported) {
2010
0
    SupportsUnalignedAtomics = UnalignedSupported;
2011
0
  }
2012
2013
public:
2014
  //===--------------------------------------------------------------------===//
2015
  // Addressing mode description hooks (used by LSR etc).
2016
  //
2017
2018
  /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
2019
  /// instructions reading the address. This allows as much computation as
2020
  /// possible to be done in the address mode for that operand. This hook lets
2021
  /// targets also pass back when this should be done on intrinsics which
2022
  /// load/store.
2023
  virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
2024
                                    SmallVectorImpl<Value*> &/*Ops*/,
2025
954k
                                    Type *&/*AccessTy*/) const {
2026
954k
    return false;
2027
954k
  }
2028
2029
  /// This represents an addressing mode of:
2030
  ///    BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
2031
  /// If BaseGV is null,  there is no BaseGV.
2032
  /// If BaseOffs is zero, there is no base offset.
2033
  /// If HasBaseReg is false, there is no base register.
2034
  /// If Scale is zero, there is no ScaleReg.  Scale of 1 indicates a reg with
2035
  /// no scale.
2036
  struct AddrMode {
2037
    GlobalValue *BaseGV = nullptr;
2038
    int64_t      BaseOffs = 0;
2039
    bool         HasBaseReg = false;
2040
    int64_t      Scale = 0;
2041
77.3M
    AddrMode() = default;
2042
  };
2043
2044
  /// Return true if the addressing mode represented by AM is legal for this
2045
  /// target, for a load/store of the specified type.
2046
  ///
2047
  /// The type may be VoidTy, in which case only return true if the addressing
2048
  /// mode is legal for a load/store of any legal type.  TODO: Handle
2049
  /// pre/postinc as well.
2050
  ///
2051
  /// If the address space cannot be determined, it will be -1.
2052
  ///
2053
  /// TODO: Remove default argument
2054
  virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
2055
                                     Type *Ty, unsigned AddrSpace,
2056
                                     Instruction *I = nullptr) const;
2057
2058
  /// Return the cost of the scaling factor used in the addressing mode
2059
  /// represented by AM for this target, for a load/store of the specified type.
2060
  ///
2061
  /// If the AM is supported, the return value must be >= 0.
2062
  /// If the AM is not supported, it returns a negative value.
2063
  /// TODO: Handle pre/postinc as well.
2064
  /// TODO: Remove default argument
2065
  virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
2066
8.27k
                                   Type *Ty, unsigned AS = 0) const {
2067
8.27k
    // Default: assume that any scaling factor used in a legal AM is free.
2068
8.27k
    if (isLegalAddressingMode(DL, AM, Ty, AS))
2069
8.27k
      return 0;
2070
0
    return -1;
2071
0
  }
2072
2073
  /// Return true if the specified immediate is legal icmp immediate, that is
2074
  /// the target has icmp instructions which can compare a register against the
2075
  /// immediate without having to materialize the immediate into a register.
2076
37.3k
  virtual bool isLegalICmpImmediate(int64_t) const {
2077
37.3k
    return true;
2078
37.3k
  }
2079
2080
  /// Return true if the specified immediate is legal add immediate, that is the
2081
  /// target has add instructions which can add a register with the immediate
2082
  /// without having to materialize the immediate into a register.
2083
1.58k
  virtual bool isLegalAddImmediate(int64_t) const {
2084
1.58k
    return true;
2085
1.58k
  }
2086
2087
  /// Return true if the specified immediate is legal for the value input of a
2088
  /// store instruction.
2089
7.74k
  virtual bool isLegalStoreImmediate(int64_t Value) const {
2090
7.74k
    // Default implementation assumes that at least 0 works since it is likely
2091
7.74k
    // that a zero register exists or a zero immediate is allowed.
2092
7.74k
    return Value == 0;
2093
7.74k
  }
2094
2095
  /// Return true if it's significantly cheaper to shift a vector by a uniform
2096
  /// scalar than by an amount which will vary across each lane. On x86, for
2097
  /// example, there is a "psllw" instruction for the former case, but no simple
2098
  /// instruction for a general "a << b" operation on vectors.
2099
162k
  virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
2100
162k
    return false;
2101
162k
  }
2102
2103
  /// Returns true if the opcode is a commutative binary operation.
2104
143M
  virtual bool isCommutativeBinOp(unsigned Opcode) const {
2105
143M
    // FIXME: This should get its info from the td file.
2106
143M
    switch (Opcode) {
2107
143M
    case ISD::ADD:
2108
21.8M
    case ISD::SMIN:
2109
21.8M
    case ISD::SMAX:
2110
21.8M
    case ISD::UMIN:
2111
21.8M
    case ISD::UMAX:
2112
21.8M
    case ISD::MUL:
2113
21.8M
    case ISD::MULHU:
2114
21.8M
    case ISD::MULHS:
2115
21.8M
    case ISD::SMUL_LOHI:
2116
21.8M
    case ISD::UMUL_LOHI:
2117
21.8M
    case ISD::FADD:
2118
21.8M
    case ISD::FMUL:
2119
21.8M
    case ISD::AND:
2120
21.8M
    case ISD::OR:
2121
21.8M
    case ISD::XOR:
2122
21.8M
    case ISD::SADDO:
2123
21.8M
    case ISD::UADDO:
2124
21.8M
    case ISD::ADDC:
2125
21.8M
    case ISD::ADDE:
2126
21.8M
    case ISD::FMINNUM:
2127
21.8M
    case ISD::FMAXNUM:
2128
21.8M
    case ISD::FMINIMUM:
2129
21.8M
    case ISD::FMAXIMUM:
2130
21.8M
      return true;
2131
122M
    default: return false;
2132
143M
    }
2133
143M
  }
2134
2135
  /// Return true if it's free to truncate a value of type FromTy to type
2136
  /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
2137
  /// by referencing its sub-register AX.
2138
  /// Targets must return false when FromTy <= ToTy.
2139
195
  virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
2140
195
    return false;
2141
195
  }
2142
2143
  /// Return true if a truncation from FromTy to ToTy is permitted when deciding
2144
  /// whether a call is in tail position. Typically this means that both results
2145
  /// would be assigned to the same register or stack slot, but it could mean
2146
  /// the target performs adequate checks of its own before proceeding with the
2147
  /// tail call.  Targets must return false when FromTy <= ToTy.
2148
8
  virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
2149
8
    return false;
2150
8
  }
2151
2152
13.8k
  virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
2153
13.8k
    return false;
2154
13.8k
  }
2155
2156
82.0k
  virtual bool isProfitableToHoist(Instruction *I) const { return true; }
2157
2158
  /// Return true if the extension represented by \p I is free.
2159
  /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2160
  /// this method can use the context provided by \p I to decide
2161
  /// whether or not \p I is free.
2162
  /// This method extends the behavior of the is[Z|FP]ExtFree family.
2163
  /// In other words, if is[Z|FP]Free returns true, then this method
2164
  /// returns true as well. The converse is not true.
2165
  /// The target can perform the adequate checks by overriding isExtFreeImpl.
2166
  /// \pre \p I must be a sign, zero, or fp extension.
2167
2.32M
  bool isExtFree(const Instruction *I) const {
2168
2.32M
    switch (I->getOpcode()) {
2169
2.32M
    case Instruction::FPExt:
2170
73.4k
      if (isFPExtFree(EVT::getEVT(I->getType()),
2171
73.4k
                      EVT::getEVT(I->getOperand(0)->getType())))
2172
6
        return true;
2173
73.3k
      break;
2174
938k
    case Instruction::ZExt:
2175
938k
      if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2176
419k
        return true;
2177
518k
      break;
2178
1.30M
    case Instruction::SExt:
2179
1.30M
      break;
2180
518k
    default:
2181
0
      llvm_unreachable("Instruction is not an extension");
2182
1.90M
    }
2183
1.90M
    return isExtFreeImpl(I);
2184
1.90M
  }
2185
2186
  /// Return true if \p Load and \p Ext can form an ExtLoad.
2187
  /// For example, in AArch64
2188
  ///   %L = load i8, i8* %ptr
2189
  ///   %E = zext i8 %L to i32
2190
  /// can be lowered into one load instruction
2191
  ///   ldrb w0, [x0]
2192
  bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2193
848k
                 const DataLayout &DL) const {
2194
848k
    EVT VT = getValueType(DL, Ext->getType());
2195
848k
    EVT LoadVT = getValueType(DL, Load->getType());
2196
848k
2197
848k
    // If the load has other users and the truncate is not free, the ext
2198
848k
    // probably isn't free.
2199
848k
    if (!Load->hasOneUse() && 
(430k
isTypeLegal(LoadVT)430k
||
!isTypeLegal(VT)208k
) &&
2200
848k
        
!isTruncateFree(Ext->getType(), Load->getType())223k
)
2201
816
      return false;
2202
848k
2203
848k
    // Check whether the target supports casts folded into loads.
2204
848k
    unsigned LType;
2205
848k
    if (isa<ZExtInst>(Ext))
2206
317k
      LType = ISD::ZEXTLOAD;
2207
530k
    else {
2208
530k
      assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
2209
530k
      LType = ISD::SEXTLOAD;
2210
530k
    }
2211
848k
2212
848k
    return isLoadExtLegal(LType, VT, LoadVT);
2213
848k
  }
2214
2215
  /// Return true if any actual instruction that defines a value of type FromTy
2216
  /// implicitly zero-extends the value to ToTy in the result register.
2217
  ///
2218
  /// The function should return true when it is likely that the truncate can
2219
  /// be freely folded with an instruction defining a value of FromTy. If
2220
  /// the defining instruction is unknown (because you're looking at a
2221
  /// function argument, PHI, etc.) then the target may require an
2222
  /// explicit truncate, which is not necessarily free, but this function
2223
  /// does not deal with those cases.
2224
  /// Targets must return false when FromTy >= ToTy.
2225
87.1k
  virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2226
87.1k
    return false;
2227
87.1k
  }
2228
2229
17.4k
  virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2230
17.4k
    return false;
2231
17.4k
  }
2232
2233
  /// Return true if sign-extension from FromTy to ToTy is cheaper than
2234
  /// zero-extension.
2235
243k
  virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const {
2236
243k
    return false;
2237
243k
  }
2238
2239
  /// Return true if the target supplies and combines to a paired load
2240
  /// two loaded values of type LoadedType next to each other in memory.
2241
  /// RequiredAlignment gives the minimal alignment constraints that must be met
2242
  /// to be able to select this paired load.
2243
  ///
2244
  /// This information is *not* used to generate actual paired loads, but it is
2245
  /// used to generate a sequence of loads that is easier to combine into a
2246
  /// paired load.
2247
  /// For instance, something like this:
2248
  /// a = load i64* addr
2249
  /// b = trunc i64 a to i32
2250
  /// c = lshr i64 a, 32
2251
  /// d = trunc i64 c to i32
2252
  /// will be optimized into:
2253
  /// b = load i32* addr1
2254
  /// d = load i32* addr2
2255
  /// Where addr1 = addr2 +/- sizeof(i32).
2256
  ///
2257
  /// In other words, unless the target performs a post-isel load combining,
2258
  /// this information should not be provided because it will generate more
2259
  /// loads.
2260
  virtual bool hasPairedLoad(EVT /*LoadedType*/,
2261
17.2k
                             unsigned & /*RequiredAlignment*/) const {
2262
17.2k
    return false;
2263
17.2k
  }
2264
2265
  /// Return true if the target has a vector blend instruction.
2266
39.0k
  virtual bool hasVectorBlend() const { return false; }
2267
2268
  /// Get the maximum supported factor for interleaved memory accesses.
2269
  /// Default to be the minimum interleave factor: 2.
2270
0
  virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2271
2272
  /// Lower an interleaved load to target specific intrinsics. Return
2273
  /// true on success.
2274
  ///
2275
  /// \p LI is the vector load instruction.
2276
  /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2277
  /// \p Indices is the corresponding indices for each shufflevector.
2278
  /// \p Factor is the interleave factor.
2279
  virtual bool lowerInterleavedLoad(LoadInst *LI,
2280
                                    ArrayRef<ShuffleVectorInst *> Shuffles,
2281
                                    ArrayRef<unsigned> Indices,
2282
0
                                    unsigned Factor) const {
2283
0
    return false;
2284
0
  }
2285
2286
  /// Lower an interleaved store to target specific intrinsics. Return
2287
  /// true on success.
2288
  ///
2289
  /// \p SI is the vector store instruction.
2290
  /// \p SVI is the shufflevector to RE-interleave the stored vector.
2291
  /// \p Factor is the interleave factor.
2292
  virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
2293
0
                                     unsigned Factor) const {
2294
0
    return false;
2295
0
  }
2296
2297
  /// Return true if zero-extending the specific node Val to type VT2 is free
2298
  /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2299
  /// because it's folded such as X86 zero-extending loads).
2300
14.7k
  virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2301
14.7k
    return isZExtFree(Val.getValueType(), VT2);
2302
14.7k
  }
2303
2304
  /// Return true if an fpext operation is free (for instance, because
2305
  /// single-precision floating-point numbers are implicitly extended to
2306
  /// double-precision).
2307
74.2k
  virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2308
74.2k
    assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2309
74.2k
           "invalid fpext types");
2310
74.2k
    return false;
2311
74.2k
  }
2312
2313
  /// Return true if an fpext operation input to an \p Opcode operation is free
2314
  /// (for instance, because half-precision floating-point numbers are
2315
  /// implicitly extended to float-precision) for an FMA instruction.
2316
44
  virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
2317
44
    assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2318
44
           "invalid fpext types");
2319
44
    return isFPExtFree(DestVT, SrcVT);
2320
44
  }
2321
2322
  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2323
  /// extend node) is profitable.
2324
7.81k
  virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2325
2326
  /// Return true if an fneg operation is free to the point where it is never
2327
  /// worthwhile to replace it with a bitwise operation.
2328
8.46k
  virtual bool isFNegFree(EVT VT) const {
2329
8.46k
    assert(VT.isFloatingPoint());
2330
8.46k
    return false;
2331
8.46k
  }
2332
2333
  /// Return true if an fabs operation is free to the point where it is never
2334
  /// worthwhile to replace it with a bitwise operation.
2335
10.0k
  virtual bool isFAbsFree(EVT VT) const {
2336
10.0k
    assert(VT.isFloatingPoint());
2337
10.0k
    return false;
2338
10.0k
  }
2339
2340
  /// Return true if an FMA operation is faster than a pair of fmul and fadd
2341
  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2342
  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2343
  ///
2344
  /// NOTE: This may be called before legalization on types for which FMAs are
2345
  /// not legal, but should return true if those types will eventually legalize
2346
  /// to types that support FMAs. After legalization, it will only be called on
2347
  /// types that support FMAs (via Legal or Custom actions)
2348
4.95k
  virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
2349
4.95k
    return false;
2350
4.95k
  }
2351
2352
  /// Return true if it's profitable to narrow operations of type VT1 to
2353
  /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2354
  /// i32 to i16.
2355
6.80k
  virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2356
6.80k
    return false;
2357
6.80k
  }
2358
2359
  /// Return true if it is beneficial to convert a load of a constant to
2360
  /// just the constant itself.
2361
  /// On some targets it might be more efficient to use a combination of
2362
  /// arithmetic instructions to materialize the constant instead of loading it
2363
  /// from a constant pool.
2364
  virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2365
12
                                                 Type *Ty) const {
2366
12
    return false;
2367
12
  }
2368
2369
  /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2370
  /// from this source type with this index. This is needed because
2371
  /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2372
  /// the first element, and only the target knows which lowering is cheap.
2373
  virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2374
86
                                       unsigned Index) const {
2375
86
    return false;
2376
86
  }
2377
2378
  // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2379
  // even if the vector itself has multiple uses.
2380
705
  virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2381
705
    return false;
2382
705
  }
2383
2384
  // Return true if CodeGenPrepare should consider splitting large offset of a
2385
  // GEP to make the GEP fit into the addressing mode and can be sunk into the
2386
  // same blocks of its users.
2387
3.26k
  virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
2388
2389
  //===--------------------------------------------------------------------===//
2390
  // Runtime Library hooks
2391
  //
2392
2393
  /// Rename the default libcall routine name for the specified libcall.
2394
26.2M
  void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2395
26.2M
    LibcallRoutineNames[Call] = Name;
2396
26.2M
  }
2397
2398
  /// Get the libcall routine name for the specified libcall.
2399
116k
  const char *getLibcallName(RTLIB::Libcall Call) const {
2400
116k
    return LibcallRoutineNames[Call];
2401
116k
  }
2402
2403
  /// Override the default CondCode to be used to test the result of the
2404
  /// comparison libcall against zero.
2405
91.3k
  void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
2406
91.3k
    CmpLibcallCCs[Call] = CC;
2407
91.3k
  }
2408
2409
  /// Get the CondCode that's to be used to test the result of the comparison
2410
  /// libcall against zero.
2411
1.97k
  ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
2412
1.97k
    return CmpLibcallCCs[Call];
2413
1.97k
  }
2414
2415
  /// Set the CallingConv that should be used for the specified libcall.
2416
27.0M
  void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
2417
27.0M
    LibcallCallingConvs[Call] = CC;
2418
27.0M
  }
2419
2420
  /// Get the CallingConv that should be used for the specified libcall.
2421
19.6k
  CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
2422
19.6k
    return LibcallCallingConvs[Call];
2423
19.6k
  }
2424
2425
  /// Execute target specific actions to finalize target lowering.
2426
  /// This is used to set extra flags in MachineFrameInformation and freezing
2427
  /// the set of reserved registers.
2428
  /// The default implementation just freezes the set of reserved registers.
2429
  virtual void finalizeLowering(MachineFunction &MF) const;
2430
2431
private:
2432
  const TargetMachine &TM;
2433
2434
  /// Tells the code generator that the target has multiple (allocatable)
2435
  /// condition registers that can be used to store the results of comparisons
2436
  /// for use by selects and conditional branches. With multiple condition
2437
  /// registers, the code generator will not aggressively sink comparisons into
2438
  /// the blocks of their users.
2439
  bool HasMultipleConditionRegisters;
2440
2441
  /// Tells the code generator that the target has BitExtract instructions.
2442
  /// The code generator will aggressively sink "shift"s into the blocks of
2443
  /// their users if the users will generate "and" instructions which can be
2444
  /// combined with "shift" to BitExtract instructions.
2445
  bool HasExtractBitsInsn;
2446
2447
  /// Tells the code generator to bypass slow divide or remainder
2448
  /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2449
  /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2450
  /// div/rem when the operands are positive and less than 256.
2451
  DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
2452
2453
  /// Tells the code generator that it shouldn't generate extra flow control
2454
  /// instructions and should attempt to combine flow control instructions via
2455
  /// predication.
2456
  bool JumpIsExpensive;
2457
2458
  /// Whether the target supports or cares about preserving floating point
2459
  /// exception behavior.
2460
  bool HasFloatingPointExceptions;
2461
2462
  /// This target prefers to use _setjmp to implement llvm.setjmp.
2463
  ///
2464
  /// Defaults to false.
2465
  bool UseUnderscoreSetJmp;
2466
2467
  /// This target prefers to use _longjmp to implement llvm.longjmp.
2468
  ///
2469
  /// Defaults to false.
2470
  bool UseUnderscoreLongJmp;
2471
2472
  /// Information about the contents of the high-bits in boolean values held in
2473
  /// a type wider than i1. See getBooleanContents.
2474
  BooleanContent BooleanContents;
2475
2476
  /// Information about the contents of the high-bits in boolean values held in
2477
  /// a type wider than i1. See getBooleanContents.
2478
  BooleanContent BooleanFloatContents;
2479
2480
  /// Information about the contents of the high-bits in boolean vector values
2481
  /// when the element type is wider than i1. See getBooleanContents.
2482
  BooleanContent BooleanVectorContents;
2483
2484
  /// The target scheduling preference: shortest possible total cycles or lowest
2485
  /// register usage.
2486
  Sched::Preference SchedPreferenceInfo;
2487
2488
  /// The size, in bytes, of the target's jmp_buf buffers
2489
  unsigned JumpBufSize;
2490
2491
  /// The alignment, in bytes, of the target's jmp_buf buffers
2492
  unsigned JumpBufAlignment;
2493
2494
  /// The minimum alignment that any argument on the stack needs to have.
2495
  unsigned MinStackArgumentAlignment;
2496
2497
  /// The minimum function alignment (used when optimizing for size, and to
2498
  /// prevent explicitly provided alignment from leading to incorrect code).
2499
  unsigned MinFunctionAlignment;
2500
2501
  /// The preferred function alignment (used when alignment unspecified and
2502
  /// optimizing for speed).
2503
  unsigned PrefFunctionAlignment;
2504
2505
  /// The preferred loop alignment.
2506
  unsigned PrefLoopAlignment;
2507
2508
  /// Size in bits of the maximum atomics size the backend supports.
2509
  /// Accesses larger than this will be expanded by AtomicExpandPass.
2510
  unsigned MaxAtomicSizeInBitsSupported;
2511
2512
  /// Size in bits of the minimum cmpxchg or ll/sc operation the
2513
  /// backend supports.
2514
  unsigned MinCmpXchgSizeInBits;
2515
2516
  /// This indicates if the target supports unaligned atomic operations.
2517
  bool SupportsUnalignedAtomics;
2518
2519
  /// If set to a physical register, this specifies the register that
2520
  /// llvm.savestack/llvm.restorestack should save and restore.
2521
  unsigned StackPointerRegisterToSaveRestore;
2522
2523
  /// This indicates the default register class to use for each ValueType the
2524
  /// target supports natively.
2525
  const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2526
  unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
2527
  MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2528
2529
  /// This indicates the "representative" register class to use for each
2530
  /// ValueType the target supports natively. This information is used by the
2531
  /// scheduler to track register pressure. By default, the representative
2532
  /// register class is the largest legal super-reg register class of the
2533
  /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2534
  /// representative class would be GR32.
2535
  const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2536
2537
  /// This indicates the "cost" of the "representative" register class for each
2538
  /// ValueType. The cost is used by the scheduler to approximate register
2539
  /// pressure.
2540
  uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2541
2542
  /// For any value types we are promoting or expanding, this contains the value
2543
  /// type that we are changing to.  For Expanded types, this contains one step
2544
  /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2545
  /// (e.g. i64 -> i16).  For types natively supported by the system, this holds
2546
  /// the same type (e.g. i32 -> i32).
2547
  MVT TransformToType[MVT::LAST_VALUETYPE];
2548
2549
  /// For each operation and each value type, keep a LegalizeAction that
2550
  /// indicates how instruction selection should deal with the operation.  Most
2551
  /// operations are Legal (aka, supported natively by the target), but
2552
  /// operations that are not should be described.  Note that operations on
2553
  /// non-legal value types are not described here.
2554
  LegalizeAction OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
2555
2556
  /// For each load extension type and each value type, keep a LegalizeAction
2557
  /// that indicates how instruction selection should deal with a load of a
2558
  /// specific value type and extension type. Uses 4-bits to store the action
2559
  /// for each of the 4 load ext types.
2560
  uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2561
2562
  /// For each value type pair keep a LegalizeAction that indicates whether a
2563
  /// truncating store of a specific value type and truncating type is legal.
2564
  LegalizeAction TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2565
2566
  /// For each indexed mode and each value type, keep a pair of LegalizeAction
2567
  /// that indicates how instruction selection should deal with the load /
2568
  /// store.
2569
  ///
2570
  /// The first dimension is the value_type for the reference. The second
2571
  /// dimension represents the various modes for load store.
2572
  uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2573
2574
  /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2575
  /// indicates how instruction selection should deal with the condition code.
2576
  ///
2577
  /// Because each CC action takes up 4 bits, we need to have the array size be
2578
  /// large enough to fit all of the value types. This can be done by rounding
2579
  /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2580
  uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2581
2582
protected:
2583
  ValueTypeActionImpl ValueTypeActions;
2584
2585
private:
2586
  LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2587
2588
  /// Targets can specify ISD nodes that they would like PerformDAGCombine
2589
  /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2590
  /// array.
2591
  unsigned char
2592
  TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2593
2594
  /// For operations that must be promoted to a specific type, this holds the
2595
  /// destination type.  This map should be sparse, so don't hold it as an
2596
  /// array.
2597
  ///
2598
  /// Targets add entries to this map with AddPromotedToType(..), clients access
2599
  /// this with getTypeToPromoteTo(..).
2600
  std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2601
    PromoteToType;
2602
2603
  /// Stores the name each libcall.
2604
  const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
2605
2606
  /// The ISD::CondCode that should be used to test the result of each of the
2607
  /// comparison libcall against zero.
2608
  ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2609
2610
  /// Stores the CallingConv that should be used for each libcall.
2611
  CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2612
2613
  /// Set default libcall names and calling conventions.
2614
  void InitLibcalls(const Triple &TT);
2615
2616
protected:
2617
  /// Return true if the extension represented by \p I is free.
2618
  /// \pre \p I is a sign, zero, or fp extension and
2619
  ///      is[Z|FP]ExtFree of the related types is not true.
2620
416k
  virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2621
2622
  /// Depth that GatherAllAliases should should continue looking for chain
2623
  /// dependencies when trying to find a more preferable chain. As an
2624
  /// approximation, this should be more than the number of consecutive stores
2625
  /// expected to be merged.
2626
  unsigned GatherAllAliasesMaxDepth;
2627
2628
  /// Specify maximum number of store instructions per memset call.
2629
  ///
2630
  /// When lowering \@llvm.memset this field specifies the maximum number of
2631
  /// store operations that may be substituted for the call to memset. Targets
2632
  /// must set this value based on the cost threshold for that target. Targets
2633
  /// should assume that the memset will be done using as many of the largest
2634
  /// store operations first, followed by smaller ones, if necessary, per
2635
  /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2636
  /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2637
  /// store.  This only applies to setting a constant array of a constant size.
2638
  unsigned MaxStoresPerMemset;
2639
2640
  /// Maximum number of stores operations that may be substituted for the call
2641
  /// to memset, used for functions with OptSize attribute.
2642
  unsigned MaxStoresPerMemsetOptSize;
2643
2644
  /// Specify maximum bytes of store instructions per memcpy call.
2645
  ///
2646
  /// When lowering \@llvm.memcpy this field specifies the maximum number of
2647
  /// store operations that may be substituted for a call to memcpy. Targets
2648
  /// must set this value based on the cost threshold for that target. Targets
2649
  /// should assume that the memcpy will be done using as many of the largest
2650
  /// store operations first, followed by smaller ones, if necessary, per
2651
  /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2652
  /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2653
  /// and one 1-byte store. This only applies to copying a constant array of
2654
  /// constant size.
2655
  unsigned MaxStoresPerMemcpy;
2656
2657
2658
  /// \brief Specify max number of store instructions to glue in inlined memcpy.
2659
  ///
2660
  /// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number
2661
  /// of store instructions to keep together. This helps in pairing and
2662
  //  vectorization later on.
2663
  unsigned MaxGluedStoresPerMemcpy = 0;
2664
2665
  /// Maximum number of store operations that may be substituted for a call to
2666
  /// memcpy, used for functions with OptSize attribute.
2667
  unsigned MaxStoresPerMemcpyOptSize;
2668
  unsigned MaxLoadsPerMemcmp;
2669
  unsigned MaxLoadsPerMemcmpOptSize;
2670
2671
  /// Specify maximum bytes of store instructions per memmove call.
2672
  ///
2673
  /// When lowering \@llvm.memmove this field specifies the maximum number of
2674
  /// store instructions that may be substituted for a call to memmove. Targets
2675
  /// must set this value based on the cost threshold for that target. Targets
2676
  /// should assume that the memmove will be done using as many of the largest
2677
  /// store operations first, followed by smaller ones, if necessary, per
2678
  /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2679
  /// with 8-bit alignment would result in nine 1-byte stores.  This only
2680
  /// applies to copying a constant array of constant size.
2681
  unsigned MaxStoresPerMemmove;
2682
2683
  /// Maximum number of store instructions that may be substituted for a call to
2684
  /// memmove, used for functions with OptSize attribute.
2685
  unsigned MaxStoresPerMemmoveOptSize;
2686
2687
  /// Tells the code generator that select is more expensive than a branch if
2688
  /// the branch is usually predicted right.
2689
  bool PredictableSelectIsExpensive;
2690
2691
  /// \see enableExtLdPromotion.
2692
  bool EnableExtLdPromotion;
2693
2694
  /// Return true if the value types that can be represented by the specified
2695
  /// register class are all legal.
2696
  bool isLegalRC(const TargetRegisterInfo &TRI,
2697
                 const TargetRegisterClass &RC) const;
2698
2699
  /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2700
  /// sequence of memory operands that is recognized by PrologEpilogInserter.
2701
  MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2702
                                    MachineBasicBlock *MBB) const;
2703
2704
  /// Replace/modify the XRay custom event operands with target-dependent
2705
  /// details.
2706
  MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
2707
                                         MachineBasicBlock *MBB) const;
2708
2709
  /// Replace/modify the XRay typed event operands with target-dependent
2710
  /// details.
2711
  MachineBasicBlock *emitXRayTypedEvent(MachineInstr &MI,
2712
                                        MachineBasicBlock *MBB) const;
2713
};
2714
2715
/// This class defines information used to lower LLVM code to legal SelectionDAG
2716
/// operators that the target instruction selector can accept natively.
2717
///
2718
/// This class also defines callbacks that targets must implement to lower
2719
/// target-specific constructs to SelectionDAG operators.
2720
class TargetLowering : public TargetLoweringBase {
2721
public:
2722
  struct DAGCombinerInfo;
2723
2724
  TargetLowering(const TargetLowering &) = delete;
2725
  TargetLowering &operator=(const TargetLowering &) = delete;
2726
2727
  /// NOTE: The TargetMachine owns TLOF.
2728
  explicit TargetLowering(const TargetMachine &TM);
2729
2730
  bool isPositionIndependent() const;
2731
2732
  virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
2733
                                          FunctionLoweringInfo *FLI,
2734
64.5M
                                          LegacyDivergenceAnalysis *DA) const {
2735
64.5M
    return false;
2736
64.5M
  }
2737
2738
54.1M
  virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
2739
54.1M
    return false;
2740
54.1M
  }
2741
2742
  /// Returns true by value, base pointer and offset pointer and addressing mode
2743
  /// by reference if the node's address can be legally represented as
2744
  /// pre-indexed load / store address.
2745
  virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2746
                                         SDValue &/*Offset*/,
2747
                                         ISD::MemIndexedMode &/*AM*/,
2748
0
                                         SelectionDAG &/*DAG*/) const {
2749
0
    return false;
2750
0
  }
2751
2752
  /// Returns true by value, base pointer and offset pointer and addressing mode
2753
  /// by reference if this node can be combined with a load / store to form a
2754
  /// post-indexed load / store.
2755
  virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2756
                                          SDValue &/*Base*/,
2757
                                          SDValue &/*Offset*/,
2758
                                          ISD::MemIndexedMode &/*AM*/,
2759
0
                                          SelectionDAG &/*DAG*/) const {
2760
0
    return false;
2761
0
  }
2762
2763
  /// Return the entry encoding for a jump table in the current function.  The
2764
  /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2765
  virtual unsigned getJumpTableEncoding() const;
2766
2767
  virtual const MCExpr *
2768
  LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
2769
                            const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2770
0
                            MCContext &/*Ctx*/) const {
2771
0
    llvm_unreachable("Need to implement this hook if target has custom JTIs");
2772
0
  }
2773
2774
  /// Returns relocation base for the given PIC jumptable.
2775
  virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2776
                                           SelectionDAG &DAG) const;
2777
2778
  /// This returns the relocation base for the given PIC jumptable, the same as
2779
  /// getPICJumpTableRelocBase, but as an MCExpr.
2780
  virtual const MCExpr *
2781
  getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2782
                               unsigned JTI, MCContext &Ctx) const;
2783
2784
  /// Return true if folding a constant offset with the given GlobalAddress is
2785
  /// legal.  It is frequently not legal in PIC relocation models.
2786
  virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2787
2788
  bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2789
                            SDValue &Chain) const;
2790
2791
  void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
2792
                           SDValue &NewRHS, ISD::CondCode &CCCode,
2793
                           const SDLoc &DL) const;
2794
2795
  /// Returns a pair of (return value, chain).
2796
  /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2797
  std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2798
                                          EVT RetVT, ArrayRef<SDValue> Ops,
2799
                                          bool isSigned, const SDLoc &dl,
2800
                                          bool doesNotReturn = false,
2801
                                          bool isReturnValueUsed = true) const;
2802
2803
  /// Check whether parameters to a call that are passed in callee saved
2804
  /// registers are the same as from the calling function.  This needs to be
2805
  /// checked for tail call eligibility.
2806
  bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
2807
      const uint32_t *CallerPreservedMask,
2808
      const SmallVectorImpl<CCValAssign> &ArgLocs,
2809
      const SmallVectorImpl<SDValue> &OutVals) const;
2810
2811
  //===--------------------------------------------------------------------===//
2812
  // TargetLowering Optimization Methods
2813
  //
2814
2815
  /// A convenience struct that encapsulates a DAG, and two SDValues for
2816
  /// returning information from TargetLowering to its clients that want to
2817
  /// combine.
2818
  struct TargetLoweringOpt {
2819
    SelectionDAG &DAG;
2820
    bool LegalTys;
2821
    bool LegalOps;
2822
    SDValue Old;
2823
    SDValue New;
2824
2825
    explicit TargetLoweringOpt(SelectionDAG &InDAG,
2826
                               bool LT, bool LO) :
2827
10.4M
      DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2828
2829
201k
    bool LegalTypes() const { return LegalTys; }
2830
137k
    bool LegalOperations() const { return LegalOps; }
2831
2832
580k
    bool CombineTo(SDValue O, SDValue N) {
2833
580k
      Old = O;
2834
580k
      New = N;
2835
580k
      return true;
2836
580k
    }
2837
  };
2838
2839
  /// Check to see if the specified operand of the specified instruction is a
2840
  /// constant integer.  If so, check to see if there are any bits set in the
2841
  /// constant that are not demanded.  If so, shrink the constant and return
2842
  /// true.
2843
  bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2844
                              TargetLoweringOpt &TLO) const;
2845
2846
  // Target hook to do target-specific const optimization, which is called by
2847
  // ShrinkDemandedConstant. This function should return true if the target
2848
  // doesn't want ShrinkDemandedConstant to further optimize the constant.
2849
  virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2850
297k
                                            TargetLoweringOpt &TLO) const {
2851
297k
    return false;
2852
297k
  }
2853
2854
  /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.  This
2855
  /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2856
  /// generalized for targets with other types of implicit widening casts.
2857
  bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2858
                        TargetLoweringOpt &TLO) const;
2859
2860
  /// Helper for SimplifyDemandedBits that can simplify an operation with
2861
  /// multiple uses.  This function simplifies operand \p OpIdx of \p User and
2862
  /// then updates \p User with the simplified version. No other uses of
2863
  /// \p OpIdx are updated. If \p User is the only user of \p OpIdx, this
2864
  /// function behaves exactly like function SimplifyDemandedBits declared
2865
  /// below except that it also updates the DAG by calling
2866
  /// DCI.CommitTargetLoweringOpt.
2867
  bool SimplifyDemandedBits(SDNode *User, unsigned OpIdx, const APInt &Demanded,
2868
                            DAGCombinerInfo &DCI, TargetLoweringOpt &TLO) const;
2869
2870
  /// Look at Op.  At this point, we know that only the DemandedMask bits of the
2871
  /// result of Op are ever used downstream.  If we can use this information to
2872
  /// simplify Op, create a new simplified DAG node and return true, returning
2873
  /// the original and new nodes in Old and New.  Otherwise, analyze the
2874
  /// expression and return a mask of KnownOne and KnownZero bits for the
2875
  /// expression (used to simplify the caller).  The KnownZero/One bits may only
2876
  /// be accurate for those bits in the DemandedMask.
2877
  /// \p AssumeSingleUse When this parameter is true, this function will
2878
  ///    attempt to simplify \p Op even if there are multiple uses.
2879
  ///    Callers are responsible for correctly updating the DAG based on the
2880
  ///    results of this function, because simply replacing replacing TLO.Old
2881
  ///    with TLO.New will be incorrect when this parameter is true and TLO.Old
2882
  ///    has multiple uses.
2883
  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2884
                            KnownBits &Known,
2885
                            TargetLoweringOpt &TLO,
2886
                            unsigned Depth = 0,
2887
                            bool AssumeSingleUse = false) const;
2888
2889
  /// Helper wrapper around SimplifyDemandedBits.
2890
  /// Adds Op back to the worklist upon success.
2891
  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2892
                            DAGCombinerInfo &DCI) const;
2893
2894
  /// Look at Vector Op. At this point, we know that only the DemandedElts
2895
  /// elements of the result of Op are ever used downstream.  If we can use
2896
  /// this information to simplify Op, create a new simplified DAG node and
2897
  /// return true, storing the original and new nodes in TLO.
2898
  /// Otherwise, analyze the expression and return a mask of KnownUndef and
2899
  /// KnownZero elements for the expression (used to simplify the caller).
2900
  /// The KnownUndef/Zero elements may only be accurate for those bits
2901
  /// in the DemandedMask.
2902
  /// \p AssumeSingleUse When this parameter is true, this function will
2903
  ///    attempt to simplify \p Op even if there are multiple uses.
2904
  ///    Callers are responsible for correctly updating the DAG based on the
2905
  ///    results of this function, because simply replacing replacing TLO.Old
2906
  ///    with TLO.New will be incorrect when this parameter is true and TLO.Old
2907
  ///    has multiple uses.
2908
  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask,
2909
                                  APInt &KnownUndef, APInt &KnownZero,
2910
                                  TargetLoweringOpt &TLO, unsigned Depth = 0,
2911
                                  bool AssumeSingleUse = false) const;
2912
2913
  /// Helper wrapper around SimplifyDemandedVectorElts.
2914
  /// Adds Op back to the worklist upon success.
2915
  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
2916
                                  APInt &KnownUndef, APInt &KnownZero,
2917
                                  DAGCombinerInfo &DCI) const;
2918
2919
  /// Determine which of the bits specified in Mask are known to be either zero
2920
  /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
2921
  /// argument allows us to only collect the known bits that are shared by the
2922
  /// requested vector elements.
2923
  virtual void computeKnownBitsForTargetNode(const SDValue Op,
2924
                                             KnownBits &Known,
2925
                                             const APInt &DemandedElts,
2926
                                             const SelectionDAG &DAG,
2927
                                             unsigned Depth = 0) const;
2928
2929
  /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
2930
  /// Default implementation computes low bits based on alignment
2931
  /// information. This should preserve known bits passed into it.
2932
  virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
2933
                                             KnownBits &Known,
2934
                                             const APInt &DemandedElts,
2935
                                             const SelectionDAG &DAG,
2936
                                             unsigned Depth = 0) const;
2937
2938
  /// This method can be implemented by targets that want to expose additional
2939
  /// information about sign bits to the DAG Combiner. The DemandedElts
2940
  /// argument allows us to only collect the minimum sign bits that are shared
2941
  /// by the requested vector elements.
2942
  virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2943
                                                   const APInt &DemandedElts,
2944
                                                   const SelectionDAG &DAG,
2945
                                                   unsigned Depth = 0) const;
2946
2947
  /// Attempt to simplify any target nodes based on the demanded vector
2948
  /// elements, returning true on success. Otherwise, analyze the expression and
2949
  /// return a mask of KnownUndef and KnownZero elements for the expression
2950
  /// (used to simplify the caller). The KnownUndef/Zero elements may only be
2951
  /// accurate for those bits in the DemandedMask.
2952
  virtual bool SimplifyDemandedVectorEltsForTargetNode(
2953
      SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
2954
      APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2955
2956
  /// Attempt to simplify any target nodes based on the demanded bits,
2957
  /// returning true on success. Otherwise, analyze the
2958
  /// expression and return a mask of KnownOne and KnownZero bits for the
2959
  /// expression (used to simplify the caller).  The KnownZero/One bits may only
2960
  /// be accurate for those bits in the DemandedMask.
2961
  virtual bool SimplifyDemandedBitsForTargetNode(SDValue Op,
2962
                                                 const APInt &DemandedBits,
2963
                                                 KnownBits &Known,
2964
                                                 TargetLoweringOpt &TLO,
2965
                                                 unsigned Depth = 0) const;
2966
2967
  /// If \p SNaN is false, \returns true if \p Op is known to never be any
2968
  /// NaN. If \p sNaN is true, returns if \p Op is known to never be a signaling
2969
  /// NaN.
2970
  virtual bool isKnownNeverNaNForTargetNode(SDValue Op,
2971
                                            const SelectionDAG &DAG,
2972
                                            bool SNaN = false,
2973
                                            unsigned Depth = 0) const;
2974
  struct DAGCombinerInfo {
2975
    void *DC;  // The DAG Combiner object.
2976
    CombineLevel Level;
2977
    bool CalledByLegalizer;
2978
2979
  public:
2980
    SelectionDAG &DAG;
2981
2982
    DAGCombinerInfo(SelectionDAG &dag, CombineLevel level,  bool cl, void *dc)
2983
27.0M
      : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2984
2985
7.23M
    bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2986
6.57M
    bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2987
304k
    bool isAfterLegalizeDAG() const {
2988
304k
      return Level == AfterLegalizeDAG;
2989
304k
    }
2990
169k
    CombineLevel getDAGCombineLevel() { return Level; }
2991
60.8k
    bool isCalledByLegalizer() const { return CalledByLegalizer; }
2992
2993
    void AddToWorklist(SDNode *N);
2994
    SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
2995
    SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2996
    SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2997
2998
    void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2999
  };
3000
3001
  /// Return if the N is a constant or constant vector equal to the true value
3002
  /// from getBooleanContents().
3003
  bool isConstTrueVal(const SDNode *N) const;
3004
3005
  /// Return if the N is a constant or constant vector equal to the false value
3006
  /// from getBooleanContents().
3007
  bool isConstFalseVal(const SDNode *N) const;
3008
3009
  /// Return if \p N is a True value when extended to \p VT.
3010
  bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const;
3011
3012
  /// Try to simplify a setcc built with the specified operands and cc. If it is
3013
  /// unable to simplify it, return a null SDValue.
3014
  SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
3015
                        bool foldBooleans, DAGCombinerInfo &DCI,
3016
                        const SDLoc &dl) const;
3017
3018
  // For targets which wrap address, unwrap for analysis.
3019
67.3M
  virtual SDValue unwrapAddress(SDValue N) const { return N; }
3020
3021
  /// Returns true (and the GlobalValue and the offset) if the node is a
3022
  /// GlobalAddress + offset.
3023
  virtual bool
3024
  isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
3025
3026
  /// This method will be invoked for all target nodes and for any
3027
  /// target-independent nodes that the target has registered with invoke it
3028
  /// for.
3029
  ///
3030
  /// The semantics are as follows:
3031
  /// Return Value:
3032
  ///   SDValue.Val == 0   - No change was made
3033
  ///   SDValue.Val == N   - N was replaced, is dead, and is already handled.
3034
  ///   otherwise          - N should be replaced by the returned Operand.
3035
  ///
3036
  /// In addition, methods provided by DAGCombinerInfo may be used to perform
3037
  /// more complex transformations.
3038
  ///
3039
  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
3040
3041
  /// Return true if it is profitable to move this shift by a constant amount
3042
  /// though its operand, adjusting any immediate operands as necessary to
3043
  /// preserve semantics. This transformation may not be desirable if it
3044
  /// disrupts a particularly auspicious target-specific tree (e.g. bitfield
3045
  /// extraction in AArch64). By default, it returns true.
3046
  ///
3047
  /// @param N the shift node
3048
  /// @param Level the current DAGCombine legalization level.
3049
  virtual bool isDesirableToCommuteWithShift(const SDNode *N,
3050
2.64k
                                             CombineLevel Level) const {
3051
2.64k
    return true;
3052
2.64k
  }
3053
3054
  // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
3055
  // to a shuffle and a truncate.
3056
  // Example of such a combine:
3057
  // v4i32 build_vector((extract_elt V, 1),
3058
  //                    (extract_elt V, 3),
3059
  //                    (extract_elt V, 5),
3060
  //                    (extract_elt V, 7))
3061
  //  -->
3062
  // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
3063
  virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(
3064
0
      ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
3065
0
    return false;
3066
0
  }
3067
3068
  /// Return true if the target has native support for the specified value type
3069
  /// and it is 'desirable' to use the type for the given node type. e.g. On x86
3070
  /// i16 is legal, but undesirable since i16 instruction encodings are longer
3071
  /// and some i16 instructions are slow.
3072
3.84M
  virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
3073
3.84M
    // By default, assume all legal types are desirable.
3074
3.84M
    return isTypeLegal(VT);
3075
3.84M
  }
3076
3077
  /// Return true if it is profitable for dag combiner to transform a floating
3078
  /// point op of specified opcode to a equivalent op of an integer
3079
  /// type. e.g. f32 load -> i32 load can be profitable on ARM.
3080
  virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
3081
395
                                                 EVT /*VT*/) const {
3082
395
    return false;
3083
395
  }
3084
3085
  /// This method query the target whether it is beneficial for dag combiner to
3086
  /// promote the specified node. If true, it should return the desired
3087
  /// promotion type by reference.
3088
4.61k
  virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
3089
4.61k
    return false;
3090
4.61k
  }
3091
3092
  /// Return true if the target supports swifterror attribute. It optimizes
3093
  /// loads and stores to reading and writing a specific register.
3094
442k
  virtual bool supportSwiftError() const {
3095
442k
    return false;
3096
442k
  }
3097
3098
  /// Return true if the target supports that a subset of CSRs for the given
3099
  /// machine function is handled explicitly via copies.
3100
30.9k
  virtual bool supportSplitCSR(MachineFunction *MF) const {
3101
30.9k
    return false;
3102
30.9k
  }
3103
3104
  /// Perform necessary initialization to handle a subset of CSRs explicitly
3105
  /// via copies. This function is called at the beginning of instruction
3106
  /// selection.
3107
0
  virtual void initializeSplitCSR(MachineBasicBlock *Entry) const {
3108
0
    llvm_unreachable("Not Implemented");
3109
0
  }
3110
3111
  /// Insert explicit copies in entry and exit blocks. We copy a subset of
3112
  /// CSRs to virtual registers in the entry block, and copy them back to
3113
  /// physical registers in the exit blocks. This function is called at the end
3114
  /// of instruction selection.
3115
  virtual void insertCopiesSplitCSR(
3116
      MachineBasicBlock *Entry,
3117
0
      const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
3118
0
    llvm_unreachable("Not Implemented");
3119
0
  }
3120
3121
  //===--------------------------------------------------------------------===//
3122
  // Lowering methods - These methods must be implemented by targets so that
3123
  // the SelectionDAGBuilder code knows how to lower these.
3124
  //
3125
3126
  /// This hook must be implemented to lower the incoming (formal) arguments,
3127
  /// described by the Ins array, into the specified DAG. The implementation
3128
  /// should fill in the InVals array with legal-type argument values, and
3129
  /// return the resulting token chain value.
3130
  virtual SDValue LowerFormalArguments(
3131
      SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
3132
      const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
3133
0
      SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
3134
0
    llvm_unreachable("Not Implemented");
3135
0
  }
3136
3137
  /// This structure contains all information that is necessary for lowering
3138
  /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
3139
  /// needs to lower a call, and targets will see this struct in their LowerCall
3140
  /// implementation.
3141
  struct CallLoweringInfo {
3142
    SDValue Chain;
3143
    Type *RetTy = nullptr;
3144
    bool RetSExt           : 1;
3145
    bool RetZExt           : 1;
3146
    bool IsVarArg          : 1;
3147
    bool IsInReg           : 1;
3148
    bool DoesNotReturn     : 1;
3149
    bool IsReturnValueUsed : 1;
3150
    bool IsConvergent      : 1;
3151
    bool IsPatchPoint      : 1;
3152
3153
    // IsTailCall should be modified by implementations of
3154
    // TargetLowering::LowerCall that perform tail call conversions.
3155
    bool IsTailCall = false;
3156
3157
    // Is Call lowering done post SelectionDAG type legalization.
3158
    bool IsPostTypeLegalization = false;
3159
3160
    unsigned NumFixedArgs = -1;
3161
    CallingConv::ID CallConv = CallingConv::C;
3162
    SDValue Callee;
3163
    ArgListTy Args;
3164
    SelectionDAG &DAG;
3165
    SDLoc DL;
3166
    ImmutableCallSite CS;
3167
    SmallVector<ISD::OutputArg, 32> Outs;
3168
    SmallVector<SDValue, 32> OutVals;
3169
    SmallVector<ISD::InputArg, 32> Ins;
3170
    SmallVector<SDValue, 4> InVals;
3171
3172
    CallLoweringInfo(SelectionDAG &DAG)
3173
        : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
3174
          DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
3175
991k
          IsPatchPoint(false), DAG(DAG) {}
3176
3177
991k
    CallLoweringInfo &setDebugLoc(const SDLoc &dl) {
3178
991k
      DL = dl;
3179
991k
      return *this;
3180
991k
    }
3181
3182
1.01M
    CallLoweringInfo &setChain(SDValue InChain) {
3183
1.01M
      Chain = InChain;
3184
1.01M
      return *this;
3185
1.01M
    }
3186
3187
    // setCallee with target/module-specific attributes
3188
    CallLoweringInfo &setLibCallee(CallingConv::ID CC, Type *ResultType,
3189
22.6k
                                   SDValue Target, ArgListTy &&ArgsList) {
3190
22.6k
      RetTy = ResultType;
3191
22.6k
      Callee = Target;
3192
22.6k
      CallConv = CC;
3193
22.6k
      NumFixedArgs = ArgsList.size();
3194
22.6k
      Args = std::move(ArgsList);
3195
22.6k
3196
22.6k
      DAG.getTargetLoweringInfo().markLibCallAttributes(
3197
22.6k
          &(DAG.getMachineFunction()), CC, Args);
3198
22.6k
      return *this;
3199
22.6k
    }
3200
3201
    CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
3202
606
                                SDValue Target, ArgListTy &&ArgsList) {
3203
606
      RetTy = ResultType;
3204
606
      Callee = Target;
3205
606
      CallConv = CC;
3206
606
      NumFixedArgs = ArgsList.size();
3207
606
      Args = std::move(ArgsList);
3208
606
      return *this;
3209
606
    }
3210
3211
    CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
3212
                                SDValue Target, ArgListTy &&ArgsList,
3213
968k
                                ImmutableCallSite Call) {
3214
968k
      RetTy = ResultType;
3215
968k
3216
968k
      IsInReg = Call.hasRetAttr(Attribute::InReg);
3217
968k
      DoesNotReturn =
3218
968k
          Call.doesNotReturn() ||
3219
968k
          
(921k
!Call.isInvoke()921k
&&
3220
921k
           
isa<UnreachableInst>(Call.getInstruction()->getNextNode())898k
);
3221
968k
      IsVarArg = FTy->isVarArg();
3222
968k
      IsReturnValueUsed = !Call.getInstruction()->use_empty();
3223
968k
      RetSExt = Call.hasRetAttr(Attribute::SExt);
3224
968k
      RetZExt = Call.hasRetAttr(Attribute::ZExt);
3225
968k
3226
968k
      Callee = Target;
3227
968k
3228
968k
      CallConv = Call.getCallingConv();
3229
968k
      NumFixedArgs = FTy->getNumParams();
3230
968k
      Args = std::move(ArgsList);
3231
968k
3232
968k
      CS = Call;
3233
968k
3234
968k
      return *this;
3235
968k
    }
3236
3237
199
    CallLoweringInfo &setInRegister(bool Value = true) {
3238
199
      IsInReg = Value;
3239
199
      return *this;
3240
199
    }
3241
3242
7.56k
    CallLoweringInfo &setNoReturn(bool Value = true) {
3243
7.56k
      DoesNotReturn = Value;
3244
7.56k
      return *this;
3245
7.56k
    }
3246
3247
    CallLoweringInfo &setVarArg(bool Value = true) {
3248
      IsVarArg = Value;
3249
      return *this;
3250
    }
3251
3252
976k
    CallLoweringInfo &setTailCall(bool Value = true) {
3253
976k
      IsTailCall = Value;
3254
976k
      return *this;
3255
976k
    }
3256
3257
17.1k
    CallLoweringInfo &setDiscardResult(bool Value = true) {
3258
17.1k
      IsReturnValueUsed = !Value;
3259
17.1k
      return *this;
3260
17.1k
    }
3261
3262
968k
    CallLoweringInfo &setConvergent(bool Value = true) {
3263
968k
      IsConvergent = Value;
3264
968k
      return *this;
3265
968k
    }
3266
3267
12.9k
    CallLoweringInfo &setSExtResult(bool Value = true) {
3268
12.9k
      RetSExt = Value;
3269
12.9k
      return *this;
3270
12.9k
    }
3271
3272
12.9k
    CallLoweringInfo &setZExtResult(bool Value = true) {
3273
12.9k
      RetZExt = Value;
3274
12.9k
      return *this;
3275
12.9k
    }
3276
3277
220
    CallLoweringInfo &setIsPatchPoint(bool Value = true) {
3278
220
      IsPatchPoint = Value;
3279
220
      return *this;
3280
220
    }
3281
3282
4.25k
    CallLoweringInfo &setIsPostTypeLegalization(bool Value=true) {
3283
4.25k
      IsPostTypeLegalization = Value;
3284
4.25k
      return *this;
3285
4.25k
    }
3286
3287
2.30M
    ArgListTy &getArgs() {
3288
2.30M
      return Args;
3289
2.30M
    }
3290
  };
3291
3292
  /// This function lowers an abstract call to a function into an actual call.
3293
  /// This returns a pair of operands.  The first element is the return value
3294
  /// for the function (if RetTy is not VoidTy).  The second element is the
3295
  /// outgoing token chain. It calls LowerCall to do the actual lowering.
3296
  std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
3297
3298
  /// This hook must be implemented to lower calls into the specified
3299
  /// DAG. The outgoing arguments to the call are described by the Outs array,
3300
  /// and the values to be returned by the call are described by the Ins
3301
  /// array. The implementation should fill in the InVals array with legal-type
3302
  /// return values from the call, and return the resulting token chain value.
3303
  virtual SDValue
3304
    LowerCall(CallLoweringInfo &/*CLI*/,
3305
0
              SmallVectorImpl<SDValue> &/*InVals*/) const {
3306
0
    llvm_unreachable("Not Implemented");
3307
0
  }
3308
3309
  /// Target-specific cleanup for formal ByVal parameters.
3310
1.69k
  virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
3311
3312
  /// This hook should be implemented to check whether the return values
3313
  /// described by the Outs array can fit into the return registers.  If false
3314
  /// is returned, an sret-demotion is performed.
3315
  virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
3316
                              MachineFunction &/*MF*/, bool /*isVarArg*/,
3317
               const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
3318
               LLVMContext &/*Context*/) const
3319
5.58k
  {
3320
5.58k
    // Return true by default to get preexisting behavior.
3321
5.58k
    return true;
3322
5.58k
  }
3323
3324
  /// This hook must be implemented to lower outgoing return values, described
3325
  /// by the Outs array, into the specified DAG. The implementation should
3326
  /// return the resulting token chain value.
3327
  virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
3328
                              bool /*isVarArg*/,
3329
                              const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
3330
                              const SmallVectorImpl<SDValue> & /*OutVals*/,
3331
                              const SDLoc & /*dl*/,
3332
0
                              SelectionDAG & /*DAG*/) const {
3333
0
    llvm_unreachable("Not Implemented");
3334
0
  }
3335
3336
  /// Return true if result of the specified node is used by a return node
3337
  /// only. It also compute and return the input chain for the tail call.
3338
  ///
3339
  /// This is used to determine whether it is possible to codegen a libcall as
3340
  /// tail call at legalization time.
3341
621
  virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
3342
621
    return false;
3343
621
  }
3344
3345
  /// Return true if the target may be able emit the call instruction as a tail
3346
  /// call. This is used by optimization passes to determine if it's profitable
3347
  /// to duplicate return instructions to enable tailcall optimization.
3348
188
  virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
3349
188
    return false;
3350
188
  }
3351
3352
  /// Return the builtin name for the __builtin___clear_cache intrinsic
3353
  /// Default is to invoke the clear cache library call
3354
2
  virtual const char * getClearCacheBuiltinName() const {
3355
2
    return "__clear_cache";
3356
2
  }
3357
3358
  /// Return the register ID of the name passed in. Used by named register
3359
  /// global variables extension. There is no target-independent behaviour
3360
  /// so the default action is to bail.
3361
  virtual unsigned getRegisterByName(const char* RegName, EVT VT,
3362
0
                                     SelectionDAG &DAG) const {
3363
0
    report_fatal_error("Named registers not implemented for this target");
3364
0
  }
3365
3366
  /// Return the type that should be used to zero or sign extend a
3367
  /// zeroext/signext integer return value.  FIXME: Some C calling conventions
3368
  /// require the return type to be promoted, but this is not true all the time,
3369
  /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3370
  /// conventions. The frontend should handle this and include all of the
3371
  /// necessary information.
3372
  virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
3373
4.65k
                                       ISD::NodeType /*ExtendKind*/) const {
3374
4.65k
    EVT MinVT = getRegisterType(Context, MVT::i32);
3375
4.65k
    return VT.bitsLT(MinVT) ? 
MinVT3.74k
:
VT905
;
3376
4.65k
  }
3377
3378
  /// For some targets, an LLVM struct type must be broken down into multiple
3379
  /// simple types, but the calling convention specifies that the entire struct
3380
  /// must be passed in a block of consecutive registers.
3381
  virtual bool
3382
  functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
3383
1.03M
                                            bool isVarArg) const {
3384
1.03M
    return false;
3385
1.03M
  }
3386
3387
  /// Returns a 0 terminated array of registers that can be safely used as
3388
  /// scratch registers.
3389
0
  virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
3390
0
    return nullptr;
3391
0
  }
3392
3393
  /// This callback is used to prepare for a volatile or atomic load.
3394
  /// It takes a chain node as input and returns the chain for the load itself.
3395
  ///
3396
  /// Having a callback like this is necessary for targets like SystemZ,
3397
  /// which allows a CPU to reuse the result of a previous load indefinitely,
3398
  /// even if a cache-coherent store is performed by another CPU.  The default
3399
  /// implementation does nothing.
3400
  virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL,
3401
26.5k
                                              SelectionDAG &DAG) const {
3402
26.5k
    return Chain;
3403
26.5k
  }
3404
3405
  /// This callback is used to inspect load/store instructions and add
3406
  /// target-specific MachineMemOperand flags to them.  The default
3407
  /// implementation does nothing.
3408
797k
  virtual MachineMemOperand::Flags getMMOFlags(const Instruction &I) const {
3409
797k
    return MachineMemOperand::MONone;
3410
797k
  }
3411
3412
  /// This callback is invoked by the type legalizer to legalize nodes with an
3413
  /// illegal operand type but legal result types.  It replaces the
3414
  /// LowerOperation callback in the type Legalizer.  The reason we can not do
3415
  /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3416
  /// use this callback.
3417
  ///
3418
  /// TODO: Consider merging with ReplaceNodeResults.
3419
  ///
3420
  /// The target places new result values for the node in Results (their number
3421
  /// and types must exactly match those of the original return values of
3422
  /// the node), or leaves Results empty, which indicates that the node is not
3423
  /// to be custom lowered after all.
3424
  /// The default implementation calls LowerOperation.
3425
  virtual void LowerOperationWrapper(SDNode *N,
3426
                                     SmallVectorImpl<SDValue> &Results,
3427
                                     SelectionDAG &DAG) const;
3428
3429
  /// This callback is invoked for operations that are unsupported by the
3430
  /// target, which are registered to use 'custom' lowering, and whose defined
3431
  /// values are all legal.  If the target has no operations that require custom
3432
  /// lowering, it need not implement this.  The default implementation of this
3433
  /// aborts.
3434
  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
3435
3436
  /// This callback is invoked when a node result type is illegal for the
3437
  /// target, and the operation was registered to use 'custom' lowering for that
3438
  /// result type.  The target places new result values for the node in Results
3439
  /// (their number and types must exactly match those of the original return
3440
  /// values of the node), or leaves Results empty, which indicates that the
3441
  /// node is not to be custom lowered after all.
3442
  ///
3443
  /// If the target has no operations that require custom lowering, it need not
3444
  /// implement this.  The default implementation aborts.
3445
  virtual void ReplaceNodeResults(SDNode * /*N*/,
3446
                                  SmallVectorImpl<SDValue> &/*Results*/,
3447
0
                                  SelectionDAG &/*DAG*/) const {
3448
0
    llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3449
0
  }
3450
3451
  /// This method returns the name of a target specific DAG node.
3452
  virtual const char *getTargetNodeName(unsigned Opcode) const;
3453
3454
  /// This method returns a target specific FastISel object, or null if the
3455
  /// target does not support "fast" ISel.
3456
  virtual FastISel *createFastISel(FunctionLoweringInfo &,
3457
2.65k
                                   const TargetLibraryInfo *) const {
3458
2.65k
    return nullptr;
3459
2.65k
  }
3460
3461
  bool verifyReturnAddressArgumentIsConstant(SDValue Op,
3462
                                             SelectionDAG &DAG) const;
3463
3464
  //===--------------------------------------------------------------------===//
3465
  // Inline Asm Support hooks
3466
  //
3467
3468
  /// This hook allows the target to expand an inline asm call to be explicit
3469
  /// llvm code if it wants to.  This is useful for turning simple inline asms
3470
  /// into LLVM intrinsics, which gives the compiler more information about the
3471
  /// behavior of the code.
3472
7.21k
  virtual bool ExpandInlineAsm(CallInst *) const {
3473
7.21k
    return false;
3474
7.21k
  }
3475
3476
  enum ConstraintType {
3477
    C_Register,            // Constraint represents specific register(s).
3478
    C_RegisterClass,       // Constraint represents any of register(s) in class.
3479
    C_Memory,              // Memory constraint.
3480
    C_Other,               // Something else.
3481
    C_Unknown              // Unsupported constraint.
3482
  };
3483
3484
  enum ConstraintWeight {
3485
    // Generic weights.
3486
    CW_Invalid  = -1,     // No match.
3487
    CW_Okay     = 0,      // Acceptable.
3488
    CW_Good     = 1,      // Good weight.
3489
    CW_Better   = 2,      // Better weight.
3490
    CW_Best     = 3,      // Best weight.
3491
3492
    // Well-known weights.
3493
    CW_SpecificReg  = CW_Okay,    // Specific register operands.
3494
    CW_Register     = CW_Good,    // Register operands.
3495
    CW_Memory       = CW_Better,  // Memory operands.
3496
    CW_Constant     = CW_Best,    // Constant operand.
3497
    CW_Default      = CW_Okay     // Default or don't know type.
3498
  };
3499
3500
  /// This contains information for each constraint that we are lowering.
3501
  struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3502
    /// This contains the actual string for the code, like "m".  TargetLowering
3503
    /// picks the 'best' code from ConstraintInfo::Codes that most closely
3504
    /// matches the operand.
3505
    std::string ConstraintCode;
3506
3507
    /// Information about the constraint code, e.g. Register, RegisterClass,
3508
    /// Memory, Other, Unknown.
3509
    TargetLowering::ConstraintType ConstraintType = TargetLowering::C_Unknown;
3510
3511
    /// If this is the result output operand or a clobber, this is null,
3512
    /// otherwise it is the incoming operand to the CallInst.  This gets
3513
    /// modified as the asm is processed.
3514
    Value *CallOperandVal = nullptr;
3515
3516
    /// The ValueType for the operand value.
3517
    MVT ConstraintVT = MVT::Other;
3518
3519
    /// Copy constructor for copying from a ConstraintInfo.
3520
    AsmOperandInfo(InlineAsm::ConstraintInfo Info)
3521
455k
        : InlineAsm::ConstraintInfo(std::move(Info)) {}
3522
3523
    /// Return true of this is an input operand that is a matching constraint
3524
    /// like "4".
3525
    bool isMatchingInputConstraint() const;
3526
3527
    /// If this is an input matching constraint, this method returns the output
3528
    /// operand it matches.
3529
    unsigned getMatchedOperand() const;
3530
  };
3531
3532
  using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
3533
3534
  /// Split up the constraint string from the inline assembly value into the
3535
  /// specific constraints and their prefixes, and also tie in the associated
3536
  /// operand values.  If this returns an empty vector, and if the constraint
3537
  /// string itself isn't empty, there was an error parsing.
3538
  virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
3539
                                                const TargetRegisterInfo *TRI,
3540
                                                ImmutableCallSite CS) const;
3541
3542
  /// Examine constraint type and operand type and determine a weight value.
3543
  /// The operand object must already have been set up with the operand type.
3544
  virtual ConstraintWeight getMultipleConstraintMatchWeight(
3545
      AsmOperandInfo &info, int maIndex) const;
3546
3547
  /// Examine constraint string and operand type and determine a weight value.
3548
  /// The operand object must already have been set up with the operand type.
3549
  virtual ConstraintWeight getSingleConstraintMatchWeight(
3550
      AsmOperandInfo &info, const char *constraint) const;
3551
3552
  /// Determines the constraint code and constraint type to use for the specific
3553
  /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3554
  /// If the actual operand being passed in is available, it can be passed in as
3555
  /// Op, otherwise an empty SDValue can be passed.
3556
  virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3557
                                      SDValue Op,
3558
                                      SelectionDAG *DAG = nullptr) const;
3559
3560
  /// Given a constraint, return the type of constraint it is for this target.
3561
  virtual ConstraintType getConstraintType(StringRef Constraint) const;
3562
3563
  /// Given a physical register constraint (e.g.  {edx}), return the register
3564
  /// number and the register class for the register.
3565
  ///
3566
  /// Given a register class constraint, like 'r', if this corresponds directly
3567
  /// to an LLVM register class, return a register of 0 and the register class
3568
  /// pointer.
3569
  ///
3570
  /// This should only be used for C_Register constraints.  On error, this
3571
  /// returns a register number of 0 and a null register class pointer.
3572
  virtual std::pair<unsigned, const TargetRegisterClass *>
3573
  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3574
                               StringRef Constraint, MVT VT) const;
3575
3576
3.22k
  virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
3577
3.22k
    if (ConstraintCode == "i")
3578
0
      return InlineAsm::Constraint_i;
3579
3.22k
    else if (ConstraintCode == "m")
3580
3.22k
      return InlineAsm::Constraint_m;
3581
0
    return InlineAsm::Constraint_Unknown;
3582
0
  }
3583
3584
  /// Try to replace an X constraint, which matches anything, with another that
3585
  /// has more specific requirements based on the type of the corresponding
3586
  /// operand.  This returns null if there is no replacement to make.
3587
  virtual const char *LowerXConstraint(EVT ConstraintVT) const;
3588
3589
  /// Lower the specified operand into the Ops vector.  If it is invalid, don't
3590
  /// add anything to Ops.
3591
  virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
3592
                                            std::vector<SDValue> &Ops,
3593
                                            SelectionDAG &DAG) const;
3594
3595
  //===--------------------------------------------------------------------===//
3596
  // Div utility functions
3597
  //
3598
  SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3599
                    SmallVectorImpl<SDNode *> &Created) const;
3600
  SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3601
                    SmallVectorImpl<SDNode *> &Created) const;
3602
3603
  /// Targets may override this function to provide custom SDIV lowering for
3604
  /// power-of-2 denominators.  If the target returns an empty SDValue, LLVM
3605
  /// assumes SDIV is expensive and replaces it with a series of other integer
3606
  /// operations.
3607
  virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
3608
                                SelectionDAG &DAG,
3609
                                SmallVectorImpl<SDNode *> &Created) const;
3610
3611
  /// Indicate whether this target prefers to combine FDIVs with the same
3612
  /// divisor. If the transform should never be done, return zero. If the
3613
  /// transform should be done, return the minimum number of divisor uses
3614
  /// that must exist.
3615
52
  virtual unsigned combineRepeatedFPDivisors() const {
3616
52
    return 0;
3617
52
  }
3618
3619
  /// Hooks for building estimates in place of slower divisions and square
3620
  /// roots.
3621
3622
  /// Return either a square root or its reciprocal estimate value for the input
3623
  /// operand.
3624
  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3625
  /// 'Enabled' as set by a potential default override attribute.
3626
  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3627
  /// refinement iterations required to generate a sufficient (though not
3628
  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3629
  /// The boolean UseOneConstNR output is used to select a Newton-Raphson
3630
  /// algorithm implementation that uses either one or two constants.
3631
  /// The boolean Reciprocal is used to select whether the estimate is for the
3632
  /// square root of the input operand or the reciprocal of its square root.
3633
  /// A target may choose to implement its own refinement within this function.
3634
  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3635
  /// any further refinement of the estimate.
3636
  /// An empty SDValue return means no estimate sequence can be created.
3637
  virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
3638
                                  int Enabled, int &RefinementSteps,
3639
16
                                  bool &UseOneConstNR, bool Reciprocal) const {
3640
16
    return SDValue();
3641
16
  }
3642
3643
  /// Return a reciprocal estimate value for the input operand.
3644
  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3645
  /// 'Enabled' as set by a potential default override attribute.
3646
  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3647
  /// refinement iterations required to generate a sufficient (though not
3648
  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3649
  /// A target may choose to implement its own refinement within this function.
3650
  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3651
  /// any further refinement of the estimate.
3652
  /// An empty SDValue return means no estimate sequence can be created.
3653
  virtual SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG,
3654
42
                                   int Enabled, int &RefinementSteps) const {
3655
42
    return SDValue();
3656
42
  }
3657
3658
  //===--------------------------------------------------------------------===//
3659
  // Legalization utility functions
3660
  //
3661
3662
  /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
3663
  /// respectively, each computing an n/2-bit part of the result.
3664
  /// \param Result A vector that will be filled with the parts of the result
3665
  ///        in little-endian order.
3666
  /// \param LL Low bits of the LHS of the MUL.  You can use this parameter
3667
  ///        if you want to control how low bits are extracted from the LHS.
3668
  /// \param LH High bits of the LHS of the MUL.  See LL for meaning.
3669
  /// \param RL Low bits of the RHS of the MUL.  See LL for meaning
3670
  /// \param RH High bits of the RHS of the MUL.  See LL for meaning.
3671
  /// \returns true if the node has been expanded, false if it has not
3672
  bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
3673
                      SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
3674
                      SelectionDAG &DAG, MulExpansionKind Kind,
3675
                      SDValue LL = SDValue(), SDValue LH = SDValue(),
3676
                      SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3677
3678
  /// Expand a MUL into two nodes.  One that computes the high bits of
3679
  /// the result and one that computes the low bits.
3680
  /// \param HiLoVT The value type to use for the Lo and Hi nodes.
3681
  /// \param LL Low bits of the LHS of the MUL.  You can use this parameter
3682
  ///        if you want to control how low bits are extracted from the LHS.
3683
  /// \param LH High bits of the LHS of the MUL.  See LL for meaning.
3684
  /// \param RL Low bits of the RHS of the MUL.  See LL for meaning
3685
  /// \param RH High bits of the RHS of the MUL.  See LL for meaning.
3686
  /// \returns true if the node has been expanded. false if it has not
3687
  bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
3688
                 SelectionDAG &DAG, MulExpansionKind Kind,
3689
                 SDValue LL = SDValue(), SDValue LH = SDValue(),
3690
                 SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3691
3692
  /// Expand funnel shift.
3693
  /// \param N Node to expand
3694
  /// \param Result output after conversion
3695
  /// \returns True, if the expansion was successful, false otherwise
3696
  bool expandFunnelShift(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3697
3698
  /// Expand float(f32) to SINT(i64) conversion
3699
  /// \param N Node to expand
3700
  /// \param Result output after conversion
3701
  /// \returns True, if the expansion was successful, false otherwise
3702
  bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3703
3704
  /// Expand float to UINT conversion
3705
  /// \param N Node to expand
3706
  /// \param Result output after conversion
3707
  /// \returns True, if the expansion was successful, false otherwise
3708
  bool expandFP_TO_UINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3709
3710
  /// Expand UINT(i64) to double(f64) conversion
3711
  /// \param N Node to expand
3712
  /// \param Result output after conversion
3713
  /// \returns True, if the expansion was successful, false otherwise
3714
  bool expandUINT_TO_FP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3715
3716
  /// Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.
3717
  SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const;
3718
3719
  /// Expand CTPOP nodes. Expands vector/scalar CTPOP nodes,
3720
  /// vector nodes can only succeed if all operations are legal/custom.
3721
  /// \param N Node to expand
3722
  /// \param Result output after conversion
3723
  /// \returns True, if the expansion was successful, false otherwise
3724
  bool expandCTPOP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3725
3726
  /// Expand CTLZ/CTLZ_ZERO_UNDEF nodes. Expands vector/scalar CTLZ nodes,
3727
  /// vector nodes can only succeed if all operations are legal/custom.
3728
  /// \param N Node to expand
3729
  /// \param Result output after conversion
3730
  /// \returns True, if the expansion was successful, false otherwise
3731
  bool expandCTLZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3732
3733
  /// Expand CTTZ/CTTZ_ZERO_UNDEF nodes. Expands vector/scalar CTTZ nodes,
3734
  /// vector nodes can only succeed if all operations are legal/custom.
3735
  /// \param N Node to expand
3736
  /// \param Result output after conversion
3737
  /// \returns True, if the expansion was successful, false otherwise
3738
  bool expandCTTZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3739
3740
  /// Turn load of vector type into a load of the individual elements.
3741
  /// \param LD load to expand
3742
  /// \returns MERGE_VALUEs of the scalar loads with their chains.
3743
  SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
3744
3745
  // Turn a store of a vector type into stores of the individual elements.
3746
  /// \param ST Store with a vector value type
3747
  /// \returns MERGE_VALUs of the individual store chains.
3748
  SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3749
3750
  /// Expands an unaligned load to 2 half-size loads for an integer, and
3751
  /// possibly more for vectors.
3752
  std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
3753
                                                  SelectionDAG &DAG) const;
3754
3755
  /// Expands an unaligned store to 2 half-size stores for integer values, and
3756
  /// possibly more for vectors.
3757
  SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3758
3759
  /// Increments memory address \p Addr according to the type of the value
3760
  /// \p DataVT that should be stored. If the data is stored in compressed
3761
  /// form, the memory address should be incremented according to the number of
3762
  /// the stored elements. This number is equal to the number of '1's bits
3763
  /// in the \p Mask.
3764
  /// \p DataVT is a vector type. \p Mask is a vector value.
3765
  /// \p DataVT and \p Mask have the same number of vector elements.
3766
  SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
3767
                                 EVT DataVT, SelectionDAG &DAG,
3768
                                 bool IsCompressedMemory) const;
3769
3770
  /// Get a pointer to vector element \p Idx located in memory for a vector of
3771
  /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
3772
  /// bounds the returned pointer is unspecified, but will be within the vector
3773
  /// bounds.
3774
  SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
3775
                                  SDValue Index) const;
3776
3777
  /// Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. This
3778
  /// method accepts integers or vectors of integers as its arguments.
3779
  SDValue getExpandedSaturationAdditionSubtraction(SDNode *Node,
3780
                                                   SelectionDAG &DAG) const;
3781
3782
  //===--------------------------------------------------------------------===//
3783
  // Instruction Emitting Hooks
3784
  //
3785
3786
  /// This method should be implemented by targets that mark instructions with
3787
  /// the 'usesCustomInserter' flag.  These instructions are special in various
3788
  /// ways, which require special support to insert.  The specified MachineInstr
3789
  /// is created but not inserted into any basic blocks, and this method is
3790
  /// called to expand it into a sequence of instructions, potentially also
3791
  /// creating new basic blocks and control flow.
3792
  /// As long as the returned basic block is different (i.e., we created a new
3793
  /// one), the custom inserter is free to modify the rest of \p MBB.
3794
  virtual MachineBasicBlock *
3795
  EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
3796
3797
  /// This method should be implemented by targets that mark instructions with
3798
  /// the 'hasPostISelHook' flag. These instructions must be adjusted after
3799
  /// instruction selection by target hooks.  e.g. To fill in optional defs for
3800
  /// ARM 's' setting instructions.
3801
  virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
3802
                                             SDNode *Node) const;
3803
3804
  /// If this function returns true, SelectionDAGBuilder emits a
3805
  /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
3806
21
  virtual bool useLoadStackGuardNode() const {
3807
21
    return false;
3808
21
  }
3809
3810
  virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
3811
0
                                      const SDLoc &DL) const {
3812
0
    llvm_unreachable("not implemented for this target");
3813
0
  }
3814
3815
  /// Lower TLS global address SDNode for target independent emulated TLS model.
3816
  virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
3817
                                          SelectionDAG &DAG) const;
3818
3819
  /// Expands target specific indirect branch for the case of JumpTable
3820
  /// expanasion.
3821
  virtual SDValue expandIndirectJTBranch(const SDLoc& dl, SDValue Value, SDValue Addr,
3822
549
                                         SelectionDAG &DAG) const {
3823
549
    return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
3824
549
  }
3825
3826
  // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
3827
  // If we're comparing for equality to zero and isCtlzFast is true, expose the
3828
  // fact that this can be implemented as a ctlz/srl pair, so that the dag
3829
  // combiner can fold the new nodes.
3830
  SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
3831
3832
private:
3833
  SDValue simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
3834
                               ISD::CondCode Cond, DAGCombinerInfo &DCI,
3835
                               const SDLoc &DL) const;
3836
3837
  SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0,
3838
                                               SDValue N1, ISD::CondCode Cond,
3839
                                               DAGCombinerInfo &DCI,
3840
                                               const SDLoc &DL) const;
3841
};
3842
3843
/// Given an LLVM IR type and return type attributes, compute the return value
3844
/// EVTs and flags, and optionally also the offsets, if the return value is
3845
/// being lowered to memory.
3846
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr,
3847
                   SmallVectorImpl<ISD::OutputArg> &Outs,
3848
                   const TargetLowering &TLI, const DataLayout &DL);
3849
3850
} // end namespace llvm
3851
3852
#endif // LLVM_CODEGEN_TARGETLOWERING_H