Coverage Report

Created: 2018-09-25 17:16

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/TargetLowering.h
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//===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file describes how to lower LLVM code to machine code.  This has two
12
/// main components:
13
///
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///  1. Which ValueTypes are natively supported by the target.
15
///  2. Which operations are supported for supported ValueTypes.
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///  3. Cost thresholds for alternative implementations of certain operations.
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///
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/// In addition it has a few other components, like information about FP
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/// immediates.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_TARGETLOWERING_H
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#define LLVM_CODEGEN_TARGETLOWERING_H
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26
#include "llvm/ADT/APInt.h"
27
#include "llvm/ADT/ArrayRef.h"
28
#include "llvm/ADT/DenseMap.h"
29
#include "llvm/ADT/STLExtras.h"
30
#include "llvm/ADT/SmallVector.h"
31
#include "llvm/ADT/StringRef.h"
32
#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
33
#include "llvm/CodeGen/DAGCombine.h"
34
#include "llvm/CodeGen/ISDOpcodes.h"
35
#include "llvm/CodeGen/RuntimeLibcalls.h"
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#include "llvm/CodeGen/SelectionDAG.h"
37
#include "llvm/CodeGen/SelectionDAGNodes.h"
38
#include "llvm/CodeGen/TargetCallingConv.h"
39
#include "llvm/CodeGen/ValueTypes.h"
40
#include "llvm/IR/Attributes.h"
41
#include "llvm/IR/CallSite.h"
42
#include "llvm/IR/CallingConv.h"
43
#include "llvm/IR/DataLayout.h"
44
#include "llvm/IR/DerivedTypes.h"
45
#include "llvm/IR/Function.h"
46
#include "llvm/IR/IRBuilder.h"
47
#include "llvm/IR/InlineAsm.h"
48
#include "llvm/IR/Instruction.h"
49
#include "llvm/IR/Instructions.h"
50
#include "llvm/IR/Type.h"
51
#include "llvm/MC/MCRegisterInfo.h"
52
#include "llvm/Support/AtomicOrdering.h"
53
#include "llvm/Support/Casting.h"
54
#include "llvm/Support/ErrorHandling.h"
55
#include "llvm/Support/MachineValueType.h"
56
#include "llvm/Target/TargetMachine.h"
57
#include <algorithm>
58
#include <cassert>
59
#include <climits>
60
#include <cstdint>
61
#include <iterator>
62
#include <map>
63
#include <string>
64
#include <utility>
65
#include <vector>
66
67
namespace llvm {
68
69
class BranchProbability;
70
class CCState;
71
class CCValAssign;
72
class Constant;
73
class FastISel;
74
class FunctionLoweringInfo;
75
class GlobalValue;
76
class IntrinsicInst;
77
struct KnownBits;
78
class LLVMContext;
79
class MachineBasicBlock;
80
class MachineFunction;
81
class MachineInstr;
82
class MachineJumpTableInfo;
83
class MachineLoop;
84
class MachineRegisterInfo;
85
class MCContext;
86
class MCExpr;
87
class Module;
88
class TargetRegisterClass;
89
class TargetLibraryInfo;
90
class TargetRegisterInfo;
91
class Value;
92
93
namespace Sched {
94
95
  enum Preference {
96
    None,             // No preference
97
    Source,           // Follow source order.
98
    RegPressure,      // Scheduling for lowest register pressure.
99
    Hybrid,           // Scheduling for both latency and register pressure.
100
    ILP,              // Scheduling for ILP in low register pressure mode.
101
    VLIW              // Scheduling for VLIW targets.
102
  };
103
104
} // end namespace Sched
105
106
/// This base class for TargetLowering contains the SelectionDAG-independent
107
/// parts that can be used from the rest of CodeGen.
108
class TargetLoweringBase {
109
public:
110
  /// This enum indicates whether operations are valid for a target, and if not,
111
  /// what action should be used to make them valid.
112
  enum LegalizeAction : uint8_t {
113
    Legal,      // The target natively supports this operation.
114
    Promote,    // This operation should be executed in a larger type.
115
    Expand,     // Try to expand this to other ops, otherwise use a libcall.
116
    LibCall,    // Don't try to expand this to other ops, always use a libcall.
117
    Custom      // Use the LowerOperation hook to implement custom lowering.
118
  };
119
120
  /// This enum indicates whether a types are legal for a target, and if not,
121
  /// what action should be used to make them valid.
122
  enum LegalizeTypeAction : uint8_t {
123
    TypeLegal,           // The target natively supports this type.
124
    TypePromoteInteger,  // Replace this integer with a larger one.
125
    TypeExpandInteger,   // Split this integer into two of half the size.
126
    TypeSoftenFloat,     // Convert this float to a same size integer type,
127
                         // if an operation is not supported in target HW.
128
    TypeExpandFloat,     // Split this float into two of half the size.
129
    TypeScalarizeVector, // Replace this one-element vector with its element.
130
    TypeSplitVector,     // Split this vector into two of half the size.
131
    TypeWidenVector,     // This vector should be widened into a larger vector.
132
    TypePromoteFloat     // Replace this float with a larger one.
133
  };
134
135
  /// LegalizeKind holds the legalization kind that needs to happen to EVT
136
  /// in order to type-legalize it.
137
  using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
138
139
  /// Enum that describes how the target represents true/false values.
140
  enum BooleanContent {
141
    UndefinedBooleanContent,    // Only bit 0 counts, the rest can hold garbage.
142
    ZeroOrOneBooleanContent,        // All bits zero except for bit 0.
143
    ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
144
  };
145
146
  /// Enum that describes what type of support for selects the target has.
147
  enum SelectSupportKind {
148
    ScalarValSelect,      // The target supports scalar selects (ex: cmov).
149
    ScalarCondVectorVal,  // The target supports selects with a scalar condition
150
                          // and vector values (ex: cmov).
151
    VectorMaskSelect      // The target supports vector selects with a vector
152
                          // mask (ex: x86 blends).
153
  };
154
155
  /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
156
  /// to, if at all. Exists because different targets have different levels of
157
  /// support for these atomic instructions, and also have different options
158
  /// w.r.t. what they should expand to.
159
  enum class AtomicExpansionKind {
160
    None,    // Don't expand the instruction.
161
    LLSC,    // Expand the instruction into loadlinked/storeconditional; used
162
             // by ARM/AArch64.
163
    LLOnly,  // Expand the (load) instruction into just a load-linked, which has
164
             // greater atomic guarantees than a normal load.
165
    CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
166
    MaskedIntrinsic, // Use a target-specific intrinsic for the LL/SC loop.
167
  };
168
169
  /// Enum that specifies when a multiplication should be expanded.
170
  enum class MulExpansionKind {
171
    Always,            // Always expand the instruction.
172
    OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
173
                       // or custom.
174
  };
175
176
  class ArgListEntry {
177
  public:
178
    Value *Val = nullptr;
179
    SDValue Node = SDValue();
180
    Type *Ty = nullptr;
181
    bool IsSExt : 1;
182
    bool IsZExt : 1;
183
    bool IsInReg : 1;
184
    bool IsSRet : 1;
185
    bool IsNest : 1;
186
    bool IsByVal : 1;
187
    bool IsInAlloca : 1;
188
    bool IsReturned : 1;
189
    bool IsSwiftSelf : 1;
190
    bool IsSwiftError : 1;
191
    uint16_t Alignment = 0;
192
193
    ArgListEntry()
194
        : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
195
          IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
196
1.80M
          IsSwiftSelf(false), IsSwiftError(false) {}
197
198
    void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx);
199
  };
200
  using ArgListTy = std::vector<ArgListEntry>;
201
202
  virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
203
17.3k
                                     ArgListTy &Args) const {};
204
205
294k
  static ISD::NodeType getExtendForContent(BooleanContent Content) {
206
294k
    switch (Content) {
207
294k
    case UndefinedBooleanContent:
208
104
      // Extend by adding rubbish bits.
209
104
      return ISD::ANY_EXTEND;
210
294k
    case ZeroOrOneBooleanContent:
211
292k
      // Extend by adding zero bits.
212
292k
      return ISD::ZERO_EXTEND;
213
294k
    case ZeroOrNegativeOneBooleanContent:
214
1.27k
      // Extend by copying the sign bit.
215
1.27k
      return ISD::SIGN_EXTEND;
216
0
    }
217
0
    llvm_unreachable("Invalid content kind");
218
0
  }
219
220
  /// NOTE: The TargetMachine owns TLOF.
221
  explicit TargetLoweringBase(const TargetMachine &TM);
222
  TargetLoweringBase(const TargetLoweringBase &) = delete;
223
  TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
224
33.9k
  virtual ~TargetLoweringBase() = default;
225
226
protected:
227
  /// Initialize all of the actions to default values.
228
  void initActions();
229
230
public:
231
11.9M
  const TargetMachine &getTargetMachine() const { return TM; }
232
233
3.13M
  virtual bool useSoftFloat() const { return false; }
234
235
  /// Return the pointer type for the given address space, defaults to
236
  /// the pointer type from the data layout.
237
  /// FIXME: The default needs to be removed once all the code is updated.
238
30.0M
  MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
239
30.0M
    return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
240
30.0M
  }
241
242
  /// Return the type for frame index, which is determined by
243
  /// the alloca address space specified through the data layout.
244
538k
  MVT getFrameIndexTy(const DataLayout &DL) const {
245
538k
    return getPointerTy(DL, DL.getAllocaAddrSpace());
246
538k
  }
247
248
  /// Return the type for operands of fence.
249
  /// TODO: Let fence operands be of i32 type and remove this.
250
7.82k
  virtual MVT getFenceOperandTy(const DataLayout &DL) const {
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7.82k
    return getPointerTy(DL);
252
7.82k
  }
253
254
  /// EVT is not used in-tree, but is used by out-of-tree target.
255
  /// A documentation for this function would be nice...
256
  virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
257
258
  EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
259
                       bool LegalTypes = true) const;
260
261
  /// Returns the type to be used for the index operand of:
262
  /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
263
  /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
264
228k
  virtual MVT getVectorIdxTy(const DataLayout &DL) const {
265
228k
    return getPointerTy(DL);
266
228k
  }
267
268
252k
  virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
269
252k
    return true;
270
252k
  }
271
272
  /// Return true if multiple condition registers are available.
273
3.63M
  bool hasMultipleConditionRegisters() const {
274
3.63M
    return HasMultipleConditionRegisters;
275
3.63M
  }
276
277
  /// Return true if the target has BitExtract instructions.
278
183k
  bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
279
280
  /// Return the preferred vector type legalization action.
281
  virtual TargetLoweringBase::LegalizeTypeAction
282
3.59M
  getPreferredVectorAction(EVT VT) const {
283
3.59M
    // The default action for one element vectors is to scalarize
284
3.59M
    if (VT.getVectorNumElements() == 1)
285
579k
      return TypeScalarizeVector;
286
3.01M
    // The default action for other vectors is to promote
287
3.01M
    return TypePromoteInteger;
288
3.01M
  }
289
290
  // There are two general methods for expanding a BUILD_VECTOR node:
291
  //  1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
292
  //     them together.
293
  //  2. Build the vector on the stack and then load it.
294
  // If this function returns true, then method (1) will be used, subject to
295
  // the constraint that all of the necessary shuffles are legal (as determined
296
  // by isShuffleMaskLegal). If this function returns false, then method (2) is
297
  // always used. The vector type, and the number of defined values, are
298
  // provided.
299
  virtual bool
300
  shouldExpandBuildVectorWithShuffles(EVT /* VT */,
301
2.23k
                                      unsigned DefinedValues) const {
302
2.23k
    return DefinedValues < 3;
303
2.23k
  }
304
305
  /// Return true if integer divide is usually cheaper than a sequence of
306
  /// several shifts, adds, and multiplies for this target.
307
  /// The definition of "cheaper" may depend on whether we're optimizing
308
  /// for speed or for size.
309
653
  virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
310
311
  /// Return true if the target can handle a standalone remainder operation.
312
0
  virtual bool hasStandaloneRem(EVT VT) const {
313
0
    return true;
314
0
  }
315
316
  /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
317
130
  virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
318
130
    // Default behavior is to replace SQRT(X) with X*RSQRT(X).
319
130
    return false;
320
130
  }
321
322
  /// Reciprocal estimate status values used by the functions below.
323
  enum ReciprocalEstimate : int {
324
    Unspecified = -1,
325
    Disabled = 0,
326
    Enabled = 1
327
  };
328
329
  /// Return a ReciprocalEstimate enum value for a square root of the given type
330
  /// based on the function's attributes. If the operation is not overridden by
331
  /// the function's attributes, "Unspecified" is returned and target defaults
332
  /// are expected to be used for instruction selection.
333
  int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
334
335
  /// Return a ReciprocalEstimate enum value for a division of the given type
336
  /// based on the function's attributes. If the operation is not overridden by
337
  /// the function's attributes, "Unspecified" is returned and target defaults
338
  /// are expected to be used for instruction selection.
339
  int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
340
341
  /// Return the refinement step count for a square root of the given type based
342
  /// on the function's attributes. If the operation is not overridden by
343
  /// the function's attributes, "Unspecified" is returned and target defaults
344
  /// are expected to be used for instruction selection.
345
  int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
346
347
  /// Return the refinement step count for a division of the given type based
348
  /// on the function's attributes. If the operation is not overridden by
349
  /// the function's attributes, "Unspecified" is returned and target defaults
350
  /// are expected to be used for instruction selection.
351
  int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
352
353
  /// Returns true if target has indicated at least one type should be bypassed.
354
451k
  bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
355
356
  /// Returns map of slow types for division or remainder with corresponding
357
  /// fast types
358
17.5k
  const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
359
17.5k
    return BypassSlowDivWidths;
360
17.5k
  }
361
362
  /// Return true if Flow Control is an expensive operation that should be
363
  /// avoided.
364
63.3k
  bool isJumpExpensive() const { return JumpIsExpensive; }
365
366
  /// Return true if selects are only cheaper than branches if the branch is
367
  /// unlikely to be predicted right.
368
261k
  bool isPredictableSelectExpensive() const {
369
261k
    return PredictableSelectIsExpensive;
370
261k
  }
371
372
  /// If a branch or a select condition is skewed in one direction by more than
373
  /// this factor, it is very likely to be predicted correctly.
374
  virtual BranchProbability getPredictableBranchThreshold() const;
375
376
  /// Return true if the following transform is beneficial:
377
  /// fold (conv (load x)) -> (load (conv*)x)
378
  /// On architectures that don't natively support some vector loads
379
  /// efficiently, casting the load to a smaller vector of larger types and
380
  /// loading is more efficient, however, this can be undone by optimizations in
381
  /// dag combiner.
382
  virtual bool isLoadBitCastBeneficial(EVT LoadVT,
383
17.8k
                                       EVT BitcastVT) const {
384
17.8k
    // Don't do if we could do an indexed load on the original type, but not on
385
17.8k
    // the new one.
386
17.8k
    if (!LoadVT.isSimple() || 
!BitcastVT.isSimple()17.7k
)
387
83
      return true;
388
17.7k
389
17.7k
    MVT LoadMVT = LoadVT.getSimpleVT();
390
17.7k
391
17.7k
    // Don't bother doing this if it's just going to be promoted again later, as
392
17.7k
    // doing so might interfere with other combines.
393
17.7k
    if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
394
17.7k
        
getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT()7.74k
)
395
6.08k
      return false;
396
11.6k
397
11.6k
    return true;
398
11.6k
  }
399
400
  /// Return true if the following transform is beneficial:
401
  /// (store (y (conv x)), y*)) -> (store x, (x*))
402
22.6k
  virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {
403
22.6k
    // Default to the same logic as loads.
404
22.6k
    return isLoadBitCastBeneficial(StoreVT, BitcastVT);
405
22.6k
  }
406
407
  /// Return true if it is expected to be cheaper to do a store of a non-zero
408
  /// vector constant with the given size and type for the address space than to
409
  /// store the individual scalar element constants.
410
  virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
411
                                            unsigned NumElem,
412
194k
                                            unsigned AddrSpace) const {
413
194k
    return false;
414
194k
  }
415
416
  /// Allow store merging after legalization in addition to before legalization.
417
  /// This may catch stores that do not exist earlier (eg, stores created from
418
  /// intrinsics).
419
1.33M
  virtual bool mergeStoresAfterLegalization() const { return true; }
420
421
  /// Returns if it's reasonable to merge stores to MemVT size.
422
  virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
423
7.14k
                                const SelectionDAG &DAG) const {
424
7.14k
    return true;
425
7.14k
  }
426
427
  /// Return true if it is cheap to speculate a call to intrinsic cttz.
428
8
  virtual bool isCheapToSpeculateCttz() const {
429
8
    return false;
430
8
  }
431
432
  /// Return true if it is cheap to speculate a call to intrinsic ctlz.
433
5
  virtual bool isCheapToSpeculateCtlz() const {
434
5
    return false;
435
5
  }
436
437
  /// Return true if ctlz instruction is fast.
438
0
  virtual bool isCtlzFast() const {
439
0
    return false;
440
0
  }
441
442
  /// Return true if it is safe to transform an integer-domain bitwise operation
443
  /// into the equivalent floating-point operation. This should be set to true
444
  /// if the target has IEEE-754-compliant fabs/fneg operations for the input
445
  /// type.
446
22.2k
  virtual bool hasBitPreservingFPLogic(EVT VT) const {
447
22.2k
    return false;
448
22.2k
  }
449
450
  /// Return true if it is cheaper to split the store of a merged int val
451
  /// from a pair of smaller values into multiple stores.
452
512
  virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
453
512
    return false;
454
512
  }
455
456
  /// Return if the target supports combining a
457
  /// chain like:
458
  /// \code
459
  ///   %andResult = and %val1, #mask
460
  ///   %icmpResult = icmp %andResult, 0
461
  /// \endcode
462
  /// into a single machine instruction of a form like:
463
  /// \code
464
  ///   cc = test %register, #mask
465
  /// \endcode
466
87
  virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
467
87
    return false;
468
87
  }
469
470
  /// Use bitwise logic to make pairs of compares more efficient. For example:
471
  /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
472
  /// This should be true when it takes more than one instruction to lower
473
  /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
474
  /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
475
7.38k
  virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
476
7.38k
    return false;
477
7.38k
  }
478
479
  /// Return the preferred operand type if the target has a quick way to compare
480
  /// integer values of the given size. Assume that any legal integer type can
481
  /// be compared efficiently. Targets may override this to allow illegal wide
482
  /// types to return a vector type if there is support to compare that type.
483
44
  virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
484
44
    MVT VT = MVT::getIntegerVT(NumBits);
485
44
    return isTypeLegal(VT) ? 
VT22
:
MVT::INVALID_SIMPLE_VALUE_TYPE22
;
486
44
  }
487
488
  /// Return true if the target should transform:
489
  /// (X & Y) == Y ---> (~X & Y) == 0
490
  /// (X & Y) != Y ---> (~X & Y) != 0
491
  ///
492
  /// This may be profitable if the target has a bitwise and-not operation that
493
  /// sets comparison flags. A target may want to limit the transformation based
494
  /// on the type of Y or if Y is a constant.
495
  ///
496
  /// Note that the transform will not occur if Y is known to be a power-of-2
497
  /// because a mask and compare of a single bit can be handled by inverting the
498
  /// predicate, for example:
499
  /// (X & 8) == 8 ---> (X & 8) != 0
500
625
  virtual bool hasAndNotCompare(SDValue Y) const {
501
625
    return false;
502
625
  }
503
504
  /// Return true if the target has a bitwise and-not operation:
505
  /// X = ~A & B
506
  /// This can be used to simplify select or other instructions.
507
705
  virtual bool hasAndNot(SDValue X) const {
508
705
    // If the target has the more complex version of this operation, assume that
509
705
    // it has this operation too.
510
705
    return hasAndNotCompare(X);
511
705
  }
512
513
  /// There are two ways to clear extreme bits (either low or high):
514
  /// Mask:    x &  (-1 << y)  (the instcombine canonical form)
515
  /// Shifts:  x >> y << y
516
  /// Return true if the variant with 2 shifts is preferred.
517
  /// Return false if there is no preference.
518
284k
  virtual bool preferShiftsToClearExtremeBits(SDValue X) const {
519
284k
    // By default, let's assume that no one prefers shifts.
520
284k
    return false;
521
284k
  }
522
523
  /// Should we tranform the IR-optimal check for whether given truncation
524
  /// down into KeptBits would be truncating or not:
525
  ///   (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
526
  /// Into it's more traditional form:
527
  ///   ((%x << C) a>> C) dstcond %x
528
  /// Return true if we should transform.
529
  /// Return false if there is no preference.
530
  virtual bool shouldTransformSignedTruncationCheck(EVT XVT,
531
45
                                                    unsigned KeptBits) const {
532
45
    // By default, let's assume that no one prefers shifts.
533
45
    return false;
534
45
  }
535
536
  /// Return true if the target wants to use the optimization that
537
  /// turns ext(promotableInst1(...(promotableInstN(load)))) into
538
  /// promotedInst1(...(promotedInstN(ext(load)))).
539
516k
  bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
540
541
  /// Return true if the target can combine store(extractelement VectorTy,
542
  /// Idx).
543
  /// \p Cost[out] gives the cost of that transformation when this is true.
544
  virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
545
42.4k
                                         unsigned &Cost) const {
546
42.4k
    return false;
547
42.4k
  }
548
549
  /// Return true if inserting a scalar into a variable element of an undef
550
  /// vector is more efficiently handled by splatting the scalar instead.
551
28
  virtual bool shouldSplatInsEltVarIndex(EVT) const {
552
28
    return false;
553
28
  }
554
555
  /// Return true if target supports floating point exceptions.
556
10.8M
  bool hasFloatingPointExceptions() const {
557
10.8M
    return HasFloatingPointExceptions;
558
10.8M
  }
559
560
  /// Return true if target always beneficiates from combining into FMA for a
561
  /// given value type. This must typically return false on targets where FMA
562
  /// takes more cycles to execute than FADD.
563
4.43k
  virtual bool enableAggressiveFMAFusion(EVT VT) const {
564
4.43k
    return false;
565
4.43k
  }
566
567
  /// Return the ValueType of the result of SETCC operations.
568
  virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
569
                                 EVT VT) const;
570
571
  /// Return the ValueType for comparison libcalls. Comparions libcalls include
572
  /// floating point comparion calls, and Ordered/Unordered check calls on
573
  /// floating point numbers.
574
  virtual
575
  MVT::SimpleValueType getCmpLibcallReturnType() const;
576
577
  /// For targets without i1 registers, this gives the nature of the high-bits
578
  /// of boolean values held in types wider than i1.
579
  ///
580
  /// "Boolean values" are special true/false values produced by nodes like
581
  /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
582
  /// Not to be confused with general values promoted from i1.  Some cpus
583
  /// distinguish between vectors of boolean and scalars; the isVec parameter
584
  /// selects between the two kinds.  For example on X86 a scalar boolean should
585
  /// be zero extended from i1, while the elements of a vector of booleans
586
  /// should be sign extended from i1.
587
  ///
588
  /// Some cpus also treat floating point types the same way as they treat
589
  /// vectors instead of the way they treat scalars.
590
1.79M
  BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
591
1.79M
    if (isVec)
592
267k
      return BooleanVectorContents;
593
1.52M
    return isFloat ? 
BooleanFloatContents37.0k
:
BooleanContents1.49M
;
594
1.52M
  }
595
596
1.77M
  BooleanContent getBooleanContents(EVT Type) const {
597
1.77M
    return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
598
1.77M
  }
599
600
  /// Return target scheduling preference.
601
303k
  Sched::Preference getSchedulingPreference() const {
602
303k
    return SchedPreferenceInfo;
603
303k
  }
604
605
  /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
606
  /// for different nodes. This function returns the preference (or none) for
607
  /// the given node.
608
15.3M
  virtual Sched::Preference getSchedulingPreference(SDNode *) const {
609
15.3M
    return Sched::None;
610
15.3M
  }
611
612
  /// Return the register class that should be used for the specified value
613
  /// type.
614
23.5M
  virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
615
23.5M
    const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
616
23.5M
    assert(RC && "This value type is not natively supported!");
617
23.5M
    return RC;
618
23.5M
  }
619
620
  /// Return the 'representative' register class for the specified value
621
  /// type.
622
  ///
623
  /// The 'representative' register class is the largest legal super-reg
624
  /// register class for the register class of the value type.  For example, on
625
  /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
626
  /// register class is GR64 on x86_64.
627
2.01M
  virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
628
2.01M
    const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
629
2.01M
    return RC;
630
2.01M
  }
631
632
  /// Return the cost of the 'representative' register class for the specified
633
  /// value type.
634
1.67M
  virtual uint8_t getRepRegClassCostFor(MVT VT) const {
635
1.67M
    return RepRegClassCostForVT[VT.SimpleTy];
636
1.67M
  }
637
638
  /// Return true if the target has native support for the specified value type.
639
  /// This means that it has a register that directly holds it without
640
  /// promotions or expansions.
641
589M
  bool isTypeLegal(EVT VT) const {
642
589M
    assert(!VT.isSimple() ||
643
589M
           (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
644
589M
    return VT.isSimple() && 
RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr588M
;
645
589M
  }
646
647
  class ValueTypeActionImpl {
648
    /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
649
    /// that indicates how instruction selection should deal with the type.
650
    LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
651
652
  public:
653
45.6k
    ValueTypeActionImpl() {
654
45.6k
      std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
655
45.6k
                TypeLegal);
656
45.6k
    }
657
658
114M
    LegalizeTypeAction getTypeAction(MVT VT) const {
659
114M
      return ValueTypeActions[VT.SimpleTy];
660
114M
    }
661
662
4.31M
    void setTypeAction(MVT VT, LegalizeTypeAction Action) {
663
4.31M
      ValueTypeActions[VT.SimpleTy] = Action;
664
4.31M
    }
665
  };
666
667
1.81M
  const ValueTypeActionImpl &getValueTypeActions() const {
668
1.81M
    return ValueTypeActions;
669
1.81M
  }
670
671
  /// Return how we should legalize values of this type, either it is already
672
  /// legal (return 'Legal') or we need to promote it to a larger type (return
673
  /// 'Promote'), or we need to expand it into multiple registers of smaller
674
  /// integer type (return 'Expand').  'Custom' is not an option.
675
106M
  LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
676
106M
    return getTypeConversion(Context, VT).first;
677
106M
  }
678
0
  LegalizeTypeAction getTypeAction(MVT VT) const {
679
0
    return ValueTypeActions.getTypeAction(VT);
680
0
  }
681
682
  /// For types supported by the target, this is an identity function.  For
683
  /// types that must be promoted to larger types, this returns the larger type
684
  /// to promote to.  For integer types that are larger than the largest integer
685
  /// register, this contains one step in the expansion to get to the smaller
686
  /// register. For illegal floating point types, this returns the integer type
687
  /// to transform to.
688
1.54M
  EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
689
1.54M
    return getTypeConversion(Context, VT).second;
690
1.54M
  }
691
692
  /// For types supported by the target, this is an identity function.  For
693
  /// types that must be expanded (i.e. integer types that are larger than the
694
  /// largest integer register or illegal floating point types), this returns
695
  /// the largest legal type it will be expanded to.
696
15.5k
  EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
697
15.5k
    assert(!VT.isVector());
698
16.9k
    while (true) {
699
16.9k
      switch (getTypeAction(Context, VT)) {
700
16.9k
      case TypeLegal:
701
15.5k
        return VT;
702
16.9k
      case TypeExpandInteger:
703
1.44k
        VT = getTypeToTransformTo(Context, VT);
704
1.44k
        break;
705
16.9k
      default:
706
0
        llvm_unreachable("Type is not legal nor is it to be expanded!");
707
16.9k
      }
708
16.9k
    }
709
15.5k
  }
710
711
  /// Vector types are broken down into some number of legal first class types.
712
  /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
713
  /// promoted EVT::f64 values with the X86 FP stack.  Similarly, EVT::v2i64
714
  /// turns into 4 EVT::i32 values with both PPC and X86.
715
  ///
716
  /// This method returns the number of registers needed, and the VT for each
717
  /// register.  It also returns the VT and quantity of the intermediate values
718
  /// before they are promoted/expanded.
719
  unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
720
                                  EVT &IntermediateVT,
721
                                  unsigned &NumIntermediates,
722
                                  MVT &RegisterVT) const;
723
724
  /// Certain targets such as MIPS require that some types such as vectors are
725
  /// always broken down into scalars in some contexts. This occurs even if the
726
  /// vector type is legal.
727
  virtual unsigned getVectorTypeBreakdownForCallingConv(
728
      LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
729
11.7k
      unsigned &NumIntermediates, MVT &RegisterVT) const {
730
11.7k
    return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
731
11.7k
                                  RegisterVT);
732
11.7k
  }
733
734
  struct IntrinsicInfo {
735
    unsigned     opc = 0;          // target opcode
736
    EVT          memVT;            // memory VT
737
738
    // value representing memory location
739
    PointerUnion<const Value *, const PseudoSourceValue *> ptrVal;
740
741
    int          offset = 0;       // offset off of ptrVal
742
    unsigned     size = 0;         // the size of the memory location
743
                                   // (taken from memVT if zero)
744
    unsigned     align = 1;        // alignment
745
746
    MachineMemOperand::Flags flags = MachineMemOperand::MONone;
747
304k
    IntrinsicInfo() = default;
748
  };
749
750
  /// Given an intrinsic, checks if on the target the intrinsic will need to map
751
  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
752
  /// true and store the intrinsic information into the IntrinsicInfo that was
753
  /// passed to the function.
754
  virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
755
                                  MachineFunction &,
756
3.91k
                                  unsigned /*Intrinsic*/) const {
757
3.91k
    return false;
758
3.91k
  }
759
760
  /// Returns true if the target can instruction select the specified FP
761
  /// immediate natively. If false, the legalizer will materialize the FP
762
  /// immediate as a load from a constant pool.
763
75
  virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
764
75
    return false;
765
75
  }
766
767
  /// Targets can use this to indicate that they only support *some*
768
  /// VECTOR_SHUFFLE operations, those with specific masks.  By default, if a
769
  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
770
  /// legal.
771
618
  virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
772
618
    return true;
773
618
  }
774
775
  /// Returns true if the operation can trap for the value type.
776
  ///
777
  /// VT must be a legal type. By default, we optimistically assume most
778
  /// operations don't trap except for integer divide and remainder.
779
  virtual bool canOpTrap(unsigned Op, EVT VT) const;
780
781
  /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
782
  /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
783
  /// constant pool entry.
784
  virtual bool isVectorClearMaskLegal(ArrayRef<int> /*Mask*/,
785
12.1k
                                      EVT /*VT*/) const {
786
12.1k
    return false;
787
12.1k
  }
788
789
  /// Return how this operation should be treated: either it is legal, needs to
790
  /// be promoted to a larger size, needs to be expanded to some other code
791
  /// sequence, or the target has a custom expander for it.
792
124M
  LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
793
124M
    if (VT.isExtended()) 
return Expand181k
;
794
123M
    // If a target-specific SDNode requires legalization, require the target
795
123M
    // to provide custom legalization for it.
796
123M
    if (Op >= array_lengthof(OpActions[0])) 
return Custom157
;
797
123M
    return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
798
123M
  }
799
800
770
  LegalizeAction getStrictFPOperationAction(unsigned Op, EVT VT) const {
801
770
    unsigned EqOpc;
802
770
    switch (Op) {
803
770
      
default: 0
llvm_unreachable0
("Unexpected FP pseudo-opcode");
804
770
      
case ISD::STRICT_FADD: EqOpc = ISD::FADD; break52
;
805
770
      
case ISD::STRICT_FSUB: EqOpc = ISD::FSUB; break60
;
806
770
      
case ISD::STRICT_FMUL: EqOpc = ISD::FMUL; break52
;
807
770
      
case ISD::STRICT_FDIV: EqOpc = ISD::FDIV; break52
;
808
770
      
case ISD::STRICT_FREM: EqOpc = ISD::FREM; break35
;
809
770
      
case ISD::STRICT_FSQRT: EqOpc = ISD::FSQRT; break52
;
810
770
      
case ISD::STRICT_FPOW: EqOpc = ISD::FPOW; break35
;
811
770
      
case ISD::STRICT_FPOWI: EqOpc = ISD::FPOWI; break35
;
812
770
      
case ISD::STRICT_FMA: EqOpc = ISD::FMA; break68
;
813
770
      
case ISD::STRICT_FSIN: EqOpc = ISD::FSIN; break35
;
814
770
      
case ISD::STRICT_FCOS: EqOpc = ISD::FCOS; break35
;
815
770
      
case ISD::STRICT_FEXP: EqOpc = ISD::FEXP; break35
;
816
770
      
case ISD::STRICT_FEXP2: EqOpc = ISD::FEXP2; break35
;
817
770
      
case ISD::STRICT_FLOG: EqOpc = ISD::FLOG; break35
;
818
770
      
case ISD::STRICT_FLOG10: EqOpc = ISD::FLOG10; break35
;
819
770
      
case ISD::STRICT_FLOG2: EqOpc = ISD::FLOG2; break35
;
820
770
      
case ISD::STRICT_FRINT: EqOpc = ISD::FRINT; break42
;
821
770
      
case ISD::STRICT_FNEARBYINT: EqOpc = ISD::FNEARBYINT; break42
;
822
770
    }
823
770
824
770
    auto Action = getOperationAction(EqOpc, VT);
825
770
826
770
    // We don't currently handle Custom or Promote for strict FP pseudo-ops.
827
770
    // For now, we just expand for those cases.
828
770
    if (Action != Legal)
829
420
      Action = Expand;
830
770
831
770
    return Action;
832
770
  }
833
834
  /// Return true if the specified operation is legal on this target or can be
835
  /// made legal with custom lowering. This is used to help guide high-level
836
  /// lowering decisions.
837
27.0M
  bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
838
27.0M
    return (VT == MVT::Other || 
isTypeLegal(VT)26.8M
) &&
839
27.0M
      
(21.9M
getOperationAction(Op, VT) == Legal21.9M
||
840
21.9M
       
getOperationAction(Op, VT) == Custom13.2M
);
841
27.0M
  }
842
843
  /// Return true if the specified operation is legal on this target or can be
844
  /// made legal using promotion. This is used to help guide high-level lowering
845
  /// decisions.
846
570k
  bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
847
570k
    return (VT == MVT::Other || isTypeLegal(VT)) &&
848
570k
      
(570k
getOperationAction(Op, VT) == Legal570k
||
849
570k
       
getOperationAction(Op, VT) == Promote63.9k
);
850
570k
  }
851
852
  /// Return true if the specified operation is legal on this target or can be
853
  /// made legal with custom lowering or using promotion. This is used to help
854
  /// guide high-level lowering decisions.
855
675k
  bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
856
675k
    return (VT == MVT::Other || isTypeLegal(VT)) &&
857
675k
      
(668k
getOperationAction(Op, VT) == Legal668k
||
858
668k
       
getOperationAction(Op, VT) == Custom60.8k
||
859
668k
       
getOperationAction(Op, VT) == Promote49.1k
);
860
675k
  }
861
862
  /// Return true if the operation uses custom lowering, regardless of whether
863
  /// the type is legal or not.
864
1.06k
  bool isOperationCustom(unsigned Op, EVT VT) const {
865
1.06k
    return getOperationAction(Op, VT) == Custom;
866
1.06k
  }
867
868
  /// Return true if lowering to a jump table is allowed.
869
50.4k
  virtual bool areJTsAllowed(const Function *Fn) const {
870
50.4k
    if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
871
2
      return false;
872
50.4k
873
50.4k
    return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
874
50.4k
           
isOperationLegalOrCustom(ISD::BRIND, MVT::Other)47.5k
;
875
50.4k
  }
876
877
  /// Check whether the range [Low,High] fits in a machine word.
878
  bool rangeFitsInWord(const APInt &Low, const APInt &High,
879
62.0k
                       const DataLayout &DL) const {
880
62.0k
    // FIXME: Using the pointer type doesn't seem ideal.
881
62.0k
    uint64_t BW = DL.getIndexSizeInBits(0u);
882
62.0k
    uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
883
62.0k
    return Range <= BW;
884
62.0k
  }
885
886
  /// Return true if lowering to a jump table is suitable for a set of case
887
  /// clusters which may contain \p NumCases cases, \p Range range of values.
888
  /// FIXME: This function check the maximum table size and density, but the
889
  /// minimum size is not checked. It would be nice if the minimum size is
890
  /// also combined within this function. Currently, the minimum size check is
891
  /// performed in findJumpTable() in SelectionDAGBuiler and
892
  /// getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
893
  virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
894
26.2k
                                      uint64_t Range) const {
895
26.2k
    const bool OptForSize = SI->getParent()->getParent()->optForSize();
896
26.2k
    const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
897
26.2k
    const unsigned MaxJumpTableSize =
898
26.2k
        OptForSize || 
getMaximumJumpTableSize() == 026.1k
899
26.2k
            ? UINT_MAX
900
26.2k
            : 
getMaximumJumpTableSize()461
;
901
26.2k
    // Check whether a range of clusters is dense enough for a jump table.
902
26.2k
    if (Range <= MaxJumpTableSize &&
903
26.2k
        
(NumCases * 100 >= Range * MinDensity)26.0k
) {
904
19.3k
      return true;
905
19.3k
    }
906
6.90k
    return false;
907
6.90k
  }
908
909
  /// Return true if lowering to a bit test is suitable for a set of case
910
  /// clusters which contains \p NumDests unique destinations, \p Low and
911
  /// \p High as its lowest and highest case values, and expects \p NumCmps
912
  /// case value comparisons. Check if the number of destinations, comparison
913
  /// metric, and range are all suitable.
914
  bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
915
                             const APInt &Low, const APInt &High,
916
48.9k
                             const DataLayout &DL) const {
917
48.9k
    // FIXME: I don't think NumCmps is the correct metric: a single case and a
918
48.9k
    // range of cases both require only one branch to lower. Just looking at the
919
48.9k
    // number of clusters and destinations should be enough to decide whether to
920
48.9k
    // build bit tests.
921
48.9k
922
48.9k
    // To lower a range with bit tests, the range must fit the bitwidth of a
923
48.9k
    // machine word.
924
48.9k
    if (!rangeFitsInWord(Low, High, DL))
925
7.59k
      return false;
926
41.3k
927
41.3k
    // Decide whether it's profitable to lower this range with bit tests. Each
928
41.3k
    // destination requires a bit test and branch, and there is an overall range
929
41.3k
    // check branch. For a small number of clusters, separate comparisons might
930
41.3k
    // be cheaper, and for many destinations, splitting the range might be
931
41.3k
    // better.
932
41.3k
    return (NumDests == 1 && 
NumCmps >= 39.30k
) ||
(36.5k
NumDests == 236.5k
&&
NumCmps >= 519.6k
) ||
933
41.3k
           
(35.8k
NumDests == 335.8k
&&
NumCmps >= 63.68k
);
934
41.3k
  }
935
936
  /// Return true if the specified operation is illegal on this target or
937
  /// unlikely to be made legal with custom lowering. This is used to help guide
938
  /// high-level lowering decisions.
939
259k
  bool isOperationExpand(unsigned Op, EVT VT) const {
940
259k
    return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
941
259k
  }
942
943
  /// Return true if the specified operation is legal on this target.
944
3.63M
  bool isOperationLegal(unsigned Op, EVT VT) const {
945
3.63M
    return (VT == MVT::Other || isTypeLegal(VT)) &&
946
3.63M
           
getOperationAction(Op, VT) == Legal3.59M
;
947
3.63M
  }
948
949
  /// Return how this load with extension should be treated: either it is legal,
950
  /// needs to be promoted to a larger size, needs to be expanded to some other
951
  /// code sequence, or the target has a custom expander for it.
952
  LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
953
1.41M
                                  EVT MemVT) const {
954
1.41M
    if (ValVT.isExtended() || 
MemVT.isExtended()1.41M
)
return Expand3.17k
;
955
1.41M
    unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
956
1.41M
    unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
957
1.41M
    assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
958
1.41M
           MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
959
1.41M
    unsigned Shift = 4 * ExtType;
960
1.41M
    return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
961
1.41M
  }
962
963
  /// Return true if the specified load with extension is legal on this target.
964
908k
  bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
965
908k
    return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
966
908k
  }
967
968
  /// Return true if the specified load with extension is legal or custom
969
  /// on this target.
970
2.07k
  bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
971
2.07k
    return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
972
2.07k
           
getLoadExtAction(ExtType, ValVT, MemVT) == Custom1.85k
;
973
2.07k
  }
974
975
  /// Return how this store with truncation should be treated: either it is
976
  /// legal, needs to be promoted to a larger size, needs to be expanded to some
977
  /// other code sequence, or the target has a custom expander for it.
978
578k
  LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
979
578k
    if (ValVT.isExtended() || MemVT.isExtended()) 
return Expand179k
;
980
399k
    unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
981
399k
    unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
982
399k
    assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
983
399k
           "Table isn't big enough!");
984
399k
    return TruncStoreActions[ValI][MemI];
985
399k
  }
986
987
  /// Return true if the specified store with truncation is legal on this
988
  /// target.
989
280k
  bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
990
280k
    return isTypeLegal(ValVT) && 
getTruncStoreAction(ValVT, MemVT) == Legal245k
;
991
280k
  }
992
993
  /// Return true if the specified store with truncation has solution on this
994
  /// target.
995
2.23k
  bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
996
2.23k
    return isTypeLegal(ValVT) &&
997
2.23k
      (getTruncStoreAction(ValVT, MemVT) == Legal ||
998
2.23k
       
getTruncStoreAction(ValVT, MemVT) == Custom1.28k
);
999
2.23k
  }
1000
1001
  /// Return how the indexed load should be treated: either it is legal, needs
1002
  /// to be promoted to a larger size, needs to be expanded to some other code
1003
  /// sequence, or the target has a custom expander for it.
1004
  LegalizeAction
1005
5.37M
  getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
1006
5.37M
    assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1007
5.37M
           "Table isn't big enough!");
1008
5.37M
    unsigned Ty = (unsigned)VT.SimpleTy;
1009
5.37M
    return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
1010
5.37M
  }
1011
1012
  /// Return true if the specified indexed load is legal on this target.
1013
3.52M
  bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
1014
3.52M
    return VT.isSimple() &&
1015
3.52M
      (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
1016
3.52M
       
getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom1.84M
);
1017
3.52M
  }
1018
1019
  /// Return how the indexed store should be treated: either it is legal, needs
1020
  /// to be promoted to a larger size, needs to be expanded to some other code
1021
  /// sequence, or the target has a custom expander for it.
1022
  LegalizeAction
1023
5.86M
  getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
1024
5.86M
    assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1025
5.86M
           "Table isn't big enough!");
1026
5.86M
    unsigned Ty = (unsigned)VT.SimpleTy;
1027
5.86M
    return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
1028
5.86M
  }
1029
1030
  /// Return true if the specified indexed load is legal on this target.
1031
3.73M
  bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
1032
3.73M
    return VT.isSimple() &&
1033
3.73M
      (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
1034
3.73M
       
getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom2.12M
);
1035
3.73M
  }
1036
1037
  /// Return how the condition code should be treated: either it is legal, needs
1038
  /// to be expanded to some other code sequence, or the target has a custom
1039
  /// expander for it.
1040
  LegalizeAction
1041
884k
  getCondCodeAction(ISD::CondCode CC, MVT VT) const {
1042
884k
    assert((unsigned)CC < array_lengthof(CondCodeActions) &&
1043
884k
           ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
1044
884k
           "Table isn't big enough!");
1045
884k
    // See setCondCodeAction for how this is encoded.
1046
884k
    uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1047
884k
    uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
1048
884k
    LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
1049
884k
    assert(Action != Promote && "Can't promote condition code!");
1050
884k
    return Action;
1051
884k
  }
1052
1053
  /// Return true if the specified condition code is legal on this target.
1054
26.9k
  bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
1055
26.9k
    return getCondCodeAction(CC, VT) == Legal;
1056
26.9k
  }
1057
1058
  /// Return true if the specified condition code is legal or custom on this
1059
  /// target.
1060
2.63k
  bool isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) const {
1061
2.63k
    return getCondCodeAction(CC, VT) == Legal ||
1062
2.63k
           
getCondCodeAction(CC, VT) == Custom887
;
1063
2.63k
  }
1064
1065
  /// If the action for this operation is to promote, this method returns the
1066
  /// ValueType to promote to.
1067
271k
  MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
1068
271k
    assert(getOperationAction(Op, VT) == Promote &&
1069
271k
           "This operation isn't promoted!");
1070
271k
1071
271k
    // See if this has an explicit type specified.
1072
271k
    std::map<std::pair<unsigned, MVT::SimpleValueType>,
1073
271k
             MVT::SimpleValueType>::const_iterator PTTI =
1074
271k
      PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1075
271k
    if (PTTI != PromoteToType.end()) 
return PTTI->second270k
;
1076
884
1077
884
    assert((VT.isInteger() || VT.isFloatingPoint()) &&
1078
884
           "Cannot autopromote this type, add it with AddPromotedToType.");
1079
884
1080
884
    MVT NVT = VT;
1081
956
    do {
1082
956
      NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1083
956
      assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1084
956
             "Didn't find type to promote to!");
1085
956
    } while (!isTypeLegal(NVT) ||
1086
956
              
getOperationAction(Op, NVT) == Promote950
);
1087
884
    return NVT;
1088
884
  }
1089
1090
  /// Return the EVT corresponding to this LLVM type.  This is fixed by the LLVM
1091
  /// operations except for the pointer size.  If AllowUnknown is true, this
1092
  /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1093
  /// otherwise it will assert.
1094
  EVT getValueType(const DataLayout &DL, Type *Ty,
1095
64.3M
                   bool AllowUnknown = false) const {
1096
64.3M
    // Lower scalar pointers to native pointer types.
1097
64.3M
    if (PointerType *PTy = dyn_cast<PointerType>(Ty))
1098
21.5M
      return getPointerTy(DL, PTy->getAddressSpace());
1099
42.7M
1100
42.7M
    if (Ty->isVectorTy()) {
1101
5.90M
      VectorType *VTy = cast<VectorType>(Ty);
1102
5.90M
      Type *Elm = VTy->getElementType();
1103
5.90M
      // Lower vectors of pointers to native pointer types.
1104
5.90M
      if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
1105
318k
        EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
1106
318k
        Elm = PointerTy.getTypeForEVT(Ty->getContext());
1107
318k
      }
1108
5.90M
1109
5.90M
      return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1110
5.90M
                       VTy->getNumElements());
1111
5.90M
    }
1112
36.8M
    return EVT::getEVT(Ty, AllowUnknown);
1113
36.8M
  }
1114
1115
  /// Return the MVT corresponding to this LLVM type. See getValueType.
1116
  MVT getSimpleValueType(const DataLayout &DL, Type *Ty,
1117
21.9k
                         bool AllowUnknown = false) const {
1118
21.9k
    return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1119
21.9k
  }
1120
1121
  /// Return the desired alignment for ByVal or InAlloca aggregate function
1122
  /// arguments in the caller parameter area.  This is the actual alignment, not
1123
  /// its logarithm.
1124
  virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1125
1126
  /// Return the type of registers that this ValueType will eventually require.
1127
3.74M
  MVT getRegisterType(MVT VT) const {
1128
3.74M
    assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
1129
3.74M
    return RegisterTypeForVT[VT.SimpleTy];
1130
3.74M
  }
1131
1132
  /// Return the type of registers that this ValueType will eventually require.
1133
11.0M
  MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1134
11.0M
    if (VT.isSimple()) {
1135
11.0M
      assert((unsigned)VT.getSimpleVT().SimpleTy <
1136
11.0M
                array_lengthof(RegisterTypeForVT));
1137
11.0M
      return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1138
11.0M
    }
1139
16.5k
    if (VT.isVector()) {
1140
3.47k
      EVT VT1;
1141
3.47k
      MVT RegisterVT;
1142
3.47k
      unsigned NumIntermediates;
1143
3.47k
      (void)getVectorTypeBreakdown(Context, VT, VT1,
1144
3.47k
                                   NumIntermediates, RegisterVT);
1145
3.47k
      return RegisterVT;
1146
3.47k
    }
1147
13.1k
    if (VT.isInteger()) {
1148
13.1k
      return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1149
13.1k
    }
1150
3
    llvm_unreachable("Unsupported extended type!");
1151
3
  }
1152
1153
  /// Return the number of registers that this ValueType will eventually
1154
  /// require.
1155
  ///
1156
  /// This is one for any types promoted to live in larger registers, but may be
1157
  /// more than one for types (like i64) that are split into pieces.  For types
1158
  /// like i140, which are first promoted then expanded, it is the number of
1159
  /// registers needed to hold all the bits of the original type.  For an i140
1160
  /// on a 32 bit machine this means 5 registers.
1161
12.5M
  unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1162
12.5M
    if (VT.isSimple()) {
1163
12.5M
      assert((unsigned)VT.getSimpleVT().SimpleTy <
1164
12.5M
                array_lengthof(NumRegistersForVT));
1165
12.5M
      return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1166
12.5M
    }
1167
8.63k
    if (VT.isVector()) {
1168
3.56k
      EVT VT1;
1169
3.56k
      MVT VT2;
1170
3.56k
      unsigned NumIntermediates;
1171
3.56k
      return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1172
3.56k
    }
1173
5.07k
    
if (5.07k
VT.isInteger()5.07k
) {
1174
5.07k
      unsigned BitWidth = VT.getSizeInBits();
1175
5.07k
      unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1176
5.07k
      return (BitWidth + RegWidth - 1) / RegWidth;
1177
5.07k
    }
1178
18.4E
    llvm_unreachable("Unsupported extended type!");
1179
18.4E
  }
1180
1181
  /// Certain combinations of ABIs, Targets and features require that types
1182
  /// are legal for some operations and not for other operations.
1183
  /// For MIPS all vector types must be passed through the integer register set.
1184
  virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context,
1185
4.65M
                                            CallingConv::ID CC, EVT VT) const {
1186
4.65M
    return getRegisterType(Context, VT);
1187
4.65M
  }
1188
1189
  /// Certain targets require unusual breakdowns of certain types. For MIPS,
1190
  /// this occurs when a vector type is used, as vector are passed through the
1191
  /// integer register set.
1192
  virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1193
                                                 CallingConv::ID CC,
1194
4.65M
                                                 EVT VT) const {
1195
4.65M
    return getNumRegisters(Context, VT);
1196
4.65M
  }
1197
1198
  /// Certain targets have context senstive alignment requirements, where one
1199
  /// type has the alignment requirement of another type.
1200
  virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
1201
2.16M
                                                 DataLayout DL) const {
1202
2.16M
    return DL.getABITypeAlignment(ArgTy);
1203
2.16M
  }
1204
1205
  /// If true, then instruction selection should seek to shrink the FP constant
1206
  /// of the specified type to a smaller type in order to save space and / or
1207
  /// reduce runtime.
1208
292
  virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1209
1210
  // Return true if it is profitable to reduce the given load node to a smaller
1211
  // type.
1212
  //
1213
  // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
1214
  virtual bool shouldReduceLoadWidth(SDNode *Load,
1215
                                     ISD::LoadExtType ExtTy,
1216
1.28k
                                     EVT NewVT) const {
1217
1.28k
    return true;
1218
1.28k
  }
1219
1220
  /// When splitting a value of the specified type into parts, does the Lo
1221
  /// or Hi part come first?  This usually follows the endianness, except
1222
  /// for ppcf128, where the Hi part always comes first.
1223
194k
  bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1224
194k
    return DL.isBigEndian() || 
VT == MVT::ppcf128190k
;
1225
194k
  }
1226
1227
  /// If true, the target has custom DAG combine transformations that it can
1228
  /// perform for the specified node.
1229
91.1M
  bool hasTargetDAGCombine(ISD::NodeType NT) const {
1230
91.1M
    assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1231
91.1M
    return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1232
91.1M
  }
1233
1234
31.3M
  unsigned getGatherAllAliasesMaxDepth() const {
1235
31.3M
    return GatherAllAliasesMaxDepth;
1236
31.3M
  }
1237
1238
  /// Returns the size of the platform's va_list object.
1239
0
  virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1240
0
    return getPointerTy(DL).getSizeInBits();
1241
0
  }
1242
1243
  /// Get maximum # of store operations permitted for llvm.memset
1244
  ///
1245
  /// This function returns the maximum number of store operations permitted
1246
  /// to replace a call to llvm.memset. The value is set by the target at the
1247
  /// performance threshold for such a replacement. If OptSize is true,
1248
  /// return the limit for functions that have OptSize attribute.
1249
14.0k
  unsigned getMaxStoresPerMemset(bool OptSize) const {
1250
14.0k
    return OptSize ? 
MaxStoresPerMemsetOptSize21
:
MaxStoresPerMemset14.0k
;
1251
14.0k
  }
1252
1253
  /// Get maximum # of store operations permitted for llvm.memcpy
1254
  ///
1255
  /// This function returns the maximum number of store operations permitted
1256
  /// to replace a call to llvm.memcpy. The value is set by the target at the
1257
  /// performance threshold for such a replacement. If OptSize is true,
1258
  /// return the limit for functions that have OptSize attribute.
1259
12.4k
  unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1260
12.4k
    return OptSize ? 
MaxStoresPerMemcpyOptSize46
:
MaxStoresPerMemcpy12.4k
;
1261
12.4k
  }
1262
1263
  /// \brief Get maximum # of store operations to be glued together
1264
  ///
1265
  /// This function returns the maximum number of store operations permitted
1266
  /// to glue together during lowering of llvm.memcpy. The value is set by
1267
  //  the target at the performance threshold for such a replacement.
1268
11.2k
  virtual unsigned getMaxGluedStoresPerMemcpy() const {
1269
11.2k
    return MaxGluedStoresPerMemcpy;
1270
11.2k
  }
1271
1272
  /// Get maximum # of load operations permitted for memcmp
1273
  ///
1274
  /// This function returns the maximum number of load operations permitted
1275
  /// to replace a call to memcmp. The value is set by the target at the
1276
  /// performance threshold for such a replacement. If OptSize is true,
1277
  /// return the limit for functions that have OptSize attribute.
1278
391
  unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1279
391
    return OptSize ? 
MaxLoadsPerMemcmpOptSize108
:
MaxLoadsPerMemcmp283
;
1280
391
  }
1281
1282
  /// For memcmp expansion when the memcmp result is only compared equal or
1283
  /// not-equal to 0, allow up to this number of load pairs per block. As an
1284
  /// example, this may allow 'memcmp(a, b, 3) == 0' in a single block:
1285
  ///   a0 = load2bytes &a[0]
1286
  ///   b0 = load2bytes &b[0]
1287
  ///   a2 = load1byte  &a[2]
1288
  ///   b2 = load1byte  &b[2]
1289
  ///   r  = cmp eq (a0 ^ b0 | a2 ^ b2), 0
1290
22
  virtual unsigned getMemcmpEqZeroLoadsPerBlock() const {
1291
22
    return 1;
1292
22
  }
1293
1294
  /// Get maximum # of store operations permitted for llvm.memmove
1295
  ///
1296
  /// This function returns the maximum number of store operations permitted
1297
  /// to replace a call to llvm.memmove. The value is set by the target at the
1298
  /// performance threshold for such a replacement. If OptSize is true,
1299
  /// return the limit for functions that have OptSize attribute.
1300
103
  unsigned getMaxStoresPerMemmove(bool OptSize) const {
1301
103
    return OptSize ? 
MaxStoresPerMemmoveOptSize0
: MaxStoresPerMemmove;
1302
103
  }
1303
1304
  /// Determine if the target supports unaligned memory accesses.
1305
  ///
1306
  /// This function returns true if the target allows unaligned memory accesses
1307
  /// of the specified type in the given address space. If true, it also returns
1308
  /// whether the unaligned memory access is "fast" in the last argument by
1309
  /// reference. This is used, for example, in situations where an array
1310
  /// copy/move/set is converted to a sequence of store operations. Its use
1311
  /// helps to ensure that such replacements don't generate code that causes an
1312
  /// alignment error (trap) on the target machine.
1313
  virtual bool allowsMisalignedMemoryAccesses(EVT,
1314
                                              unsigned AddrSpace = 0,
1315
                                              unsigned Align = 1,
1316
1.17k
                                              bool * /*Fast*/ = nullptr) const {
1317
1.17k
    return false;
1318
1.17k
  }
1319
1320
  /// Return true if the target supports a memory access of this type for the
1321
  /// given address space and alignment. If the access is allowed, the optional
1322
  /// final parameter returns if the access is also fast (as defined by the
1323
  /// target).
1324
  bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1325
                          unsigned AddrSpace = 0, unsigned Alignment = 1,
1326
                          bool *Fast = nullptr) const;
1327
1328
  /// Returns the target specific optimal type for load and store operations as
1329
  /// a result of memset, memcpy, and memmove lowering.
1330
  ///
1331
  /// If DstAlign is zero that means it's safe to destination alignment can
1332
  /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1333
  /// a need to check it against alignment requirement, probably because the
1334
  /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1335
  /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1336
  /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1337
  /// does not need to be loaded.  It returns EVT::Other if the type should be
1338
  /// determined using generic target-independent logic.
1339
  virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
1340
                                  unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
1341
                                  bool /*IsMemset*/,
1342
                                  bool /*ZeroMemset*/,
1343
                                  bool /*MemcpyStrSrc*/,
1344
133
                                  MachineFunction &/*MF*/) const {
1345
133
    return MVT::Other;
1346
133
  }
1347
1348
  /// Returns true if it's safe to use load / store of the specified type to
1349
  /// expand memcpy / memset inline.
1350
  ///
1351
  /// This is mostly true for all types except for some special cases. For
1352
  /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1353
  /// fstpl which also does type conversion. Note the specified type doesn't
1354
  /// have to be legal as the hook is used before type legalization.
1355
8.56k
  virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1356
1357
  /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1358
0
  bool usesUnderscoreSetJmp() const {
1359
0
    return UseUnderscoreSetJmp;
1360
0
  }
1361
1362
  /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1363
0
  bool usesUnderscoreLongJmp() const {
1364
0
    return UseUnderscoreLongJmp;
1365
0
  }
1366
1367
  /// Return lower limit for number of blocks in a jump table.
1368
  virtual unsigned getMinimumJumpTableEntries() const;
1369
1370
  /// Return lower limit of the density in a jump table.
1371
  unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1372
1373
  /// Return upper limit for number of entries in a jump table.
1374
  /// Zero if no limit.
1375
  unsigned getMaximumJumpTableSize() const;
1376
1377
2.32k
  virtual bool isJumpTableRelative() const {
1378
2.32k
    return TM.isPositionIndependent();
1379
2.32k
  }
1380
1381
  /// If a physical register, this specifies the register that
1382
  /// llvm.savestack/llvm.restorestack should save and restore.
1383
20.3M
  unsigned getStackPointerRegisterToSaveRestore() const {
1384
20.3M
    return StackPointerRegisterToSaveRestore;
1385
20.3M
  }
1386
1387
  /// If a physical register, this returns the register that receives the
1388
  /// exception address on entry to an EH pad.
1389
  virtual unsigned
1390
0
  getExceptionPointerRegister(const Constant *PersonalityFn) const {
1391
0
    // 0 is guaranteed to be the NoRegister value on all targets
1392
0
    return 0;
1393
0
  }
1394
1395
  /// If a physical register, this returns the register that receives the
1396
  /// exception typeid on entry to a landing pad.
1397
  virtual unsigned
1398
0
  getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1399
0
    // 0 is guaranteed to be the NoRegister value on all targets
1400
0
    return 0;
1401
0
  }
1402
1403
0
  virtual bool needsFixedCatchObjects() const {
1404
0
    report_fatal_error("Funclet EH is not implemented for this target");
1405
0
  }
1406
1407
  /// Returns the target's jmp_buf size in bytes (if never set, the default is
1408
  /// 200)
1409
0
  unsigned getJumpBufSize() const {
1410
0
    return JumpBufSize;
1411
0
  }
1412
1413
  /// Returns the target's jmp_buf alignment in bytes (if never set, the default
1414
  /// is 0)
1415
0
  unsigned getJumpBufAlignment() const {
1416
0
    return JumpBufAlignment;
1417
0
  }
1418
1419
  /// Return the minimum stack alignment of an argument.
1420
170
  unsigned getMinStackArgumentAlignment() const {
1421
170
    return MinStackArgumentAlignment;
1422
170
  }
1423
1424
  /// Return the minimum function alignment.
1425
513k
  unsigned getMinFunctionAlignment() const {
1426
513k
    return MinFunctionAlignment;
1427
513k
  }
1428
1429
  /// Return the preferred function alignment.
1430
506k
  unsigned getPrefFunctionAlignment() const {
1431
506k
    return PrefFunctionAlignment;
1432
506k
  }
1433
1434
  /// Return the preferred loop alignment.
1435
643k
  virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1436
643k
    return PrefLoopAlignment;
1437
643k
  }
1438
1439
  /// Should loops be aligned even when the function is marked OptSize (but not
1440
  /// MinSize).
1441
147
  virtual bool alignLoopsWithOptSize() const {
1442
147
    return false;
1443
147
  }
1444
1445
  /// If the target has a standard location for the stack protector guard,
1446
  /// returns the address of that location. Otherwise, returns nullptr.
1447
  /// DEPRECATED: please override useLoadStackGuardNode and customize
1448
  ///             LOAD_STACK_GUARD, or customize \@llvm.stackguard().
1449
  virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1450
1451
  /// Inserts necessary declarations for SSP (stack protection) purpose.
1452
  /// Should be used only when getIRStackGuard returns nullptr.
1453
  virtual void insertSSPDeclarations(Module &M) const;
1454
1455
  /// Return the variable that's previously inserted by insertSSPDeclarations,
1456
  /// if any, otherwise return nullptr. Should be used only when
1457
  /// getIRStackGuard returns nullptr.
1458
  virtual Value *getSDagStackGuard(const Module &M) const;
1459
1460
  /// If this function returns true, stack protection checks should XOR the
1461
  /// frame pointer (or whichever pointer is used to address locals) into the
1462
  /// stack guard value before checking it. getIRStackGuard must return nullptr
1463
  /// if this returns true.
1464
5.95k
  virtual bool useStackGuardXorFP() const { return false; }
1465
1466
  /// If the target has a standard stack protection check function that
1467
  /// performs validation and error handling, returns the function. Otherwise,
1468
  /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1469
  /// Should be used only when getIRStackGuard returns nullptr.
1470
  virtual Value *getSSPStackGuardCheck(const Module &M) const;
1471
1472
protected:
1473
  Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1474
                                            bool UseTLS) const;
1475
1476
public:
1477
  /// Returns the target-specific address of the unsafe stack pointer.
1478
  virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1479
1480
  /// Returns the name of the symbol used to emit stack probes or the empty
1481
  /// string if not applicable.
1482
0
  virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const {
1483
0
    return "";
1484
0
  }
1485
1486
  /// Returns true if a cast between SrcAS and DestAS is a noop.
1487
465
  virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1488
465
    return false;
1489
465
  }
1490
1491
  /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1492
  /// are happy to sink it into basic blocks.
1493
200
  virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1494
200
    return isNoopAddrSpaceCast(SrcAS, DestAS);
1495
200
  }
1496
1497
  /// Return true if the pointer arguments to CI should be aligned by aligning
1498
  /// the object whose address is being passed. If so then MinSize is set to the
1499
  /// minimum size the object must be to be aligned and PrefAlign is set to the
1500
  /// preferred alignment.
1501
  virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1502
3.83M
                                      unsigned & /*PrefAlign*/) const {
1503
3.83M
    return false;
1504
3.83M
  }
1505
1506
  //===--------------------------------------------------------------------===//
1507
  /// \name Helpers for TargetTransformInfo implementations
1508
  /// @{
1509
1510
  /// Get the ISD node that corresponds to the Instruction class opcode.
1511
  int InstructionOpcodeToISD(unsigned Opcode) const;
1512
1513
  /// Estimate the cost of type-legalization and the legalized type.
1514
  std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1515
                                              Type *Ty) const;
1516
1517
  /// @}
1518
1519
  //===--------------------------------------------------------------------===//
1520
  /// \name Helpers for atomic expansion.
1521
  /// @{
1522
1523
  /// Returns the maximum atomic operation size (in bits) supported by
1524
  /// the backend. Atomic operations greater than this size (as well
1525
  /// as ones that are not naturally aligned), will be expanded by
1526
  /// AtomicExpandPass into an __atomic_* library call.
1527
38.1k
  unsigned getMaxAtomicSizeInBitsSupported() const {
1528
38.1k
    return MaxAtomicSizeInBitsSupported;
1529
38.1k
  }
1530
1531
  /// Returns the size of the smallest cmpxchg or ll/sc instruction
1532
  /// the backend supports.  Any smaller operations are widened in
1533
  /// AtomicExpandPass.
1534
  ///
1535
  /// Note that *unlike* operations above the maximum size, atomic ops
1536
  /// are still natively supported below the minimum; they just
1537
  /// require a more complex expansion.
1538
52.0k
  unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1539
1540
  /// Whether the target supports unaligned atomic operations.
1541
1.02k
  bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
1542
1543
  /// Whether AtomicExpandPass should automatically insert fences and reduce
1544
  /// ordering for this atomic. This should be true for most architectures with
1545
  /// weak memory ordering. Defaults to false.
1546
40.0k
  virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1547
40.0k
    return false;
1548
40.0k
  }
1549
1550
  /// Perform a load-linked operation on Addr, returning a "Value *" with the
1551
  /// corresponding pointee type. This may entail some non-trivial operations to
1552
  /// truncate or reconstruct types that will be illegal in the backend. See
1553
  /// ARMISelLowering for an example implementation.
1554
  virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1555
0
                                AtomicOrdering Ord) const {
1556
0
    llvm_unreachable("Load linked unimplemented on this target");
1557
0
  }
1558
1559
  /// Perform a store-conditional operation to Addr. Return the status of the
1560
  /// store. This should be 0 if the store succeeded, non-zero otherwise.
1561
  virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1562
0
                                      Value *Addr, AtomicOrdering Ord) const {
1563
0
    llvm_unreachable("Store conditional unimplemented on this target");
1564
0
  }
1565
1566
  /// Perform a masked atomicrmw using a target-specific intrinsic. This
1567
  /// represents the core LL/SC loop which will be lowered at a late stage by
1568
  /// the backend.
1569
  virtual Value *emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder,
1570
                                              AtomicRMWInst *AI,
1571
                                              Value *AlignedAddr, Value *Incr,
1572
                                              Value *Mask, Value *ShiftAmt,
1573
0
                                              AtomicOrdering Ord) const {
1574
0
    llvm_unreachable("Masked atomicrmw expansion unimplemented on this target");
1575
0
  }
1576
1577
  /// Perform a masked cmpxchg using a target-specific intrinsic. This
1578
  /// represents the core LL/SC loop which will be lowered at a late stage by
1579
  /// the backend.
1580
  virtual Value *emitMaskedAtomicCmpXchgIntrinsic(
1581
      IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
1582
0
      Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
1583
0
    llvm_unreachable("Masked cmpxchg expansion unimplemented on this target");
1584
0
  }
1585
1586
  /// Inserts in the IR a target-specific intrinsic specifying a fence.
1587
  /// It is called by AtomicExpandPass before expanding an
1588
  ///   AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1589
  ///   if shouldInsertFencesForAtomic returns true.
1590
  ///
1591
  /// Inst is the original atomic instruction, prior to other expansions that
1592
  /// may be performed.
1593
  ///
1594
  /// This function should either return a nullptr, or a pointer to an IR-level
1595
  ///   Instruction*. Even complex fence sequences can be represented by a
1596
  ///   single Instruction* through an intrinsic to be lowered later.
1597
  /// Backends should override this method to produce target-specific intrinsic
1598
  ///   for their fences.
1599
  /// FIXME: Please note that the default implementation here in terms of
1600
  ///   IR-level fences exists for historical/compatibility reasons and is
1601
  ///   *unsound* ! Fences cannot, in general, be used to restore sequential
1602
  ///   consistency. For example, consider the following example:
1603
  /// atomic<int> x = y = 0;
1604
  /// int r1, r2, r3, r4;
1605
  /// Thread 0:
1606
  ///   x.store(1);
1607
  /// Thread 1:
1608
  ///   y.store(1);
1609
  /// Thread 2:
1610
  ///   r1 = x.load();
1611
  ///   r2 = y.load();
1612
  /// Thread 3:
1613
  ///   r3 = y.load();
1614
  ///   r4 = x.load();
1615
  ///  r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1616
  ///  seq_cst. But if they are lowered to monotonic accesses, no amount of
1617
  ///  IR-level fences can prevent it.
1618
  /// @{
1619
  virtual Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
1620
127
                                        AtomicOrdering Ord) const {
1621
127
    if (isReleaseOrStronger(Ord) && 
Inst->hasAtomicStore()97
)
1622
94
      return Builder.CreateFence(Ord);
1623
33
    else
1624
33
      return nullptr;
1625
127
  }
1626
1627
  virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
1628
                                         Instruction *Inst,
1629
127
                                         AtomicOrdering Ord) const {
1630
127
    if (isAcquireOrStronger(Ord))
1631
104
      return Builder.CreateFence(Ord);
1632
23
    else
1633
23
      return nullptr;
1634
127
  }
1635
  /// @}
1636
1637
  // Emits code that executes when the comparison result in the ll/sc
1638
  // expansion of a cmpxchg instruction is such that the store-conditional will
1639
  // not execute.  This makes it possible to balance out the load-linked with
1640
  // a dedicated instruction, if desired.
1641
  // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1642
  // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1643
3
  virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1644
1645
  /// Returns true if the given (atomic) store should be expanded by the
1646
  /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1647
67
  virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1648
67
    return false;
1649
67
  }
1650
1651
  /// Returns true if arguments should be sign-extended in lib calls.
1652
35.1k
  virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1653
35.1k
    return IsSigned;
1654
35.1k
  }
1655
1656
  /// Returns how the given (atomic) load should be expanded by the
1657
  /// IR-level AtomicExpand pass.
1658
79
  virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const {
1659
79
    return AtomicExpansionKind::None;
1660
79
  }
1661
1662
  /// Returns how the given atomic cmpxchg should be expanded by the IR-level
1663
  /// AtomicExpand pass.
1664
  virtual AtomicExpansionKind
1665
1.05k
  shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
1666
1.05k
    return AtomicExpansionKind::None;
1667
1.05k
  }
1668
1669
  /// Returns how the IR-level AtomicExpand pass should expand the given
1670
  /// AtomicRMW, if at all. Default is to never expand.
1671
786
  virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
1672
786
    return AtomicExpansionKind::None;
1673
786
  }
1674
1675
  /// On some platforms, an AtomicRMW that never actually modifies the value
1676
  /// (such as fetch_add of 0) can be turned into a fence followed by an
1677
  /// atomic load. This may sound useless, but it makes it possible for the
1678
  /// processor to keep the cacheline shared, dramatically improving
1679
  /// performance. And such idempotent RMWs are useful for implementing some
1680
  /// kinds of locks, see for example (justification + benchmarks):
1681
  /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1682
  /// This method tries doing that transformation, returning the atomic load if
1683
  /// it succeeds, and nullptr otherwise.
1684
  /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1685
  /// another round of expansion.
1686
  virtual LoadInst *
1687
0
  lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1688
0
    return nullptr;
1689
0
  }
1690
1691
  /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1692
  /// SIGN_EXTEND, or ANY_EXTEND).
1693
1.47k
  virtual ISD::NodeType getExtendForAtomicOps() const {
1694
1.47k
    return ISD::ZERO_EXTEND;
1695
1.47k
  }
1696
1697
  /// @}
1698
1699
  /// Returns true if we should normalize
1700
  /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1701
  /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1702
  /// that it saves us from materializing N0 and N1 in an integer register.
1703
  /// Targets that are able to perform and/or on flags should return false here.
1704
  virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
1705
33.6k
                                               EVT VT) const {
1706
33.6k
    // If a target has multiple condition registers, then it likely has logical
1707
33.6k
    // operations on those registers.
1708
33.6k
    if (hasMultipleConditionRegisters())
1709
12.7k
      return false;
1710
20.9k
    // Only do the transform if the value won't be split into multiple
1711
20.9k
    // registers.
1712
20.9k
    LegalizeTypeAction Action = getTypeAction(Context, VT);
1713
20.9k
    return Action != TypeExpandInteger && 
Action != TypeExpandFloat20.4k
&&
1714
20.9k
      
Action != TypeSplitVector20.4k
;
1715
20.9k
  }
1716
1717
  /// Return true if a select of constants (select Cond, C1, C2) should be
1718
  /// transformed into simple math ops with the condition value. For example:
1719
  /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1720
8.07k
  virtual bool convertSelectOfConstantsToMath(EVT VT) const {
1721
8.07k
    return false;
1722
8.07k
  }
1723
1724
  /// Return true if it is profitable to transform an integer
1725
  /// multiplication-by-constant into simpler operations like shifts and adds.
1726
  /// This may be true if the target does not directly support the
1727
  /// multiplication operation for the specified type or the sequence of simpler
1728
  /// ops is faster than the multiply.
1729
103k
  virtual bool decomposeMulByConstant(EVT VT, SDValue C) const {
1730
103k
    return false;
1731
103k
  }
1732
1733
  //===--------------------------------------------------------------------===//
1734
  // TargetLowering Configuration Methods - These methods should be invoked by
1735
  // the derived class constructor to configure this object for the target.
1736
  //
1737
protected:
1738
  /// Specify how the target extends the result of integer and floating point
1739
  /// boolean values from i1 to a wider type.  See getBooleanContents.
1740
45.6k
  void setBooleanContents(BooleanContent Ty) {
1741
45.6k
    BooleanContents = Ty;
1742
45.6k
    BooleanFloatContents = Ty;
1743
45.6k
  }
1744
1745
  /// Specify how the target extends the result of integer and floating point
1746
  /// boolean values from i1 to a wider type.  See getBooleanContents.
1747
1.25k
  void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1748
1.25k
    BooleanContents = IntTy;
1749
1.25k
    BooleanFloatContents = FloatTy;
1750
1.25k
  }
1751
1752
  /// Specify how the target extends the result of a vector boolean value from a
1753
  /// vector of i1 to a wider type.  See getBooleanContents.
1754
44.9k
  void setBooleanVectorContents(BooleanContent Ty) {
1755
44.9k
    BooleanVectorContents = Ty;
1756
44.9k
  }
1757
1758
  /// Specify the target scheduling preference.
1759
37.6k
  void setSchedulingPreference(Sched::Preference Pref) {
1760
37.6k
    SchedPreferenceInfo = Pref;
1761
37.6k
  }
1762
1763
  /// Indicate whether this target prefers to use _setjmp to implement
1764
  /// llvm.setjmp or the version without _.  Defaults to false.
1765
14.1k
  void setUseUnderscoreSetJmp(bool Val) {
1766
14.1k
    UseUnderscoreSetJmp = Val;
1767
14.1k
  }
1768
1769
  /// Indicate whether this target prefers to use _longjmp to implement
1770
  /// llvm.longjmp or the version without _.  Defaults to false.
1771
14.1k
  void setUseUnderscoreLongJmp(bool Val) {
1772
14.1k
    UseUnderscoreLongJmp = Val;
1773
14.1k
  }
1774
1775
  /// Indicate the minimum number of blocks to generate jump tables.
1776
  void setMinimumJumpTableEntries(unsigned Val);
1777
1778
  /// Indicate the maximum number of entries in jump tables.
1779
  /// Set to zero to generate unlimited jump tables.
1780
  void setMaximumJumpTableSize(unsigned);
1781
1782
  /// If set to a physical register, this specifies the register that
1783
  /// llvm.savestack/llvm.restorestack should save and restore.
1784
42.2k
  void setStackPointerRegisterToSaveRestore(unsigned R) {
1785
42.2k
    StackPointerRegisterToSaveRestore = R;
1786
42.2k
  }
1787
1788
  /// Tells the code generator that the target has multiple (allocatable)
1789
  /// condition registers that can be used to store the results of comparisons
1790
  /// for use by selects and conditional branches. With multiple condition
1791
  /// registers, the code generator will not aggressively sink comparisons into
1792
  /// the blocks of their users.
1793
4.12k
  void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1794
4.12k
    HasMultipleConditionRegisters = hasManyRegs;
1795
4.12k
  }
1796
1797
  /// Tells the code generator that the target has BitExtract instructions.
1798
  /// The code generator will aggressively sink "shift"s into the blocks of
1799
  /// their users if the users will generate "and" instructions which can be
1800
  /// combined with "shift" to BitExtract instructions.
1801
11.2k
  void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1802
11.2k
    HasExtractBitsInsn = hasExtractInsn;
1803
11.2k
  }
1804
1805
  /// Tells the code generator not to expand logic operations on comparison
1806
  /// predicates into separate sequences that increase the amount of flow
1807
  /// control.
1808
  void setJumpIsExpensive(bool isExpensive = true);
1809
1810
  /// Tells the code generator that this target supports floating point
1811
  /// exceptions and cares about preserving floating point exception behavior.
1812
2.42k
  void setHasFloatingPointExceptions(bool FPExceptions = true) {
1813
2.42k
    HasFloatingPointExceptions = FPExceptions;
1814
2.42k
  }
1815
1816
  /// Tells the code generator which bitwidths to bypass.
1817
1.70k
  void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1818
1.70k
    BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1819
1.70k
  }
1820
1821
  /// Add the specified register class as an available regclass for the
1822
  /// specified value type. This indicates the selector can handle values of
1823
  /// that class natively.
1824
561k
  void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1825
561k
    assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1826
561k
    RegClassForVT[VT.SimpleTy] = RC;
1827
561k
  }
1828
1829
  /// Return the largest legal super-reg register class of the register class
1830
  /// for the specified type and its associated "cost".
1831
  virtual std::pair<const TargetRegisterClass *, uint8_t>
1832
  findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1833
1834
  /// Once all of the register classes are added, this allows us to compute
1835
  /// derived properties we expose.
1836
  void computeRegisterProperties(const TargetRegisterInfo *TRI);
1837
1838
  /// Indicate that the specified operation does not work with the specified
1839
  /// type and indicate what to do about it. Note that VT may refer to either
1840
  /// the type of a result or that of an operand of Op.
1841
  void setOperationAction(unsigned Op, MVT VT,
1842
299M
                          LegalizeAction Action) {
1843
299M
    assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1844
299M
    OpActions[(unsigned)VT.SimpleTy][Op] = Action;
1845
299M
  }
1846
1847
  /// Indicate that the specified load with extension does not work with the
1848
  /// specified type and indicate what to do about it.
1849
  void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1850
800M
                        LegalizeAction Action) {
1851
800M
    assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1852
800M
           MemVT.isValid() && "Table isn't big enough!");
1853
800M
    assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1854
800M
    unsigned Shift = 4 * ExtType;
1855
800M
    LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
1856
800M
    LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
1857
800M
  }
1858
1859
  /// Indicate that the specified truncating store does not work with the
1860
  /// specified type and indicate what to do about it.
1861
  void setTruncStoreAction(MVT ValVT, MVT MemVT,
1862
286M
                           LegalizeAction Action) {
1863
286M
    assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1864
286M
    TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
1865
286M
  }
1866
1867
  /// Indicate that the specified indexed load does or does not work with the
1868
  /// specified type and indicate what to do abort it.
1869
  ///
1870
  /// NOTE: All indexed mode loads are initialized to Expand in
1871
  /// TargetLowering.cpp
1872
  void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1873
21.4M
                            LegalizeAction Action) {
1874
21.4M
    assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1875
21.4M
           (unsigned)Action < 0xf && "Table isn't big enough!");
1876
21.4M
    // Load action are kept in the upper half.
1877
21.4M
    IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1878
21.4M
    IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1879
21.4M
  }
1880
1881
  /// Indicate that the specified indexed store does or does not work with the
1882
  /// specified type and indicate what to do about it.
1883
  ///
1884
  /// NOTE: All indexed mode stores are initialized to Expand in
1885
  /// TargetLowering.cpp
1886
  void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1887
21.4M
                             LegalizeAction Action) {
1888
21.4M
    assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1889
21.4M
           (unsigned)Action < 0xf && "Table isn't big enough!");
1890
21.4M
    // Store action are kept in the lower half.
1891
21.4M
    IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1892
21.4M
    IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1893
21.4M
  }
1894
1895
  /// Indicate that the specified condition code is or isn't supported on the
1896
  /// target and indicate what to do about it.
1897
  void setCondCodeAction(ISD::CondCode CC, MVT VT,
1898
285k
                         LegalizeAction Action) {
1899
285k
    assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1900
285k
           "Table isn't big enough!");
1901
285k
    assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1902
285k
    /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
1903
285k
    /// value and the upper 29 bits index into the second dimension of the array
1904
285k
    /// to select what 32-bit value to use.
1905
285k
    uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1906
285k
    CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
1907
285k
    CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
1908
285k
  }
1909
1910
  /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1911
  /// to trying a larger integer/fp until it can find one that works. If that
1912
  /// default is insufficient, this method can be used by the target to override
1913
  /// the default.
1914
1.62M
  void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1915
1.62M
    PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1916
1.62M
  }
1917
1918
  /// Convenience method to set an operation to Promote and specify the type
1919
  /// in a single call.
1920
449k
  void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1921
449k
    setOperationAction(Opc, OrigVT, Promote);
1922
449k
    AddPromotedToType(Opc, OrigVT, DestVT);
1923
449k
  }
1924
1925
  /// Targets should invoke this method for each target independent node that
1926
  /// they want to provide a custom DAG combiner for by implementing the
1927
  /// PerformDAGCombine virtual method.
1928
1.09M
  void setTargetDAGCombine(ISD::NodeType NT) {
1929
1.09M
    assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1930
1.09M
    TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1931
1.09M
  }
1932
1933
  /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1934
0
  void setJumpBufSize(unsigned Size) {
1935
0
    JumpBufSize = Size;
1936
0
  }
1937
1938
  /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1939
  /// 0
1940
0
  void setJumpBufAlignment(unsigned Align) {
1941
0
    JumpBufAlignment = Align;
1942
0
  }
1943
1944
  /// Set the target's minimum function alignment (in log2(bytes))
1945
29.7k
  void setMinFunctionAlignment(unsigned Align) {
1946
29.7k
    MinFunctionAlignment = Align;
1947
29.7k
  }
1948
1949
  /// Set the target's preferred function alignment.  This should be set if
1950
  /// there is a performance benefit to higher-than-minimum alignment (in
1951
  /// log2(bytes))
1952
24.3k
  void setPrefFunctionAlignment(unsigned Align) {
1953
24.3k
    PrefFunctionAlignment = Align;
1954
24.3k
  }
1955
1956
  /// Set the target's preferred loop alignment. Default alignment is zero, it
1957
  /// means the target does not care about loop alignment.  The alignment is
1958
  /// specified in log2(bytes). The target may also override
1959
  /// getPrefLoopAlignment to provide per-loop values.
1960
29.9k
  void setPrefLoopAlignment(unsigned Align) {
1961
29.9k
    PrefLoopAlignment = Align;
1962
29.9k
  }
1963
1964
  /// Set the minimum stack alignment of an argument (in log2(bytes)).
1965
18.5k
  void setMinStackArgumentAlignment(unsigned Align) {
1966
18.5k
    MinStackArgumentAlignment = Align;
1967
18.5k
  }
1968
1969
  /// Set the maximum atomic operation size supported by the
1970
  /// backend. Atomic operations greater than this size (as well as
1971
  /// ones that are not naturally aligned), will be expanded by
1972
  /// AtomicExpandPass into an __atomic_* library call.
1973
1.41k
  void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
1974
1.41k
    MaxAtomicSizeInBitsSupported = SizeInBits;
1975
1.41k
  }
1976
1977
  /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
1978
1.41k
  void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
1979
1.41k
    MinCmpXchgSizeInBits = SizeInBits;
1980
1.41k
  }
1981
1982
  /// Sets whether unaligned atomic operations are supported.
1983
0
  void setSupportsUnalignedAtomics(bool UnalignedSupported) {
1984
0
    SupportsUnalignedAtomics = UnalignedSupported;
1985
0
  }
1986
1987
public:
1988
  //===--------------------------------------------------------------------===//
1989
  // Addressing mode description hooks (used by LSR etc).
1990
  //
1991
1992
  /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1993
  /// instructions reading the address. This allows as much computation as
1994
  /// possible to be done in the address mode for that operand. This hook lets
1995
  /// targets also pass back when this should be done on intrinsics which
1996
  /// load/store.
1997
  virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
1998
                                    SmallVectorImpl<Value*> &/*Ops*/,
1999
807k
                                    Type *&/*AccessTy*/) const {
2000
807k
    return false;
2001
807k
  }
2002
2003
  /// This represents an addressing mode of:
2004
  ///    BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
2005
  /// If BaseGV is null,  there is no BaseGV.
2006
  /// If BaseOffs is zero, there is no base offset.
2007
  /// If HasBaseReg is false, there is no base register.
2008
  /// If Scale is zero, there is no ScaleReg.  Scale of 1 indicates a reg with
2009
  /// no scale.
2010
  struct AddrMode {
2011
    GlobalValue *BaseGV = nullptr;
2012
    int64_t      BaseOffs = 0;
2013
    bool         HasBaseReg = false;
2014
    int64_t      Scale = 0;
2015
69.0M
    AddrMode() = default;
2016
  };
2017
2018
  /// Return true if the addressing mode represented by AM is legal for this
2019
  /// target, for a load/store of the specified type.
2020
  ///
2021
  /// The type may be VoidTy, in which case only return true if the addressing
2022
  /// mode is legal for a load/store of any legal type.  TODO: Handle
2023
  /// pre/postinc as well.
2024
  ///
2025
  /// If the address space cannot be determined, it will be -1.
2026
  ///
2027
  /// TODO: Remove default argument
2028
  virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
2029
                                     Type *Ty, unsigned AddrSpace,
2030
                                     Instruction *I = nullptr) const;
2031
2032
  /// Return the cost of the scaling factor used in the addressing mode
2033
  /// represented by AM for this target, for a load/store of the specified type.
2034
  ///
2035
  /// If the AM is supported, the return value must be >= 0.
2036
  /// If the AM is not supported, it returns a negative value.
2037
  /// TODO: Handle pre/postinc as well.
2038
  /// TODO: Remove default argument
2039
  virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
2040
7.56k
                                   Type *Ty, unsigned AS = 0) const {
2041
7.56k
    // Default: assume that any scaling factor used in a legal AM is free.
2042
7.56k
    if (isLegalAddressingMode(DL, AM, Ty, AS))
2043
7.56k
      return 0;
2044
0
    return -1;
2045
0
  }
2046
2047
  /// Return true if the specified immediate is legal icmp immediate, that is
2048
  /// the target has icmp instructions which can compare a register against the
2049
  /// immediate without having to materialize the immediate into a register.
2050
35.1k
  virtual bool isLegalICmpImmediate(int64_t) const {
2051
35.1k
    return true;
2052
35.1k
  }
2053
2054
  /// Return true if the specified immediate is legal add immediate, that is the
2055
  /// target has add instructions which can add a register with the immediate
2056
  /// without having to materialize the immediate into a register.
2057
1.57k
  virtual bool isLegalAddImmediate(int64_t) const {
2058
1.57k
    return true;
2059
1.57k
  }
2060
2061
  /// Return true if it's significantly cheaper to shift a vector by a uniform
2062
  /// scalar than by an amount which will vary across each lane. On x86, for
2063
  /// example, there is a "psllw" instruction for the former case, but no simple
2064
  /// instruction for a general "a << b" operation on vectors.
2065
161k
  virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
2066
161k
    return false;
2067
161k
  }
2068
2069
  /// Returns true if the opcode is a commutative binary operation.
2070
119M
  virtual bool isCommutativeBinOp(unsigned Opcode) const {
2071
119M
    // FIXME: This should get its info from the td file.
2072
119M
    switch (Opcode) {
2073
119M
    case ISD::ADD:
2074
18.2M
    case ISD::SMIN:
2075
18.2M
    case ISD::SMAX:
2076
18.2M
    case ISD::UMIN:
2077
18.2M
    case ISD::UMAX:
2078
18.2M
    case ISD::MUL:
2079
18.2M
    case ISD::MULHU:
2080
18.2M
    case ISD::MULHS:
2081
18.2M
    case ISD::SMUL_LOHI:
2082
18.2M
    case ISD::UMUL_LOHI:
2083
18.2M
    case ISD::FADD:
2084
18.2M
    case ISD::FMUL:
2085
18.2M
    case ISD::AND:
2086
18.2M
    case ISD::OR:
2087
18.2M
    case ISD::XOR:
2088
18.2M
    case ISD::SADDO:
2089
18.2M
    case ISD::UADDO:
2090
18.2M
    case ISD::ADDC:
2091
18.2M
    case ISD::ADDE:
2092
18.2M
    case ISD::FMINNUM:
2093
18.2M
    case ISD::FMAXNUM:
2094
18.2M
    case ISD::FMINNAN:
2095
18.2M
    case ISD::FMAXNAN:
2096
18.2M
      return true;
2097
101M
    default: return false;
2098
119M
    }
2099
119M
  }
2100
2101
  /// Return true if it's free to truncate a value of type FromTy to type
2102
  /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
2103
  /// by referencing its sub-register AX.
2104
  /// Targets must return false when FromTy <= ToTy.
2105
91
  virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
2106
91
    return false;
2107
91
  }
2108
2109
  /// Return true if a truncation from FromTy to ToTy is permitted when deciding
2110
  /// whether a call is in tail position. Typically this means that both results
2111
  /// would be assigned to the same register or stack slot, but it could mean
2112
  /// the target performs adequate checks of its own before proceeding with the
2113
  /// tail call.  Targets must return false when FromTy <= ToTy.
2114
5
  virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
2115
5
    return false;
2116
5
  }
2117
2118
6.29k
  virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
2119
6.29k
    return false;
2120
6.29k
  }
2121
2122
44.5k
  virtual bool isProfitableToHoist(Instruction *I) const { return true; }
2123
2124
  /// Return true if the extension represented by \p I is free.
2125
  /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2126
  /// this method can use the context provided by \p I to decide
2127
  /// whether or not \p I is free.
2128
  /// This method extends the behavior of the is[Z|FP]ExtFree family.
2129
  /// In other words, if is[Z|FP]Free returns true, then this method
2130
  /// returns true as well. The converse is not true.
2131
  /// The target can perform the adequate checks by overriding isExtFreeImpl.
2132
  /// \pre \p I must be a sign, zero, or fp extension.
2133
2.02M
  bool isExtFree(const Instruction *I) const {
2134
2.02M
    switch (I->getOpcode()) {
2135
2.02M
    case Instruction::FPExt:
2136
73.1k
      if (isFPExtFree(EVT::getEVT(I->getType()),
2137
73.1k
                      EVT::getEVT(I->getOperand(0)->getType())))
2138
6
        return true;
2139
73.1k
      break;
2140
787k
    case Instruction::ZExt:
2141
787k
      if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2142
364k
        return true;
2143
422k
      break;
2144
1.16M
    case Instruction::SExt:
2145
1.16M
      break;
2146
422k
    default:
2147
0
      llvm_unreachable("Instruction is not an extension");
2148
1.66M
    }
2149
1.66M
    return isExtFreeImpl(I);
2150
1.66M
  }
2151
2152
  /// Return true if \p Load and \p Ext can form an ExtLoad.
2153
  /// For example, in AArch64
2154
  ///   %L = load i8, i8* %ptr
2155
  ///   %E = zext i8 %L to i32
2156
  /// can be lowered into one load instruction
2157
  ///   ldrb w0, [x0]
2158
  bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2159
691k
                 const DataLayout &DL) const {
2160
691k
    EVT VT = getValueType(DL, Ext->getType());
2161
691k
    EVT LoadVT = getValueType(DL, Load->getType());
2162
691k
2163
691k
    // If the load has other users and the truncate is not free, the ext
2164
691k
    // probably isn't free.
2165
691k
    if (!Load->hasOneUse() && 
(300k
isTypeLegal(LoadVT)300k
||
!isTypeLegal(VT)139k
) &&
2166
691k
        
!isTruncateFree(Ext->getType(), Load->getType())162k
)
2167
422
      return false;
2168
691k
2169
691k
    // Check whether the target supports casts folded into loads.
2170
691k
    unsigned LType;
2171
691k
    if (isa<ZExtInst>(Ext))
2172
275k
      LType = ISD::ZEXTLOAD;
2173
415k
    else {
2174
415k
      assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
2175
415k
      LType = ISD::SEXTLOAD;
2176
415k
    }
2177
691k
2178
691k
    return isLoadExtLegal(LType, VT, LoadVT);
2179
691k
  }
2180
2181
  /// Return true if any actual instruction that defines a value of type FromTy
2182
  /// implicitly zero-extends the value to ToTy in the result register.
2183
  ///
2184
  /// The function should return true when it is likely that the truncate can
2185
  /// be freely folded with an instruction defining a value of FromTy. If
2186
  /// the defining instruction is unknown (because you're looking at a
2187
  /// function argument, PHI, etc.) then the target may require an
2188
  /// explicit truncate, which is not necessarily free, but this function
2189
  /// does not deal with those cases.
2190
  /// Targets must return false when FromTy >= ToTy.
2191
43.8k
  virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2192
43.8k
    return false;
2193
43.8k
  }
2194
2195
16.2k
  virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2196
16.2k
    return false;
2197
16.2k
  }
2198
2199
  /// Return true if the target supplies and combines to a paired load
2200
  /// two loaded values of type LoadedType next to each other in memory.
2201
  /// RequiredAlignment gives the minimal alignment constraints that must be met
2202
  /// to be able to select this paired load.
2203
  ///
2204
  /// This information is *not* used to generate actual paired loads, but it is
2205
  /// used to generate a sequence of loads that is easier to combine into a
2206
  /// paired load.
2207
  /// For instance, something like this:
2208
  /// a = load i64* addr
2209
  /// b = trunc i64 a to i32
2210
  /// c = lshr i64 a, 32
2211
  /// d = trunc i64 c to i32
2212
  /// will be optimized into:
2213
  /// b = load i32* addr1
2214
  /// d = load i32* addr2
2215
  /// Where addr1 = addr2 +/- sizeof(i32).
2216
  ///
2217
  /// In other words, unless the target performs a post-isel load combining,
2218
  /// this information should not be provided because it will generate more
2219
  /// loads.
2220
  virtual bool hasPairedLoad(EVT /*LoadedType*/,
2221
14.4k
                             unsigned & /*RequiredAlignment*/) const {
2222
14.4k
    return false;
2223
14.4k
  }
2224
2225
  /// Return true if the target has a vector blend instruction.
2226
37.3k
  virtual bool hasVectorBlend() const { return false; }
2227
2228
  /// Get the maximum supported factor for interleaved memory accesses.
2229
  /// Default to be the minimum interleave factor: 2.
2230
0
  virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2231
2232
  /// Lower an interleaved load to target specific intrinsics. Return
2233
  /// true on success.
2234
  ///
2235
  /// \p LI is the vector load instruction.
2236
  /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2237
  /// \p Indices is the corresponding indices for each shufflevector.
2238
  /// \p Factor is the interleave factor.
2239
  virtual bool lowerInterleavedLoad(LoadInst *LI,
2240
                                    ArrayRef<ShuffleVectorInst *> Shuffles,
2241
                                    ArrayRef<unsigned> Indices,
2242
0
                                    unsigned Factor) const {
2243
0
    return false;
2244
0
  }
2245
2246
  /// Lower an interleaved store to target specific intrinsics. Return
2247
  /// true on success.
2248
  ///
2249
  /// \p SI is the vector store instruction.
2250
  /// \p SVI is the shufflevector to RE-interleave the stored vector.
2251
  /// \p Factor is the interleave factor.
2252
  virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
2253
0
                                     unsigned Factor) const {
2254
0
    return false;
2255
0
  }
2256
2257
  /// Return true if zero-extending the specific node Val to type VT2 is free
2258
  /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2259
  /// because it's folded such as X86 zero-extending loads).
2260
13.8k
  virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2261
13.8k
    return isZExtFree(Val.getValueType(), VT2);
2262
13.8k
  }
2263
2264
  /// Return true if an fpext operation is free (for instance, because
2265
  /// single-precision floating-point numbers are implicitly extended to
2266
  /// double-precision).
2267
73.8k
  virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2268
73.8k
    assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2269
73.8k
           "invalid fpext types");
2270
73.8k
    return false;
2271
73.8k
  }
2272
2273
  /// Return true if an fpext operation input to an \p Opcode operation is free
2274
  /// (for instance, because half-precision floating-point numbers are
2275
  /// implicitly extended to float-precision) for an FMA instruction.
2276
44
  virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
2277
44
    assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2278
44
           "invalid fpext types");
2279
44
    return isFPExtFree(DestVT, SrcVT);
2280
44
  }
2281
2282
  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2283
  /// extend node) is profitable.
2284
7.77k
  virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2285
2286
  /// Return true if an fneg operation is free to the point where it is never
2287
  /// worthwhile to replace it with a bitwise operation.
2288
8.10k
  virtual bool isFNegFree(EVT VT) const {
2289
8.10k
    assert(VT.isFloatingPoint());
2290
8.10k
    return false;
2291
8.10k
  }
2292
2293
  /// Return true if an fabs operation is free to the point where it is never
2294
  /// worthwhile to replace it with a bitwise operation.
2295
7.43k
  virtual bool isFAbsFree(EVT VT) const {
2296
7.43k
    assert(VT.isFloatingPoint());
2297
7.43k
    return false;
2298
7.43k
  }
2299
2300
  /// Return true if an FMA operation is faster than a pair of fmul and fadd
2301
  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2302
  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2303
  ///
2304
  /// NOTE: This may be called before legalization on types for which FMAs are
2305
  /// not legal, but should return true if those types will eventually legalize
2306
  /// to types that support FMAs. After legalization, it will only be called on
2307
  /// types that support FMAs (via Legal or Custom actions)
2308
4.83k
  virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
2309
4.83k
    return false;
2310
4.83k
  }
2311
2312
  /// Return true if it's profitable to narrow operations of type VT1 to
2313
  /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2314
  /// i32 to i16.
2315
5.77k
  virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2316
5.77k
    return false;
2317
5.77k
  }
2318
2319
  /// Return true if it is beneficial to convert a load of a constant to
2320
  /// just the constant itself.
2321
  /// On some targets it might be more efficient to use a combination of
2322
  /// arithmetic instructions to materialize the constant instead of loading it
2323
  /// from a constant pool.
2324
  virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2325
12
                                                 Type *Ty) const {
2326
12
    return false;
2327
12
  }
2328
2329
  /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2330
  /// from this source type with this index. This is needed because
2331
  /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2332
  /// the first element, and only the target knows which lowering is cheap.
2333
  virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2334
59
                                       unsigned Index) const {
2335
59
    return false;
2336
59
  }
2337
2338
  // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2339
  // even if the vector itself has multiple uses.
2340
723
  virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2341
723
    return false;
2342
723
  }
2343
2344
  // Return true if CodeGenPrepare should consider splitting large offset of a
2345
  // GEP to make the GEP fit into the addressing mode and can be sunk into the
2346
  // same blocks of its users.
2347
3.15k
  virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
2348
2349
  //===--------------------------------------------------------------------===//
2350
  // Runtime Library hooks
2351
  //
2352
2353
  /// Rename the default libcall routine name for the specified libcall.
2354
23.3M
  void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2355
23.3M
    LibcallRoutineNames[Call] = Name;
2356
23.3M
  }
2357
2358
  /// Get the libcall routine name for the specified libcall.
2359
105k
  const char *getLibcallName(RTLIB::Libcall Call) const {
2360
105k
    return LibcallRoutineNames[Call];
2361
105k
  }
2362
2363
  /// Override the default CondCode to be used to test the result of the
2364
  /// comparison libcall against zero.
2365
75.3k
  void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
2366
75.3k
    CmpLibcallCCs[Call] = CC;
2367
75.3k
  }
2368
2369
  /// Get the CondCode that's to be used to test the result of the comparison
2370
  /// libcall against zero.
2371
1.16k
  ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
2372
1.16k
    return CmpLibcallCCs[Call];
2373
1.16k
  }
2374
2375
  /// Set the CallingConv that should be used for the specified libcall.
2376
24.0M
  void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
2377
24.0M
    LibcallCallingConvs[Call] = CC;
2378
24.0M
  }
2379
2380
  /// Get the CallingConv that should be used for the specified libcall.
2381
17.7k
  CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
2382
17.7k
    return LibcallCallingConvs[Call];
2383
17.7k
  }
2384
2385
  /// Execute target specific actions to finalize target lowering.
2386
  /// This is used to set extra flags in MachineFrameInformation and freezing
2387
  /// the set of reserved registers.
2388
  /// The default implementation just freezes the set of reserved registers.
2389
  virtual void finalizeLowering(MachineFunction &MF) const;
2390
2391
private:
2392
  const TargetMachine &TM;
2393
2394
  /// Tells the code generator that the target has multiple (allocatable)
2395
  /// condition registers that can be used to store the results of comparisons
2396
  /// for use by selects and conditional branches. With multiple condition
2397
  /// registers, the code generator will not aggressively sink comparisons into
2398
  /// the blocks of their users.
2399
  bool HasMultipleConditionRegisters;
2400
2401
  /// Tells the code generator that the target has BitExtract instructions.
2402
  /// The code generator will aggressively sink "shift"s into the blocks of
2403
  /// their users if the users will generate "and" instructions which can be
2404
  /// combined with "shift" to BitExtract instructions.
2405
  bool HasExtractBitsInsn;
2406
2407
  /// Tells the code generator to bypass slow divide or remainder
2408
  /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2409
  /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2410
  /// div/rem when the operands are positive and less than 256.
2411
  DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
2412
2413
  /// Tells the code generator that it shouldn't generate extra flow control
2414
  /// instructions and should attempt to combine flow control instructions via
2415
  /// predication.
2416
  bool JumpIsExpensive;
2417
2418
  /// Whether the target supports or cares about preserving floating point
2419
  /// exception behavior.
2420
  bool HasFloatingPointExceptions;
2421
2422
  /// This target prefers to use _setjmp to implement llvm.setjmp.
2423
  ///
2424
  /// Defaults to false.
2425
  bool UseUnderscoreSetJmp;
2426
2427
  /// This target prefers to use _longjmp to implement llvm.longjmp.
2428
  ///
2429
  /// Defaults to false.
2430
  bool UseUnderscoreLongJmp;
2431
2432
  /// Information about the contents of the high-bits in boolean values held in
2433
  /// a type wider than i1. See getBooleanContents.
2434
  BooleanContent BooleanContents;
2435
2436
  /// Information about the contents of the high-bits in boolean values held in
2437
  /// a type wider than i1. See getBooleanContents.
2438
  BooleanContent BooleanFloatContents;
2439
2440
  /// Information about the contents of the high-bits in boolean vector values
2441
  /// when the element type is wider than i1. See getBooleanContents.
2442
  BooleanContent BooleanVectorContents;
2443
2444
  /// The target scheduling preference: shortest possible total cycles or lowest
2445
  /// register usage.
2446
  Sched::Preference SchedPreferenceInfo;
2447
2448
  /// The size, in bytes, of the target's jmp_buf buffers
2449
  unsigned JumpBufSize;
2450
2451
  /// The alignment, in bytes, of the target's jmp_buf buffers
2452
  unsigned JumpBufAlignment;
2453
2454
  /// The minimum alignment that any argument on the stack needs to have.
2455
  unsigned MinStackArgumentAlignment;
2456
2457
  /// The minimum function alignment (used when optimizing for size, and to
2458
  /// prevent explicitly provided alignment from leading to incorrect code).
2459
  unsigned MinFunctionAlignment;
2460
2461
  /// The preferred function alignment (used when alignment unspecified and
2462
  /// optimizing for speed).
2463
  unsigned PrefFunctionAlignment;
2464
2465
  /// The preferred loop alignment.
2466
  unsigned PrefLoopAlignment;
2467
2468
  /// Size in bits of the maximum atomics size the backend supports.
2469
  /// Accesses larger than this will be expanded by AtomicExpandPass.
2470
  unsigned MaxAtomicSizeInBitsSupported;
2471
2472
  /// Size in bits of the minimum cmpxchg or ll/sc operation the
2473
  /// backend supports.
2474
  unsigned MinCmpXchgSizeInBits;
2475
2476
  /// This indicates if the target supports unaligned atomic operations.
2477
  bool SupportsUnalignedAtomics;
2478
2479
  /// If set to a physical register, this specifies the register that
2480
  /// llvm.savestack/llvm.restorestack should save and restore.
2481
  unsigned StackPointerRegisterToSaveRestore;
2482
2483
  /// This indicates the default register class to use for each ValueType the
2484
  /// target supports natively.
2485
  const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2486
  unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
2487
  MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2488
2489
  /// This indicates the "representative" register class to use for each
2490
  /// ValueType the target supports natively. This information is used by the
2491
  /// scheduler to track register pressure. By default, the representative
2492
  /// register class is the largest legal super-reg register class of the
2493
  /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2494
  /// representative class would be GR32.
2495
  const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2496
2497
  /// This indicates the "cost" of the "representative" register class for each
2498
  /// ValueType. The cost is used by the scheduler to approximate register
2499
  /// pressure.
2500
  uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2501
2502
  /// For any value types we are promoting or expanding, this contains the value
2503
  /// type that we are changing to.  For Expanded types, this contains one step
2504
  /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2505
  /// (e.g. i64 -> i16).  For types natively supported by the system, this holds
2506
  /// the same type (e.g. i32 -> i32).
2507
  MVT TransformToType[MVT::LAST_VALUETYPE];
2508
2509
  /// For each operation and each value type, keep a LegalizeAction that
2510
  /// indicates how instruction selection should deal with the operation.  Most
2511
  /// operations are Legal (aka, supported natively by the target), but
2512
  /// operations that are not should be described.  Note that operations on
2513
  /// non-legal value types are not described here.
2514
  LegalizeAction OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
2515
2516
  /// For each load extension type and each value type, keep a LegalizeAction
2517
  /// that indicates how instruction selection should deal with a load of a
2518
  /// specific value type and extension type. Uses 4-bits to store the action
2519
  /// for each of the 4 load ext types.
2520
  uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2521
2522
  /// For each value type pair keep a LegalizeAction that indicates whether a
2523
  /// truncating store of a specific value type and truncating type is legal.
2524
  LegalizeAction TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2525
2526
  /// For each indexed mode and each value type, keep a pair of LegalizeAction
2527
  /// that indicates how instruction selection should deal with the load /
2528
  /// store.
2529
  ///
2530
  /// The first dimension is the value_type for the reference. The second
2531
  /// dimension represents the various modes for load store.
2532
  uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2533
2534
  /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2535
  /// indicates how instruction selection should deal with the condition code.
2536
  ///
2537
  /// Because each CC action takes up 4 bits, we need to have the array size be
2538
  /// large enough to fit all of the value types. This can be done by rounding
2539
  /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2540
  uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2541
2542
protected:
2543
  ValueTypeActionImpl ValueTypeActions;
2544
2545
private:
2546
  LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2547
2548
  /// Targets can specify ISD nodes that they would like PerformDAGCombine
2549
  /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2550
  /// array.
2551
  unsigned char
2552
  TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2553
2554
  /// For operations that must be promoted to a specific type, this holds the
2555
  /// destination type.  This map should be sparse, so don't hold it as an
2556
  /// array.
2557
  ///
2558
  /// Targets add entries to this map with AddPromotedToType(..), clients access
2559
  /// this with getTypeToPromoteTo(..).
2560
  std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2561
    PromoteToType;
2562
2563
  /// Stores the name each libcall.
2564
  const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
2565
2566
  /// The ISD::CondCode that should be used to test the result of each of the
2567
  /// comparison libcall against zero.
2568
  ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2569
2570
  /// Stores the CallingConv that should be used for each libcall.
2571
  CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2572
2573
  /// Set default libcall names and calling conventions.
2574
  void InitLibcalls(const Triple &TT);
2575
2576
protected:
2577
  /// Return true if the extension represented by \p I is free.
2578
  /// \pre \p I is a sign, zero, or fp extension and
2579
  ///      is[Z|FP]ExtFree of the related types is not true.
2580
232k
  virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2581
2582
  /// Depth that GatherAllAliases should should continue looking for chain
2583
  /// dependencies when trying to find a more preferable chain. As an
2584
  /// approximation, this should be more than the number of consecutive stores
2585
  /// expected to be merged.
2586
  unsigned GatherAllAliasesMaxDepth;
2587
2588
  /// Specify maximum number of store instructions per memset call.
2589
  ///
2590
  /// When lowering \@llvm.memset this field specifies the maximum number of
2591
  /// store operations that may be substituted for the call to memset. Targets
2592
  /// must set this value based on the cost threshold for that target. Targets
2593
  /// should assume that the memset will be done using as many of the largest
2594
  /// store operations first, followed by smaller ones, if necessary, per
2595
  /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2596
  /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2597
  /// store.  This only applies to setting a constant array of a constant size.
2598
  unsigned MaxStoresPerMemset;
2599
2600
  /// Maximum number of stores operations that may be substituted for the call
2601
  /// to memset, used for functions with OptSize attribute.
2602
  unsigned MaxStoresPerMemsetOptSize;
2603
2604
  /// Specify maximum bytes of store instructions per memcpy call.
2605
  ///
2606
  /// When lowering \@llvm.memcpy this field specifies the maximum number of
2607
  /// store operations that may be substituted for a call to memcpy. Targets
2608
  /// must set this value based on the cost threshold for that target. Targets
2609
  /// should assume that the memcpy will be done using as many of the largest
2610
  /// store operations first, followed by smaller ones, if necessary, per
2611
  /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2612
  /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2613
  /// and one 1-byte store. This only applies to copying a constant array of
2614
  /// constant size.
2615
  unsigned MaxStoresPerMemcpy;
2616
2617
2618
  /// \brief Specify max number of store instructions to glue in inlined memcpy.
2619
  ///
2620
  /// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number
2621
  /// of store instructions to keep together. This helps in pairing and
2622
  //  vectorization later on.
2623
  unsigned MaxGluedStoresPerMemcpy = 0;
2624
2625
  /// Maximum number of store operations that may be substituted for a call to
2626
  /// memcpy, used for functions with OptSize attribute.
2627
  unsigned MaxStoresPerMemcpyOptSize;
2628
  unsigned MaxLoadsPerMemcmp;
2629
  unsigned MaxLoadsPerMemcmpOptSize;
2630
2631
  /// Specify maximum bytes of store instructions per memmove call.
2632
  ///
2633
  /// When lowering \@llvm.memmove this field specifies the maximum number of
2634
  /// store instructions that may be substituted for a call to memmove. Targets
2635
  /// must set this value based on the cost threshold for that target. Targets
2636
  /// should assume that the memmove will be done using as many of the largest
2637
  /// store operations first, followed by smaller ones, if necessary, per
2638
  /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2639
  /// with 8-bit alignment would result in nine 1-byte stores.  This only
2640
  /// applies to copying a constant array of constant size.
2641
  unsigned MaxStoresPerMemmove;
2642
2643
  /// Maximum number of store instructions that may be substituted for a call to
2644
  /// memmove, used for functions with OptSize attribute.
2645
  unsigned MaxStoresPerMemmoveOptSize;
2646
2647
  /// Tells the code generator that select is more expensive than a branch if
2648
  /// the branch is usually predicted right.
2649
  bool PredictableSelectIsExpensive;
2650
2651
  /// \see enableExtLdPromotion.
2652
  bool EnableExtLdPromotion;
2653
2654
  /// Return true if the value types that can be represented by the specified
2655
  /// register class are all legal.
2656
  bool isLegalRC(const TargetRegisterInfo &TRI,
2657
                 const TargetRegisterClass &RC) const;
2658
2659
  /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2660
  /// sequence of memory operands that is recognized by PrologEpilogInserter.
2661
  MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2662
                                    MachineBasicBlock *MBB) const;
2663
2664
  /// Replace/modify the XRay custom event operands with target-dependent
2665
  /// details.
2666
  MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
2667
                                         MachineBasicBlock *MBB) const;
2668
2669
  /// Replace/modify the XRay typed event operands with target-dependent
2670
  /// details.
2671
  MachineBasicBlock *emitXRayTypedEvent(MachineInstr &MI,
2672
                                        MachineBasicBlock *MBB) const;
2673
};
2674
2675
/// This class defines information used to lower LLVM code to legal SelectionDAG
2676
/// operators that the target instruction selector can accept natively.
2677
///
2678
/// This class also defines callbacks that targets must implement to lower
2679
/// target-specific constructs to SelectionDAG operators.
2680
class TargetLowering : public TargetLoweringBase {
2681
public:
2682
  struct DAGCombinerInfo;
2683
2684
  TargetLowering(const TargetLowering &) = delete;
2685
  TargetLowering &operator=(const TargetLowering &) = delete;
2686
2687
  /// NOTE: The TargetMachine owns TLOF.
2688
  explicit TargetLowering(const TargetMachine &TM);
2689
2690
  bool isPositionIndependent() const;
2691
2692
  virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
2693
                                          FunctionLoweringInfo *FLI,
2694
53.2M
                                          LegacyDivergenceAnalysis *DA) const {
2695
53.2M
    return false;
2696
53.2M
  }
2697
2698
44.7M
  virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
2699
44.7M
    return false;
2700
44.7M
  }
2701
2702
  /// Returns true by value, base pointer and offset pointer and addressing mode
2703
  /// by reference if the node's address can be legally represented as
2704
  /// pre-indexed load / store address.
2705
  virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2706
                                         SDValue &/*Offset*/,
2707
                                         ISD::MemIndexedMode &/*AM*/,
2708
0
                                         SelectionDAG &/*DAG*/) const {
2709
0
    return false;
2710
0
  }
2711
2712
  /// Returns true by value, base pointer and offset pointer and addressing mode
2713
  /// by reference if this node can be combined with a load / store to form a
2714
  /// post-indexed load / store.
2715
  virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2716
                                          SDValue &/*Base*/,
2717
                                          SDValue &/*Offset*/,
2718
                                          ISD::MemIndexedMode &/*AM*/,
2719
0
                                          SelectionDAG &/*DAG*/) const {
2720
0
    return false;
2721
0
  }
2722
2723
  /// Return the entry encoding for a jump table in the current function.  The
2724
  /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2725
  virtual unsigned getJumpTableEncoding() const;
2726
2727
  virtual const MCExpr *
2728
  LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
2729
                            const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2730
0
                            MCContext &/*Ctx*/) const {
2731
0
    llvm_unreachable("Need to implement this hook if target has custom JTIs");
2732
0
  }
2733
2734
  /// Returns relocation base for the given PIC jumptable.
2735
  virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2736
                                           SelectionDAG &DAG) const;
2737
2738
  /// This returns the relocation base for the given PIC jumptable, the same as
2739
  /// getPICJumpTableRelocBase, but as an MCExpr.
2740
  virtual const MCExpr *
2741
  getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2742
                               unsigned JTI, MCContext &Ctx) const;
2743
2744
  /// Return true if folding a constant offset with the given GlobalAddress is
2745
  /// legal.  It is frequently not legal in PIC relocation models.
2746
  virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2747
2748
  bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2749
                            SDValue &Chain) const;
2750
2751
  void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
2752
                           SDValue &NewRHS, ISD::CondCode &CCCode,
2753
                           const SDLoc &DL) const;
2754
2755
  /// Returns a pair of (return value, chain).
2756
  /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2757
  std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2758
                                          EVT RetVT, ArrayRef<SDValue> Ops,
2759
                                          bool isSigned, const SDLoc &dl,
2760
                                          bool doesNotReturn = false,
2761
                                          bool isReturnValueUsed = true) const;
2762
2763
  /// Check whether parameters to a call that are passed in callee saved
2764
  /// registers are the same as from the calling function.  This needs to be
2765
  /// checked for tail call eligibility.
2766
  bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
2767
      const uint32_t *CallerPreservedMask,
2768
      const SmallVectorImpl<CCValAssign> &ArgLocs,
2769
      const SmallVectorImpl<SDValue> &OutVals) const;
2770
2771
  //===--------------------------------------------------------------------===//
2772
  // TargetLowering Optimization Methods
2773
  //
2774
2775
  /// A convenience struct that encapsulates a DAG, and two SDValues for
2776
  /// returning information from TargetLowering to its clients that want to
2777
  /// combine.
2778
  struct TargetLoweringOpt {
2779
    SelectionDAG &DAG;
2780
    bool LegalTys;
2781
    bool LegalOps;
2782
    SDValue Old;
2783
    SDValue New;
2784
2785
    explicit TargetLoweringOpt(SelectionDAG &InDAG,
2786
                               bool LT, bool LO) :
2787
8.60M
      DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2788
2789
162k
    bool LegalTypes() const { return LegalTys; }
2790
118k
    bool LegalOperations() const { return LegalOps; }
2791
2792
394k
    bool CombineTo(SDValue O, SDValue N) {
2793
394k
      Old = O;
2794
394k
      New = N;
2795
394k
      return true;
2796
394k
    }
2797
  };
2798
2799
  /// Check to see if the specified operand of the specified instruction is a
2800
  /// constant integer.  If so, check to see if there are any bits set in the
2801
  /// constant that are not demanded.  If so, shrink the constant and return
2802
  /// true.
2803
  bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2804
                              TargetLoweringOpt &TLO) const;
2805
2806
  // Target hook to do target-specific const optimization, which is called by
2807
  // ShrinkDemandedConstant. This function should return true if the target
2808
  // doesn't want ShrinkDemandedConstant to further optimize the constant.
2809
  virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2810
264k
                                            TargetLoweringOpt &TLO) const {
2811
264k
    return false;
2812
264k
  }
2813
2814
  /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.  This
2815
  /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2816
  /// generalized for targets with other types of implicit widening casts.
2817
  bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2818
                        TargetLoweringOpt &TLO) const;
2819
2820
  /// Helper for SimplifyDemandedBits that can simplify an operation with
2821
  /// multiple uses.  This function simplifies operand \p OpIdx of \p User and
2822
  /// then updates \p User with the simplified version. No other uses of
2823
  /// \p OpIdx are updated. If \p User is the only user of \p OpIdx, this
2824
  /// function behaves exactly like function SimplifyDemandedBits declared
2825
  /// below except that it also updates the DAG by calling
2826
  /// DCI.CommitTargetLoweringOpt.
2827
  bool SimplifyDemandedBits(SDNode *User, unsigned OpIdx, const APInt &Demanded,
2828
                            DAGCombinerInfo &DCI, TargetLoweringOpt &TLO) const;
2829
2830
  /// Look at Op.  At this point, we know that only the DemandedMask bits of the
2831
  /// result of Op are ever used downstream.  If we can use this information to
2832
  /// simplify Op, create a new simplified DAG node and return true, returning
2833
  /// the original and new nodes in Old and New.  Otherwise, analyze the
2834
  /// expression and return a mask of KnownOne and KnownZero bits for the
2835
  /// expression (used to simplify the caller).  The KnownZero/One bits may only
2836
  /// be accurate for those bits in the DemandedMask.
2837
  /// \p AssumeSingleUse When this parameter is true, this function will
2838
  ///    attempt to simplify \p Op even if there are multiple uses.
2839
  ///    Callers are responsible for correctly updating the DAG based on the
2840
  ///    results of this function, because simply replacing replacing TLO.Old
2841
  ///    with TLO.New will be incorrect when this parameter is true and TLO.Old
2842
  ///    has multiple uses.
2843
  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2844
                            KnownBits &Known,
2845
                            TargetLoweringOpt &TLO,
2846
                            unsigned Depth = 0,
2847
                            bool AssumeSingleUse = false) const;
2848
2849
  /// Helper wrapper around SimplifyDemandedBits
2850
  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2851
                            DAGCombinerInfo &DCI) const;
2852
2853
  /// Look at Vector Op. At this point, we know that only the DemandedElts
2854
  /// elements of the result of Op are ever used downstream.  If we can use
2855
  /// this information to simplify Op, create a new simplified DAG node and
2856
  /// return true, storing the original and new nodes in TLO.
2857
  /// Otherwise, analyze the expression and return a mask of KnownUndef and
2858
  /// KnownZero elements for the expression (used to simplify the caller).
2859
  /// The KnownUndef/Zero elements may only be accurate for those bits
2860
  /// in the DemandedMask.
2861
  /// \p AssumeSingleUse When this parameter is true, this function will
2862
  ///    attempt to simplify \p Op even if there are multiple uses.
2863
  ///    Callers are responsible for correctly updating the DAG based on the
2864
  ///    results of this function, because simply replacing replacing TLO.Old
2865
  ///    with TLO.New will be incorrect when this parameter is true and TLO.Old
2866
  ///    has multiple uses.
2867
  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask,
2868
                                  APInt &KnownUndef, APInt &KnownZero,
2869
                                  TargetLoweringOpt &TLO, unsigned Depth = 0,
2870
                                  bool AssumeSingleUse = false) const;
2871
2872
  /// Helper wrapper around SimplifyDemandedVectorElts
2873
  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
2874
                                  APInt &KnownUndef, APInt &KnownZero,
2875
                                  DAGCombinerInfo &DCI) const;
2876
2877
  /// Determine which of the bits specified in Mask are known to be either zero
2878
  /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
2879
  /// argument allows us to only collect the known bits that are shared by the
2880
  /// requested vector elements.
2881
  virtual void computeKnownBitsForTargetNode(const SDValue Op,
2882
                                             KnownBits &Known,
2883
                                             const APInt &DemandedElts,
2884
                                             const SelectionDAG &DAG,
2885
                                             unsigned Depth = 0) const;
2886
2887
  /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
2888
  /// Default implementation computes low bits based on alignment
2889
  /// information. This should preserve known bits passed into it.
2890
  virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
2891
                                             KnownBits &Known,
2892
                                             const APInt &DemandedElts,
2893
                                             const SelectionDAG &DAG,
2894
                                             unsigned Depth = 0) const;
2895
2896
  /// This method can be implemented by targets that want to expose additional
2897
  /// information about sign bits to the DAG Combiner. The DemandedElts
2898
  /// argument allows us to only collect the minimum sign bits that are shared
2899
  /// by the requested vector elements.
2900
  virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2901
                                                   const APInt &DemandedElts,
2902
                                                   const SelectionDAG &DAG,
2903
                                                   unsigned Depth = 0) const;
2904
2905
  /// Attempt to simplify any target nodes based on the demanded vector
2906
  /// elements, returning true on success. Otherwise, analyze the expression and
2907
  /// return a mask of KnownUndef and KnownZero elements for the expression
2908
  /// (used to simplify the caller). The KnownUndef/Zero elements may only be
2909
  /// accurate for those bits in the DemandedMask
2910
  virtual bool SimplifyDemandedVectorEltsForTargetNode(
2911
      SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
2912
      APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2913
2914
  /// If \p SNaN is false, \returns true if \p Op is known to never be any
2915
  /// NaN. If \p sNaN is true, returns if \p Op is known to never be a signaling
2916
  /// NaN.
2917
  virtual bool isKnownNeverNaNForTargetNode(SDValue Op,
2918
                                            const SelectionDAG &DAG,
2919
                                            bool SNaN = false,
2920
                                            unsigned Depth = 0) const;
2921
  struct DAGCombinerInfo {
2922
    void *DC;  // The DAG Combiner object.
2923
    CombineLevel Level;
2924
    bool CalledByLegalizer;
2925
2926
  public:
2927
    SelectionDAG &DAG;
2928
2929
    DAGCombinerInfo(SelectionDAG &dag, CombineLevel level,  bool cl, void *dc)
2930
23.9M
      : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2931
2932
5.49M
    bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2933
6.06M
    bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2934
242k
    bool isAfterLegalizeDAG() const {
2935
242k
      return Level == AfterLegalizeDAG;
2936
242k
    }
2937
173k
    CombineLevel getDAGCombineLevel() { return Level; }
2938
46.8k
    bool isCalledByLegalizer() const { return CalledByLegalizer; }
2939
2940
    void AddToWorklist(SDNode *N);
2941
    SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
2942
    SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2943
    SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2944
2945
    void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2946
  };
2947
2948
  /// Return if the N is a constant or constant vector equal to the true value
2949
  /// from getBooleanContents().
2950
  bool isConstTrueVal(const SDNode *N) const;
2951
2952
  /// Return if the N is a constant or constant vector equal to the false value
2953
  /// from getBooleanContents().
2954
  bool isConstFalseVal(const SDNode *N) const;
2955
2956
  /// Return if \p N is a True value when extended to \p VT.
2957
  bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const;
2958
2959
  /// Try to simplify a setcc built with the specified operands and cc. If it is
2960
  /// unable to simplify it, return a null SDValue.
2961
  SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
2962
                        bool foldBooleans, DAGCombinerInfo &DCI,
2963
                        const SDLoc &dl) const;
2964
2965
  // For targets which wrap address, unwrap for analysis.
2966
51.4M
  virtual SDValue unwrapAddress(SDValue N) const { return N; }
2967
2968
  /// Returns true (and the GlobalValue and the offset) if the node is a
2969
  /// GlobalAddress + offset.
2970
  virtual bool
2971
  isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2972
2973
  /// This method will be invoked for all target nodes and for any
2974
  /// target-independent nodes that the target has registered with invoke it
2975
  /// for.
2976
  ///
2977
  /// The semantics are as follows:
2978
  /// Return Value:
2979
  ///   SDValue.Val == 0   - No change was made
2980
  ///   SDValue.Val == N   - N was replaced, is dead, and is already handled.
2981
  ///   otherwise          - N should be replaced by the returned Operand.
2982
  ///
2983
  /// In addition, methods provided by DAGCombinerInfo may be used to perform
2984
  /// more complex transformations.
2985
  ///
2986
  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2987
2988
  /// Return true if it is profitable to move this shift by a constant amount
2989
  /// though its operand, adjusting any immediate operands as necessary to
2990
  /// preserve semantics. This transformation may not be desirable if it
2991
  /// disrupts a particularly auspicious target-specific tree (e.g. bitfield
2992
  /// extraction in AArch64). By default, it returns true.
2993
  ///
2994
  /// @param N the shift node
2995
  /// @param Level the current DAGCombine legalization level.
2996
  virtual bool isDesirableToCommuteWithShift(const SDNode *N,
2997
2.11k
                                             CombineLevel Level) const {
2998
2.11k
    return true;
2999
2.11k
  }
3000
3001
  // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
3002
  // to a shuffle and a truncate.
3003
  // Example of such a combine:
3004
  // v4i32 build_vector((extract_elt V, 1),
3005
  //                    (extract_elt V, 3),
3006
  //                    (extract_elt V, 5),
3007
  //                    (extract_elt V, 7))
3008
  //  -->
3009
  // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
3010
  virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(
3011
0
      ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
3012
0
    return false;
3013
0
  }
3014
3015
  /// Return true if the target has native support for the specified value type
3016
  /// and it is 'desirable' to use the type for the given node type. e.g. On x86
3017
  /// i16 is legal, but undesirable since i16 instruction encodings are longer
3018
  /// and some i16 instructions are slow.
3019
3.51M
  virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
3020
3.51M
    // By default, assume all legal types are desirable.
3021
3.51M
    return isTypeLegal(VT);
3022
3.51M
  }
3023
3024
  /// Return true if it is profitable for dag combiner to transform a floating
3025
  /// point op of specified opcode to a equivalent op of an integer
3026
  /// type. e.g. f32 load -> i32 load can be profitable on ARM.
3027
  virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
3028
388
                                                 EVT /*VT*/) const {
3029
388
    return false;
3030
388
  }
3031
3032
  /// This method query the target whether it is beneficial for dag combiner to
3033
  /// promote the specified node. If true, it should return the desired
3034
  /// promotion type by reference.
3035
3.89k
  virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
3036
3.89k
    return false;
3037
3.89k
  }
3038
3039
  /// Return true if the target supports swifterror attribute. It optimizes
3040
  /// loads and stores to reading and writing a specific register.
3041
408k
  virtual bool supportSwiftError() const {
3042
408k
    return false;
3043
408k
  }
3044
3045
  /// Return true if the target supports that a subset of CSRs for the given
3046
  /// machine function is handled explicitly via copies.
3047
27.3k
  virtual bool supportSplitCSR(MachineFunction *MF) const {
3048
27.3k
    return false;
3049
27.3k
  }
3050
3051
  /// Perform necessary initialization to handle a subset of CSRs explicitly
3052
  /// via copies. This function is called at the beginning of instruction
3053
  /// selection.
3054
0
  virtual void initializeSplitCSR(MachineBasicBlock *Entry) const {
3055
0
    llvm_unreachable("Not Implemented");
3056
0
  }
3057
3058
  /// Insert explicit copies in entry and exit blocks. We copy a subset of
3059
  /// CSRs to virtual registers in the entry block, and copy them back to
3060
  /// physical registers in the exit blocks. This function is called at the end
3061
  /// of instruction selection.
3062
  virtual void insertCopiesSplitCSR(
3063
      MachineBasicBlock *Entry,
3064
0
      const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
3065
0
    llvm_unreachable("Not Implemented");
3066
0
  }
3067
3068
  //===--------------------------------------------------------------------===//
3069
  // Lowering methods - These methods must be implemented by targets so that
3070
  // the SelectionDAGBuilder code knows how to lower these.
3071
  //
3072
3073
  /// This hook must be implemented to lower the incoming (formal) arguments,
3074
  /// described by the Ins array, into the specified DAG. The implementation
3075
  /// should fill in the InVals array with legal-type argument values, and
3076
  /// return the resulting token chain value.
3077
  virtual SDValue LowerFormalArguments(
3078
      SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
3079
      const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
3080
0
      SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
3081
0
    llvm_unreachable("Not Implemented");
3082
0
  }
3083
3084
  /// This structure contains all information that is necessary for lowering
3085
  /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
3086
  /// needs to lower a call, and targets will see this struct in their LowerCall
3087
  /// implementation.
3088
  struct CallLoweringInfo {
3089
    SDValue Chain;
3090
    Type *RetTy = nullptr;
3091
    bool RetSExt           : 1;
3092
    bool RetZExt           : 1;
3093
    bool IsVarArg          : 1;
3094
    bool IsInReg           : 1;
3095
    bool DoesNotReturn     : 1;
3096
    bool IsReturnValueUsed : 1;
3097
    bool IsConvergent      : 1;
3098
    bool IsPatchPoint      : 1;
3099
3100
    // IsTailCall should be modified by implementations of
3101
    // TargetLowering::LowerCall that perform tail call conversions.
3102
    bool IsTailCall = false;
3103
3104
    // Is Call lowering done post SelectionDAG type legalization.
3105
    bool IsPostTypeLegalization = false;
3106
3107
    unsigned NumFixedArgs = -1;
3108
    CallingConv::ID CallConv = CallingConv::C;
3109
    SDValue Callee;
3110
    ArgListTy Args;
3111
    SelectionDAG &DAG;
3112
    SDLoc DL;
3113
    ImmutableCallSite CS;
3114
    SmallVector<ISD::OutputArg, 32> Outs;
3115
    SmallVector<SDValue, 32> OutVals;
3116
    SmallVector<ISD::InputArg, 32> Ins;
3117
    SmallVector<SDValue, 4> InVals;
3118
3119
    CallLoweringInfo(SelectionDAG &DAG)
3120
        : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
3121
          DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
3122
778k
          IsPatchPoint(false), DAG(DAG) {}
3123
3124
778k
    CallLoweringInfo &setDebugLoc(const SDLoc &dl) {
3125
778k
      DL = dl;
3126
778k
      return *this;
3127
778k
    }
3128
3129
803k
    CallLoweringInfo &setChain(SDValue InChain) {
3130
803k
      Chain = InChain;
3131
803k
      return *this;
3132
803k
    }
3133
3134
    // setCallee with target/module-specific attributes
3135
    CallLoweringInfo &setLibCallee(CallingConv::ID CC, Type *ResultType,
3136
20.5k
                                   SDValue Target, ArgListTy &&ArgsList) {
3137
20.5k
      RetTy = ResultType;
3138
20.5k
      Callee = Target;
3139
20.5k
      CallConv = CC;
3140
20.5k
      NumFixedArgs = ArgsList.size();
3141
20.5k
      Args = std::move(ArgsList);
3142
20.5k
3143
20.5k
      DAG.getTargetLoweringInfo().markLibCallAttributes(
3144
20.5k
          &(DAG.getMachineFunction()), CC, Args);
3145
20.5k
      return *this;
3146
20.5k
    }
3147
3148
    CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
3149
598
                                SDValue Target, ArgListTy &&ArgsList) {
3150
598
      RetTy = ResultType;
3151
598
      Callee = Target;
3152
598
      CallConv = CC;
3153
598
      NumFixedArgs = ArgsList.size();
3154
598
      Args = std::move(ArgsList);
3155
598
      return *this;
3156
598
    }
3157
3158
    CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
3159
                                SDValue Target, ArgListTy &&ArgsList,
3160
757k
                                ImmutableCallSite Call) {
3161
757k
      RetTy = ResultType;
3162
757k
3163
757k
      IsInReg = Call.hasRetAttr(Attribute::InReg);
3164
757k
      DoesNotReturn =
3165
757k
          Call.doesNotReturn() ||
3166
757k
          
(729k
!Call.isInvoke()729k
&&
3167
729k
           
isa<UnreachableInst>(Call.getInstruction()->getNextNode())705k
);
3168
757k
      IsVarArg = FTy->isVarArg();
3169
757k
      IsReturnValueUsed = !Call.getInstruction()->use_empty();
3170
757k
      RetSExt = Call.hasRetAttr(Attribute::SExt);
3171
757k
      RetZExt = Call.hasRetAttr(Attribute::ZExt);
3172
757k
3173
757k
      Callee = Target;
3174
757k
3175
757k
      CallConv = Call.getCallingConv();
3176
757k
      NumFixedArgs = FTy->getNumParams();
3177
757k
      Args = std::move(ArgsList);
3178
757k
3179
757k
      CS = Call;
3180
757k
3181
757k
      return *this;
3182
757k
    }
3183
3184
198
    CallLoweringInfo &setInRegister(bool Value = true) {
3185
198
      IsInReg = Value;
3186
198
      return *this;
3187
198
    }
3188
3189
7.02k
    CallLoweringInfo &setNoReturn(bool Value = true) {
3190
7.02k
      DoesNotReturn = Value;
3191
7.02k
      return *this;
3192
7.02k
    }
3193
3194
    CallLoweringInfo &setVarArg(bool Value = true) {
3195
      IsVarArg = Value;
3196
      return *this;
3197
    }
3198
3199
764k
    CallLoweringInfo &setTailCall(bool Value = true) {
3200
764k
      IsTailCall = Value;
3201
764k
      return *this;
3202
764k
    }
3203
3204
15.6k
    CallLoweringInfo &setDiscardResult(bool Value = true) {
3205
15.6k
      IsReturnValueUsed = !Value;
3206
15.6k
      return *this;
3207
15.6k
    }
3208
3209
757k
    CallLoweringInfo &setConvergent(bool Value = true) {
3210
757k
      IsConvergent = Value;
3211
757k
      return *this;
3212
757k
    }
3213
3214
11.8k
    CallLoweringInfo &setSExtResult(bool Value = true) {
3215
11.8k
      RetSExt = Value;
3216
11.8k
      return *this;
3217
11.8k
    }
3218
3219
11.8k
    CallLoweringInfo &setZExtResult(bool Value = true) {
3220
11.8k
      RetZExt = Value;
3221
11.8k
      return *this;
3222
11.8k
    }
3223
3224
216
    CallLoweringInfo &setIsPatchPoint(bool Value = true) {
3225
216
      IsPatchPoint = Value;
3226
216
      return *this;
3227
216
    }
3228
3229
3.94k
    CallLoweringInfo &setIsPostTypeLegalization(bool Value=true) {
3230
3.94k
      IsPostTypeLegalization = Value;
3231
3.94k
      return *this;
3232
3.94k
    }
3233
3234
2.01M
    ArgListTy &getArgs() {
3235
2.01M
      return Args;
3236
2.01M
    }
3237
  };
3238
3239
  /// This function lowers an abstract call to a function into an actual call.
3240
  /// This returns a pair of operands.  The first element is the return value
3241
  /// for the function (if RetTy is not VoidTy).  The second element is the
3242
  /// outgoing token chain. It calls LowerCall to do the actual lowering.
3243
  std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
3244
3245
  /// This hook must be implemented to lower calls into the specified
3246
  /// DAG. The outgoing arguments to the call are described by the Outs array,
3247
  /// and the values to be returned by the call are described by the Ins
3248
  /// array. The implementation should fill in the InVals array with legal-type
3249
  /// return values from the call, and return the resulting token chain value.
3250
  virtual SDValue
3251
    LowerCall(CallLoweringInfo &/*CLI*/,
3252
0
              SmallVectorImpl<SDValue> &/*InVals*/) const {
3253
0
    llvm_unreachable("Not Implemented");
3254
0
  }
3255
3256
  /// Target-specific cleanup for formal ByVal parameters.
3257
1.11k
  virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
3258
3259
  /// This hook should be implemented to check whether the return values
3260
  /// described by the Outs array can fit into the return registers.  If false
3261
  /// is returned, an sret-demotion is performed.
3262
  virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
3263
                              MachineFunction &/*MF*/, bool /*isVarArg*/,
3264
               const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
3265
               LLVMContext &/*Context*/) const
3266
5.58k
  {
3267
5.58k
    // Return true by default to get preexisting behavior.
3268
5.58k
    return true;
3269
5.58k
  }
3270
3271
  /// This hook must be implemented to lower outgoing return values, described
3272
  /// by the Outs array, into the specified DAG. The implementation should
3273
  /// return the resulting token chain value.
3274
  virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
3275
                              bool /*isVarArg*/,
3276
                              const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
3277
                              const SmallVectorImpl<SDValue> & /*OutVals*/,
3278
                              const SDLoc & /*dl*/,
3279
0
                              SelectionDAG & /*DAG*/) const {
3280
0
    llvm_unreachable("Not Implemented");
3281
0
  }
3282
3283
  /// Return true if result of the specified node is used by a return node
3284
  /// only. It also compute and return the input chain for the tail call.
3285
  ///
3286
  /// This is used to determine whether it is possible to codegen a libcall as
3287
  /// tail call at legalization time.
3288
611
  virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
3289
611
    return false;
3290
611
  }
3291
3292
  /// Return true if the target may be able emit the call instruction as a tail
3293
  /// call. This is used by optimization passes to determine if it's profitable
3294
  /// to duplicate return instructions to enable tailcall optimization.
3295
149
  virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
3296
149
    return false;
3297
149
  }
3298
3299
  /// Return the builtin name for the __builtin___clear_cache intrinsic
3300
  /// Default is to invoke the clear cache library call
3301
2
  virtual const char * getClearCacheBuiltinName() const {
3302
2
    return "__clear_cache";
3303
2
  }
3304
3305
  /// Return the register ID of the name passed in. Used by named register
3306
  /// global variables extension. There is no target-independent behaviour
3307
  /// so the default action is to bail.
3308
  virtual unsigned getRegisterByName(const char* RegName, EVT VT,
3309
0
                                     SelectionDAG &DAG) const {
3310
0
    report_fatal_error("Named registers not implemented for this target");
3311
0
  }
3312
3313
  /// Return the type that should be used to zero or sign extend a
3314
  /// zeroext/signext integer return value.  FIXME: Some C calling conventions
3315
  /// require the return type to be promoted, but this is not true all the time,
3316
  /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3317
  /// conventions. The frontend should handle this and include all of the
3318
  /// necessary information.
3319
  virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
3320
3.33k
                                       ISD::NodeType /*ExtendKind*/) const {
3321
3.33k
    EVT MinVT = getRegisterType(Context, MVT::i32);
3322
3.33k
    return VT.bitsLT(MinVT) ? 
MinVT2.48k
:
VT852
;
3323
3.33k
  }
3324
3325
  /// For some targets, an LLVM struct type must be broken down into multiple
3326
  /// simple types, but the calling convention specifies that the entire struct
3327
  /// must be passed in a block of consecutive registers.
3328
  virtual bool
3329
  functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
3330
704k
                                            bool isVarArg) const {
3331
704k
    return false;
3332
704k
  }
3333
3334
  /// Returns a 0 terminated array of registers that can be safely used as
3335
  /// scratch registers.
3336
0
  virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
3337
0
    return nullptr;
3338
0
  }
3339
3340
  /// This callback is used to prepare for a volatile or atomic load.
3341
  /// It takes a chain node as input and returns the chain for the load itself.
3342
  ///
3343
  /// Having a callback like this is necessary for targets like SystemZ,
3344
  /// which allows a CPU to reuse the result of a previous load indefinitely,
3345
  /// even if a cache-coherent store is performed by another CPU.  The default
3346
  /// implementation does nothing.
3347
  virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL,
3348
17.9k
                                              SelectionDAG &DAG) const {
3349
17.9k
    return Chain;
3350
17.9k
  }
3351
3352
  /// This callback is used to inspect load/store instructions and add
3353
  /// target-specific MachineMemOperand flags to them.  The default
3354
  /// implementation does nothing.
3355
496k
  virtual MachineMemOperand::Flags getMMOFlags(const Instruction &I) const {
3356
496k
    return MachineMemOperand::MONone;
3357
496k
  }
3358
3359
  /// This callback is invoked by the type legalizer to legalize nodes with an
3360
  /// illegal operand type but legal result types.  It replaces the
3361
  /// LowerOperation callback in the type Legalizer.  The reason we can not do
3362
  /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3363
  /// use this callback.
3364
  ///
3365
  /// TODO: Consider merging with ReplaceNodeResults.
3366
  ///
3367
  /// The target places new result values for the node in Results (their number
3368
  /// and types must exactly match those of the original return values of
3369
  /// the node), or leaves Results empty, which indicates that the node is not
3370
  /// to be custom lowered after all.
3371
  /// The default implementation calls LowerOperation.
3372
  virtual void LowerOperationWrapper(SDNode *N,
3373
                                     SmallVectorImpl<SDValue> &Results,
3374
                                     SelectionDAG &DAG) const;
3375
3376
  /// This callback is invoked for operations that are unsupported by the
3377
  /// target, which are registered to use 'custom' lowering, and whose defined
3378
  /// values are all legal.  If the target has no operations that require custom
3379
  /// lowering, it need not implement this.  The default implementation of this
3380
  /// aborts.
3381
  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
3382
3383
  /// This callback is invoked when a node result type is illegal for the
3384
  /// target, and the operation was registered to use 'custom' lowering for that
3385
  /// result type.  The target places new result values for the node in Results
3386
  /// (their number and types must exactly match those of the original return
3387
  /// values of the node), or leaves Results empty, which indicates that the
3388
  /// node is not to be custom lowered after all.
3389
  ///
3390
  /// If the target has no operations that require custom lowering, it need not
3391
  /// implement this.  The default implementation aborts.
3392
  virtual void ReplaceNodeResults(SDNode * /*N*/,
3393
                                  SmallVectorImpl<SDValue> &/*Results*/,
3394
0
                                  SelectionDAG &/*DAG*/) const {
3395
0
    llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3396
0
  }
3397
3398
  /// This method returns the name of a target specific DAG node.
3399
  virtual const char *getTargetNodeName(unsigned Opcode) const;
3400
3401
  /// This method returns a target specific FastISel object, or null if the
3402
  /// target does not support "fast" ISel.
3403
  virtual FastISel *createFastISel(FunctionLoweringInfo &,
3404
2.63k
                                   const TargetLibraryInfo *) const {
3405
2.63k
    return nullptr;
3406
2.63k
  }
3407
3408
  bool verifyReturnAddressArgumentIsConstant(SDValue Op,
3409
                                             SelectionDAG &DAG) const;
3410
3411
  //===--------------------------------------------------------------------===//
3412
  // Inline Asm Support hooks
3413
  //
3414
3415
  /// This hook allows the target to expand an inline asm call to be explicit
3416
  /// llvm code if it wants to.  This is useful for turning simple inline asms
3417
  /// into LLVM intrinsics, which gives the compiler more information about the
3418
  /// behavior of the code.
3419
4.99k
  virtual bool ExpandInlineAsm(CallInst *) const {
3420
4.99k
    return false;
3421
4.99k
  }
3422
3423
  enum ConstraintType {
3424
    C_Register,            // Constraint represents specific register(s).
3425
    C_RegisterClass,       // Constraint represents any of register(s) in class.
3426
    C_Memory,              // Memory constraint.
3427
    C_Other,               // Something else.
3428
    C_Unknown              // Unsupported constraint.
3429
  };
3430
3431
  enum ConstraintWeight {
3432
    // Generic weights.
3433
    CW_Invalid  = -1,     // No match.
3434
    CW_Okay     = 0,      // Acceptable.
3435
    CW_Good     = 1,      // Good weight.
3436
    CW_Better   = 2,      // Better weight.
3437
    CW_Best     = 3,      // Best weight.
3438
3439
    // Well-known weights.
3440
    CW_SpecificReg  = CW_Okay,    // Specific register operands.
3441
    CW_Register     = CW_Good,    // Register operands.
3442
    CW_Memory       = CW_Better,  // Memory operands.
3443
    CW_Constant     = CW_Best,    // Constant operand.
3444
    CW_Default      = CW_Okay     // Default or don't know type.
3445
  };
3446
3447
  /// This contains information for each constraint that we are lowering.
3448
  struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3449
    /// This contains the actual string for the code, like "m".  TargetLowering
3450
    /// picks the 'best' code from ConstraintInfo::Codes that most closely
3451
    /// matches the operand.
3452
    std::string ConstraintCode;
3453
3454
    /// Information about the constraint code, e.g. Register, RegisterClass,
3455
    /// Memory, Other, Unknown.
3456
    TargetLowering::ConstraintType ConstraintType = TargetLowering::C_Unknown;
3457
3458
    /// If this is the result output operand or a clobber, this is null,
3459
    /// otherwise it is the incoming operand to the CallInst.  This gets
3460
    /// modified as the asm is processed.
3461
    Value *CallOperandVal = nullptr;
3462
3463
    /// The ValueType for the operand value.
3464
    MVT ConstraintVT = MVT::Other;
3465
3466
    /// Copy constructor for copying from a ConstraintInfo.
3467
    AsmOperandInfo(InlineAsm::ConstraintInfo Info)
3468
340k
        : InlineAsm::ConstraintInfo(std::move(Info)) {}
3469
3470
    /// Return true of this is an input operand that is a matching constraint
3471
    /// like "4".
3472
    bool isMatchingInputConstraint() const;
3473
3474
    /// If this is an input matching constraint, this method returns the output
3475
    /// operand it matches.
3476
    unsigned getMatchedOperand() const;
3477
  };
3478
3479
  using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
3480
3481
  /// Split up the constraint string from the inline assembly value into the
3482
  /// specific constraints and their prefixes, and also tie in the associated
3483
  /// operand values.  If this returns an empty vector, and if the constraint
3484
  /// string itself isn't empty, there was an error parsing.
3485
  virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
3486
                                                const TargetRegisterInfo *TRI,
3487
                                                ImmutableCallSite CS) const;
3488
3489
  /// Examine constraint type and operand type and determine a weight value.
3490
  /// The operand object must already have been set up with the operand type.
3491
  virtual ConstraintWeight getMultipleConstraintMatchWeight(
3492
      AsmOperandInfo &info, int maIndex) const;
3493
3494
  /// Examine constraint string and operand type and determine a weight value.
3495
  /// The operand object must already have been set up with the operand type.
3496
  virtual ConstraintWeight getSingleConstraintMatchWeight(
3497
      AsmOperandInfo &info, const char *constraint) const;
3498
3499
  /// Determines the constraint code and constraint type to use for the specific
3500
  /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3501
  /// If the actual operand being passed in is available, it can be passed in as
3502
  /// Op, otherwise an empty SDValue can be passed.
3503
  virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3504
                                      SDValue Op,
3505
                                      SelectionDAG *DAG = nullptr) const;
3506
3507
  /// Given a constraint, return the type of constraint it is for this target.
3508
  virtual ConstraintType getConstraintType(StringRef Constraint) const;
3509
3510
  /// Given a physical register constraint (e.g.  {edx}), return the register
3511
  /// number and the register class for the register.
3512
  ///
3513
  /// Given a register class constraint, like 'r', if this corresponds directly
3514
  /// to an LLVM register class, return a register of 0 and the register class
3515
  /// pointer.
3516
  ///
3517
  /// This should only be used for C_Register constraints.  On error, this
3518
  /// returns a register number of 0 and a null register class pointer.
3519
  virtual std::pair<unsigned, const TargetRegisterClass *>
3520
  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3521
                               StringRef Constraint, MVT VT) const;
3522
3523
3.00k
  virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
3524
3.00k
    if (ConstraintCode == "i")
3525
0
      return InlineAsm::Constraint_i;
3526
3.00k
    else if (ConstraintCode == "m")
3527
3.00k
      return InlineAsm::Constraint_m;
3528
0
    return InlineAsm::Constraint_Unknown;
3529
0
  }
3530
3531
  /// Try to replace an X constraint, which matches anything, with another that
3532
  /// has more specific requirements based on the type of the corresponding
3533
  /// operand.  This returns null if there is no replacement to make.
3534
  virtual const char *LowerXConstraint(EVT ConstraintVT) const;
3535
3536
  /// Lower the specified operand into the Ops vector.  If it is invalid, don't
3537
  /// add anything to Ops.
3538
  virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
3539
                                            std::vector<SDValue> &Ops,
3540
                                            SelectionDAG &DAG) const;
3541
3542
  //===--------------------------------------------------------------------===//
3543
  // Div utility functions
3544
  //
3545
  SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3546
                    SmallVectorImpl<SDNode *> &Created) const;
3547
  SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3548
                    SmallVectorImpl<SDNode *> &Created) const;
3549
3550
  /// Targets may override this function to provide custom SDIV lowering for
3551
  /// power-of-2 denominators.  If the target returns an empty SDValue, LLVM
3552
  /// assumes SDIV is expensive and replaces it with a series of other integer
3553
  /// operations.
3554
  virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
3555
                                SelectionDAG &DAG,
3556
                                SmallVectorImpl<SDNode *> &Created) const;
3557
3558
  /// Indicate whether this target prefers to combine FDIVs with the same
3559
  /// divisor. If the transform should never be done, return zero. If the
3560
  /// transform should be done, return the minimum number of divisor uses
3561
  /// that must exist.
3562
52
  virtual unsigned combineRepeatedFPDivisors() const {
3563
52
    return 0;
3564
52
  }
3565
3566
  /// Hooks for building estimates in place of slower divisions and square
3567
  /// roots.
3568
3569
  /// Return either a square root or its reciprocal estimate value for the input
3570
  /// operand.
3571
  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3572
  /// 'Enabled' as set by a potential default override attribute.
3573
  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3574
  /// refinement iterations required to generate a sufficient (though not
3575
  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3576
  /// The boolean UseOneConstNR output is used to select a Newton-Raphson
3577
  /// algorithm implementation that uses either one or two constants.
3578
  /// The boolean Reciprocal is used to select whether the estimate is for the
3579
  /// square root of the input operand or the reciprocal of its square root.
3580
  /// A target may choose to implement its own refinement within this function.
3581
  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3582
  /// any further refinement of the estimate.
3583
  /// An empty SDValue return means no estimate sequence can be created.
3584
  virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
3585
                                  int Enabled, int &RefinementSteps,
3586
16
                                  bool &UseOneConstNR, bool Reciprocal) const {
3587
16
    return SDValue();
3588
16
  }
3589
3590
  /// Return a reciprocal estimate value for the input operand.
3591
  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3592
  /// 'Enabled' as set by a potential default override attribute.
3593
  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3594
  /// refinement iterations required to generate a sufficient (though not
3595
  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3596
  /// A target may choose to implement its own refinement within this function.
3597
  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3598
  /// any further refinement of the estimate.
3599
  /// An empty SDValue return means no estimate sequence can be created.
3600
  virtual SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG,
3601
42
                                   int Enabled, int &RefinementSteps) const {
3602
42
    return SDValue();
3603
42
  }
3604
3605
  //===--------------------------------------------------------------------===//
3606
  // Legalization utility functions
3607
  //
3608
3609
  /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
3610
  /// respectively, each computing an n/2-bit part of the result.
3611
  /// \param Result A vector that will be filled with the parts of the result
3612
  ///        in little-endian order.
3613
  /// \param LL Low bits of the LHS of the MUL.  You can use this parameter
3614
  ///        if you want to control how low bits are extracted from the LHS.
3615
  /// \param LH High bits of the LHS of the MUL.  See LL for meaning.
3616
  /// \param RL Low bits of the RHS of the MUL.  See LL for meaning
3617
  /// \param RH High bits of the RHS of the MUL.  See LL for meaning.
3618
  /// \returns true if the node has been expanded, false if it has not
3619
  bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
3620
                      SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
3621
                      SelectionDAG &DAG, MulExpansionKind Kind,
3622
                      SDValue LL = SDValue(), SDValue LH = SDValue(),
3623
                      SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3624
3625
  /// Expand a MUL into two nodes.  One that computes the high bits of
3626
  /// the result and one that computes the low bits.
3627
  /// \param HiLoVT The value type to use for the Lo and Hi nodes.
3628
  /// \param LL Low bits of the LHS of the MUL.  You can use this parameter
3629
  ///        if you want to control how low bits are extracted from the LHS.
3630
  /// \param LH High bits of the LHS of the MUL.  See LL for meaning.
3631
  /// \param RL Low bits of the RHS of the MUL.  See LL for meaning
3632
  /// \param RH High bits of the RHS of the MUL.  See LL for meaning.
3633
  /// \returns true if the node has been expanded. false if it has not
3634
  bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
3635
                 SelectionDAG &DAG, MulExpansionKind Kind,
3636
                 SDValue LL = SDValue(), SDValue LH = SDValue(),
3637
                 SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3638
3639
  /// Expand float(f32) to SINT(i64) conversion
3640
  /// \param N Node to expand
3641
  /// \param Result output after conversion
3642
  /// \returns True, if the expansion was successful, false otherwise
3643
  bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3644
3645
  /// Turn load of vector type into a load of the individual elements.
3646
  /// \param LD load to expand
3647
  /// \returns MERGE_VALUEs of the scalar loads with their chains.
3648
  SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
3649
3650
  // Turn a store of a vector type into stores of the individual elements.
3651
  /// \param ST Store with a vector value type
3652
  /// \returns MERGE_VALUs of the individual store chains.
3653
  SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3654
3655
  /// Expands an unaligned load to 2 half-size loads for an integer, and
3656
  /// possibly more for vectors.
3657
  std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
3658
                                                  SelectionDAG &DAG) const;
3659
3660
  /// Expands an unaligned store to 2 half-size stores for integer values, and
3661
  /// possibly more for vectors.
3662
  SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3663
3664
  /// Increments memory address \p Addr according to the type of the value
3665
  /// \p DataVT that should be stored. If the data is stored in compressed
3666
  /// form, the memory address should be incremented according to the number of
3667
  /// the stored elements. This number is equal to the number of '1's bits
3668
  /// in the \p Mask.
3669
  /// \p DataVT is a vector type. \p Mask is a vector value.
3670
  /// \p DataVT and \p Mask have the same number of vector elements.
3671
  SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
3672
                                 EVT DataVT, SelectionDAG &DAG,
3673
                                 bool IsCompressedMemory) const;
3674
3675
  /// Get a pointer to vector element \p Idx located in memory for a vector of
3676
  /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
3677
  /// bounds the returned pointer is unspecified, but will be within the vector
3678
  /// bounds.
3679
  SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
3680
                                  SDValue Index) const;
3681
3682
  //===--------------------------------------------------------------------===//
3683
  // Instruction Emitting Hooks
3684
  //
3685
3686
  /// This method should be implemented by targets that mark instructions with
3687
  /// the 'usesCustomInserter' flag.  These instructions are special in various
3688
  /// ways, which require special support to insert.  The specified MachineInstr
3689
  /// is created but not inserted into any basic blocks, and this method is
3690
  /// called to expand it into a sequence of instructions, potentially also
3691
  /// creating new basic blocks and control flow.
3692
  /// As long as the returned basic block is different (i.e., we created a new
3693
  /// one), the custom inserter is free to modify the rest of \p MBB.
3694
  virtual MachineBasicBlock *
3695
  EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
3696
3697
  /// This method should be implemented by targets that mark instructions with
3698
  /// the 'hasPostISelHook' flag. These instructions must be adjusted after
3699
  /// instruction selection by target hooks.  e.g. To fill in optional defs for
3700
  /// ARM 's' setting instructions.
3701
  virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
3702
                                             SDNode *Node) const;
3703
3704
  /// If this function returns true, SelectionDAGBuilder emits a
3705
  /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
3706
21
  virtual bool useLoadStackGuardNode() const {
3707
21
    return false;
3708
21
  }
3709
3710
  virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
3711
0
                                      const SDLoc &DL) const {
3712
0
    llvm_unreachable("not implemented for this target");
3713
0
  }
3714
3715
  /// Lower TLS global address SDNode for target independent emulated TLS model.
3716
  virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
3717
                                          SelectionDAG &DAG) const;
3718
3719
  /// Expands target specific indirect branch for the case of JumpTable
3720
  /// expanasion.
3721
  virtual SDValue expandIndirectJTBranch(const SDLoc& dl, SDValue Value, SDValue Addr,
3722
2.34k
                                         SelectionDAG &DAG) const {
3723
2.34k
    return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
3724
2.34k
  }
3725
3726
  // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
3727
  // If we're comparing for equality to zero and isCtlzFast is true, expose the
3728
  // fact that this can be implemented as a ctlz/srl pair, so that the dag
3729
  // combiner can fold the new nodes.
3730
  SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
3731
3732
private:
3733
  SDValue simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
3734
                               ISD::CondCode Cond, DAGCombinerInfo &DCI,
3735
                               const SDLoc &DL) const;
3736
3737
  SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0,
3738
                                               SDValue N1, ISD::CondCode Cond,
3739
                                               DAGCombinerInfo &DCI,
3740
                                               const SDLoc &DL) const;
3741
};
3742
3743
/// Given an LLVM IR type and return type attributes, compute the return value
3744
/// EVTs and flags, and optionally also the offsets, if the return value is
3745
/// being lowered to memory.
3746
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr,
3747
                   SmallVectorImpl<ISD::OutputArg> &Outs,
3748
                   const TargetLowering &TLI, const DataLayout &DL);
3749
3750
} // end namespace llvm
3751
3752
#endif // LLVM_CODEGEN_TARGETLOWERING_H