Coverage Report

Created: 2019-03-22 08:08

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/TargetLowering.h
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//===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
8
///
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/// \file
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/// This file describes how to lower LLVM code to machine code.  This has two
11
/// main components:
12
///
13
///  1. Which ValueTypes are natively supported by the target.
14
///  2. Which operations are supported for supported ValueTypes.
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///  3. Cost thresholds for alternative implementations of certain operations.
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///
17
/// In addition it has a few other components, like information about FP
18
/// immediates.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_TARGETLOWERING_H
23
#define LLVM_CODEGEN_TARGETLOWERING_H
24
25
#include "llvm/ADT/APInt.h"
26
#include "llvm/ADT/ArrayRef.h"
27
#include "llvm/ADT/DenseMap.h"
28
#include "llvm/ADT/STLExtras.h"
29
#include "llvm/ADT/SmallVector.h"
30
#include "llvm/ADT/StringRef.h"
31
#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
32
#include "llvm/CodeGen/DAGCombine.h"
33
#include "llvm/CodeGen/ISDOpcodes.h"
34
#include "llvm/CodeGen/RuntimeLibcalls.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/CodeGen/TargetCallingConv.h"
38
#include "llvm/CodeGen/ValueTypes.h"
39
#include "llvm/IR/Attributes.h"
40
#include "llvm/IR/CallSite.h"
41
#include "llvm/IR/CallingConv.h"
42
#include "llvm/IR/DataLayout.h"
43
#include "llvm/IR/DerivedTypes.h"
44
#include "llvm/IR/Function.h"
45
#include "llvm/IR/IRBuilder.h"
46
#include "llvm/IR/InlineAsm.h"
47
#include "llvm/IR/Instruction.h"
48
#include "llvm/IR/Instructions.h"
49
#include "llvm/IR/Type.h"
50
#include "llvm/MC/MCRegisterInfo.h"
51
#include "llvm/Support/AtomicOrdering.h"
52
#include "llvm/Support/Casting.h"
53
#include "llvm/Support/ErrorHandling.h"
54
#include "llvm/Support/MachineValueType.h"
55
#include "llvm/Target/TargetMachine.h"
56
#include <algorithm>
57
#include <cassert>
58
#include <climits>
59
#include <cstdint>
60
#include <iterator>
61
#include <map>
62
#include <string>
63
#include <utility>
64
#include <vector>
65
66
namespace llvm {
67
68
class BranchProbability;
69
class CCState;
70
class CCValAssign;
71
class Constant;
72
class FastISel;
73
class FunctionLoweringInfo;
74
class GlobalValue;
75
class IntrinsicInst;
76
struct KnownBits;
77
class LLVMContext;
78
class MachineBasicBlock;
79
class MachineFunction;
80
class MachineInstr;
81
class MachineJumpTableInfo;
82
class MachineLoop;
83
class MachineRegisterInfo;
84
class MCContext;
85
class MCExpr;
86
class Module;
87
class TargetRegisterClass;
88
class TargetLibraryInfo;
89
class TargetRegisterInfo;
90
class Value;
91
92
namespace Sched {
93
94
  enum Preference {
95
    None,             // No preference
96
    Source,           // Follow source order.
97
    RegPressure,      // Scheduling for lowest register pressure.
98
    Hybrid,           // Scheduling for both latency and register pressure.
99
    ILP,              // Scheduling for ILP in low register pressure mode.
100
    VLIW              // Scheduling for VLIW targets.
101
  };
102
103
} // end namespace Sched
104
105
/// This base class for TargetLowering contains the SelectionDAG-independent
106
/// parts that can be used from the rest of CodeGen.
107
class TargetLoweringBase {
108
public:
109
  /// This enum indicates whether operations are valid for a target, and if not,
110
  /// what action should be used to make them valid.
111
  enum LegalizeAction : uint8_t {
112
    Legal,      // The target natively supports this operation.
113
    Promote,    // This operation should be executed in a larger type.
114
    Expand,     // Try to expand this to other ops, otherwise use a libcall.
115
    LibCall,    // Don't try to expand this to other ops, always use a libcall.
116
    Custom      // Use the LowerOperation hook to implement custom lowering.
117
  };
118
119
  /// This enum indicates whether a types are legal for a target, and if not,
120
  /// what action should be used to make them valid.
121
  enum LegalizeTypeAction : uint8_t {
122
    TypeLegal,           // The target natively supports this type.
123
    TypePromoteInteger,  // Replace this integer with a larger one.
124
    TypeExpandInteger,   // Split this integer into two of half the size.
125
    TypeSoftenFloat,     // Convert this float to a same size integer type,
126
                         // if an operation is not supported in target HW.
127
    TypeExpandFloat,     // Split this float into two of half the size.
128
    TypeScalarizeVector, // Replace this one-element vector with its element.
129
    TypeSplitVector,     // Split this vector into two of half the size.
130
    TypeWidenVector,     // This vector should be widened into a larger vector.
131
    TypePromoteFloat     // Replace this float with a larger one.
132
  };
133
134
  /// LegalizeKind holds the legalization kind that needs to happen to EVT
135
  /// in order to type-legalize it.
136
  using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
137
138
  /// Enum that describes how the target represents true/false values.
139
  enum BooleanContent {
140
    UndefinedBooleanContent,    // Only bit 0 counts, the rest can hold garbage.
141
    ZeroOrOneBooleanContent,        // All bits zero except for bit 0.
142
    ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
143
  };
144
145
  /// Enum that describes what type of support for selects the target has.
146
  enum SelectSupportKind {
147
    ScalarValSelect,      // The target supports scalar selects (ex: cmov).
148
    ScalarCondVectorVal,  // The target supports selects with a scalar condition
149
                          // and vector values (ex: cmov).
150
    VectorMaskSelect      // The target supports vector selects with a vector
151
                          // mask (ex: x86 blends).
152
  };
153
154
  /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
155
  /// to, if at all. Exists because different targets have different levels of
156
  /// support for these atomic instructions, and also have different options
157
  /// w.r.t. what they should expand to.
158
  enum class AtomicExpansionKind {
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    None,    // Don't expand the instruction.
160
    LLSC,    // Expand the instruction into loadlinked/storeconditional; used
161
             // by ARM/AArch64.
162
    LLOnly,  // Expand the (load) instruction into just a load-linked, which has
163
             // greater atomic guarantees than a normal load.
164
    CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
165
    MaskedIntrinsic, // Use a target-specific intrinsic for the LL/SC loop.
166
  };
167
168
  /// Enum that specifies when a multiplication should be expanded.
169
  enum class MulExpansionKind {
170
    Always,            // Always expand the instruction.
171
    OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
172
                       // or custom.
173
  };
174
175
  class ArgListEntry {
176
  public:
177
    Value *Val = nullptr;
178
    SDValue Node = SDValue();
179
    Type *Ty = nullptr;
180
    bool IsSExt : 1;
181
    bool IsZExt : 1;
182
    bool IsInReg : 1;
183
    bool IsSRet : 1;
184
    bool IsNest : 1;
185
    bool IsByVal : 1;
186
    bool IsInAlloca : 1;
187
    bool IsReturned : 1;
188
    bool IsSwiftSelf : 1;
189
    bool IsSwiftError : 1;
190
    uint16_t Alignment = 0;
191
192
    ArgListEntry()
193
        : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
194
          IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
195
1.03M
          IsSwiftSelf(false), IsSwiftError(false) {}
196
197
    void setAttributes(const CallBase *Call, unsigned ArgIdx);
198
199
1.01M
    void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx) {
200
1.01M
      return setAttributes(cast<CallBase>(CS->getInstruction()), ArgIdx);
201
1.01M
    }
202
  };
203
  using ArgListTy = std::vector<ArgListEntry>;
204
205
  virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
206
14.4k
                                     ArgListTy &Args) const {};
207
208
248k
  static ISD::NodeType getExtendForContent(BooleanContent Content) {
209
248k
    switch (Content) {
210
248k
    case UndefinedBooleanContent:
211
103
      // Extend by adding rubbish bits.
212
103
      return ISD::ANY_EXTEND;
213
248k
    case ZeroOrOneBooleanContent:
214
246k
      // Extend by adding zero bits.
215
246k
      return ISD::ZERO_EXTEND;
216
248k
    case ZeroOrNegativeOneBooleanContent:
217
2.23k
      // Extend by copying the sign bit.
218
2.23k
      return ISD::SIGN_EXTEND;
219
0
    }
220
0
    llvm_unreachable("Invalid content kind");
221
0
  }
222
223
  /// NOTE: The TargetMachine owns TLOF.
224
  explicit TargetLoweringBase(const TargetMachine &TM);
225
  TargetLoweringBase(const TargetLoweringBase &) = delete;
226
  TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
227
37.5k
  virtual ~TargetLoweringBase() = default;
228
229
protected:
230
  /// Initialize all of the actions to default values.
231
  void initActions();
232
233
public:
234
12.1M
  const TargetMachine &getTargetMachine() const { return TM; }
235
236
3.22M
  virtual bool useSoftFloat() const { return false; }
237
238
  /// Return the pointer type for the given address space, defaults to
239
  /// the pointer type from the data layout.
240
  /// FIXME: The default needs to be removed once all the code is updated.
241
25.3M
  MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
242
25.3M
    return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
243
25.3M
  }
244
245
  /// Return the type for frame index, which is determined by
246
  /// the alloca address space specified through the data layout.
247
257k
  MVT getFrameIndexTy(const DataLayout &DL) const {
248
257k
    return getPointerTy(DL, DL.getAllocaAddrSpace());
249
257k
  }
250
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  /// Return the type for operands of fence.
252
  /// TODO: Let fence operands be of i32 type and remove this.
253
7.91k
  virtual MVT getFenceOperandTy(const DataLayout &DL) const {
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7.91k
    return getPointerTy(DL);
255
7.91k
  }
256
257
  /// EVT is not used in-tree, but is used by out-of-tree target.
258
  /// A documentation for this function would be nice...
259
  virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
260
261
  EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
262
                       bool LegalTypes = true) const;
263
264
  /// Returns the type to be used for the index operand of:
265
  /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
266
  /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
267
275k
  virtual MVT getVectorIdxTy(const DataLayout &DL) const {
268
275k
    return getPointerTy(DL);
269
275k
  }
270
271
254k
  virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
272
254k
    return true;
273
254k
  }
274
275
  /// Return true if it is profitable to convert a select of FP constants into
276
  /// a constant pool load whose address depends on the select condition. The
277
  /// parameter may be used to differentiate a select with FP compare from
278
  /// integer compare.
279
91.8k
  virtual bool reduceSelectOfFPConstantLoads(bool IsFPSetCC) const {
280
91.8k
    return true;
281
91.8k
  }
282
283
  /// Return true if multiple condition registers are available.
284
3.69M
  bool hasMultipleConditionRegisters() const {
285
3.69M
    return HasMultipleConditionRegisters;
286
3.69M
  }
287
288
  /// Return true if the target has BitExtract instructions.
289
189k
  bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
290
291
  /// Return the preferred vector type legalization action.
292
  virtual TargetLoweringBase::LegalizeTypeAction
293
4.12M
  getPreferredVectorAction(MVT VT) const {
294
4.12M
    // The default action for one element vectors is to scalarize
295
4.12M
    if (VT.getVectorNumElements() == 1)
296
644k
      return TypeScalarizeVector;
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3.47M
    // The default action for an odd-width vector is to widen.
298
3.47M
    if (!VT.isPow2VectorType())
299
178k
      return TypeWidenVector;
300
3.29M
    // The default action for other vectors is to promote
301
3.29M
    return TypePromoteInteger;
302
3.29M
  }
303
304
  // There are two general methods for expanding a BUILD_VECTOR node:
305
  //  1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
306
  //     them together.
307
  //  2. Build the vector on the stack and then load it.
308
  // If this function returns true, then method (1) will be used, subject to
309
  // the constraint that all of the necessary shuffles are legal (as determined
310
  // by isShuffleMaskLegal). If this function returns false, then method (2) is
311
  // always used. The vector type, and the number of defined values, are
312
  // provided.
313
  virtual bool
314
  shouldExpandBuildVectorWithShuffles(EVT /* VT */,
315
2.33k
                                      unsigned DefinedValues) const {
316
2.33k
    return DefinedValues < 3;
317
2.33k
  }
318
319
  /// Return true if integer divide is usually cheaper than a sequence of
320
  /// several shifts, adds, and multiplies for this target.
321
  /// The definition of "cheaper" may depend on whether we're optimizing
322
  /// for speed or for size.
323
1.22k
  virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
324
325
  /// Return true if the target can handle a standalone remainder operation.
326
0
  virtual bool hasStandaloneRem(EVT VT) const {
327
0
    return true;
328
0
  }
329
330
  /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
331
124
  virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
332
124
    // Default behavior is to replace SQRT(X) with X*RSQRT(X).
333
124
    return false;
334
124
  }
335
336
  /// Reciprocal estimate status values used by the functions below.
337
  enum ReciprocalEstimate : int {
338
    Unspecified = -1,
339
    Disabled = 0,
340
    Enabled = 1
341
  };
342
343
  /// Return a ReciprocalEstimate enum value for a square root of the given type
344
  /// based on the function's attributes. If the operation is not overridden by
345
  /// the function's attributes, "Unspecified" is returned and target defaults
346
  /// are expected to be used for instruction selection.
347
  int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
348
349
  /// Return a ReciprocalEstimate enum value for a division of the given type
350
  /// based on the function's attributes. If the operation is not overridden by
351
  /// the function's attributes, "Unspecified" is returned and target defaults
352
  /// are expected to be used for instruction selection.
353
  int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
354
355
  /// Return the refinement step count for a square root of the given type based
356
  /// on the function's attributes. If the operation is not overridden by
357
  /// the function's attributes, "Unspecified" is returned and target defaults
358
  /// are expected to be used for instruction selection.
359
  int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
360
361
  /// Return the refinement step count for a division of the given type based
362
  /// on the function's attributes. If the operation is not overridden by
363
  /// the function's attributes, "Unspecified" is returned and target defaults
364
  /// are expected to be used for instruction selection.
365
  int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
366
367
  /// Returns true if target has indicated at least one type should be bypassed.
368
466k
  bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
369
370
  /// Returns map of slow types for division or remainder with corresponding
371
  /// fast types
372
11.4k
  const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
373
11.4k
    return BypassSlowDivWidths;
374
11.4k
  }
375
376
  /// Return true if Flow Control is an expensive operation that should be
377
  /// avoided.
378
49.8k
  bool isJumpExpensive() const { return JumpIsExpensive; }
379
380
  /// Return true if selects are only cheaper than branches if the branch is
381
  /// unlikely to be predicted right.
382
264k
  bool isPredictableSelectExpensive() const {
383
264k
    return PredictableSelectIsExpensive;
384
264k
  }
385
386
  /// If a branch or a select condition is skewed in one direction by more than
387
  /// this factor, it is very likely to be predicted correctly.
388
  virtual BranchProbability getPredictableBranchThreshold() const;
389
390
  /// Return true if the following transform is beneficial:
391
  /// fold (conv (load x)) -> (load (conv*)x)
392
  /// On architectures that don't natively support some vector loads
393
  /// efficiently, casting the load to a smaller vector of larger types and
394
  /// loading is more efficient, however, this can be undone by optimizations in
395
  /// dag combiner.
396
  virtual bool isLoadBitCastBeneficial(EVT LoadVT,
397
15.4k
                                       EVT BitcastVT) const {
398
15.4k
    // Don't do if we could do an indexed load on the original type, but not on
399
15.4k
    // the new one.
400
15.4k
    if (!LoadVT.isSimple() || 
!BitcastVT.isSimple()15.3k
)
401
86
      return true;
402
15.3k
403
15.3k
    MVT LoadMVT = LoadVT.getSimpleVT();
404
15.3k
405
15.3k
    // Don't bother doing this if it's just going to be promoted again later, as
406
15.3k
    // doing so might interfere with other combines.
407
15.3k
    if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
408
15.3k
        
getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT()367
)
409
243
      return false;
410
15.0k
411
15.0k
    return true;
412
15.0k
  }
413
414
  /// Return true if the following transform is beneficial:
415
  /// (store (y (conv x)), y*)) -> (store x, (x*))
416
18.5k
  virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {
417
18.5k
    // Default to the same logic as loads.
418
18.5k
    return isLoadBitCastBeneficial(StoreVT, BitcastVT);
419
18.5k
  }
420
421
  /// Return true if it is expected to be cheaper to do a store of a non-zero
422
  /// vector constant with the given size and type for the address space than to
423
  /// store the individual scalar element constants.
424
  virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
425
                                            unsigned NumElem,
426
82.1k
                                            unsigned AddrSpace) const {
427
82.1k
    return false;
428
82.1k
  }
429
430
  /// Allow store merging after legalization in addition to before legalization.
431
  /// This may catch stores that do not exist earlier (eg, stores created from
432
  /// intrinsics).
433
900k
  virtual bool mergeStoresAfterLegalization() const { return true; }
434
435
  /// Returns if it's reasonable to merge stores to MemVT size.
436
  virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
437
6.73k
                                const SelectionDAG &DAG) const {
438
6.73k
    return true;
439
6.73k
  }
440
441
  /// Return true if it is cheap to speculate a call to intrinsic cttz.
442
16
  virtual bool isCheapToSpeculateCttz() const {
443
16
    return false;
444
16
  }
445
446
  /// Return true if it is cheap to speculate a call to intrinsic ctlz.
447
1
  virtual bool isCheapToSpeculateCtlz() const {
448
1
    return false;
449
1
  }
450
451
  /// Return true if ctlz instruction is fast.
452
0
  virtual bool isCtlzFast() const {
453
0
    return false;
454
0
  }
455
456
  /// Return true if it is safe to transform an integer-domain bitwise operation
457
  /// into the equivalent floating-point operation. This should be set to true
458
  /// if the target has IEEE-754-compliant fabs/fneg operations for the input
459
  /// type.
460
21.5k
  virtual bool hasBitPreservingFPLogic(EVT VT) const {
461
21.5k
    return false;
462
21.5k
  }
463
464
  /// Return true if it is cheaper to split the store of a merged int val
465
  /// from a pair of smaller values into multiple stores.
466
417
  virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
467
417
    return false;
468
417
  }
469
470
  /// Return if the target supports combining a
471
  /// chain like:
472
  /// \code
473
  ///   %andResult = and %val1, #mask
474
  ///   %icmpResult = icmp %andResult, 0
475
  /// \endcode
476
  /// into a single machine instruction of a form like:
477
  /// \code
478
  ///   cc = test %register, #mask
479
  /// \endcode
480
88
  virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
481
88
    return false;
482
88
  }
483
484
  /// Use bitwise logic to make pairs of compares more efficient. For example:
485
  /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
486
  /// This should be true when it takes more than one instruction to lower
487
  /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
488
  /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
489
2.54k
  virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
490
2.54k
    return false;
491
2.54k
  }
492
493
  /// Return the preferred operand type if the target has a quick way to compare
494
  /// integer values of the given size. Assume that any legal integer type can
495
  /// be compared efficiently. Targets may override this to allow illegal wide
496
  /// types to return a vector type if there is support to compare that type.
497
0
  virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
498
0
    MVT VT = MVT::getIntegerVT(NumBits);
499
0
    return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
500
0
  }
501
502
  /// Return true if the target should transform:
503
  /// (X & Y) == Y ---> (~X & Y) == 0
504
  /// (X & Y) != Y ---> (~X & Y) != 0
505
  ///
506
  /// This may be profitable if the target has a bitwise and-not operation that
507
  /// sets comparison flags. A target may want to limit the transformation based
508
  /// on the type of Y or if Y is a constant.
509
  ///
510
  /// Note that the transform will not occur if Y is known to be a power-of-2
511
  /// because a mask and compare of a single bit can be handled by inverting the
512
  /// predicate, for example:
513
  /// (X & 8) == 8 ---> (X & 8) != 0
514
622
  virtual bool hasAndNotCompare(SDValue Y) const {
515
622
    return false;
516
622
  }
517
518
  /// Return true if the target has a bitwise and-not operation:
519
  /// X = ~A & B
520
  /// This can be used to simplify select or other instructions.
521
747
  virtual bool hasAndNot(SDValue X) const {
522
747
    // If the target has the more complex version of this operation, assume that
523
747
    // it has this operation too.
524
747
    return hasAndNotCompare(X);
525
747
  }
526
527
  /// There are two ways to clear extreme bits (either low or high):
528
  /// Mask:    x &  (-1 << y)  (the instcombine canonical form)
529
  /// Shifts:  x >> y << y
530
  /// Return true if the variant with 2 shifts is preferred.
531
  /// Return false if there is no preference.
532
231k
  virtual bool preferShiftsToClearExtremeBits(SDValue X) const {
533
231k
    // By default, let's assume that no one prefers shifts.
534
231k
    return false;
535
231k
  }
536
537
  /// Should we tranform the IR-optimal check for whether given truncation
538
  /// down into KeptBits would be truncating or not:
539
  ///   (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
540
  /// Into it's more traditional form:
541
  ///   ((%x << C) a>> C) dstcond %x
542
  /// Return true if we should transform.
543
  /// Return false if there is no preference.
544
  virtual bool shouldTransformSignedTruncationCheck(EVT XVT,
545
33
                                                    unsigned KeptBits) const {
546
33
    // By default, let's assume that no one prefers shifts.
547
33
    return false;
548
33
  }
549
550
  /// Return true if the target wants to use the optimization that
551
  /// turns ext(promotableInst1(...(promotableInstN(load)))) into
552
  /// promotedInst1(...(promotedInstN(ext(load)))).
553
522k
  bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
554
555
  /// Return true if the target can combine store(extractelement VectorTy,
556
  /// Idx).
557
  /// \p Cost[out] gives the cost of that transformation when this is true.
558
  virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
559
50.7k
                                         unsigned &Cost) const {
560
50.7k
    return false;
561
50.7k
  }
562
563
  /// Return true if inserting a scalar into a variable element of an undef
564
  /// vector is more efficiently handled by splatting the scalar instead.
565
75
  virtual bool shouldSplatInsEltVarIndex(EVT) const {
566
75
    return false;
567
75
  }
568
569
  /// Return true if target supports floating point exceptions.
570
7.72M
  bool hasFloatingPointExceptions() const {
571
7.72M
    return HasFloatingPointExceptions;
572
7.72M
  }
573
574
  /// Return true if target always beneficiates from combining into FMA for a
575
  /// given value type. This must typically return false on targets where FMA
576
  /// takes more cycles to execute than FADD.
577
4.58k
  virtual bool enableAggressiveFMAFusion(EVT VT) const {
578
4.58k
    return false;
579
4.58k
  }
580
581
  /// Return the ValueType of the result of SETCC operations.
582
  virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
583
                                 EVT VT) const;
584
585
  /// Return the ValueType for comparison libcalls. Comparions libcalls include
586
  /// floating point comparion calls, and Ordered/Unordered check calls on
587
  /// floating point numbers.
588
  virtual
589
  MVT::SimpleValueType getCmpLibcallReturnType() const;
590
591
  /// For targets without i1 registers, this gives the nature of the high-bits
592
  /// of boolean values held in types wider than i1.
593
  ///
594
  /// "Boolean values" are special true/false values produced by nodes like
595
  /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
596
  /// Not to be confused with general values promoted from i1.  Some cpus
597
  /// distinguish between vectors of boolean and scalars; the isVec parameter
598
  /// selects between the two kinds.  For example on X86 a scalar boolean should
599
  /// be zero extended from i1, while the elements of a vector of booleans
600
  /// should be sign extended from i1.
601
  ///
602
  /// Some cpus also treat floating point types the same way as they treat
603
  /// vectors instead of the way they treat scalars.
604
1.52M
  BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
605
1.52M
    if (isVec)
606
333k
      return BooleanVectorContents;
607
1.19M
    return isFloat ? 
BooleanFloatContents31.3k
:
BooleanContents1.16M
;
608
1.19M
  }
609
610
1.51M
  BooleanContent getBooleanContents(EVT Type) const {
611
1.51M
    return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
612
1.51M
  }
613
614
  /// Return target scheduling preference.
615
297k
  Sched::Preference getSchedulingPreference() const {
616
297k
    return SchedPreferenceInfo;
617
297k
  }
618
619
  /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
620
  /// for different nodes. This function returns the preference (or none) for
621
  /// the given node.
622
10.1M
  virtual Sched::Preference getSchedulingPreference(SDNode *) const {
623
10.1M
    return Sched::None;
624
10.1M
  }
625
626
  /// Return the register class that should be used for the specified value
627
  /// type.
628
19.1M
  virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
629
19.1M
    const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
630
19.1M
    assert(RC && "This value type is not natively supported!");
631
19.1M
    return RC;
632
19.1M
  }
633
634
  /// Return the 'representative' register class for the specified value
635
  /// type.
636
  ///
637
  /// The 'representative' register class is the largest legal super-reg
638
  /// register class for the register class of the value type.  For example, on
639
  /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
640
  /// register class is GR64 on x86_64.
641
1.78M
  virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
642
1.78M
    const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
643
1.78M
    return RC;
644
1.78M
  }
645
646
  /// Return the cost of the 'representative' register class for the specified
647
  /// value type.
648
1.45M
  virtual uint8_t getRepRegClassCostFor(MVT VT) const {
649
1.45M
    return RepRegClassCostForVT[VT.SimpleTy];
650
1.45M
  }
651
652
  /// Return true if SHIFT instructions should be expanded to SHIFT_PARTS
653
  /// instructions, and false if a library call is preferred (e.g for code-size
654
  /// reasons).
655
255
  virtual bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const {
656
255
    return true;
657
255
  }
658
659
  /// Return true if the target has native support for the specified value type.
660
  /// This means that it has a register that directly holds it without
661
  /// promotions or expansions.
662
466M
  bool isTypeLegal(EVT VT) const {
663
466M
    assert(!VT.isSimple() ||
664
466M
           (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
665
466M
    return VT.isSimple() && 
RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr465M
;
666
466M
  }
667
668
  class ValueTypeActionImpl {
669
    /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
670
    /// that indicates how instruction selection should deal with the type.
671
    LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
672
673
  public:
674
50.2k
    ValueTypeActionImpl() {
675
50.2k
      std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
676
50.2k
                TypeLegal);
677
50.2k
    }
678
679
84.7M
    LegalizeTypeAction getTypeAction(MVT VT) const {
680
84.7M
      return ValueTypeActions[VT.SimpleTy];
681
84.7M
    }
682
683
4.94M
    void setTypeAction(MVT VT, LegalizeTypeAction Action) {
684
4.94M
      ValueTypeActions[VT.SimpleTy] = Action;
685
4.94M
    }
686
  };
687
688
1.27M
  const ValueTypeActionImpl &getValueTypeActions() const {
689
1.27M
    return ValueTypeActions;
690
1.27M
  }
691
692
  /// Return how we should legalize values of this type, either it is already
693
  /// legal (return 'Legal') or we need to promote it to a larger type (return
694
  /// 'Promote'), or we need to expand it into multiple registers of smaller
695
  /// integer type (return 'Expand').  'Custom' is not an option.
696
77.2M
  LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
697
77.2M
    return getTypeConversion(Context, VT).first;
698
77.2M
  }
699
34.8k
  LegalizeTypeAction getTypeAction(MVT VT) const {
700
34.8k
    return ValueTypeActions.getTypeAction(VT);
701
34.8k
  }
702
703
  /// For types supported by the target, this is an identity function.  For
704
  /// types that must be promoted to larger types, this returns the larger type
705
  /// to promote to.  For integer types that are larger than the largest integer
706
  /// register, this contains one step in the expansion to get to the smaller
707
  /// register. For illegal floating point types, this returns the integer type
708
  /// to transform to.
709
1.29M
  EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
710
1.29M
    return getTypeConversion(Context, VT).second;
711
1.29M
  }
712
713
  /// For types supported by the target, this is an identity function.  For
714
  /// types that must be expanded (i.e. integer types that are larger than the
715
  /// largest integer register or illegal floating point types), this returns
716
  /// the largest legal type it will be expanded to.
717
15.3k
  EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
718
15.3k
    assert(!VT.isVector());
719
17.1k
    while (true) {
720
17.1k
      switch (getTypeAction(Context, VT)) {
721
17.1k
      case TypeLegal:
722
15.3k
        return VT;
723
17.1k
      case TypeExpandInteger:
724
1.77k
        VT = getTypeToTransformTo(Context, VT);
725
1.77k
        break;
726
17.1k
      default:
727
0
        llvm_unreachable("Type is not legal nor is it to be expanded!");
728
17.1k
      }
729
17.1k
    }
730
15.3k
  }
731
732
  /// Vector types are broken down into some number of legal first class types.
733
  /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
734
  /// promoted EVT::f64 values with the X86 FP stack.  Similarly, EVT::v2i64
735
  /// turns into 4 EVT::i32 values with both PPC and X86.
736
  ///
737
  /// This method returns the number of registers needed, and the VT for each
738
  /// register.  It also returns the VT and quantity of the intermediate values
739
  /// before they are promoted/expanded.
740
  unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
741
                                  EVT &IntermediateVT,
742
                                  unsigned &NumIntermediates,
743
                                  MVT &RegisterVT) const;
744
745
  /// Certain targets such as MIPS require that some types such as vectors are
746
  /// always broken down into scalars in some contexts. This occurs even if the
747
  /// vector type is legal.
748
  virtual unsigned getVectorTypeBreakdownForCallingConv(
749
      LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
750
17.2k
      unsigned &NumIntermediates, MVT &RegisterVT) const {
751
17.2k
    return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
752
17.2k
                                  RegisterVT);
753
17.2k
  }
754
755
  struct IntrinsicInfo {
756
    unsigned     opc = 0;          // target opcode
757
    EVT          memVT;            // memory VT
758
759
    // value representing memory location
760
    PointerUnion<const Value *, const PseudoSourceValue *> ptrVal;
761
762
    int          offset = 0;       // offset off of ptrVal
763
    unsigned     size = 0;         // the size of the memory location
764
                                   // (taken from memVT if zero)
765
    unsigned     align = 1;        // alignment
766
767
    MachineMemOperand::Flags flags = MachineMemOperand::MONone;
768
197k
    IntrinsicInfo() = default;
769
  };
770
771
  /// Given an intrinsic, checks if on the target the intrinsic will need to map
772
  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
773
  /// true and store the intrinsic information into the IntrinsicInfo that was
774
  /// passed to the function.
775
  virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
776
                                  MachineFunction &,
777
5.05k
                                  unsigned /*Intrinsic*/) const {
778
5.05k
    return false;
779
5.05k
  }
780
781
  /// Returns true if the target can instruction select the specified FP
782
  /// immediate natively. If false, the legalizer will materialize the FP
783
  /// immediate as a load from a constant pool.
784
  virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/,
785
77
          bool ForCodeSize = false) const {
786
77
    return false;
787
77
  }
788
789
  /// Targets can use this to indicate that they only support *some*
790
  /// VECTOR_SHUFFLE operations, those with specific masks.  By default, if a
791
  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
792
  /// legal.
793
1.44k
  virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
794
1.44k
    return true;
795
1.44k
  }
796
797
  /// Returns true if the operation can trap for the value type.
798
  ///
799
  /// VT must be a legal type. By default, we optimistically assume most
800
  /// operations don't trap except for integer divide and remainder.
801
  virtual bool canOpTrap(unsigned Op, EVT VT) const;
802
803
  /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
804
  /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
805
  /// constant pool entry.
806
  virtual bool isVectorClearMaskLegal(ArrayRef<int> /*Mask*/,
807
12.1k
                                      EVT /*VT*/) const {
808
12.1k
    return false;
809
12.1k
  }
810
811
  /// Return how this operation should be treated: either it is legal, needs to
812
  /// be promoted to a larger size, needs to be expanded to some other code
813
  /// sequence, or the target has a custom expander for it.
814
100M
  LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
815
100M
    if (VT.isExtended()) 
return Expand182k
;
816
100M
    // If a target-specific SDNode requires legalization, require the target
817
100M
    // to provide custom legalization for it.
818
100M
    if (Op >= array_lengthof(OpActions[0])) 
return Custom164
;
819
100M
    return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
820
100M
  }
821
822
  /// Custom method defined by each target to indicate if an operation which
823
  /// may require a scale is supported natively by the target.
824
  /// If not, the operation is illegal.
825
  virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT,
826
0
                                              unsigned Scale) const {
827
0
    return false;
828
0
  }
829
830
  /// Some fixed point operations may be natively supported by the target but
831
  /// only for specific scales. This method allows for checking
832
  /// if the width is supported by the target for a given operation that may
833
  /// depend on scale.
834
  LegalizeAction getFixedPointOperationAction(unsigned Op, EVT VT,
835
45
                                              unsigned Scale) const {
836
45
    auto Action = getOperationAction(Op, VT);
837
45
    if (Action != Legal)
838
45
      return Action;
839
0
840
0
    // This operation is supported in this type but may only work on specific
841
0
    // scales.
842
0
    bool Supported;
843
0
    switch (Op) {
844
0
    default:
845
0
      llvm_unreachable("Unexpected fixed point operation.");
846
0
    case ISD::SMULFIX:
847
0
    case ISD::UMULFIX:
848
0
      Supported = isSupportedFixedPointOperation(Op, VT, Scale);
849
0
      break;
850
0
    }
851
0
852
0
    return Supported ? Action : Expand;
853
0
  }
854
855
502
  LegalizeAction getStrictFPOperationAction(unsigned Op, EVT VT) const {
856
502
    unsigned EqOpc;
857
502
    switch (Op) {
858
502
      
default: 0
llvm_unreachable0
("Unexpected FP pseudo-opcode");
859
502
      
case ISD::STRICT_FADD: EqOpc = ISD::FADD; break30
;
860
502
      
case ISD::STRICT_FSUB: EqOpc = ISD::FSUB; break38
;
861
502
      
case ISD::STRICT_FMUL: EqOpc = ISD::FMUL; break30
;
862
502
      
case ISD::STRICT_FDIV: EqOpc = ISD::FDIV; break30
;
863
502
      
case ISD::STRICT_FREM: EqOpc = ISD::FREM; break19
;
864
502
      
case ISD::STRICT_FSQRT: EqOpc = ISD::FSQRT; break30
;
865
502
      
case ISD::STRICT_FPOW: EqOpc = ISD::FPOW; break19
;
866
502
      
case ISD::STRICT_FPOWI: EqOpc = ISD::FPOWI; break19
;
867
502
      
case ISD::STRICT_FMA: EqOpc = ISD::FMA; break36
;
868
502
      
case ISD::STRICT_FSIN: EqOpc = ISD::FSIN; break19
;
869
502
      
case ISD::STRICT_FCOS: EqOpc = ISD::FCOS; break19
;
870
502
      
case ISD::STRICT_FEXP: EqOpc = ISD::FEXP; break19
;
871
502
      
case ISD::STRICT_FEXP2: EqOpc = ISD::FEXP2; break19
;
872
502
      
case ISD::STRICT_FLOG: EqOpc = ISD::FLOG; break19
;
873
502
      
case ISD::STRICT_FLOG10: EqOpc = ISD::FLOG10; break19
;
874
502
      
case ISD::STRICT_FLOG2: EqOpc = ISD::FLOG2; break19
;
875
502
      
case ISD::STRICT_FRINT: EqOpc = ISD::FRINT; break20
;
876
502
      
case ISD::STRICT_FNEARBYINT: EqOpc = ISD::FNEARBYINT; break20
;
877
502
      
case ISD::STRICT_FMAXNUM: EqOpc = ISD::FMAXNUM; break17
;
878
502
      
case ISD::STRICT_FMINNUM: EqOpc = ISD::FMINNUM; break17
;
879
502
      
case ISD::STRICT_FCEIL: EqOpc = ISD::FCEIL; break11
;
880
502
      
case ISD::STRICT_FFLOOR: EqOpc = ISD::FFLOOR; break11
;
881
502
      
case ISD::STRICT_FROUND: EqOpc = ISD::FROUND; break11
;
882
502
      
case ISD::STRICT_FTRUNC: EqOpc = ISD::FTRUNC; break11
;
883
502
    }
884
502
885
502
    auto Action = getOperationAction(EqOpc, VT);
886
502
887
502
    // We don't currently handle Custom or Promote for strict FP pseudo-ops.
888
502
    // For now, we just expand for those cases.
889
502
    if (Action != Legal)
890
342
      Action = Expand;
891
502
892
502
    return Action;
893
502
  }
894
895
  /// Return true if the specified operation is legal on this target or can be
896
  /// made legal with custom lowering. This is used to help guide high-level
897
  /// lowering decisions.
898
23.1M
  bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
899
23.1M
    return (VT == MVT::Other || 
isTypeLegal(VT)23.0M
) &&
900
23.1M
      
(18.1M
getOperationAction(Op, VT) == Legal18.1M
||
901
18.1M
       
getOperationAction(Op, VT) == Custom9.50M
);
902
23.1M
  }
903
904
  /// Return true if the specified operation is legal on this target or can be
905
  /// made legal using promotion. This is used to help guide high-level lowering
906
  /// decisions.
907
591k
  bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
908
591k
    return (VT == MVT::Other || isTypeLegal(VT)) &&
909
591k
      
(591k
getOperationAction(Op, VT) == Legal591k
||
910
591k
       
getOperationAction(Op, VT) == Promote65.2k
);
911
591k
  }
912
913
  /// Return true if the specified operation is legal on this target or can be
914
  /// made legal with custom lowering or using promotion. This is used to help
915
  /// guide high-level lowering decisions.
916
573k
  bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
917
573k
    return (VT == MVT::Other || isTypeLegal(VT)) &&
918
573k
      
(562k
getOperationAction(Op, VT) == Legal562k
||
919
562k
       
getOperationAction(Op, VT) == Custom35.9k
||
920
562k
       
getOperationAction(Op, VT) == Promote19.4k
);
921
573k
  }
922
923
  /// Return true if the operation uses custom lowering, regardless of whether
924
  /// the type is legal or not.
925
1.21k
  bool isOperationCustom(unsigned Op, EVT VT) const {
926
1.21k
    return getOperationAction(Op, VT) == Custom;
927
1.21k
  }
928
929
  /// Return true if lowering to a jump table is allowed.
930
39.1k
  virtual bool areJTsAllowed(const Function *Fn) const {
931
39.1k
    if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
932
2
      return false;
933
39.1k
934
39.1k
    return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
935
39.1k
           
isOperationLegalOrCustom(ISD::BRIND, MVT::Other)7.30k
;
936
39.1k
  }
937
938
  /// Check whether the range [Low,High] fits in a machine word.
939
  bool rangeFitsInWord(const APInt &Low, const APInt &High,
940
48.1k
                       const DataLayout &DL) const {
941
48.1k
    // FIXME: Using the pointer type doesn't seem ideal.
942
48.1k
    uint64_t BW = DL.getIndexSizeInBits(0u);
943
48.1k
    uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
944
48.1k
    return Range <= BW;
945
48.1k
  }
946
947
  /// Return true if lowering to a jump table is suitable for a set of case
948
  /// clusters which may contain \p NumCases cases, \p Range range of values.
949
  /// FIXME: This function check the maximum table size and density, but the
950
  /// minimum size is not checked. It would be nice if the minimum size is
951
  /// also combined within this function. Currently, the minimum size check is
952
  /// performed in findJumpTable() in SelectionDAGBuiler and
953
  /// getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
954
  virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
955
19.4k
                                      uint64_t Range) const {
956
19.4k
    const bool OptForSize = SI->getParent()->getParent()->optForSize();
957
19.4k
    const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
958
19.4k
    const unsigned MaxJumpTableSize =
959
19.4k
        OptForSize || 
getMaximumJumpTableSize() == 019.3k
960
19.4k
            ? UINT_MAX
961
19.4k
            : 
getMaximumJumpTableSize()464
;
962
19.4k
    // Check whether a range of clusters is dense enough for a jump table.
963
19.4k
    if (Range <= MaxJumpTableSize &&
964
19.4k
        
(NumCases * 100 >= Range * MinDensity)19.2k
) {
965
14.2k
      return true;
966
14.2k
    }
967
5.18k
    return false;
968
5.18k
  }
969
970
  /// Return true if lowering to a bit test is suitable for a set of case
971
  /// clusters which contains \p NumDests unique destinations, \p Low and
972
  /// \p High as its lowest and highest case values, and expects \p NumCmps
973
  /// case value comparisons. Check if the number of destinations, comparison
974
  /// metric, and range are all suitable.
975
  bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
976
                             const APInt &Low, const APInt &High,
977
38.2k
                             const DataLayout &DL) const {
978
38.2k
    // FIXME: I don't think NumCmps is the correct metric: a single case and a
979
38.2k
    // range of cases both require only one branch to lower. Just looking at the
980
38.2k
    // number of clusters and destinations should be enough to decide whether to
981
38.2k
    // build bit tests.
982
38.2k
983
38.2k
    // To lower a range with bit tests, the range must fit the bitwidth of a
984
38.2k
    // machine word.
985
38.2k
    if (!rangeFitsInWord(Low, High, DL))
986
6.73k
      return false;
987
31.4k
988
31.4k
    // Decide whether it's profitable to lower this range with bit tests. Each
989
31.4k
    // destination requires a bit test and branch, and there is an overall range
990
31.4k
    // check branch. For a small number of clusters, separate comparisons might
991
31.4k
    // be cheaper, and for many destinations, splitting the range might be
992
31.4k
    // better.
993
31.4k
    return (NumDests == 1 && 
NumCmps >= 36.29k
) ||
(28.4k
NumDests == 228.4k
&&
NumCmps >= 515.3k
) ||
994
31.4k
           
(27.8k
NumDests == 327.8k
&&
NumCmps >= 62.61k
);
995
31.4k
  }
996
997
  /// Return true if the specified operation is illegal on this target or
998
  /// unlikely to be made legal with custom lowering. This is used to help guide
999
  /// high-level lowering decisions.
1000
254k
  bool isOperationExpand(unsigned Op, EVT VT) const {
1001
254k
    return (!isTypeLegal(VT) || 
getOperationAction(Op, VT) == Expand254k
);
1002
254k
  }
1003
1004
  /// Return true if the specified operation is legal on this target.
1005
2.89M
  bool isOperationLegal(unsigned Op, EVT VT) const {
1006
2.89M
    return (VT == MVT::Other || isTypeLegal(VT)) &&
1007
2.89M
           
getOperationAction(Op, VT) == Legal2.86M
;
1008
2.89M
  }
1009
1010
  /// Return how this load with extension should be treated: either it is legal,
1011
  /// needs to be promoted to a larger size, needs to be expanded to some other
1012
  /// code sequence, or the target has a custom expander for it.
1013
  LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
1014
1.16M
                                  EVT MemVT) const {
1015
1.16M
    if (ValVT.isExtended() || 
MemVT.isExtended()1.16M
)
return Expand4.42k
;
1016
1.15M
    unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1017
1.15M
    unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1018
1.15M
    assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
1019
1.15M
           MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
1020
1.15M
    unsigned Shift = 4 * ExtType;
1021
1.15M
    return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
1022
1.15M
  }
1023
1024
  /// Return true if the specified load with extension is legal on this target.
1025
776k
  bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
1026
776k
    return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
1027
776k
  }
1028
1029
  /// Return true if the specified load with extension is legal or custom
1030
  /// on this target.
1031
3.78k
  bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
1032
3.78k
    return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
1033
3.78k
           
getLoadExtAction(ExtType, ValVT, MemVT) == Custom3.29k
;
1034
3.78k
  }
1035
1036
  /// Return how this store with truncation should be treated: either it is
1037
  /// legal, needs to be promoted to a larger size, needs to be expanded to some
1038
  /// other code sequence, or the target has a custom expander for it.
1039
378k
  LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
1040
378k
    if (ValVT.isExtended() || MemVT.isExtended()) 
return Expand125k
;
1041
252k
    unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1042
252k
    unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1043
252k
    assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
1044
252k
           "Table isn't big enough!");
1045
252k
    return TruncStoreActions[ValI][MemI];
1046
252k
  }
1047
1048
  /// Return true if the specified store with truncation is legal on this
1049
  /// target.
1050
218k
  bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
1051
218k
    return isTypeLegal(ValVT) && 
getTruncStoreAction(ValVT, MemVT) == Legal161k
;
1052
218k
  }
1053
1054
  /// Return true if the specified store with truncation has solution on this
1055
  /// target.
1056
2.59k
  bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
1057
2.59k
    return isTypeLegal(ValVT) &&
1058
2.59k
      (getTruncStoreAction(ValVT, MemVT) == Legal ||
1059
2.59k
       
getTruncStoreAction(ValVT, MemVT) == Custom1.15k
);
1060
2.59k
  }
1061
1062
  /// Return how the indexed load should be treated: either it is legal, needs
1063
  /// to be promoted to a larger size, needs to be expanded to some other code
1064
  /// sequence, or the target has a custom expander for it.
1065
  LegalizeAction
1066
13.0M
  getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
1067
13.0M
    assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1068
13.0M
           "Table isn't big enough!");
1069
13.0M
    unsigned Ty = (unsigned)VT.SimpleTy;
1070
13.0M
    return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
1071
13.0M
  }
1072
1073
  /// Return true if the specified indexed load is legal on this target.
1074
10.4M
  bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
1075
10.4M
    return VT.isSimple() &&
1076
10.4M
      (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
1077
10.4M
       
getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom2.57M
);
1078
10.4M
  }
1079
1080
  /// Return how the indexed store should be treated: either it is legal, needs
1081
  /// to be promoted to a larger size, needs to be expanded to some other code
1082
  /// sequence, or the target has a custom expander for it.
1083
  LegalizeAction
1084
6.32M
  getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
1085
6.32M
    assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1086
6.32M
           "Table isn't big enough!");
1087
6.32M
    unsigned Ty = (unsigned)VT.SimpleTy;
1088
6.32M
    return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
1089
6.32M
  }
1090
1091
  /// Return true if the specified indexed load is legal on this target.
1092
3.64M
  bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
1093
3.64M
    return VT.isSimple() &&
1094
3.64M
      (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
1095
3.64M
       
getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom2.68M
);
1096
3.64M
  }
1097
1098
  /// Return how the condition code should be treated: either it is legal, needs
1099
  /// to be expanded to some other code sequence, or the target has a custom
1100
  /// expander for it.
1101
  LegalizeAction
1102
567k
  getCondCodeAction(ISD::CondCode CC, MVT VT) const {
1103
567k
    assert((unsigned)CC < array_lengthof(CondCodeActions) &&
1104
567k
           ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
1105
567k
           "Table isn't big enough!");
1106
567k
    // See setCondCodeAction for how this is encoded.
1107
567k
    uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1108
567k
    uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
1109
567k
    LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
1110
567k
    assert(Action != Promote && "Can't promote condition code!");
1111
567k
    return Action;
1112
567k
  }
1113
1114
  /// Return true if the specified condition code is legal on this target.
1115
13.3k
  bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
1116
13.3k
    return getCondCodeAction(CC, VT) == Legal;
1117
13.3k
  }
1118
1119
  /// Return true if the specified condition code is legal or custom on this
1120
  /// target.
1121
4.10k
  bool isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) const {
1122
4.10k
    return getCondCodeAction(CC, VT) == Legal ||
1123
4.10k
           
getCondCodeAction(CC, VT) == Custom1.61k
;
1124
4.10k
  }
1125
1126
  /// If the action for this operation is to promote, this method returns the
1127
  /// ValueType to promote to.
1128
203k
  MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
1129
203k
    assert(getOperationAction(Op, VT) == Promote &&
1130
203k
           "This operation isn't promoted!");
1131
203k
1132
203k
    // See if this has an explicit type specified.
1133
203k
    std::map<std::pair<unsigned, MVT::SimpleValueType>,
1134
203k
             MVT::SimpleValueType>::const_iterator PTTI =
1135
203k
      PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1136
203k
    if (PTTI != PromoteToType.end()) 
return PTTI->second201k
;
1137
1.68k
1138
1.68k
    assert((VT.isInteger() || VT.isFloatingPoint()) &&
1139
1.68k
           "Cannot autopromote this type, add it with AddPromotedToType.");
1140
1.68k
1141
1.68k
    MVT NVT = VT;
1142
2.05k
    do {
1143
2.05k
      NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1144
2.05k
      assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1145
2.05k
             "Didn't find type to promote to!");
1146
2.05k
    } while (!isTypeLegal(NVT) ||
1147
2.05k
              
getOperationAction(Op, NVT) == Promote1.79k
);
1148
1.68k
    return NVT;
1149
1.68k
  }
1150
1151
  /// Return the EVT corresponding to this LLVM type.  This is fixed by the LLVM
1152
  /// operations except for the pointer size.  If AllowUnknown is true, this
1153
  /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1154
  /// otherwise it will assert.
1155
  EVT getValueType(const DataLayout &DL, Type *Ty,
1156
65.8M
                   bool AllowUnknown = false) const {
1157
65.8M
    // Lower scalar pointers to native pointer types.
1158
65.8M
    if (PointerType *PTy = dyn_cast<PointerType>(Ty))
1159
19.8M
      return getPointerTy(DL, PTy->getAddressSpace());
1160
46.0M
1161
46.0M
    if (Ty->isVectorTy()) {
1162
6.58M
      VectorType *VTy = cast<VectorType>(Ty);
1163
6.58M
      Type *Elm = VTy->getElementType();
1164
6.58M
      // Lower vectors of pointers to native pointer types.
1165
6.58M
      if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
1166
322k
        EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
1167
322k
        Elm = PointerTy.getTypeForEVT(Ty->getContext());
1168
322k
      }
1169
6.58M
1170
6.58M
      return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1171
6.58M
                       VTy->getNumElements());
1172
6.58M
    }
1173
39.4M
    return EVT::getEVT(Ty, AllowUnknown);
1174
39.4M
  }
1175
1176
  /// Return the MVT corresponding to this LLVM type. See getValueType.
1177
  MVT getSimpleValueType(const DataLayout &DL, Type *Ty,
1178
21.2k
                         bool AllowUnknown = false) const {
1179
21.2k
    return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1180
21.2k
  }
1181
1182
  /// Return the desired alignment for ByVal or InAlloca aggregate function
1183
  /// arguments in the caller parameter area.  This is the actual alignment, not
1184
  /// its logarithm.
1185
  virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1186
1187
  /// Return the type of registers that this ValueType will eventually require.
1188
4.23M
  MVT getRegisterType(MVT VT) const {
1189
4.23M
    assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
1190
4.23M
    return RegisterTypeForVT[VT.SimpleTy];
1191
4.23M
  }
1192
1193
  /// Return the type of registers that this ValueType will eventually require.
1194
7.15M
  MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1195
7.15M
    if (VT.isSimple()) {
1196
7.14M
      assert((unsigned)VT.getSimpleVT().SimpleTy <
1197
7.14M
                array_lengthof(RegisterTypeForVT));
1198
7.14M
      return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1199
7.14M
    }
1200
15.6k
    if (VT.isVector()) {
1201
4.04k
      EVT VT1;
1202
4.04k
      MVT RegisterVT;
1203
4.04k
      unsigned NumIntermediates;
1204
4.04k
      (void)getVectorTypeBreakdown(Context, VT, VT1,
1205
4.04k
                                   NumIntermediates, RegisterVT);
1206
4.04k
      return RegisterVT;
1207
4.04k
    }
1208
11.5k
    if (VT.isInteger()) {
1209
11.5k
      return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1210
11.5k
    }
1211
0
    llvm_unreachable("Unsupported extended type!");
1212
0
  }
1213
1214
  /// Return the number of registers that this ValueType will eventually
1215
  /// require.
1216
  ///
1217
  /// This is one for any types promoted to live in larger registers, but may be
1218
  /// more than one for types (like i64) that are split into pieces.  For types
1219
  /// like i140, which are first promoted then expanded, it is the number of
1220
  /// registers needed to hold all the bits of the original type.  For an i140
1221
  /// on a 32 bit machine this means 5 registers.
1222
7.98M
  unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1223
7.98M
    if (VT.isSimple()) {
1224
7.97M
      assert((unsigned)VT.getSimpleVT().SimpleTy <
1225
7.97M
                array_lengthof(NumRegistersForVT));
1226
7.97M
      return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1227
7.97M
    }
1228
8.69k
    if (VT.isVector()) {
1229
4.12k
      EVT VT1;
1230
4.12k
      MVT VT2;
1231
4.12k
      unsigned NumIntermediates;
1232
4.12k
      return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1233
4.12k
    }
1234
4.57k
    
if (4.57k
VT.isInteger()4.57k
) {
1235
4.57k
      unsigned BitWidth = VT.getSizeInBits();
1236
4.57k
      unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1237
4.57k
      return (BitWidth + RegWidth - 1) / RegWidth;
1238
4.57k
    }
1239
18.4E
    llvm_unreachable("Unsupported extended type!");
1240
18.4E
  }
1241
1242
  /// Certain combinations of ABIs, Targets and features require that types
1243
  /// are legal for some operations and not for other operations.
1244
  /// For MIPS all vector types must be passed through the integer register set.
1245
  virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context,
1246
3.04M
                                            CallingConv::ID CC, EVT VT) const {
1247
3.04M
    return getRegisterType(Context, VT);
1248
3.04M
  }
1249
1250
  /// Certain targets require unusual breakdowns of certain types. For MIPS,
1251
  /// this occurs when a vector type is used, as vector are passed through the
1252
  /// integer register set.
1253
  virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1254
                                                 CallingConv::ID CC,
1255
3.04M
                                                 EVT VT) const {
1256
3.04M
    return getNumRegisters(Context, VT);
1257
3.04M
  }
1258
1259
  /// Certain targets have context senstive alignment requirements, where one
1260
  /// type has the alignment requirement of another type.
1261
  virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
1262
1.34M
                                                 DataLayout DL) const {
1263
1.34M
    return DL.getABITypeAlignment(ArgTy);
1264
1.34M
  }
1265
1266
  /// If true, then instruction selection should seek to shrink the FP constant
1267
  /// of the specified type to a smaller type in order to save space and / or
1268
  /// reduce runtime.
1269
290
  virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1270
1271
  /// Return true if it is profitable to reduce a load to a smaller type.
1272
  /// Example: (i16 (trunc (i32 (load x))) -> i16 load x
1273
  virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
1274
19.7k
                                     EVT NewVT) const {
1275
19.7k
    // By default, assume that it is cheaper to extract a subvector from a wide
1276
19.7k
    // vector load rather than creating multiple narrow vector loads.
1277
19.7k
    if (NewVT.isVector() && 
!Load->hasOneUse()9.54k
)
1278
9.40k
      return false;
1279
10.3k
1280
10.3k
    return true;
1281
10.3k
  }
1282
1283
  /// When splitting a value of the specified type into parts, does the Lo
1284
  /// or Hi part come first?  This usually follows the endianness, except
1285
  /// for ppcf128, where the Hi part always comes first.
1286
139k
  bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1287
139k
    return DL.isBigEndian() || 
VT == MVT::ppcf128133k
;
1288
139k
  }
1289
1290
  /// If true, the target has custom DAG combine transformations that it can
1291
  /// perform for the specified node.
1292
61.9M
  bool hasTargetDAGCombine(ISD::NodeType NT) const {
1293
61.9M
    assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1294
61.9M
    return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1295
61.9M
  }
1296
1297
10.1M
  unsigned getGatherAllAliasesMaxDepth() const {
1298
10.1M
    return GatherAllAliasesMaxDepth;
1299
10.1M
  }
1300
1301
  /// Returns the size of the platform's va_list object.
1302
0
  virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1303
0
    return getPointerTy(DL).getSizeInBits();
1304
0
  }
1305
1306
  /// Get maximum # of store operations permitted for llvm.memset
1307
  ///
1308
  /// This function returns the maximum number of store operations permitted
1309
  /// to replace a call to llvm.memset. The value is set by the target at the
1310
  /// performance threshold for such a replacement. If OptSize is true,
1311
  /// return the limit for functions that have OptSize attribute.
1312
5.15k
  unsigned getMaxStoresPerMemset(bool OptSize) const {
1313
5.15k
    return OptSize ? 
MaxStoresPerMemsetOptSize21
:
MaxStoresPerMemset5.13k
;
1314
5.15k
  }
1315
1316
  /// Get maximum # of store operations permitted for llvm.memcpy
1317
  ///
1318
  /// This function returns the maximum number of store operations permitted
1319
  /// to replace a call to llvm.memcpy. The value is set by the target at the
1320
  /// performance threshold for such a replacement. If OptSize is true,
1321
  /// return the limit for functions that have OptSize attribute.
1322
7.64k
  unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1323
7.64k
    return OptSize ? 
MaxStoresPerMemcpyOptSize46
:
MaxStoresPerMemcpy7.59k
;
1324
7.64k
  }
1325
1326
  /// \brief Get maximum # of store operations to be glued together
1327
  ///
1328
  /// This function returns the maximum number of store operations permitted
1329
  /// to glue together during lowering of llvm.memcpy. The value is set by
1330
  //  the target at the performance threshold for such a replacement.
1331
6.57k
  virtual unsigned getMaxGluedStoresPerMemcpy() const {
1332
6.57k
    return MaxGluedStoresPerMemcpy;
1333
6.57k
  }
1334
1335
  /// Get maximum # of load operations permitted for memcmp
1336
  ///
1337
  /// This function returns the maximum number of load operations permitted
1338
  /// to replace a call to memcmp. The value is set by the target at the
1339
  /// performance threshold for such a replacement. If OptSize is true,
1340
  /// return the limit for functions that have OptSize attribute.
1341
443
  unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1342
443
    return OptSize ? 
MaxLoadsPerMemcmpOptSize112
:
MaxLoadsPerMemcmp331
;
1343
443
  }
1344
1345
  /// For memcmp expansion when the memcmp result is only compared equal or
1346
  /// not-equal to 0, allow up to this number of load pairs per block. As an
1347
  /// example, this may allow 'memcmp(a, b, 3) == 0' in a single block:
1348
  ///   a0 = load2bytes &a[0]
1349
  ///   b0 = load2bytes &b[0]
1350
  ///   a2 = load1byte  &a[2]
1351
  ///   b2 = load1byte  &b[2]
1352
  ///   r  = cmp eq (a0 ^ b0 | a2 ^ b2), 0
1353
22
  virtual unsigned getMemcmpEqZeroLoadsPerBlock() const {
1354
22
    return 1;
1355
22
  }
1356
1357
  /// Get maximum # of store operations permitted for llvm.memmove
1358
  ///
1359
  /// This function returns the maximum number of store operations permitted
1360
  /// to replace a call to llvm.memmove. The value is set by the target at the
1361
  /// performance threshold for such a replacement. If OptSize is true,
1362
  /// return the limit for functions that have OptSize attribute.
1363
91
  unsigned getMaxStoresPerMemmove(bool OptSize) const {
1364
91
    return OptSize ? 
MaxStoresPerMemmoveOptSize0
: MaxStoresPerMemmove;
1365
91
  }
1366
1367
  /// Determine if the target supports unaligned memory accesses.
1368
  ///
1369
  /// This function returns true if the target allows unaligned memory accesses
1370
  /// of the specified type in the given address space. If true, it also returns
1371
  /// whether the unaligned memory access is "fast" in the last argument by
1372
  /// reference. This is used, for example, in situations where an array
1373
  /// copy/move/set is converted to a sequence of store operations. Its use
1374
  /// helps to ensure that such replacements don't generate code that causes an
1375
  /// alignment error (trap) on the target machine.
1376
  virtual bool allowsMisalignedMemoryAccesses(EVT,
1377
                                              unsigned AddrSpace = 0,
1378
                                              unsigned Align = 1,
1379
1.21k
                                              bool * /*Fast*/ = nullptr) const {
1380
1.21k
    return false;
1381
1.21k
  }
1382
1383
  /// Return true if the target supports a memory access of this type for the
1384
  /// given address space and alignment. If the access is allowed, the optional
1385
  /// final parameter returns if the access is also fast (as defined by the
1386
  /// target).
1387
  bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1388
                          unsigned AddrSpace = 0, unsigned Alignment = 1,
1389
                          bool *Fast = nullptr) const;
1390
1391
  /// Returns the target specific optimal type for load and store operations as
1392
  /// a result of memset, memcpy, and memmove lowering.
1393
  ///
1394
  /// If DstAlign is zero that means it's safe to destination alignment can
1395
  /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1396
  /// a need to check it against alignment requirement, probably because the
1397
  /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1398
  /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1399
  /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1400
  /// does not need to be loaded.  It returns EVT::Other if the type should be
1401
  /// determined using generic target-independent logic.
1402
  virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
1403
                                  unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
1404
                                  bool /*IsMemset*/,
1405
                                  bool /*ZeroMemset*/,
1406
                                  bool /*MemcpyStrSrc*/,
1407
162
                                  MachineFunction &/*MF*/) const {
1408
162
    return MVT::Other;
1409
162
  }
1410
1411
  /// Returns true if it's safe to use load / store of the specified type to
1412
  /// expand memcpy / memset inline.
1413
  ///
1414
  /// This is mostly true for all types except for some special cases. For
1415
  /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1416
  /// fstpl which also does type conversion. Note the specified type doesn't
1417
  /// have to be legal as the hook is used before type legalization.
1418
3.57k
  virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1419
1420
  /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1421
0
  bool usesUnderscoreSetJmp() const {
1422
0
    return UseUnderscoreSetJmp;
1423
0
  }
1424
1425
  /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1426
0
  bool usesUnderscoreLongJmp() const {
1427
0
    return UseUnderscoreLongJmp;
1428
0
  }
1429
1430
  /// Return lower limit for number of blocks in a jump table.
1431
  virtual unsigned getMinimumJumpTableEntries() const;
1432
1433
  /// Return lower limit of the density in a jump table.
1434
  unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1435
1436
  /// Return upper limit for number of entries in a jump table.
1437
  /// Zero if no limit.
1438
  unsigned getMaximumJumpTableSize() const;
1439
1440
324
  virtual bool isJumpTableRelative() const {
1441
324
    return TM.isPositionIndependent();
1442
324
  }
1443
1444
  /// If a physical register, this specifies the register that
1445
  /// llvm.savestack/llvm.restorestack should save and restore.
1446
20.7M
  unsigned getStackPointerRegisterToSaveRestore() const {
1447
20.7M
    return StackPointerRegisterToSaveRestore;
1448
20.7M
  }
1449
1450
  /// If a physical register, this returns the register that receives the
1451
  /// exception address on entry to an EH pad.
1452
  virtual unsigned
1453
0
  getExceptionPointerRegister(const Constant *PersonalityFn) const {
1454
0
    // 0 is guaranteed to be the NoRegister value on all targets
1455
0
    return 0;
1456
0
  }
1457
1458
  /// If a physical register, this returns the register that receives the
1459
  /// exception typeid on entry to a landing pad.
1460
  virtual unsigned
1461
0
  getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1462
0
    // 0 is guaranteed to be the NoRegister value on all targets
1463
0
    return 0;
1464
0
  }
1465
1466
0
  virtual bool needsFixedCatchObjects() const {
1467
0
    report_fatal_error("Funclet EH is not implemented for this target");
1468
0
  }
1469
1470
  /// Returns the target's jmp_buf size in bytes (if never set, the default is
1471
  /// 200)
1472
0
  unsigned getJumpBufSize() const {
1473
0
    return JumpBufSize;
1474
0
  }
1475
1476
  /// Returns the target's jmp_buf alignment in bytes (if never set, the default
1477
  /// is 0)
1478
0
  unsigned getJumpBufAlignment() const {
1479
0
    return JumpBufAlignment;
1480
0
  }
1481
1482
  /// Return the minimum stack alignment of an argument.
1483
174
  unsigned getMinStackArgumentAlignment() const {
1484
174
    return MinStackArgumentAlignment;
1485
174
  }
1486
1487
  /// Return the minimum function alignment.
1488
503k
  unsigned getMinFunctionAlignment() const {
1489
503k
    return MinFunctionAlignment;
1490
503k
  }
1491
1492
  /// Return the preferred function alignment.
1493
500k
  unsigned getPrefFunctionAlignment() const {
1494
500k
    return PrefFunctionAlignment;
1495
500k
  }
1496
1497
  /// Return the preferred loop alignment.
1498
638k
  virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1499
638k
    return PrefLoopAlignment;
1500
638k
  }
1501
1502
  /// Should loops be aligned even when the function is marked OptSize (but not
1503
  /// MinSize).
1504
147
  virtual bool alignLoopsWithOptSize() const {
1505
147
    return false;
1506
147
  }
1507
1508
  /// If the target has a standard location for the stack protector guard,
1509
  /// returns the address of that location. Otherwise, returns nullptr.
1510
  /// DEPRECATED: please override useLoadStackGuardNode and customize
1511
  ///             LOAD_STACK_GUARD, or customize \@llvm.stackguard().
1512
  virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1513
1514
  /// Inserts necessary declarations for SSP (stack protection) purpose.
1515
  /// Should be used only when getIRStackGuard returns nullptr.
1516
  virtual void insertSSPDeclarations(Module &M) const;
1517
1518
  /// Return the variable that's previously inserted by insertSSPDeclarations,
1519
  /// if any, otherwise return nullptr. Should be used only when
1520
  /// getIRStackGuard returns nullptr.
1521
  virtual Value *getSDagStackGuard(const Module &M) const;
1522
1523
  /// If this function returns true, stack protection checks should XOR the
1524
  /// frame pointer (or whichever pointer is used to address locals) into the
1525
  /// stack guard value before checking it. getIRStackGuard must return nullptr
1526
  /// if this returns true.
1527
3.31k
  virtual bool useStackGuardXorFP() const { return false; }
1528
1529
  /// If the target has a standard stack protection check function that
1530
  /// performs validation and error handling, returns the function. Otherwise,
1531
  /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1532
  /// Should be used only when getIRStackGuard returns nullptr.
1533
  virtual Function *getSSPStackGuardCheck(const Module &M) const;
1534
1535
protected:
1536
  Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1537
                                            bool UseTLS) const;
1538
1539
public:
1540
  /// Returns the target-specific address of the unsafe stack pointer.
1541
  virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1542
1543
  /// Returns the name of the symbol used to emit stack probes or the empty
1544
  /// string if not applicable.
1545
0
  virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const {
1546
0
    return "";
1547
0
  }
1548
1549
  /// Returns true if a cast between SrcAS and DestAS is a noop.
1550
474
  virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1551
474
    return false;
1552
474
  }
1553
1554
  /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1555
  /// are happy to sink it into basic blocks.
1556
205
  virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1557
205
    return isNoopAddrSpaceCast(SrcAS, DestAS);
1558
205
  }
1559
1560
  /// Return true if the pointer arguments to CI should be aligned by aligning
1561
  /// the object whose address is being passed. If so then MinSize is set to the
1562
  /// minimum size the object must be to be aligned and PrefAlign is set to the
1563
  /// preferred alignment.
1564
  virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1565
3.88M
                                      unsigned & /*PrefAlign*/) const {
1566
3.88M
    return false;
1567
3.88M
  }
1568
1569
  //===--------------------------------------------------------------------===//
1570
  /// \name Helpers for TargetTransformInfo implementations
1571
  /// @{
1572
1573
  /// Get the ISD node that corresponds to the Instruction class opcode.
1574
  int InstructionOpcodeToISD(unsigned Opcode) const;
1575
1576
  /// Estimate the cost of type-legalization and the legalized type.
1577
  std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1578
                                              Type *Ty) const;
1579
1580
  /// @}
1581
1582
  //===--------------------------------------------------------------------===//
1583
  /// \name Helpers for atomic expansion.
1584
  /// @{
1585
1586
  /// Returns the maximum atomic operation size (in bits) supported by
1587
  /// the backend. Atomic operations greater than this size (as well
1588
  /// as ones that are not naturally aligned), will be expanded by
1589
  /// AtomicExpandPass into an __atomic_* library call.
1590
41.0k
  unsigned getMaxAtomicSizeInBitsSupported() const {
1591
41.0k
    return MaxAtomicSizeInBitsSupported;
1592
41.0k
  }
1593
1594
  /// Returns the size of the smallest cmpxchg or ll/sc instruction
1595
  /// the backend supports.  Any smaller operations are widened in
1596
  /// AtomicExpandPass.
1597
  ///
1598
  /// Note that *unlike* operations above the maximum size, atomic ops
1599
  /// are still natively supported below the minimum; they just
1600
  /// require a more complex expansion.
1601
54.2k
  unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1602
1603
  /// Whether the target supports unaligned atomic operations.
1604
1.32k
  bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
1605
1606
  /// Whether AtomicExpandPass should automatically insert fences and reduce
1607
  /// ordering for this atomic. This should be true for most architectures with
1608
  /// weak memory ordering. Defaults to false.
1609
42.9k
  virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1610
42.9k
    return false;
1611
42.9k
  }
1612
1613
  /// Perform a load-linked operation on Addr, returning a "Value *" with the
1614
  /// corresponding pointee type. This may entail some non-trivial operations to
1615
  /// truncate or reconstruct types that will be illegal in the backend. See
1616
  /// ARMISelLowering for an example implementation.
1617
  virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1618
0
                                AtomicOrdering Ord) const {
1619
0
    llvm_unreachable("Load linked unimplemented on this target");
1620
0
  }
1621
1622
  /// Perform a store-conditional operation to Addr. Return the status of the
1623
  /// store. This should be 0 if the store succeeded, non-zero otherwise.
1624
  virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1625
0
                                      Value *Addr, AtomicOrdering Ord) const {
1626
0
    llvm_unreachable("Store conditional unimplemented on this target");
1627
0
  }
1628
1629
  /// Perform a masked atomicrmw using a target-specific intrinsic. This
1630
  /// represents the core LL/SC loop which will be lowered at a late stage by
1631
  /// the backend.
1632
  virtual Value *emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder,
1633
                                              AtomicRMWInst *AI,
1634
                                              Value *AlignedAddr, Value *Incr,
1635
                                              Value *Mask, Value *ShiftAmt,
1636
0
                                              AtomicOrdering Ord) const {
1637
0
    llvm_unreachable("Masked atomicrmw expansion unimplemented on this target");
1638
0
  }
1639
1640
  /// Perform a masked cmpxchg using a target-specific intrinsic. This
1641
  /// represents the core LL/SC loop which will be lowered at a late stage by
1642
  /// the backend.
1643
  virtual Value *emitMaskedAtomicCmpXchgIntrinsic(
1644
      IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
1645
0
      Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
1646
0
    llvm_unreachable("Masked cmpxchg expansion unimplemented on this target");
1647
0
  }
1648
1649
  /// Inserts in the IR a target-specific intrinsic specifying a fence.
1650
  /// It is called by AtomicExpandPass before expanding an
1651
  ///   AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1652
  ///   if shouldInsertFencesForAtomic returns true.
1653
  ///
1654
  /// Inst is the original atomic instruction, prior to other expansions that
1655
  /// may be performed.
1656
  ///
1657
  /// This function should either return a nullptr, or a pointer to an IR-level
1658
  ///   Instruction*. Even complex fence sequences can be represented by a
1659
  ///   single Instruction* through an intrinsic to be lowered later.
1660
  /// Backends should override this method to produce target-specific intrinsic
1661
  ///   for their fences.
1662
  /// FIXME: Please note that the default implementation here in terms of
1663
  ///   IR-level fences exists for historical/compatibility reasons and is
1664
  ///   *unsound* ! Fences cannot, in general, be used to restore sequential
1665
  ///   consistency. For example, consider the following example:
1666
  /// atomic<int> x = y = 0;
1667
  /// int r1, r2, r3, r4;
1668
  /// Thread 0:
1669
  ///   x.store(1);
1670
  /// Thread 1:
1671
  ///   y.store(1);
1672
  /// Thread 2:
1673
  ///   r1 = x.load();
1674
  ///   r2 = y.load();
1675
  /// Thread 3:
1676
  ///   r3 = y.load();
1677
  ///   r4 = x.load();
1678
  ///  r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1679
  ///  seq_cst. But if they are lowered to monotonic accesses, no amount of
1680
  ///  IR-level fences can prevent it.
1681
  /// @{
1682
  virtual Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
1683
129
                                        AtomicOrdering Ord) const {
1684
129
    if (isReleaseOrStronger(Ord) && 
Inst->hasAtomicStore()99
)
1685
96
      return Builder.CreateFence(Ord);
1686
33
    else
1687
33
      return nullptr;
1688
129
  }
1689
1690
  virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
1691
                                         Instruction *Inst,
1692
129
                                         AtomicOrdering Ord) const {
1693
129
    if (isAcquireOrStronger(Ord))
1694
106
      return Builder.CreateFence(Ord);
1695
23
    else
1696
23
      return nullptr;
1697
129
  }
1698
  /// @}
1699
1700
  // Emits code that executes when the comparison result in the ll/sc
1701
  // expansion of a cmpxchg instruction is such that the store-conditional will
1702
  // not execute.  This makes it possible to balance out the load-linked with
1703
  // a dedicated instruction, if desired.
1704
  // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1705
  // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1706
3
  virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1707
1708
  /// Returns true if the given (atomic) store should be expanded by the
1709
  /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1710
246
  virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1711
246
    return false;
1712
246
  }
1713
1714
  /// Returns true if arguments should be sign-extended in lib calls.
1715
35.9k
  virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1716
35.9k
    return IsSigned;
1717
35.9k
  }
1718
1719
  /// Returns how the given (atomic) load should be expanded by the
1720
  /// IR-level AtomicExpand pass.
1721
264
  virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const {
1722
264
    return AtomicExpansionKind::None;
1723
264
  }
1724
1725
  /// Returns how the given atomic cmpxchg should be expanded by the IR-level
1726
  /// AtomicExpand pass.
1727
  virtual AtomicExpansionKind
1728
1.31k
  shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
1729
1.31k
    return AtomicExpansionKind::None;
1730
1.31k
  }
1731
1732
  /// Returns how the IR-level AtomicExpand pass should expand the given
1733
  /// AtomicRMW, if at all. Default is to never expand.
1734
788
  virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
1735
788
    return RMW->isFloatingPointOperation() ?
1736
786
      
AtomicExpansionKind::CmpXChg2
: AtomicExpansionKind::None;
1737
788
  }
1738
1739
  /// On some platforms, an AtomicRMW that never actually modifies the value
1740
  /// (such as fetch_add of 0) can be turned into a fence followed by an
1741
  /// atomic load. This may sound useless, but it makes it possible for the
1742
  /// processor to keep the cacheline shared, dramatically improving
1743
  /// performance. And such idempotent RMWs are useful for implementing some
1744
  /// kinds of locks, see for example (justification + benchmarks):
1745
  /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1746
  /// This method tries doing that transformation, returning the atomic load if
1747
  /// it succeeds, and nullptr otherwise.
1748
  /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1749
  /// another round of expansion.
1750
  virtual LoadInst *
1751
0
  lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1752
0
    return nullptr;
1753
0
  }
1754
1755
  /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1756
  /// SIGN_EXTEND, or ANY_EXTEND).
1757
1.55k
  virtual ISD::NodeType getExtendForAtomicOps() const {
1758
1.55k
    return ISD::ZERO_EXTEND;
1759
1.55k
  }
1760
1761
  /// @}
1762
1763
  /// Returns true if we should normalize
1764
  /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1765
  /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1766
  /// that it saves us from materializing N0 and N1 in an integer register.
1767
  /// Targets that are able to perform and/or on flags should return false here.
1768
  virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
1769
36.7k
                                               EVT VT) const {
1770
36.7k
    // If a target has multiple condition registers, then it likely has logical
1771
36.7k
    // operations on those registers.
1772
36.7k
    if (hasMultipleConditionRegisters())
1773
14.9k
      return false;
1774
21.8k
    // Only do the transform if the value won't be split into multiple
1775
21.8k
    // registers.
1776
21.8k
    LegalizeTypeAction Action = getTypeAction(Context, VT);
1777
21.8k
    return Action != TypeExpandInteger && 
Action != TypeExpandFloat21.3k
&&
1778
21.8k
      
Action != TypeSplitVector21.3k
;
1779
21.8k
  }
1780
1781
435
  virtual bool isProfitableToCombineMinNumMaxNum(EVT VT) const { return true; }
1782
1783
  /// Return true if a select of constants (select Cond, C1, C2) should be
1784
  /// transformed into simple math ops with the condition value. For example:
1785
  /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1786
5.96k
  virtual bool convertSelectOfConstantsToMath(EVT VT) const {
1787
5.96k
    return false;
1788
5.96k
  }
1789
1790
  /// Return true if it is profitable to transform an integer
1791
  /// multiplication-by-constant into simpler operations like shifts and adds.
1792
  /// This may be true if the target does not directly support the
1793
  /// multiplication operation for the specified type or the sequence of simpler
1794
  /// ops is faster than the multiply.
1795
38.6k
  virtual bool decomposeMulByConstant(EVT VT, SDValue C) const {
1796
38.6k
    return false;
1797
38.6k
  }
1798
1799
  /// Return true if it is more correct/profitable to use strict FP_TO_INT
1800
  /// conversion operations - canonicalizing the FP source value instead of
1801
  /// converting all cases and then selecting based on value.
1802
  /// This may be true if the target throws exceptions for out of bounds
1803
  /// conversions or has fast FP CMOV.
1804
  virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT,
1805
49
                                        bool IsSigned) const {
1806
49
    return false;
1807
49
  }
1808
1809
  //===--------------------------------------------------------------------===//
1810
  // TargetLowering Configuration Methods - These methods should be invoked by
1811
  // the derived class constructor to configure this object for the target.
1812
  //
1813
protected:
1814
  /// Specify how the target extends the result of integer and floating point
1815
  /// boolean values from i1 to a wider type.  See getBooleanContents.
1816
50.2k
  void setBooleanContents(BooleanContent Ty) {
1817
50.2k
    BooleanContents = Ty;
1818
50.2k
    BooleanFloatContents = Ty;
1819
50.2k
  }
1820
1821
  /// Specify how the target extends the result of integer and floating point
1822
  /// boolean values from i1 to a wider type.  See getBooleanContents.
1823
1.45k
  void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1824
1.45k
    BooleanContents = IntTy;
1825
1.45k
    BooleanFloatContents = FloatTy;
1826
1.45k
  }
1827
1828
  /// Specify how the target extends the result of a vector boolean value from a
1829
  /// vector of i1 to a wider type.  See getBooleanContents.
1830
49.4k
  void setBooleanVectorContents(BooleanContent Ty) {
1831
49.4k
    BooleanVectorContents = Ty;
1832
49.4k
  }
1833
1834
  /// Specify the target scheduling preference.
1835
41.9k
  void setSchedulingPreference(Sched::Preference Pref) {
1836
41.9k
    SchedPreferenceInfo = Pref;
1837
41.9k
  }
1838
1839
  /// Indicate whether this target prefers to use _setjmp to implement
1840
  /// llvm.setjmp or the version without _.  Defaults to false.
1841
16.4k
  void setUseUnderscoreSetJmp(bool Val) {
1842
16.4k
    UseUnderscoreSetJmp = Val;
1843
16.4k
  }
1844
1845
  /// Indicate whether this target prefers to use _longjmp to implement
1846
  /// llvm.longjmp or the version without _.  Defaults to false.
1847
16.4k
  void setUseUnderscoreLongJmp(bool Val) {
1848
16.4k
    UseUnderscoreLongJmp = Val;
1849
16.4k
  }
1850
1851
  /// Indicate the minimum number of blocks to generate jump tables.
1852
  void setMinimumJumpTableEntries(unsigned Val);
1853
1854
  /// Indicate the maximum number of entries in jump tables.
1855
  /// Set to zero to generate unlimited jump tables.
1856
  void setMaximumJumpTableSize(unsigned);
1857
1858
  /// If set to a physical register, this specifies the register that
1859
  /// llvm.savestack/llvm.restorestack should save and restore.
1860
46.5k
  void setStackPointerRegisterToSaveRestore(unsigned R) {
1861
46.5k
    StackPointerRegisterToSaveRestore = R;
1862
46.5k
  }
1863
1864
  /// Tells the code generator that the target has multiple (allocatable)
1865
  /// condition registers that can be used to store the results of comparisons
1866
  /// for use by selects and conditional branches. With multiple condition
1867
  /// registers, the code generator will not aggressively sink comparisons into
1868
  /// the blocks of their users.
1869
4.80k
  void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1870
4.80k
    HasMultipleConditionRegisters = hasManyRegs;
1871
4.80k
  }
1872
1873
  /// Tells the code generator that the target has BitExtract instructions.
1874
  /// The code generator will aggressively sink "shift"s into the blocks of
1875
  /// their users if the users will generate "and" instructions which can be
1876
  /// combined with "shift" to BitExtract instructions.
1877
12.1k
  void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1878
12.1k
    HasExtractBitsInsn = hasExtractInsn;
1879
12.1k
  }
1880
1881
  /// Tells the code generator not to expand logic operations on comparison
1882
  /// predicates into separate sequences that increase the amount of flow
1883
  /// control.
1884
  void setJumpIsExpensive(bool isExpensive = true);
1885
1886
  /// Tells the code generator that this target supports floating point
1887
  /// exceptions and cares about preserving floating point exception behavior.
1888
3.42k
  void setHasFloatingPointExceptions(bool FPExceptions = true) {
1889
3.42k
    HasFloatingPointExceptions = FPExceptions;
1890
3.42k
  }
1891
1892
  /// Tells the code generator which bitwidths to bypass.
1893
1.69k
  void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1894
1.69k
    BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1895
1.69k
  }
1896
1897
  /// Add the specified register class as an available regclass for the
1898
  /// specified value type. This indicates the selector can handle values of
1899
  /// that class natively.
1900
631k
  void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1901
631k
    assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1902
631k
    RegClassForVT[VT.SimpleTy] = RC;
1903
631k
  }
1904
1905
  /// Return the largest legal super-reg register class of the register class
1906
  /// for the specified type and its associated "cost".
1907
  virtual std::pair<const TargetRegisterClass *, uint8_t>
1908
  findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1909
1910
  /// Once all of the register classes are added, this allows us to compute
1911
  /// derived properties we expose.
1912
  void computeRegisterProperties(const TargetRegisterInfo *TRI);
1913
1914
  /// Indicate that the specified operation does not work with the specified
1915
  /// type and indicate what to do about it. Note that VT may refer to either
1916
  /// the type of a result or that of an operand of Op.
1917
  void setOperationAction(unsigned Op, MVT VT,
1918
480M
                          LegalizeAction Action) {
1919
480M
    assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1920
480M
    OpActions[(unsigned)VT.SimpleTy][Op] = Action;
1921
480M
  }
1922
1923
  /// Indicate that the specified load with extension does not work with the
1924
  /// specified type and indicate what to do about it.
1925
  void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1926
938M
                        LegalizeAction Action) {
1927
938M
    assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1928
938M
           MemVT.isValid() && "Table isn't big enough!");
1929
938M
    assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1930
938M
    unsigned Shift = 4 * ExtType;
1931
938M
    LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
1932
938M
    LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
1933
938M
  }
1934
1935
  /// Indicate that the specified truncating store does not work with the
1936
  /// specified type and indicate what to do about it.
1937
  void setTruncStoreAction(MVT ValVT, MVT MemVT,
1938
340M
                           LegalizeAction Action) {
1939
340M
    assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1940
340M
    TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
1941
340M
  }
1942
1943
  /// Indicate that the specified indexed load does or does not work with the
1944
  /// specified type and indicate what to do abort it.
1945
  ///
1946
  /// NOTE: All indexed mode loads are initialized to Expand in
1947
  /// TargetLowering.cpp
1948
  void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1949
24.4M
                            LegalizeAction Action) {
1950
24.4M
    assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1951
24.4M
           (unsigned)Action < 0xf && "Table isn't big enough!");
1952
24.4M
    // Load action are kept in the upper half.
1953
24.4M
    IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1954
24.4M
    IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1955
24.4M
  }
1956
1957
  /// Indicate that the specified indexed store does or does not work with the
1958
  /// specified type and indicate what to do about it.
1959
  ///
1960
  /// NOTE: All indexed mode stores are initialized to Expand in
1961
  /// TargetLowering.cpp
1962
  void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1963
24.4M
                             LegalizeAction Action) {
1964
24.4M
    assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1965
24.4M
           (unsigned)Action < 0xf && "Table isn't big enough!");
1966
24.4M
    // Store action are kept in the lower half.
1967
24.4M
    IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1968
24.4M
    IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1969
24.4M
  }
1970
1971
  /// Indicate that the specified condition code is or isn't supported on the
1972
  /// target and indicate what to do about it.
1973
  void setCondCodeAction(ISD::CondCode CC, MVT VT,
1974
343k
                         LegalizeAction Action) {
1975
343k
    assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1976
343k
           "Table isn't big enough!");
1977
343k
    assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1978
343k
    /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
1979
343k
    /// value and the upper 29 bits index into the second dimension of the array
1980
343k
    /// to select what 32-bit value to use.
1981
343k
    uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1982
343k
    CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
1983
343k
    CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
1984
343k
  }
1985
1986
  /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1987
  /// to trying a larger integer/fp until it can find one that works. If that
1988
  /// default is insufficient, this method can be used by the target to override
1989
  /// the default.
1990
1.82M
  void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1991
1.82M
    PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1992
1.82M
  }
1993
1994
  /// Convenience method to set an operation to Promote and specify the type
1995
  /// in a single call.
1996
236k
  void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1997
236k
    setOperationAction(Opc, OrigVT, Promote);
1998
236k
    AddPromotedToType(Opc, OrigVT, DestVT);
1999
236k
  }
2000
2001
  /// Targets should invoke this method for each target independent node that
2002
  /// they want to provide a custom DAG combiner for by implementing the
2003
  /// PerformDAGCombine virtual method.
2004
1.26M
  void setTargetDAGCombine(ISD::NodeType NT) {
2005
1.26M
    assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
2006
1.26M
    TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
2007
1.26M
  }
2008
2009
  /// Set the target's required jmp_buf buffer size (in bytes); default is 200
2010
0
  void setJumpBufSize(unsigned Size) {
2011
0
    JumpBufSize = Size;
2012
0
  }
2013
2014
  /// Set the target's required jmp_buf buffer alignment (in bytes); default is
2015
  /// 0
2016
0
  void setJumpBufAlignment(unsigned Align) {
2017
0
    JumpBufAlignment = Align;
2018
0
  }
2019
2020
  /// Set the target's minimum function alignment (in log2(bytes))
2021
31.4k
  void setMinFunctionAlignment(unsigned Align) {
2022
31.4k
    MinFunctionAlignment = Align;
2023
31.4k
  }
2024
2025
  /// Set the target's preferred function alignment.  This should be set if
2026
  /// there is a performance benefit to higher-than-minimum alignment (in
2027
  /// log2(bytes))
2028
27.1k
  void setPrefFunctionAlignment(unsigned Align) {
2029
27.1k
    PrefFunctionAlignment = Align;
2030
27.1k
  }
2031
2032
  /// Set the target's preferred loop alignment. Default alignment is zero, it
2033
  /// means the target does not care about loop alignment.  The alignment is
2034
  /// specified in log2(bytes). The target may also override
2035
  /// getPrefLoopAlignment to provide per-loop values.
2036
32.8k
  void setPrefLoopAlignment(unsigned Align) {
2037
32.8k
    PrefLoopAlignment = Align;
2038
32.8k
  }
2039
2040
  /// Set the minimum stack alignment of an argument (in log2(bytes)).
2041
19.7k
  void setMinStackArgumentAlignment(unsigned Align) {
2042
19.7k
    MinStackArgumentAlignment = Align;
2043
19.7k
  }
2044
2045
  /// Set the maximum atomic operation size supported by the
2046
  /// backend. Atomic operations greater than this size (as well as
2047
  /// ones that are not naturally aligned), will be expanded by
2048
  /// AtomicExpandPass into an __atomic_* library call.
2049
1.90k
  void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
2050
1.90k
    MaxAtomicSizeInBitsSupported = SizeInBits;
2051
1.90k
  }
2052
2053
  /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
2054
1.42k
  void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
2055
1.42k
    MinCmpXchgSizeInBits = SizeInBits;
2056
1.42k
  }
2057
2058
  /// Sets whether unaligned atomic operations are supported.
2059
0
  void setSupportsUnalignedAtomics(bool UnalignedSupported) {
2060
0
    SupportsUnalignedAtomics = UnalignedSupported;
2061
0
  }
2062
2063
public:
2064
  //===--------------------------------------------------------------------===//
2065
  // Addressing mode description hooks (used by LSR etc).
2066
  //
2067
2068
  /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
2069
  /// instructions reading the address. This allows as much computation as
2070
  /// possible to be done in the address mode for that operand. This hook lets
2071
  /// targets also pass back when this should be done on intrinsics which
2072
  /// load/store.
2073
  virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
2074
                                    SmallVectorImpl<Value*> &/*Ops*/,
2075
832k
                                    Type *&/*AccessTy*/) const {
2076
832k
    return false;
2077
832k
  }
2078
2079
  /// This represents an addressing mode of:
2080
  ///    BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
2081
  /// If BaseGV is null,  there is no BaseGV.
2082
  /// If BaseOffs is zero, there is no base offset.
2083
  /// If HasBaseReg is false, there is no base register.
2084
  /// If Scale is zero, there is no ScaleReg.  Scale of 1 indicates a reg with
2085
  /// no scale.
2086
  struct AddrMode {
2087
    GlobalValue *BaseGV = nullptr;
2088
    int64_t      BaseOffs = 0;
2089
    bool         HasBaseReg = false;
2090
    int64_t      Scale = 0;
2091
72.9M
    AddrMode() = default;
2092
  };
2093
2094
  /// Return true if the addressing mode represented by AM is legal for this
2095
  /// target, for a load/store of the specified type.
2096
  ///
2097
  /// The type may be VoidTy, in which case only return true if the addressing
2098
  /// mode is legal for a load/store of any legal type.  TODO: Handle
2099
  /// pre/postinc as well.
2100
  ///
2101
  /// If the address space cannot be determined, it will be -1.
2102
  ///
2103
  /// TODO: Remove default argument
2104
  virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
2105
                                     Type *Ty, unsigned AddrSpace,
2106
                                     Instruction *I = nullptr) const;
2107
2108
  /// Return the cost of the scaling factor used in the addressing mode
2109
  /// represented by AM for this target, for a load/store of the specified type.
2110
  ///
2111
  /// If the AM is supported, the return value must be >= 0.
2112
  /// If the AM is not supported, it returns a negative value.
2113
  /// TODO: Handle pre/postinc as well.
2114
  /// TODO: Remove default argument
2115
  virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
2116
8.27k
                                   Type *Ty, unsigned AS = 0) const {
2117
8.27k
    // Default: assume that any scaling factor used in a legal AM is free.
2118
8.27k
    if (isLegalAddressingMode(DL, AM, Ty, AS))
2119
8.27k
      return 0;
2120
0
    return -1;
2121
0
  }
2122
2123
  /// Return true if the specified immediate is legal icmp immediate, that is
2124
  /// the target has icmp instructions which can compare a register against the
2125
  /// immediate without having to materialize the immediate into a register.
2126
19.6k
  virtual bool isLegalICmpImmediate(int64_t) const {
2127
19.6k
    return true;
2128
19.6k
  }
2129
2130
  /// Return true if the specified immediate is legal add immediate, that is the
2131
  /// target has add instructions which can add a register with the immediate
2132
  /// without having to materialize the immediate into a register.
2133
1.88k
  virtual bool isLegalAddImmediate(int64_t) const {
2134
1.88k
    return true;
2135
1.88k
  }
2136
2137
  /// Return true if the specified immediate is legal for the value input of a
2138
  /// store instruction.
2139
2.17k
  virtual bool isLegalStoreImmediate(int64_t Value) const {
2140
2.17k
    // Default implementation assumes that at least 0 works since it is likely
2141
2.17k
    // that a zero register exists or a zero immediate is allowed.
2142
2.17k
    return Value == 0;
2143
2.17k
  }
2144
2145
  /// Return true if it's significantly cheaper to shift a vector by a uniform
2146
  /// scalar than by an amount which will vary across each lane. On x86, for
2147
  /// example, there is a "psllw" instruction for the former case, but no simple
2148
  /// instruction for a general "a << b" operation on vectors.
2149
179k
  virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
2150
179k
    return false;
2151
179k
  }
2152
2153
  /// Returns true if the opcode is a commutative binary operation.
2154
82.3M
  virtual bool isCommutativeBinOp(unsigned Opcode) const {
2155
82.3M
    // FIXME: This should get its info from the td file.
2156
82.3M
    switch (Opcode) {
2157
82.3M
    case ISD::ADD:
2158
12.9M
    case ISD::SMIN:
2159
12.9M
    case ISD::SMAX:
2160
12.9M
    case ISD::UMIN:
2161
12.9M
    case ISD::UMAX:
2162
12.9M
    case ISD::MUL:
2163
12.9M
    case ISD::MULHU:
2164
12.9M
    case ISD::MULHS:
2165
12.9M
    case ISD::SMUL_LOHI:
2166
12.9M
    case ISD::UMUL_LOHI:
2167
12.9M
    case ISD::FADD:
2168
12.9M
    case ISD::FMUL:
2169
12.9M
    case ISD::AND:
2170
12.9M
    case ISD::OR:
2171
12.9M
    case ISD::XOR:
2172
12.9M
    case ISD::SADDO:
2173
12.9M
    case ISD::UADDO:
2174
12.9M
    case ISD::ADDC:
2175
12.9M
    case ISD::ADDE:
2176
12.9M
    case ISD::SADDSAT:
2177
12.9M
    case ISD::UADDSAT:
2178
12.9M
    case ISD::FMINNUM:
2179
12.9M
    case ISD::FMAXNUM:
2180
12.9M
    case ISD::FMINIMUM:
2181
12.9M
    case ISD::FMAXIMUM:
2182
12.9M
      return true;
2183
69.4M
    default: return false;
2184
82.3M
    }
2185
82.3M
  }
2186
2187
  /// Return true if it's free to truncate a value of type FromTy to type
2188
  /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
2189
  /// by referencing its sub-register AX.
2190
  /// Targets must return false when FromTy <= ToTy.
2191
229
  virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
2192
229
    return false;
2193
229
  }
2194
2195
  /// Return true if a truncation from FromTy to ToTy is permitted when deciding
2196
  /// whether a call is in tail position. Typically this means that both results
2197
  /// would be assigned to the same register or stack slot, but it could mean
2198
  /// the target performs adequate checks of its own before proceeding with the
2199
  /// tail call.  Targets must return false when FromTy <= ToTy.
2200
5
  virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
2201
5
    return false;
2202
5
  }
2203
2204
14.6k
  virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
2205
14.6k
    return false;
2206
14.6k
  }
2207
2208
41.9k
  virtual bool isProfitableToHoist(Instruction *I) const { return true; }
2209
2210
  /// Return true if the extension represented by \p I is free.
2211
  /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2212
  /// this method can use the context provided by \p I to decide
2213
  /// whether or not \p I is free.
2214
  /// This method extends the behavior of the is[Z|FP]ExtFree family.
2215
  /// In other words, if is[Z|FP]Free returns true, then this method
2216
  /// returns true as well. The converse is not true.
2217
  /// The target can perform the adequate checks by overriding isExtFreeImpl.
2218
  /// \pre \p I must be a sign, zero, or fp extension.
2219
1.81M
  bool isExtFree(const Instruction *I) const {
2220
1.81M
    switch (I->getOpcode()) {
2221
1.81M
    case Instruction::FPExt:
2222
73.0k
      if (isFPExtFree(EVT::getEVT(I->getType()),
2223
73.0k
                      EVT::getEVT(I->getOperand(0)->getType())))
2224
6
        return true;
2225
73.0k
      break;
2226
724k
    case Instruction::ZExt:
2227
724k
      if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2228
338k
        return true;
2229
385k
      break;
2230
1.01M
    case Instruction::SExt:
2231
1.01M
      break;
2232
385k
    default:
2233
0
      llvm_unreachable("Instruction is not an extension");
2234
1.47M
    }
2235
1.47M
    return isExtFreeImpl(I);
2236
1.47M
  }
2237
2238
  /// Return true if \p Load and \p Ext can form an ExtLoad.
2239
  /// For example, in AArch64
2240
  ///   %L = load i8, i8* %ptr
2241
  ///   %E = zext i8 %L to i32
2242
  /// can be lowered into one load instruction
2243
  ///   ldrb w0, [x0]
2244
  bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2245
593k
                 const DataLayout &DL) const {
2246
593k
    EVT VT = getValueType(DL, Ext->getType());
2247
593k
    EVT LoadVT = getValueType(DL, Load->getType());
2248
593k
2249
593k
    // If the load has other users and the truncate is not free, the ext
2250
593k
    // probably isn't free.
2251
593k
    if (!Load->hasOneUse() && 
(226k
isTypeLegal(LoadVT)226k
||
!isTypeLegal(VT)115k
) &&
2252
593k
        
!isTruncateFree(Ext->getType(), Load->getType())112k
)
2253
369
      return false;
2254
593k
2255
593k
    // Check whether the target supports casts folded into loads.
2256
593k
    unsigned LType;
2257
593k
    if (isa<ZExtInst>(Ext))
2258
260k
      LType = ISD::ZEXTLOAD;
2259
332k
    else {
2260
332k
      assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
2261
332k
      LType = ISD::SEXTLOAD;
2262
332k
    }
2263
593k
2264
593k
    return isLoadExtLegal(LType, VT, LoadVT);
2265
593k
  }
2266
2267
  /// Return true if any actual instruction that defines a value of type FromTy
2268
  /// implicitly zero-extends the value to ToTy in the result register.
2269
  ///
2270
  /// The function should return true when it is likely that the truncate can
2271
  /// be freely folded with an instruction defining a value of FromTy. If
2272
  /// the defining instruction is unknown (because you're looking at a
2273
  /// function argument, PHI, etc.) then the target may require an
2274
  /// explicit truncate, which is not necessarily free, but this function
2275
  /// does not deal with those cases.
2276
  /// Targets must return false when FromTy >= ToTy.
2277
30.1k
  virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2278
30.1k
    return false;
2279
30.1k
  }
2280
2281
32.5k
  virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2282
32.5k
    return false;
2283
32.5k
  }
2284
2285
  /// Return true if sign-extension from FromTy to ToTy is cheaper than
2286
  /// zero-extension.
2287
167k
  virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const {
2288
167k
    return false;
2289
167k
  }
2290
2291
  /// Return true if sinking I's operands to the same basic block as I is
2292
  /// profitable, e.g. because the operands can be folded into a target
2293
  /// instruction during instruction selection. After calling the function
2294
  /// \p Ops contains the Uses to sink ordered by dominance (dominating users
2295
  /// come first).
2296
  virtual bool shouldSinkOperands(Instruction *I,
2297
2.03M
                                  SmallVectorImpl<Use *> &Ops) const {
2298
2.03M
    return false;
2299
2.03M
  }
2300
2301
  /// Return true if the target supplies and combines to a paired load
2302
  /// two loaded values of type LoadedType next to each other in memory.
2303
  /// RequiredAlignment gives the minimal alignment constraints that must be met
2304
  /// to be able to select this paired load.
2305
  ///
2306
  /// This information is *not* used to generate actual paired loads, but it is
2307
  /// used to generate a sequence of loads that is easier to combine into a
2308
  /// paired load.
2309
  /// For instance, something like this:
2310
  /// a = load i64* addr
2311
  /// b = trunc i64 a to i32
2312
  /// c = lshr i64 a, 32
2313
  /// d = trunc i64 c to i32
2314
  /// will be optimized into:
2315
  /// b = load i32* addr1
2316
  /// d = load i32* addr2
2317
  /// Where addr1 = addr2 +/- sizeof(i32).
2318
  ///
2319
  /// In other words, unless the target performs a post-isel load combining,
2320
  /// this information should not be provided because it will generate more
2321
  /// loads.
2322
  virtual bool hasPairedLoad(EVT /*LoadedType*/,
2323
13.4k
                             unsigned & /*RequiredAlignment*/) const {
2324
13.4k
    return false;
2325
13.4k
  }
2326
2327
  /// Return true if the target has a vector blend instruction.
2328
37.3k
  virtual bool hasVectorBlend() const { return false; }
2329
2330
  /// Get the maximum supported factor for interleaved memory accesses.
2331
  /// Default to be the minimum interleave factor: 2.
2332
0
  virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2333
2334
  /// Lower an interleaved load to target specific intrinsics. Return
2335
  /// true on success.
2336
  ///
2337
  /// \p LI is the vector load instruction.
2338
  /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2339
  /// \p Indices is the corresponding indices for each shufflevector.
2340
  /// \p Factor is the interleave factor.
2341
  virtual bool lowerInterleavedLoad(LoadInst *LI,
2342
                                    ArrayRef<ShuffleVectorInst *> Shuffles,
2343
                                    ArrayRef<unsigned> Indices,
2344
0
                                    unsigned Factor) const {
2345
0
    return false;
2346
0
  }
2347
2348
  /// Lower an interleaved store to target specific intrinsics. Return
2349
  /// true on success.
2350
  ///
2351
  /// \p SI is the vector store instruction.
2352
  /// \p SVI is the shufflevector to RE-interleave the stored vector.
2353
  /// \p Factor is the interleave factor.
2354
  virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
2355
0
                                     unsigned Factor) const {
2356
0
    return false;
2357
0
  }
2358
2359
  /// Return true if zero-extending the specific node Val to type VT2 is free
2360
  /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2361
  /// because it's folded such as X86 zero-extending loads).
2362
14.7k
  virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2363
14.7k
    return isZExtFree(Val.getValueType(), VT2);
2364
14.7k
  }
2365
2366
  /// Return true if an fpext operation is free (for instance, because
2367
  /// single-precision floating-point numbers are implicitly extended to
2368
  /// double-precision).
2369
73.6k
  virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2370
73.6k
    assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2371
73.6k
           "invalid fpext types");
2372
73.6k
    return false;
2373
73.6k
  }
2374
2375
  /// Return true if an fpext operation input to an \p Opcode operation is free
2376
  /// (for instance, because half-precision floating-point numbers are
2377
  /// implicitly extended to float-precision) for an FMA instruction.
2378
44
  virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
2379
44
    assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2380
44
           "invalid fpext types");
2381
44
    return isFPExtFree(DestVT, SrcVT);
2382
44
  }
2383
2384
  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2385
  /// extend node) is profitable.
2386
7.81k
  virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2387
2388
  /// Return true if an fneg operation is free to the point where it is never
2389
  /// worthwhile to replace it with a bitwise operation.
2390
4.17k
  virtual bool isFNegFree(EVT VT) const {
2391
4.17k
    assert(VT.isFloatingPoint());
2392
4.17k
    return false;
2393
4.17k
  }
2394
2395
  /// Return true if an fabs operation is free to the point where it is never
2396
  /// worthwhile to replace it with a bitwise operation.
2397
5.06k
  virtual bool isFAbsFree(EVT VT) const {
2398
5.06k
    assert(VT.isFloatingPoint());
2399
5.06k
    return false;
2400
5.06k
  }
2401
2402
  /// Return true if an FMA operation is faster than a pair of fmul and fadd
2403
  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2404
  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2405
  ///
2406
  /// NOTE: This may be called before legalization on types for which FMAs are
2407
  /// not legal, but should return true if those types will eventually legalize
2408
  /// to types that support FMAs. After legalization, it will only be called on
2409
  /// types that support FMAs (via Legal or Custom actions)
2410
4.94k
  virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
2411
4.94k
    return false;
2412
4.94k
  }
2413
2414
  /// Return true if it's profitable to narrow operations of type VT1 to
2415
  /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2416
  /// i32 to i16.
2417
4.90k
  virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2418
4.90k
    return false;
2419
4.90k
  }
2420
2421
  /// Return true if it is beneficial to convert a load of a constant to
2422
  /// just the constant itself.
2423
  /// On some targets it might be more efficient to use a combination of
2424
  /// arithmetic instructions to materialize the constant instead of loading it
2425
  /// from a constant pool.
2426
  virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2427
10
                                                 Type *Ty) const {
2428
10
    return false;
2429
10
  }
2430
2431
  /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2432
  /// from this source type with this index. This is needed because
2433
  /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2434
  /// the first element, and only the target knows which lowering is cheap.
2435
  virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2436
89
                                       unsigned Index) const {
2437
89
    return false;
2438
89
  }
2439
2440
  /// Try to convert an extract element of a vector binary operation into an
2441
  /// extract element followed by a scalar operation.
2442
520
  virtual bool shouldScalarizeBinop(SDValue VecOp) const {
2443
520
    return false;
2444
520
  }
2445
2446
  /// Try to convert math with an overflow comparison into the corresponding DAG
2447
  /// node operation. Targets may want to override this independently of whether
2448
  /// the operation is legal/custom for the given type because it may obscure
2449
  /// matching of other patterns.
2450
16.3k
  virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT) const {
2451
16.3k
    // TODO: The default logic is inherited from code in CodeGenPrepare.
2452
16.3k
    // The opcode should not make a difference by default?
2453
16.3k
    if (Opcode != ISD::UADDO)
2454
14.0k
      return false;
2455
2.34k
2456
2.34k
    // Allow the transform as long as we have an integer type that is not
2457
2.34k
    // obviously illegal and unsupported.
2458
2.34k
    if (VT.isVector())
2459
16
      return false;
2460
2.32k
    return VT.isSimple() || 
!isOperationExpand(Opcode, VT)0
;
2461
2.32k
  }
2462
2463
  // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2464
  // even if the vector itself has multiple uses.
2465
704
  virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2466
704
    return false;
2467
704
  }
2468
2469
  // Return true if CodeGenPrepare should consider splitting large offset of a
2470
  // GEP to make the GEP fit into the addressing mode and can be sunk into the
2471
  // same blocks of its users.
2472
3.39k
  virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
2473
2474
  //===--------------------------------------------------------------------===//
2475
  // Runtime Library hooks
2476
  //
2477
2478
  /// Rename the default libcall routine name for the specified libcall.
2479
25.8M
  void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2480
25.8M
    LibcallRoutineNames[Call] = Name;
2481
25.8M
  }
2482
2483
  /// Get the libcall routine name for the specified libcall.
2484
90.8k
  const char *getLibcallName(RTLIB::Libcall Call) const {
2485
90.8k
    return LibcallRoutineNames[Call];
2486
90.8k
  }
2487
2488
  /// Override the default CondCode to be used to test the result of the
2489
  /// comparison libcall against zero.
2490
77.7k
  void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
2491
77.7k
    CmpLibcallCCs[Call] = CC;
2492
77.7k
  }
2493
2494
  /// Get the CondCode that's to be used to test the result of the comparison
2495
  /// libcall against zero.
2496
1.15k
  ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
2497
1.15k
    return CmpLibcallCCs[Call];
2498
1.15k
  }
2499
2500
  /// Set the CallingConv that should be used for the specified libcall.
2501
26.3M
  void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
2502
26.3M
    LibcallCallingConvs[Call] = CC;
2503
26.3M
  }
2504
2505
  /// Get the CallingConv that should be used for the specified libcall.
2506
16.3k
  CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
2507
16.3k
    return LibcallCallingConvs[Call];
2508
16.3k
  }
2509
2510
  /// Execute target specific actions to finalize target lowering.
2511
  /// This is used to set extra flags in MachineFrameInformation and freezing
2512
  /// the set of reserved registers.
2513
  /// The default implementation just freezes the set of reserved registers.
2514
  virtual void finalizeLowering(MachineFunction &MF) const;
2515
2516
private:
2517
  const TargetMachine &TM;
2518
2519
  /// Tells the code generator that the target has multiple (allocatable)
2520
  /// condition registers that can be used to store the results of comparisons
2521
  /// for use by selects and conditional branches. With multiple condition
2522
  /// registers, the code generator will not aggressively sink comparisons into
2523
  /// the blocks of their users.
2524
  bool HasMultipleConditionRegisters;
2525
2526
  /// Tells the code generator that the target has BitExtract instructions.
2527
  /// The code generator will aggressively sink "shift"s into the blocks of
2528
  /// their users if the users will generate "and" instructions which can be
2529
  /// combined with "shift" to BitExtract instructions.
2530
  bool HasExtractBitsInsn;
2531
2532
  /// Tells the code generator to bypass slow divide or remainder
2533
  /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2534
  /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2535
  /// div/rem when the operands are positive and less than 256.
2536
  DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
2537
2538
  /// Tells the code generator that it shouldn't generate extra flow control
2539
  /// instructions and should attempt to combine flow control instructions via
2540
  /// predication.
2541
  bool JumpIsExpensive;
2542
2543
  /// Whether the target supports or cares about preserving floating point
2544
  /// exception behavior.
2545
  bool HasFloatingPointExceptions;
2546
2547
  /// This target prefers to use _setjmp to implement llvm.setjmp.
2548
  ///
2549
  /// Defaults to false.
2550
  bool UseUnderscoreSetJmp;
2551
2552
  /// This target prefers to use _longjmp to implement llvm.longjmp.
2553
  ///
2554
  /// Defaults to false.
2555
  bool UseUnderscoreLongJmp;
2556
2557
  /// Information about the contents of the high-bits in boolean values held in
2558
  /// a type wider than i1. See getBooleanContents.
2559
  BooleanContent BooleanContents;
2560
2561
  /// Information about the contents of the high-bits in boolean values held in
2562
  /// a type wider than i1. See getBooleanContents.
2563
  BooleanContent BooleanFloatContents;
2564
2565
  /// Information about the contents of the high-bits in boolean vector values
2566
  /// when the element type is wider than i1. See getBooleanContents.
2567
  BooleanContent BooleanVectorContents;
2568
2569
  /// The target scheduling preference: shortest possible total cycles or lowest
2570
  /// register usage.
2571
  Sched::Preference SchedPreferenceInfo;
2572
2573
  /// The size, in bytes, of the target's jmp_buf buffers
2574
  unsigned JumpBufSize;
2575
2576
  /// The alignment, in bytes, of the target's jmp_buf buffers
2577
  unsigned JumpBufAlignment;
2578
2579
  /// The minimum alignment that any argument on the stack needs to have.
2580
  unsigned MinStackArgumentAlignment;
2581
2582
  /// The minimum function alignment (used when optimizing for size, and to
2583
  /// prevent explicitly provided alignment from leading to incorrect code).
2584
  unsigned MinFunctionAlignment;
2585
2586
  /// The preferred function alignment (used when alignment unspecified and
2587
  /// optimizing for speed).
2588
  unsigned PrefFunctionAlignment;
2589
2590
  /// The preferred loop alignment.
2591
  unsigned PrefLoopAlignment;
2592
2593
  /// Size in bits of the maximum atomics size the backend supports.
2594
  /// Accesses larger than this will be expanded by AtomicExpandPass.
2595
  unsigned MaxAtomicSizeInBitsSupported;
2596
2597
  /// Size in bits of the minimum cmpxchg or ll/sc operation the
2598
  /// backend supports.
2599
  unsigned MinCmpXchgSizeInBits;
2600
2601
  /// This indicates if the target supports unaligned atomic operations.
2602
  bool SupportsUnalignedAtomics;
2603
2604
  /// If set to a physical register, this specifies the register that
2605
  /// llvm.savestack/llvm.restorestack should save and restore.
2606
  unsigned StackPointerRegisterToSaveRestore;
2607
2608
  /// This indicates the default register class to use for each ValueType the
2609
  /// target supports natively.
2610
  const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2611
  unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
2612
  MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2613
2614
  /// This indicates the "representative" register class to use for each
2615
  /// ValueType the target supports natively. This information is used by the
2616
  /// scheduler to track register pressure. By default, the representative
2617
  /// register class is the largest legal super-reg register class of the
2618
  /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2619
  /// representative class would be GR32.
2620
  const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2621
2622
  /// This indicates the "cost" of the "representative" register class for each
2623
  /// ValueType. The cost is used by the scheduler to approximate register
2624
  /// pressure.
2625
  uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2626
2627
  /// For any value types we are promoting or expanding, this contains the value
2628
  /// type that we are changing to.  For Expanded types, this contains one step
2629
  /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2630
  /// (e.g. i64 -> i16).  For types natively supported by the system, this holds
2631
  /// the same type (e.g. i32 -> i32).
2632
  MVT TransformToType[MVT::LAST_VALUETYPE];
2633
2634
  /// For each operation and each value type, keep a LegalizeAction that
2635
  /// indicates how instruction selection should deal with the operation.  Most
2636
  /// operations are Legal (aka, supported natively by the target), but
2637
  /// operations that are not should be described.  Note that operations on
2638
  /// non-legal value types are not described here.
2639
  LegalizeAction OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
2640
2641
  /// For each load extension type and each value type, keep a LegalizeAction
2642
  /// that indicates how instruction selection should deal with a load of a
2643
  /// specific value type and extension type. Uses 4-bits to store the action
2644
  /// for each of the 4 load ext types.
2645
  uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2646
2647
  /// For each value type pair keep a LegalizeAction that indicates whether a
2648
  /// truncating store of a specific value type and truncating type is legal.
2649
  LegalizeAction TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2650
2651
  /// For each indexed mode and each value type, keep a pair of LegalizeAction
2652
  /// that indicates how instruction selection should deal with the load /
2653
  /// store.
2654
  ///
2655
  /// The first dimension is the value_type for the reference. The second
2656
  /// dimension represents the various modes for load store.
2657
  uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2658
2659
  /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2660
  /// indicates how instruction selection should deal with the condition code.
2661
  ///
2662
  /// Because each CC action takes up 4 bits, we need to have the array size be
2663
  /// large enough to fit all of the value types. This can be done by rounding
2664
  /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2665
  uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2666
2667
protected:
2668
  ValueTypeActionImpl ValueTypeActions;
2669
2670
private:
2671
  LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2672
2673
  /// Targets can specify ISD nodes that they would like PerformDAGCombine
2674
  /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2675
  /// array.
2676
  unsigned char
2677
  TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2678
2679
  /// For operations that must be promoted to a specific type, this holds the
2680
  /// destination type.  This map should be sparse, so don't hold it as an
2681
  /// array.
2682
  ///
2683
  /// Targets add entries to this map with AddPromotedToType(..), clients access
2684
  /// this with getTypeToPromoteTo(..).
2685
  std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2686
    PromoteToType;
2687
2688
  /// Stores the name each libcall.
2689
  const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
2690
2691
  /// The ISD::CondCode that should be used to test the result of each of the
2692
  /// comparison libcall against zero.
2693
  ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2694
2695
  /// Stores the CallingConv that should be used for each libcall.
2696
  CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2697
2698
  /// Set default libcall names and calling conventions.
2699
  void InitLibcalls(const Triple &TT);
2700
2701
protected:
2702
  /// Return true if the extension represented by \p I is free.
2703
  /// \pre \p I is a sign, zero, or fp extension and
2704
  ///      is[Z|FP]ExtFree of the related types is not true.
2705
128k
  virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2706
2707
  /// Depth that GatherAllAliases should should continue looking for chain
2708
  /// dependencies when trying to find a more preferable chain. As an
2709
  /// approximation, this should be more than the number of consecutive stores
2710
  /// expected to be merged.
2711
  unsigned GatherAllAliasesMaxDepth;
2712
2713
  /// Specify maximum number of store instructions per memset call.
2714
  ///
2715
  /// When lowering \@llvm.memset this field specifies the maximum number of
2716
  /// store operations that may be substituted for the call to memset. Targets
2717
  /// must set this value based on the cost threshold for that target. Targets
2718
  /// should assume that the memset will be done using as many of the largest
2719
  /// store operations first, followed by smaller ones, if necessary, per
2720
  /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2721
  /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2722
  /// store.  This only applies to setting a constant array of a constant size.
2723
  unsigned MaxStoresPerMemset;
2724
2725
  /// Maximum number of stores operations that may be substituted for the call
2726
  /// to memset, used for functions with OptSize attribute.
2727
  unsigned MaxStoresPerMemsetOptSize;
2728
2729
  /// Specify maximum bytes of store instructions per memcpy call.
2730
  ///
2731
  /// When lowering \@llvm.memcpy this field specifies the maximum number of
2732
  /// store operations that may be substituted for a call to memcpy. Targets
2733
  /// must set this value based on the cost threshold for that target. Targets
2734
  /// should assume that the memcpy will be done using as many of the largest
2735
  /// store operations first, followed by smaller ones, if necessary, per
2736
  /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2737
  /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2738
  /// and one 1-byte store. This only applies to copying a constant array of
2739
  /// constant size.
2740
  unsigned MaxStoresPerMemcpy;
2741
2742
2743
  /// \brief Specify max number of store instructions to glue in inlined memcpy.
2744
  ///
2745
  /// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number
2746
  /// of store instructions to keep together. This helps in pairing and
2747
  //  vectorization later on.
2748
  unsigned MaxGluedStoresPerMemcpy = 0;
2749
2750
  /// Maximum number of store operations that may be substituted for a call to
2751
  /// memcpy, used for functions with OptSize attribute.
2752
  unsigned MaxStoresPerMemcpyOptSize;
2753
  unsigned MaxLoadsPerMemcmp;
2754
  unsigned MaxLoadsPerMemcmpOptSize;
2755
2756
  /// Specify maximum bytes of store instructions per memmove call.
2757
  ///
2758
  /// When lowering \@llvm.memmove this field specifies the maximum number of
2759
  /// store instructions that may be substituted for a call to memmove. Targets
2760
  /// must set this value based on the cost threshold for that target. Targets
2761
  /// should assume that the memmove will be done using as many of the largest
2762
  /// store operations first, followed by smaller ones, if necessary, per
2763
  /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2764
  /// with 8-bit alignment would result in nine 1-byte stores.  This only
2765
  /// applies to copying a constant array of constant size.
2766
  unsigned MaxStoresPerMemmove;
2767
2768
  /// Maximum number of store instructions that may be substituted for a call to
2769
  /// memmove, used for functions with OptSize attribute.
2770
  unsigned MaxStoresPerMemmoveOptSize;
2771
2772
  /// Tells the code generator that select is more expensive than a branch if
2773
  /// the branch is usually predicted right.
2774
  bool PredictableSelectIsExpensive;
2775
2776
  /// \see enableExtLdPromotion.
2777
  bool EnableExtLdPromotion;
2778
2779
  /// Return true if the value types that can be represented by the specified
2780
  /// register class are all legal.
2781
  bool isLegalRC(const TargetRegisterInfo &TRI,
2782
                 const TargetRegisterClass &RC) const;
2783
2784
  /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2785
  /// sequence of memory operands that is recognized by PrologEpilogInserter.
2786
  MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2787
                                    MachineBasicBlock *MBB) const;
2788
2789
  /// Replace/modify the XRay custom event operands with target-dependent
2790
  /// details.
2791
  MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
2792
                                         MachineBasicBlock *MBB) const;
2793
2794
  /// Replace/modify the XRay typed event operands with target-dependent
2795
  /// details.
2796
  MachineBasicBlock *emitXRayTypedEvent(MachineInstr &MI,
2797
                                        MachineBasicBlock *MBB) const;
2798
};
2799
2800
/// This class defines information used to lower LLVM code to legal SelectionDAG
2801
/// operators that the target instruction selector can accept natively.
2802
///
2803
/// This class also defines callbacks that targets must implement to lower
2804
/// target-specific constructs to SelectionDAG operators.
2805
class TargetLowering : public TargetLoweringBase {
2806
public:
2807
  struct DAGCombinerInfo;
2808
2809
  TargetLowering(const TargetLowering &) = delete;
2810
  TargetLowering &operator=(const TargetLowering &) = delete;
2811
2812
  /// NOTE: The TargetMachine owns TLOF.
2813
  explicit TargetLowering(const TargetMachine &TM);
2814
2815
  bool isPositionIndependent() const;
2816
2817
  virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
2818
                                          FunctionLoweringInfo *FLI,
2819
36.0M
                                          LegacyDivergenceAnalysis *DA) const {
2820
36.0M
    return false;
2821
36.0M
  }
2822
2823
30.3M
  virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
2824
30.3M
    return false;
2825
30.3M
  }
2826
2827
  /// Returns true by value, base pointer and offset pointer and addressing mode
2828
  /// by reference if the node's address can be legally represented as
2829
  /// pre-indexed load / store address.
2830
  virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2831
                                         SDValue &/*Offset*/,
2832
                                         ISD::MemIndexedMode &/*AM*/,
2833
0
                                         SelectionDAG &/*DAG*/) const {
2834
0
    return false;
2835
0
  }
2836
2837
  /// Returns true by value, base pointer and offset pointer and addressing mode
2838
  /// by reference if this node can be combined with a load / store to form a
2839
  /// post-indexed load / store.
2840
  virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2841
                                          SDValue &/*Base*/,
2842
                                          SDValue &/*Offset*/,
2843
                                          ISD::MemIndexedMode &/*AM*/,
2844
0
                                          SelectionDAG &/*DAG*/) const {
2845
0
    return false;
2846
0
  }
2847
2848
  /// Return the entry encoding for a jump table in the current function.  The
2849
  /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2850
  virtual unsigned getJumpTableEncoding() const;
2851
2852
  virtual const MCExpr *
2853
  LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
2854
                            const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2855
0
                            MCContext &/*Ctx*/) const {
2856
0
    llvm_unreachable("Need to implement this hook if target has custom JTIs");
2857
0
  }
2858
2859
  /// Returns relocation base for the given PIC jumptable.
2860
  virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2861
                                           SelectionDAG &DAG) const;
2862
2863
  /// This returns the relocation base for the given PIC jumptable, the same as
2864
  /// getPICJumpTableRelocBase, but as an MCExpr.
2865
  virtual const MCExpr *
2866
  getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2867
                               unsigned JTI, MCContext &Ctx) const;
2868
2869
  /// Return true if folding a constant offset with the given GlobalAddress is
2870
  /// legal.  It is frequently not legal in PIC relocation models.
2871
  virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2872
2873
  bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2874
                            SDValue &Chain) const;
2875
2876
  void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
2877
                           SDValue &NewRHS, ISD::CondCode &CCCode,
2878
                           const SDLoc &DL) const;
2879
2880
  /// Returns a pair of (return value, chain).
2881
  /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2882
  std::pair<SDValue, SDValue> makeLibCall(
2883
      SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef<SDValue> Ops,
2884
      bool isSigned, const SDLoc &dl, bool doesNotReturn = false,
2885
      bool isReturnValueUsed = true, bool isPostTypeLegalization = false) const;
2886
2887
  /// Check whether parameters to a call that are passed in callee saved
2888
  /// registers are the same as from the calling function.  This needs to be
2889
  /// checked for tail call eligibility.
2890
  bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
2891
      const uint32_t *CallerPreservedMask,
2892
      const SmallVectorImpl<CCValAssign> &ArgLocs,
2893
      const SmallVectorImpl<SDValue> &OutVals) const;
2894
2895
  //===--------------------------------------------------------------------===//
2896
  // TargetLowering Optimization Methods
2897
  //
2898
2899
  /// A convenience struct that encapsulates a DAG, and two SDValues for
2900
  /// returning information from TargetLowering to its clients that want to
2901
  /// combine.
2902
  struct TargetLoweringOpt {
2903
    SelectionDAG &DAG;
2904
    bool LegalTys;
2905
    bool LegalOps;
2906
    SDValue Old;
2907
    SDValue New;
2908
2909
    explicit TargetLoweringOpt(SelectionDAG &InDAG,
2910
                               bool LT, bool LO) :
2911
6.70M
      DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2912
2913
126k
    bool LegalTypes() const { return LegalTys; }
2914
158k
    bool LegalOperations() const { return LegalOps; }
2915
2916
340k
    bool CombineTo(SDValue O, SDValue N) {
2917
340k
      Old = O;
2918
340k
      New = N;
2919
340k
      return true;
2920
340k
    }
2921
  };
2922
2923
  /// Check to see if the specified operand of the specified instruction is a
2924
  /// constant integer.  If so, check to see if there are any bits set in the
2925
  /// constant that are not demanded.  If so, shrink the constant and return
2926
  /// true.
2927
  bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2928
                              TargetLoweringOpt &TLO) const;
2929
2930
  // Target hook to do target-specific const optimization, which is called by
2931
  // ShrinkDemandedConstant. This function should return true if the target
2932
  // doesn't want ShrinkDemandedConstant to further optimize the constant.
2933
  virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2934
303k
                                            TargetLoweringOpt &TLO) const {
2935
303k
    return false;
2936
303k
  }
2937
2938
  /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.  This
2939
  /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2940
  /// generalized for targets with other types of implicit widening casts.
2941
  bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2942
                        TargetLoweringOpt &TLO) const;
2943
2944
  /// Look at Op.  At this point, we know that only the DemandedBits bits of the
2945
  /// result of Op are ever used downstream.  If we can use this information to
2946
  /// simplify Op, create a new simplified DAG node and return true, returning
2947
  /// the original and new nodes in Old and New.  Otherwise, analyze the
2948
  /// expression and return a mask of KnownOne and KnownZero bits for the
2949
  /// expression (used to simplify the caller).  The KnownZero/One bits may only
2950
  /// be accurate for those bits in the Demanded masks.
2951
  /// \p AssumeSingleUse When this parameter is true, this function will
2952
  ///    attempt to simplify \p Op even if there are multiple uses.
2953
  ///    Callers are responsible for correctly updating the DAG based on the
2954
  ///    results of this function, because simply replacing replacing TLO.Old
2955
  ///    with TLO.New will be incorrect when this parameter is true and TLO.Old
2956
  ///    has multiple uses.
2957
  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
2958
                            const APInt &DemandedElts, KnownBits &Known,
2959
                            TargetLoweringOpt &TLO, unsigned Depth = 0,
2960
                            bool AssumeSingleUse = false) const;
2961
2962
  /// Helper wrapper around SimplifyDemandedBits, demanding all elements.
2963
  /// Adds Op back to the worklist upon success.
2964
  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
2965
                            KnownBits &Known, TargetLoweringOpt &TLO,
2966
                            unsigned Depth = 0,
2967
                            bool AssumeSingleUse = false) const;
2968
2969
  /// Helper wrapper around SimplifyDemandedBits.
2970
  /// Adds Op back to the worklist upon success.
2971
  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2972
                            DAGCombinerInfo &DCI) const;
2973
2974
  /// Look at Vector Op. At this point, we know that only the DemandedElts
2975
  /// elements of the result of Op are ever used downstream.  If we can use
2976
  /// this information to simplify Op, create a new simplified DAG node and
2977
  /// return true, storing the original and new nodes in TLO.
2978
  /// Otherwise, analyze the expression and return a mask of KnownUndef and
2979
  /// KnownZero elements for the expression (used to simplify the caller).
2980
  /// The KnownUndef/Zero elements may only be accurate for those bits
2981
  /// in the DemandedMask.
2982
  /// \p AssumeSingleUse When this parameter is true, this function will
2983
  ///    attempt to simplify \p Op even if there are multiple uses.
2984
  ///    Callers are responsible for correctly updating the DAG based on the
2985
  ///    results of this function, because simply replacing replacing TLO.Old
2986
  ///    with TLO.New will be incorrect when this parameter is true and TLO.Old
2987
  ///    has multiple uses.
2988
  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask,
2989
                                  APInt &KnownUndef, APInt &KnownZero,
2990
                                  TargetLoweringOpt &TLO, unsigned Depth = 0,
2991
                                  bool AssumeSingleUse = false) const;
2992
2993
  /// Helper wrapper around SimplifyDemandedVectorElts.
2994
  /// Adds Op back to the worklist upon success.
2995
  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
2996
                                  APInt &KnownUndef, APInt &KnownZero,
2997
                                  DAGCombinerInfo &DCI) const;
2998
2999
  /// Determine which of the bits specified in Mask are known to be either zero
3000
  /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
3001
  /// argument allows us to only collect the known bits that are shared by the
3002
  /// requested vector elements.
3003
  virtual void computeKnownBitsForTargetNode(const SDValue Op,
3004
                                             KnownBits &Known,
3005
                                             const APInt &DemandedElts,
3006
                                             const SelectionDAG &DAG,
3007
                                             unsigned Depth = 0) const;
3008
3009
  /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
3010
  /// Default implementation computes low bits based on alignment
3011
  /// information. This should preserve known bits passed into it.
3012
  virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
3013
                                             KnownBits &Known,
3014
                                             const APInt &DemandedElts,
3015
                                             const SelectionDAG &DAG,
3016
                                             unsigned Depth = 0) const;
3017
3018
  /// This method can be implemented by targets that want to expose additional
3019
  /// information about sign bits to the DAG Combiner. The DemandedElts
3020
  /// argument allows us to only collect the minimum sign bits that are shared
3021
  /// by the requested vector elements.
3022
  virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
3023
                                                   const APInt &DemandedElts,
3024
                                                   const SelectionDAG &DAG,
3025
                                                   unsigned Depth = 0) const;
3026
3027
  /// Attempt to simplify any target nodes based on the demanded vector
3028
  /// elements, returning true on success. Otherwise, analyze the expression and
3029
  /// return a mask of KnownUndef and KnownZero elements for the expression
3030
  /// (used to simplify the caller). The KnownUndef/Zero elements may only be
3031
  /// accurate for those bits in the DemandedMask.
3032
  virtual bool SimplifyDemandedVectorEltsForTargetNode(
3033
      SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
3034
      APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
3035
3036
  /// Attempt to simplify any target nodes based on the demanded bits/elts,
3037
  /// returning true on success. Otherwise, analyze the
3038
  /// expression and return a mask of KnownOne and KnownZero bits for the
3039
  /// expression (used to simplify the caller).  The KnownZero/One bits may only
3040
  /// be accurate for those bits in the Demanded masks.
3041
  virtual bool SimplifyDemandedBitsForTargetNode(SDValue Op,
3042
                                                 const APInt &DemandedBits,
3043
                                                 const APInt &DemandedElts,
3044
                                                 KnownBits &Known,
3045
                                                 TargetLoweringOpt &TLO,
3046
                                                 unsigned Depth = 0) const;
3047
3048
  /// If \p SNaN is false, \returns true if \p Op is known to never be any
3049
  /// NaN. If \p sNaN is true, returns if \p Op is known to never be a signaling
3050
  /// NaN.
3051
  virtual bool isKnownNeverNaNForTargetNode(SDValue Op,
3052
                                            const SelectionDAG &DAG,
3053
                                            bool SNaN = false,
3054
                                            unsigned Depth = 0) const;
3055
  struct DAGCombinerInfo {
3056
    void *DC;  // The DAG Combiner object.
3057
    CombineLevel Level;
3058
    bool CalledByLegalizer;
3059
3060
  public:
3061
    SelectionDAG &DAG;
3062
3063
    DAGCombinerInfo(SelectionDAG &dag, CombineLevel level,  bool cl, void *dc)
3064
16.9M
      : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
3065
3066
4.85M
    bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
3067
4.35M
    bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
3068
265k
    bool isAfterLegalizeDAG() const {
3069
265k
      return Level == AfterLegalizeDAG;
3070
265k
    }
3071
172k
    CombineLevel getDAGCombineLevel() { return Level; }
3072
53.7k
    bool isCalledByLegalizer() const { return CalledByLegalizer; }
3073
3074
    void AddToWorklist(SDNode *N);
3075
    SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
3076
    SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
3077
    SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
3078
3079
    void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
3080
  };
3081
3082
  /// Return if the N is a constant or constant vector equal to the true value
3083
  /// from getBooleanContents().
3084
  bool isConstTrueVal(const SDNode *N) const;
3085
3086
  /// Return if the N is a constant or constant vector equal to the false value
3087
  /// from getBooleanContents().
3088
  bool isConstFalseVal(const SDNode *N) const;
3089
3090
  /// Return if \p N is a True value when extended to \p VT.
3091
  bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const;
3092
3093
  /// Try to simplify a setcc built with the specified operands and cc. If it is
3094
  /// unable to simplify it, return a null SDValue.
3095
  SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
3096
                        bool foldBooleans, DAGCombinerInfo &DCI,
3097
                        const SDLoc &dl) const;
3098
3099
  // For targets which wrap address, unwrap for analysis.
3100
45.7M
  virtual SDValue unwrapAddress(SDValue N) const { return N; }
3101
3102
  /// Returns true (and the GlobalValue and the offset) if the node is a
3103
  /// GlobalAddress + offset.
3104
  virtual bool
3105
  isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
3106
3107
  /// This method will be invoked for all target nodes and for any
3108
  /// target-independent nodes that the target has registered with invoke it
3109
  /// for.
3110
  ///
3111
  /// The semantics are as follows:
3112
  /// Return Value:
3113
  ///   SDValue.Val == 0   - No change was made
3114
  ///   SDValue.Val == N   - N was replaced, is dead, and is already handled.
3115
  ///   otherwise          - N should be replaced by the returned Operand.
3116
  ///
3117
  /// In addition, methods provided by DAGCombinerInfo may be used to perform
3118
  /// more complex transformations.
3119
  ///
3120
  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
3121
3122
  /// Return true if it is profitable to move this shift by a constant amount
3123
  /// though its operand, adjusting any immediate operands as necessary to
3124
  /// preserve semantics. This transformation may not be desirable if it
3125
  /// disrupts a particularly auspicious target-specific tree (e.g. bitfield
3126
  /// extraction in AArch64). By default, it returns true.
3127
  ///
3128
  /// @param N the shift node
3129
  /// @param Level the current DAGCombine legalization level.
3130
  virtual bool isDesirableToCommuteWithShift(const SDNode *N,
3131
2.08k
                                             CombineLevel Level) const {
3132
2.08k
    return true;
3133
2.08k
  }
3134
3135
  /// Return true if it is profitable to fold a pair of shifts into a mask.
3136
  /// This is usually true on most targets. But some targets, like Thumb1,
3137
  /// have immediate shift instructions, but no immediate "and" instruction;
3138
  /// this makes the fold unprofitable.
3139
  virtual bool shouldFoldShiftPairToMask(const SDNode *N,
3140
4.78k
                                         CombineLevel Level) const {
3141
4.78k
    return true;
3142
4.78k
  }
3143
3144
  // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
3145
  // to a shuffle and a truncate.
3146
  // Example of such a combine:
3147
  // v4i32 build_vector((extract_elt V, 1),
3148
  //                    (extract_elt V, 3),
3149
  //                    (extract_elt V, 5),
3150
  //                    (extract_elt V, 7))
3151
  //  -->
3152
  // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
3153
  virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(
3154
0
      ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
3155
0
    return false;
3156
0
  }
3157
3158
  /// Return true if the target has native support for the specified value type
3159
  /// and it is 'desirable' to use the type for the given node type. e.g. On x86
3160
  /// i16 is legal, but undesirable since i16 instruction encodings are longer
3161
  /// and some i16 instructions are slow.
3162
2.31M
  virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
3163
2.31M
    // By default, assume all legal types are desirable.
3164
2.31M
    return isTypeLegal(VT);
3165
2.31M
  }
3166
3167
  /// Return true if it is profitable for dag combiner to transform a floating
3168
  /// point op of specified opcode to a equivalent op of an integer
3169
  /// type. e.g. f32 load -> i32 load can be profitable on ARM.
3170
  virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
3171
310
                                                 EVT /*VT*/) const {
3172
310
    return false;
3173
310
  }
3174
3175
  /// This method query the target whether it is beneficial for dag combiner to
3176
  /// promote the specified node. If true, it should return the desired
3177
  /// promotion type by reference.
3178
4.64k
  virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
3179
4.64k
    return false;
3180
4.64k
  }
3181
3182
  /// Return true if the target supports swifterror attribute. It optimizes
3183
  /// loads and stores to reading and writing a specific register.
3184
459k
  virtual bool supportSwiftError() const {
3185
459k
    return false;
3186
459k
  }
3187
3188
  /// Return true if the target supports that a subset of CSRs for the given
3189
  /// machine function is handled explicitly via copies.
3190
31.7k
  virtual bool supportSplitCSR(MachineFunction *MF) const {
3191
31.7k
    return false;
3192
31.7k
  }
3193
3194
  /// Perform necessary initialization to handle a subset of CSRs explicitly
3195
  /// via copies. This function is called at the beginning of instruction
3196
  /// selection.
3197
0
  virtual void initializeSplitCSR(MachineBasicBlock *Entry) const {
3198
0
    llvm_unreachable("Not Implemented");
3199
0
  }
3200
3201
  /// Insert explicit copies in entry and exit blocks. We copy a subset of
3202
  /// CSRs to virtual registers in the entry block, and copy them back to
3203
  /// physical registers in the exit blocks. This function is called at the end
3204
  /// of instruction selection.
3205
  virtual void insertCopiesSplitCSR(
3206
      MachineBasicBlock *Entry,
3207
0
      const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
3208
0
    llvm_unreachable("Not Implemented");
3209
0
  }
3210
3211
  //===--------------------------------------------------------------------===//
3212
  // Lowering methods - These methods must be implemented by targets so that
3213
  // the SelectionDAGBuilder code knows how to lower these.
3214
  //
3215
3216
  /// This hook must be implemented to lower the incoming (formal) arguments,
3217
  /// described by the Ins array, into the specified DAG. The implementation
3218
  /// should fill in the InVals array with legal-type argument values, and
3219
  /// return the resulting token chain value.
3220
  virtual SDValue LowerFormalArguments(
3221
      SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
3222
      const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
3223
0
      SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
3224
0
    llvm_unreachable("Not Implemented");
3225
0
  }
3226
3227
  /// This structure contains all information that is necessary for lowering
3228
  /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
3229
  /// needs to lower a call, and targets will see this struct in their LowerCall
3230
  /// implementation.
3231
  struct CallLoweringInfo {
3232
    SDValue Chain;
3233
    Type *RetTy = nullptr;
3234
    bool RetSExt           : 1;
3235
    bool RetZExt           : 1;
3236
    bool IsVarArg          : 1;
3237
    bool IsInReg           : 1;
3238
    bool DoesNotReturn     : 1;
3239
    bool IsReturnValueUsed : 1;
3240
    bool IsConvergent      : 1;
3241
    bool IsPatchPoint      : 1;
3242
3243
    // IsTailCall should be modified by implementations of
3244
    // TargetLowering::LowerCall that perform tail call conversions.
3245
    bool IsTailCall = false;
3246
3247
    // Is Call lowering done post SelectionDAG type legalization.
3248
    bool IsPostTypeLegalization = false;
3249
3250
    unsigned NumFixedArgs = -1;
3251
    CallingConv::ID CallConv = CallingConv::C;
3252
    SDValue Callee;
3253
    ArgListTy Args;
3254
    SelectionDAG &DAG;
3255
    SDLoc DL;
3256
    ImmutableCallSite CS;
3257
    SmallVector<ISD::OutputArg, 32> Outs;
3258
    SmallVector<SDValue, 32> OutVals;
3259
    SmallVector<ISD::InputArg, 32> Ins;
3260
    SmallVector<SDValue, 4> InVals;
3261
3262
    CallLoweringInfo(SelectionDAG &DAG)
3263
        : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
3264
          DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
3265
462k
          IsPatchPoint(false), DAG(DAG) {}
3266
3267
462k
    CallLoweringInfo &setDebugLoc(const SDLoc &dl) {
3268
462k
      DL = dl;
3269
462k
      return *this;
3270
462k
    }
3271
3272
470k
    CallLoweringInfo &setChain(SDValue InChain) {
3273
470k
      Chain = InChain;
3274
470k
      return *this;
3275
470k
    }
3276
3277
    // setCallee with target/module-specific attributes
3278
    CallLoweringInfo &setLibCallee(CallingConv::ID CC, Type *ResultType,
3279
17.6k
                                   SDValue Target, ArgListTy &&ArgsList) {
3280
17.6k
      RetTy = ResultType;
3281
17.6k
      Callee = Target;
3282
17.6k
      CallConv = CC;
3283
17.6k
      NumFixedArgs = ArgsList.size();
3284
17.6k
      Args = std::move(ArgsList);
3285
17.6k
3286
17.6k
      DAG.getTargetLoweringInfo().markLibCallAttributes(
3287
17.6k
          &(DAG.getMachineFunction()), CC, Args);
3288
17.6k
      return *this;
3289
17.6k
    }
3290
3291
    CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
3292
618
                                SDValue Target, ArgListTy &&ArgsList) {
3293
618
      RetTy = ResultType;
3294
618
      Callee = Target;
3295
618
      CallConv = CC;
3296
618
      NumFixedArgs = ArgsList.size();
3297
618
      Args = std::move(ArgsList);
3298
618
      return *this;
3299
618
    }
3300
3301
    CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
3302
                                SDValue Target, ArgListTy &&ArgsList,
3303
444k
                                ImmutableCallSite Call) {
3304
444k
      RetTy = ResultType;
3305
444k
3306
444k
      IsInReg = Call.hasRetAttr(Attribute::InReg);
3307
444k
      DoesNotReturn =
3308
444k
          Call.doesNotReturn() ||
3309
444k
          
(420k
!Call.isInvoke()420k
&&
3310
420k
           
isa<UnreachableInst>(Call.getInstruction()->getNextNode())413k
);
3311
444k
      IsVarArg = FTy->isVarArg();
3312
444k
      IsReturnValueUsed = !Call.getInstruction()->use_empty();
3313
444k
      RetSExt = Call.hasRetAttr(Attribute::SExt);
3314
444k
      RetZExt = Call.hasRetAttr(Attribute::ZExt);
3315
444k
3316
444k
      Callee = Target;
3317
444k
3318
444k
      CallConv = Call.getCallingConv();
3319
444k
      NumFixedArgs = FTy->getNumParams();
3320
444k
      Args = std::move(ArgsList);
3321
444k
3322
444k
      CS = Call;
3323
444k
3324
444k
      return *this;
3325
444k
    }
3326
3327
200
    CallLoweringInfo &setInRegister(bool Value = true) {
3328
200
      IsInReg = Value;
3329
200
      return *this;
3330
200
    }
3331
3332
5.68k
    CallLoweringInfo &setNoReturn(bool Value = true) {
3333
5.68k
      DoesNotReturn = Value;
3334
5.68k
      return *this;
3335
5.68k
    }
3336
3337
    CallLoweringInfo &setVarArg(bool Value = true) {
3338
      IsVarArg = Value;
3339
      return *this;
3340
    }
3341
3342
450k
    CallLoweringInfo &setTailCall(bool Value = true) {
3343
450k
      IsTailCall = Value;
3344
450k
      return *this;
3345
450k
    }
3346
3347
12.7k
    CallLoweringInfo &setDiscardResult(bool Value = true) {
3348
12.7k
      IsReturnValueUsed = !Value;
3349
12.7k
      return *this;
3350
12.7k
    }
3351
3352
444k
    CallLoweringInfo &setConvergent(bool Value = true) {
3353
444k
      IsConvergent = Value;
3354
444k
      return *this;
3355
444k
    }
3356
3357
10.6k
    CallLoweringInfo &setSExtResult(bool Value = true) {
3358
10.6k
      RetSExt = Value;
3359
10.6k
      return *this;
3360
10.6k
    }
3361
3362
10.6k
    CallLoweringInfo &setZExtResult(bool Value = true) {
3363
10.6k
      RetZExt = Value;
3364
10.6k
      return *this;
3365
10.6k
    }
3366
3367
231
    CallLoweringInfo &setIsPatchPoint(bool Value = true) {
3368
231
      IsPatchPoint = Value;
3369
231
      return *this;
3370
231
    }
3371
3372
9.68k
    CallLoweringInfo &setIsPostTypeLegalization(bool Value=true) {
3373
9.68k
      IsPostTypeLegalization = Value;
3374
9.68k
      return *this;
3375
9.68k
    }
3376
3377
1.03M
    ArgListTy &getArgs() {
3378
1.03M
      return Args;
3379
1.03M
    }
3380
  };
3381
3382
  /// This function lowers an abstract call to a function into an actual call.
3383
  /// This returns a pair of operands.  The first element is the return value
3384
  /// for the function (if RetTy is not VoidTy).  The second element is the
3385
  /// outgoing token chain. It calls LowerCall to do the actual lowering.
3386
  std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
3387
3388
  /// This hook must be implemented to lower calls into the specified
3389
  /// DAG. The outgoing arguments to the call are described by the Outs array,
3390
  /// and the values to be returned by the call are described by the Ins
3391
  /// array. The implementation should fill in the InVals array with legal-type
3392
  /// return values from the call, and return the resulting token chain value.
3393
  virtual SDValue
3394
    LowerCall(CallLoweringInfo &/*CLI*/,
3395
0
              SmallVectorImpl<SDValue> &/*InVals*/) const {
3396
0
    llvm_unreachable("Not Implemented");
3397
0
  }
3398
3399
  /// Target-specific cleanup for formal ByVal parameters.
3400
1.08k
  virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
3401
3402
  /// This hook should be implemented to check whether the return values
3403
  /// described by the Outs array can fit into the return registers.  If false
3404
  /// is returned, an sret-demotion is performed.
3405
  virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
3406
                              MachineFunction &/*MF*/, bool /*isVarArg*/,
3407
               const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
3408
               LLVMContext &/*Context*/) const
3409
5.68k
  {
3410
5.68k
    // Return true by default to get preexisting behavior.
3411
5.68k
    return true;
3412
5.68k
  }
3413
3414
  /// This hook must be implemented to lower outgoing return values, described
3415
  /// by the Outs array, into the specified DAG. The implementation should
3416
  /// return the resulting token chain value.
3417
  virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
3418
                              bool /*isVarArg*/,
3419
                              const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
3420
                              const SmallVectorImpl<SDValue> & /*OutVals*/,
3421
                              const SDLoc & /*dl*/,
3422
0
                              SelectionDAG & /*DAG*/) const {
3423
0
    llvm_unreachable("Not Implemented");
3424
0
  }
3425
3426
  /// Return true if result of the specified node is used by a return node
3427
  /// only. It also compute and return the input chain for the tail call.
3428
  ///
3429
  /// This is used to determine whether it is possible to codegen a libcall as
3430
  /// tail call at legalization time.
3431
621
  virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
3432
621
    return false;
3433
621
  }
3434
3435
  /// Return true if the target may be able emit the call instruction as a tail
3436
  /// call. This is used by optimization passes to determine if it's profitable
3437
  /// to duplicate return instructions to enable tailcall optimization.
3438
194
  virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
3439
194
    return false;
3440
194
  }
3441
3442
  /// Return the builtin name for the __builtin___clear_cache intrinsic
3443
  /// Default is to invoke the clear cache library call
3444
2
  virtual const char * getClearCacheBuiltinName() const {
3445
2
    return "__clear_cache";
3446
2
  }
3447
3448
  /// Return the register ID of the name passed in. Used by named register
3449
  /// global variables extension. There is no target-independent behaviour
3450
  /// so the default action is to bail.
3451
  virtual unsigned getRegisterByName(const char* RegName, EVT VT,
3452
0
                                     SelectionDAG &DAG) const {
3453
0
    report_fatal_error("Named registers not implemented for this target");
3454
0
  }
3455
3456
  /// Return the type that should be used to zero or sign extend a
3457
  /// zeroext/signext integer return value.  FIXME: Some C calling conventions
3458
  /// require the return type to be promoted, but this is not true all the time,
3459
  /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3460
  /// conventions. The frontend should handle this and include all of the
3461
  /// necessary information.
3462
  virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
3463
3.32k
                                       ISD::NodeType /*ExtendKind*/) const {
3464
3.32k
    EVT MinVT = getRegisterType(Context, MVT::i32);
3465
3.32k
    return VT.bitsLT(MinVT) ? 
MinVT2.39k
:
VT930
;
3466
3.32k
  }
3467
3468
  /// For some targets, an LLVM struct type must be broken down into multiple
3469
  /// simple types, but the calling convention specifies that the entire struct
3470
  /// must be passed in a block of consecutive registers.
3471
  virtual bool
3472
  functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
3473
640k
                                            bool isVarArg) const {
3474
640k
    return false;
3475
640k
  }
3476
3477
  /// Returns a 0 terminated array of registers that can be safely used as
3478
  /// scratch registers.
3479
0
  virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
3480
0
    return nullptr;
3481
0
  }
3482
3483
  /// This callback is used to prepare for a volatile or atomic load.
3484
  /// It takes a chain node as input and returns the chain for the load itself.
3485
  ///
3486
  /// Having a callback like this is necessary for targets like SystemZ,
3487
  /// which allows a CPU to reuse the result of a previous load indefinitely,
3488
  /// even if a cache-coherent store is performed by another CPU.  The default
3489
  /// implementation does nothing.
3490
  virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL,
3491
23.6k
                                              SelectionDAG &DAG) const {
3492
23.6k
    return Chain;
3493
23.6k
  }
3494
3495
  /// This callback is used to inspect load/store instructions and add
3496
  /// target-specific MachineMemOperand flags to them.  The default
3497
  /// implementation does nothing.
3498
470k
  virtual MachineMemOperand::Flags getMMOFlags(const Instruction &I) const {
3499
470k
    return MachineMemOperand::MONone;
3500
470k
  }
3501
3502
  /// This callback is invoked by the type legalizer to legalize nodes with an
3503
  /// illegal operand type but legal result types.  It replaces the
3504
  /// LowerOperation callback in the type Legalizer.  The reason we can not do
3505
  /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3506
  /// use this callback.
3507
  ///
3508
  /// TODO: Consider merging with ReplaceNodeResults.
3509
  ///
3510
  /// The target places new result values for the node in Results (their number
3511
  /// and types must exactly match those of the original return values of
3512
  /// the node), or leaves Results empty, which indicates that the node is not
3513
  /// to be custom lowered after all.
3514
  /// The default implementation calls LowerOperation.
3515
  virtual void LowerOperationWrapper(SDNode *N,
3516
                                     SmallVectorImpl<SDValue> &Results,
3517
                                     SelectionDAG &DAG) const;
3518
3519
  /// This callback is invoked for operations that are unsupported by the
3520
  /// target, which are registered to use 'custom' lowering, and whose defined
3521
  /// values are all legal.  If the target has no operations that require custom
3522
  /// lowering, it need not implement this.  The default implementation of this
3523
  /// aborts.
3524
  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
3525
3526
  /// This callback is invoked when a node result type is illegal for the
3527
  /// target, and the operation was registered to use 'custom' lowering for that
3528
  /// result type.  The target places new result values for the node in Results
3529
  /// (their number and types must exactly match those of the original return
3530
  /// values of the node), or leaves Results empty, which indicates that the
3531
  /// node is not to be custom lowered after all.
3532
  ///
3533
  /// If the target has no operations that require custom lowering, it need not
3534
  /// implement this.  The default implementation aborts.
3535
  virtual void ReplaceNodeResults(SDNode * /*N*/,
3536
                                  SmallVectorImpl<SDValue> &/*Results*/,
3537
0
                                  SelectionDAG &/*DAG*/) const {
3538
0
    llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3539
0
  }
3540
3541
  /// This method returns the name of a target specific DAG node.
3542
  virtual const char *getTargetNodeName(unsigned Opcode) const;
3543
3544
  /// This method returns a target specific FastISel object, or null if the
3545
  /// target does not support "fast" ISel.
3546
  virtual FastISel *createFastISel(FunctionLoweringInfo &,
3547
2.65k
                                   const TargetLibraryInfo *) const {
3548
2.65k
    return nullptr;
3549
2.65k
  }
3550
3551
  bool verifyReturnAddressArgumentIsConstant(SDValue Op,
3552
                                             SelectionDAG &DAG) const;
3553
3554
  //===--------------------------------------------------------------------===//
3555
  // Inline Asm Support hooks
3556
  //
3557
3558
  /// This hook allows the target to expand an inline asm call to be explicit
3559
  /// llvm code if it wants to.  This is useful for turning simple inline asms
3560
  /// into LLVM intrinsics, which gives the compiler more information about the
3561
  /// behavior of the code.
3562
5.09k
  virtual bool ExpandInlineAsm(CallInst *) const {
3563
5.09k
    return false;
3564
5.09k
  }
3565
3566
  enum ConstraintType {
3567
    C_Register,            // Constraint represents specific register(s).
3568
    C_RegisterClass,       // Constraint represents any of register(s) in class.
3569
    C_Memory,              // Memory constraint.
3570
    C_Other,               // Something else.
3571
    C_Unknown              // Unsupported constraint.
3572
  };
3573
3574
  enum ConstraintWeight {
3575
    // Generic weights.
3576
    CW_Invalid  = -1,     // No match.
3577
    CW_Okay     = 0,      // Acceptable.
3578
    CW_Good     = 1,      // Good weight.
3579
    CW_Better   = 2,      // Better weight.
3580
    CW_Best     = 3,      // Best weight.
3581
3582
    // Well-known weights.
3583
    CW_SpecificReg  = CW_Okay,    // Specific register operands.
3584
    CW_Register     = CW_Good,    // Register operands.
3585
    CW_Memory       = CW_Better,  // Memory operands.
3586
    CW_Constant     = CW_Best,    // Constant operand.
3587
    CW_Default      = CW_Okay     // Default or don't know type.
3588
  };
3589
3590
  /// This contains information for each constraint that we are lowering.
3591
  struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3592
    /// This contains the actual string for the code, like "m".  TargetLowering
3593
    /// picks the 'best' code from ConstraintInfo::Codes that most closely
3594
    /// matches the operand.
3595
    std::string ConstraintCode;
3596
3597
    /// Information about the constraint code, e.g. Register, RegisterClass,
3598
    /// Memory, Other, Unknown.
3599
    TargetLowering::ConstraintType ConstraintType = TargetLowering::C_Unknown;
3600
3601
    /// If this is the result output operand or a clobber, this is null,
3602
    /// otherwise it is the incoming operand to the CallInst.  This gets
3603
    /// modified as the asm is processed.
3604
    Value *CallOperandVal = nullptr;
3605
3606
    /// The ValueType for the operand value.
3607
    MVT ConstraintVT = MVT::Other;
3608
3609
    /// Copy constructor for copying from a ConstraintInfo.
3610
    AsmOperandInfo(InlineAsm::ConstraintInfo Info)
3611
307k
        : InlineAsm::ConstraintInfo(std::move(Info)) {}
3612
3613
    /// Return true of this is an input operand that is a matching constraint
3614
    /// like "4".
3615
    bool isMatchingInputConstraint() const;
3616
3617
    /// If this is an input matching constraint, this method returns the output
3618
    /// operand it matches.
3619
    unsigned getMatchedOperand() const;
3620
  };
3621
3622
  using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
3623
3624
  /// Split up the constraint string from the inline assembly value into the
3625
  /// specific constraints and their prefixes, and also tie in the associated
3626
  /// operand values.  If this returns an empty vector, and if the constraint
3627
  /// string itself isn't empty, there was an error parsing.
3628
  virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
3629
                                                const TargetRegisterInfo *TRI,
3630
                                                ImmutableCallSite CS) const;
3631
3632
  /// Examine constraint type and operand type and determine a weight value.
3633
  /// The operand object must already have been set up with the operand type.
3634
  virtual ConstraintWeight getMultipleConstraintMatchWeight(
3635
      AsmOperandInfo &info, int maIndex) const;
3636
3637
  /// Examine constraint string and operand type and determine a weight value.
3638
  /// The operand object must already have been set up with the operand type.
3639
  virtual ConstraintWeight getSingleConstraintMatchWeight(
3640
      AsmOperandInfo &info, const char *constraint) const;
3641
3642
  /// Determines the constraint code and constraint type to use for the specific
3643
  /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3644
  /// If the actual operand being passed in is available, it can be passed in as
3645
  /// Op, otherwise an empty SDValue can be passed.
3646
  virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3647
                                      SDValue Op,
3648
                                      SelectionDAG *DAG = nullptr) const;
3649
3650
  /// Given a constraint, return the type of constraint it is for this target.
3651
  virtual ConstraintType getConstraintType(StringRef Constraint) const;
3652
3653
  /// Given a physical register constraint (e.g.  {edx}), return the register
3654
  /// number and the register class for the register.
3655
  ///
3656
  /// Given a register class constraint, like 'r', if this corresponds directly
3657
  /// to an LLVM register class, return a register of 0 and the register class
3658
  /// pointer.
3659
  ///
3660
  /// This should only be used for C_Register constraints.  On error, this
3661
  /// returns a register number of 0 and a null register class pointer.
3662
  virtual std::pair<unsigned, const TargetRegisterClass *>
3663
  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3664
                               StringRef Constraint, MVT VT) const;
3665
3666
429
  virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
3667
429
    if (ConstraintCode == "i")
3668
0
      return InlineAsm::Constraint_i;
3669
429
    else if (ConstraintCode == "m")
3670
429
      return InlineAsm::Constraint_m;
3671
0
    return InlineAsm::Constraint_Unknown;
3672
0
  }
3673
3674
  /// Try to replace an X constraint, which matches anything, with another that
3675
  /// has more specific requirements based on the type of the corresponding
3676
  /// operand.  This returns null if there is no replacement to make.
3677
  virtual const char *LowerXConstraint(EVT ConstraintVT) const;
3678
3679
  /// Lower the specified operand into the Ops vector.  If it is invalid, don't
3680
  /// add anything to Ops.
3681
  virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
3682
                                            std::vector<SDValue> &Ops,
3683
                                            SelectionDAG &DAG) const;
3684
3685
  // Lower custom output constraints. If invalid, return SDValue().
3686
  virtual SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,
3687
                                              SDLoc DL,
3688
                                              const AsmOperandInfo &OpInfo,
3689
                                              SelectionDAG &DAG) const;
3690
3691
  //===--------------------------------------------------------------------===//
3692
  // Div utility functions
3693
  //
3694
  SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3695
                    SmallVectorImpl<SDNode *> &Created) const;
3696
  SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3697
                    SmallVectorImpl<SDNode *> &Created) const;
3698
3699
  /// Targets may override this function to provide custom SDIV lowering for
3700
  /// power-of-2 denominators.  If the target returns an empty SDValue, LLVM
3701
  /// assumes SDIV is expensive and replaces it with a series of other integer
3702
  /// operations.
3703
  virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
3704
                                SelectionDAG &DAG,
3705
                                SmallVectorImpl<SDNode *> &Created) const;
3706
3707
  /// Indicate whether this target prefers to combine FDIVs with the same
3708
  /// divisor. If the transform should never be done, return zero. If the
3709
  /// transform should be done, return the minimum number of divisor uses
3710
  /// that must exist.
3711
52
  virtual unsigned combineRepeatedFPDivisors() const {
3712
52
    return 0;
3713
52
  }
3714
3715
  /// Hooks for building estimates in place of slower divisions and square
3716
  /// roots.
3717
3718
  /// Return either a square root or its reciprocal estimate value for the input
3719
  /// operand.
3720
  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3721
  /// 'Enabled' as set by a potential default override attribute.
3722
  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3723
  /// refinement iterations required to generate a sufficient (though not
3724
  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3725
  /// The boolean UseOneConstNR output is used to select a Newton-Raphson
3726
  /// algorithm implementation that uses either one or two constants.
3727
  /// The boolean Reciprocal is used to select whether the estimate is for the
3728
  /// square root of the input operand or the reciprocal of its square root.
3729
  /// A target may choose to implement its own refinement within this function.
3730
  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3731
  /// any further refinement of the estimate.
3732
  /// An empty SDValue return means no estimate sequence can be created.
3733
  virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
3734
                                  int Enabled, int &RefinementSteps,
3735
16
                                  bool &UseOneConstNR, bool Reciprocal) const {
3736
16
    return SDValue();
3737
16
  }
3738
3739
  /// Return a reciprocal estimate value for the input operand.
3740
  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3741
  /// 'Enabled' as set by a potential default override attribute.
3742
  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3743
  /// refinement iterations required to generate a sufficient (though not
3744
  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3745
  /// A target may choose to implement its own refinement within this function.
3746
  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3747
  /// any further refinement of the estimate.
3748
  /// An empty SDValue return means no estimate sequence can be created.
3749
  virtual SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG,
3750
42
                                   int Enabled, int &RefinementSteps) const {
3751
42
    return SDValue();
3752
42
  }
3753
3754
  //===--------------------------------------------------------------------===//
3755
  // Legalization utility functions
3756
  //
3757
3758
  /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
3759
  /// respectively, each computing an n/2-bit part of the result.
3760
  /// \param Result A vector that will be filled with the parts of the result
3761
  ///        in little-endian order.
3762
  /// \param LL Low bits of the LHS of the MUL.  You can use this parameter
3763
  ///        if you want to control how low bits are extracted from the LHS.
3764
  /// \param LH High bits of the LHS of the MUL.  See LL for meaning.
3765
  /// \param RL Low bits of the RHS of the MUL.  See LL for meaning
3766
  /// \param RH High bits of the RHS of the MUL.  See LL for meaning.
3767
  /// \returns true if the node has been expanded, false if it has not
3768
  bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
3769
                      SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
3770
                      SelectionDAG &DAG, MulExpansionKind Kind,
3771
                      SDValue LL = SDValue(), SDValue LH = SDValue(),
3772
                      SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3773
3774
  /// Expand a MUL into two nodes.  One that computes the high bits of
3775
  /// the result and one that computes the low bits.
3776
  /// \param HiLoVT The value type to use for the Lo and Hi nodes.
3777
  /// \param LL Low bits of the LHS of the MUL.  You can use this parameter
3778
  ///        if you want to control how low bits are extracted from the LHS.
3779
  /// \param LH High bits of the LHS of the MUL.  See LL for meaning.
3780
  /// \param RL Low bits of the RHS of the MUL.  See LL for meaning
3781
  /// \param RH High bits of the RHS of the MUL.  See LL for meaning.
3782
  /// \returns true if the node has been expanded. false if it has not
3783
  bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
3784
                 SelectionDAG &DAG, MulExpansionKind Kind,
3785
                 SDValue LL = SDValue(), SDValue LH = SDValue(),
3786
                 SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3787
3788
  /// Expand funnel shift.
3789
  /// \param N Node to expand
3790
  /// \param Result output after conversion
3791
  /// \returns True, if the expansion was successful, false otherwise
3792
  bool expandFunnelShift(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3793
3794
  /// Expand rotations.
3795
  /// \param N Node to expand
3796
  /// \param Result output after conversion
3797
  /// \returns True, if the expansion was successful, false otherwise
3798
  bool expandROT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3799
3800
  /// Expand float(f32) to SINT(i64) conversion
3801
  /// \param N Node to expand
3802
  /// \param Result output after conversion
3803
  /// \returns True, if the expansion was successful, false otherwise
3804
  bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3805
3806
  /// Expand float to UINT conversion
3807
  /// \param N Node to expand
3808
  /// \param Result output after conversion
3809
  /// \returns True, if the expansion was successful, false otherwise
3810
  bool expandFP_TO_UINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3811
3812
  /// Expand UINT(i64) to double(f64) conversion
3813
  /// \param N Node to expand
3814
  /// \param Result output after conversion
3815
  /// \returns True, if the expansion was successful, false otherwise
3816
  bool expandUINT_TO_FP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3817
3818
  /// Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.
3819
  SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const;
3820
3821
  /// Expand CTPOP nodes. Expands vector/scalar CTPOP nodes,
3822
  /// vector nodes can only succeed if all operations are legal/custom.
3823
  /// \param N Node to expand
3824
  /// \param Result output after conversion
3825
  /// \returns True, if the expansion was successful, false otherwise
3826
  bool expandCTPOP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3827
3828
  /// Expand CTLZ/CTLZ_ZERO_UNDEF nodes. Expands vector/scalar CTLZ nodes,
3829
  /// vector nodes can only succeed if all operations are legal/custom.
3830
  /// \param N Node to expand
3831
  /// \param Result output after conversion
3832
  /// \returns True, if the expansion was successful, false otherwise
3833
  bool expandCTLZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3834
3835
  /// Expand CTTZ/CTTZ_ZERO_UNDEF nodes. Expands vector/scalar CTTZ nodes,
3836
  /// vector nodes can only succeed if all operations are legal/custom.
3837
  /// \param N Node to expand
3838
  /// \param Result output after conversion
3839
  /// \returns True, if the expansion was successful, false otherwise
3840
  bool expandCTTZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3841
3842
  /// Expand ABS nodes. Expands vector/scalar ABS nodes,
3843
  /// vector nodes can only succeed if all operations are legal/custom.
3844
  /// (ABS x) -> (XOR (ADD x, (SRA x, type_size)), (SRA x, type_size))
3845
  /// \param N Node to expand
3846
  /// \param Result output after conversion
3847
  /// \returns True, if the expansion was successful, false otherwise
3848
  bool expandABS(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3849
3850
  /// Turn load of vector type into a load of the individual elements.
3851
  /// \param LD load to expand
3852
  /// \returns MERGE_VALUEs of the scalar loads with their chains.
3853
  SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
3854
3855
  // Turn a store of a vector type into stores of the individual elements.
3856
  /// \param ST Store with a vector value type
3857
  /// \returns MERGE_VALUs of the individual store chains.
3858
  SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3859
3860
  /// Expands an unaligned load to 2 half-size loads for an integer, and
3861
  /// possibly more for vectors.
3862
  std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
3863
                                                  SelectionDAG &DAG) const;
3864
3865
  /// Expands an unaligned store to 2 half-size stores for integer values, and
3866
  /// possibly more for vectors.
3867
  SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3868
3869
  /// Increments memory address \p Addr according to the type of the value
3870
  /// \p DataVT that should be stored. If the data is stored in compressed
3871
  /// form, the memory address should be incremented according to the number of
3872
  /// the stored elements. This number is equal to the number of '1's bits
3873
  /// in the \p Mask.
3874
  /// \p DataVT is a vector type. \p Mask is a vector value.
3875
  /// \p DataVT and \p Mask have the same number of vector elements.
3876
  SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
3877
                                 EVT DataVT, SelectionDAG &DAG,
3878
                                 bool IsCompressedMemory) const;
3879
3880
  /// Get a pointer to vector element \p Idx located in memory for a vector of
3881
  /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
3882
  /// bounds the returned pointer is unspecified, but will be within the vector
3883
  /// bounds.
3884
  SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
3885
                                  SDValue Index) const;
3886
3887
  /// Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. This
3888
  /// method accepts integers as its arguments.
3889
  SDValue expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const;
3890
3891
  /// Method for building the DAG expansion of ISD::SMULFIX. This method accepts
3892
  /// integers as its arguments.
3893
  SDValue expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const;
3894
3895
  /// Method for building the DAG expansion of ISD::[US]MULO. Returns whether
3896
  /// expansion was successful and populates the Result and Overflow arguments.
3897
  bool expandMULO(SDNode *Node, SDValue &Result, SDValue &Overflow,
3898
                  SelectionDAG &DAG) const;
3899
3900
  /// Expand a VECREDUCE_* into an explicit calculation. If Count is specified,
3901
  /// only the first Count elements of the vector are used.
3902
  SDValue expandVecReduce(SDNode *Node, SelectionDAG &DAG) const;
3903
3904
  //===--------------------------------------------------------------------===//
3905
  // Instruction Emitting Hooks
3906
  //
3907
3908
  /// This method should be implemented by targets that mark instructions with
3909
  /// the 'usesCustomInserter' flag.  These instructions are special in various
3910
  /// ways, which require special support to insert.  The specified MachineInstr
3911
  /// is created but not inserted into any basic blocks, and this method is
3912
  /// called to expand it into a sequence of instructions, potentially also
3913
  /// creating new basic blocks and control flow.
3914
  /// As long as the returned basic block is different (i.e., we created a new
3915
  /// one), the custom inserter is free to modify the rest of \p MBB.
3916
  virtual MachineBasicBlock *
3917
  EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
3918
3919
  /// This method should be implemented by targets that mark instructions with
3920
  /// the 'hasPostISelHook' flag. These instructions must be adjusted after
3921
  /// instruction selection by target hooks.  e.g. To fill in optional defs for
3922
  /// ARM 's' setting instructions.
3923
  virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
3924
                                             SDNode *Node) const;
3925
3926
  /// If this function returns true, SelectionDAGBuilder emits a
3927
  /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
3928
21
  virtual bool useLoadStackGuardNode() const {
3929
21
    return false;
3930
21
  }
3931
3932
  virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
3933
0
                                      const SDLoc &DL) const {
3934
0
    llvm_unreachable("not implemented for this target");
3935
0
  }
3936
3937
  /// Lower TLS global address SDNode for target independent emulated TLS model.
3938
  virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
3939
                                          SelectionDAG &DAG) const;
3940
3941
  /// Expands target specific indirect branch for the case of JumpTable
3942
  /// expanasion.
3943
  virtual SDValue expandIndirectJTBranch(const SDLoc& dl, SDValue Value, SDValue Addr,
3944
349
                                         SelectionDAG &DAG) const {
3945
349
    return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
3946
349
  }
3947
3948
  // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
3949
  // If we're comparing for equality to zero and isCtlzFast is true, expose the
3950
  // fact that this can be implemented as a ctlz/srl pair, so that the dag
3951
  // combiner can fold the new nodes.
3952
  SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
3953
3954
private:
3955
  SDValue foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
3956
                           const SDLoc &DL, DAGCombinerInfo &DCI) const;
3957
  SDValue foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
3958
                             const SDLoc &DL, DAGCombinerInfo &DCI) const;
3959
3960
  SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0,
3961
                                               SDValue N1, ISD::CondCode Cond,
3962
                                               DAGCombinerInfo &DCI,
3963
                                               const SDLoc &DL) const;
3964
};
3965
3966
/// Given an LLVM IR type and return type attributes, compute the return value
3967
/// EVTs and flags, and optionally also the offsets, if the return value is
3968
/// being lowered to memory.
3969
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr,
3970
                   SmallVectorImpl<ISD::OutputArg> &Outs,
3971
                   const TargetLowering &TLI, const DataLayout &DL);
3972
3973
} // end namespace llvm
3974
3975
#endif // LLVM_CODEGEN_TARGETLOWERING_H