Coverage Report

Created: 2018-07-12 09:57

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/TargetLowering.h
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//===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
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//
3
//                     The LLVM Compiler Infrastructure
4
//
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// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
///
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/// \file
11
/// This file describes how to lower LLVM code to machine code.  This has two
12
/// main components:
13
///
14
///  1. Which ValueTypes are natively supported by the target.
15
///  2. Which operations are supported for supported ValueTypes.
16
///  3. Cost thresholds for alternative implementations of certain operations.
17
///
18
/// In addition it has a few other components, like information about FP
19
/// immediates.
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///
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//===----------------------------------------------------------------------===//
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23
#ifndef LLVM_CODEGEN_TARGETLOWERING_H
24
#define LLVM_CODEGEN_TARGETLOWERING_H
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26
#include "llvm/ADT/APInt.h"
27
#include "llvm/ADT/ArrayRef.h"
28
#include "llvm/ADT/DenseMap.h"
29
#include "llvm/ADT/STLExtras.h"
30
#include "llvm/ADT/SmallVector.h"
31
#include "llvm/ADT/StringRef.h"
32
#include "llvm/Analysis/DivergenceAnalysis.h"
33
#include "llvm/CodeGen/DAGCombine.h"
34
#include "llvm/CodeGen/ISDOpcodes.h"
35
#include "llvm/CodeGen/RuntimeLibcalls.h"
36
#include "llvm/CodeGen/SelectionDAG.h"
37
#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/CodeGen/TargetCallingConv.h"
39
#include "llvm/CodeGen/ValueTypes.h"
40
#include "llvm/IR/Attributes.h"
41
#include "llvm/IR/CallSite.h"
42
#include "llvm/IR/CallingConv.h"
43
#include "llvm/IR/DataLayout.h"
44
#include "llvm/IR/DerivedTypes.h"
45
#include "llvm/IR/Function.h"
46
#include "llvm/IR/IRBuilder.h"
47
#include "llvm/IR/InlineAsm.h"
48
#include "llvm/IR/Instruction.h"
49
#include "llvm/IR/Instructions.h"
50
#include "llvm/IR/Type.h"
51
#include "llvm/MC/MCRegisterInfo.h"
52
#include "llvm/Support/AtomicOrdering.h"
53
#include "llvm/Support/Casting.h"
54
#include "llvm/Support/ErrorHandling.h"
55
#include "llvm/Support/MachineValueType.h"
56
#include "llvm/Target/TargetMachine.h"
57
#include <algorithm>
58
#include <cassert>
59
#include <climits>
60
#include <cstdint>
61
#include <iterator>
62
#include <map>
63
#include <string>
64
#include <utility>
65
#include <vector>
66
67
namespace llvm {
68
69
class BranchProbability;
70
class CCState;
71
class CCValAssign;
72
class Constant;
73
class FastISel;
74
class FunctionLoweringInfo;
75
class GlobalValue;
76
class IntrinsicInst;
77
struct KnownBits;
78
class LLVMContext;
79
class MachineBasicBlock;
80
class MachineFunction;
81
class MachineInstr;
82
class MachineJumpTableInfo;
83
class MachineLoop;
84
class MachineRegisterInfo;
85
class MCContext;
86
class MCExpr;
87
class Module;
88
class TargetRegisterClass;
89
class TargetLibraryInfo;
90
class TargetRegisterInfo;
91
class Value;
92
93
namespace Sched {
94
95
  enum Preference {
96
    None,             // No preference
97
    Source,           // Follow source order.
98
    RegPressure,      // Scheduling for lowest register pressure.
99
    Hybrid,           // Scheduling for both latency and register pressure.
100
    ILP,              // Scheduling for ILP in low register pressure mode.
101
    VLIW              // Scheduling for VLIW targets.
102
  };
103
104
} // end namespace Sched
105
106
/// This base class for TargetLowering contains the SelectionDAG-independent
107
/// parts that can be used from the rest of CodeGen.
108
class TargetLoweringBase {
109
public:
110
  /// This enum indicates whether operations are valid for a target, and if not,
111
  /// what action should be used to make them valid.
112
  enum LegalizeAction : uint8_t {
113
    Legal,      // The target natively supports this operation.
114
    Promote,    // This operation should be executed in a larger type.
115
    Expand,     // Try to expand this to other ops, otherwise use a libcall.
116
    LibCall,    // Don't try to expand this to other ops, always use a libcall.
117
    Custom      // Use the LowerOperation hook to implement custom lowering.
118
  };
119
120
  /// This enum indicates whether a types are legal for a target, and if not,
121
  /// what action should be used to make them valid.
122
  enum LegalizeTypeAction : uint8_t {
123
    TypeLegal,           // The target natively supports this type.
124
    TypePromoteInteger,  // Replace this integer with a larger one.
125
    TypeExpandInteger,   // Split this integer into two of half the size.
126
    TypeSoftenFloat,     // Convert this float to a same size integer type,
127
                         // if an operation is not supported in target HW.
128
    TypeExpandFloat,     // Split this float into two of half the size.
129
    TypeScalarizeVector, // Replace this one-element vector with its element.
130
    TypeSplitVector,     // Split this vector into two of half the size.
131
    TypeWidenVector,     // This vector should be widened into a larger vector.
132
    TypePromoteFloat     // Replace this float with a larger one.
133
  };
134
135
  /// LegalizeKind holds the legalization kind that needs to happen to EVT
136
  /// in order to type-legalize it.
137
  using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
138
139
  /// Enum that describes how the target represents true/false values.
140
  enum BooleanContent {
141
    UndefinedBooleanContent,    // Only bit 0 counts, the rest can hold garbage.
142
    ZeroOrOneBooleanContent,        // All bits zero except for bit 0.
143
    ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
144
  };
145
146
  /// Enum that describes what type of support for selects the target has.
147
  enum SelectSupportKind {
148
    ScalarValSelect,      // The target supports scalar selects (ex: cmov).
149
    ScalarCondVectorVal,  // The target supports selects with a scalar condition
150
                          // and vector values (ex: cmov).
151
    VectorMaskSelect      // The target supports vector selects with a vector
152
                          // mask (ex: x86 blends).
153
  };
154
155
  /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
156
  /// to, if at all. Exists because different targets have different levels of
157
  /// support for these atomic instructions, and also have different options
158
  /// w.r.t. what they should expand to.
159
  enum class AtomicExpansionKind {
160
    None,    // Don't expand the instruction.
161
    LLSC,    // Expand the instruction into loadlinked/storeconditional; used
162
             // by ARM/AArch64.
163
    LLOnly,  // Expand the (load) instruction into just a load-linked, which has
164
             // greater atomic guarantees than a normal load.
165
    CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
166
  };
167
168
  /// Enum that specifies when a multiplication should be expanded.
169
  enum class MulExpansionKind {
170
    Always,            // Always expand the instruction.
171
    OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
172
                       // or custom.
173
  };
174
175
  class ArgListEntry {
176
  public:
177
    Value *Val = nullptr;
178
    SDValue Node = SDValue();
179
    Type *Ty = nullptr;
180
    bool IsSExt : 1;
181
    bool IsZExt : 1;
182
    bool IsInReg : 1;
183
    bool IsSRet : 1;
184
    bool IsNest : 1;
185
    bool IsByVal : 1;
186
    bool IsInAlloca : 1;
187
    bool IsReturned : 1;
188
    bool IsSwiftSelf : 1;
189
    bool IsSwiftError : 1;
190
    uint16_t Alignment = 0;
191
192
    ArgListEntry()
193
        : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
194
          IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
195
1.76M
          IsSwiftSelf(false), IsSwiftError(false) {}
196
197
    void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx);
198
  };
199
  using ArgListTy = std::vector<ArgListEntry>;
200
201
  virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
202
16.8k
                                     ArgListTy &Args) const {};
203
204
289k
  static ISD::NodeType getExtendForContent(BooleanContent Content) {
205
289k
    switch (Content) {
206
289k
    case UndefinedBooleanContent:
207
104
      // Extend by adding rubbish bits.
208
104
      return ISD::ANY_EXTEND;
209
289k
    case ZeroOrOneBooleanContent:
210
288k
      // Extend by adding zero bits.
211
288k
      return ISD::ZERO_EXTEND;
212
289k
    case ZeroOrNegativeOneBooleanContent:
213
918
      // Extend by copying the sign bit.
214
918
      return ISD::SIGN_EXTEND;
215
0
    }
216
0
    llvm_unreachable("Invalid content kind");
217
0
  }
218
219
  /// NOTE: The TargetMachine owns TLOF.
220
  explicit TargetLoweringBase(const TargetMachine &TM);
221
  TargetLoweringBase(const TargetLoweringBase &) = delete;
222
  TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
223
32.6k
  virtual ~TargetLoweringBase() = default;
224
225
protected:
226
  /// Initialize all of the actions to default values.
227
  void initActions();
228
229
public:
230
11.1M
  const TargetMachine &getTargetMachine() const { return TM; }
231
232
3.07M
  virtual bool useSoftFloat() const { return false; }
233
234
  /// Return the pointer type for the given address space, defaults to
235
  /// the pointer type from the data layout.
236
  /// FIXME: The default needs to be removed once all the code is updated.
237
28.8M
  MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
238
28.8M
    return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
239
28.8M
  }
240
241
  /// Return the type for frame index, which is determined by
242
  /// the alloca address space specified through the data layout.
243
500k
  MVT getFrameIndexTy(const DataLayout &DL) const {
244
500k
    return getPointerTy(DL, DL.getAllocaAddrSpace());
245
500k
  }
246
247
  /// Return the type for operands of fence.
248
  /// TODO: Let fence operands be of i32 type and remove this.
249
7.82k
  virtual MVT getFenceOperandTy(const DataLayout &DL) const {
250
7.82k
    return getPointerTy(DL);
251
7.82k
  }
252
253
  /// EVT is not used in-tree, but is used by out-of-tree target.
254
  /// A documentation for this function would be nice...
255
  virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
256
257
  EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
258
                       bool LegalTypes = true) const;
259
260
  /// Returns the type to be used for the index operand of:
261
  /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
262
  /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
263
234k
  virtual MVT getVectorIdxTy(const DataLayout &DL) const {
264
234k
    return getPointerTy(DL);
265
234k
  }
266
267
250k
  virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
268
250k
    return true;
269
250k
  }
270
271
  /// Return true if multiple condition registers are available.
272
3.55M
  bool hasMultipleConditionRegisters() const {
273
3.55M
    return HasMultipleConditionRegisters;
274
3.55M
  }
275
276
  /// Return true if the target has BitExtract instructions.
277
175k
  bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
278
279
  /// Return the preferred vector type legalization action.
280
  virtual TargetLoweringBase::LegalizeTypeAction
281
3.49M
  getPreferredVectorAction(EVT VT) const {
282
3.49M
    // The default action for one element vectors is to scalarize
283
3.49M
    if (VT.getVectorNumElements() == 1)
284
562k
      return TypeScalarizeVector;
285
2.93M
    // The default action for other vectors is to promote
286
2.93M
    return TypePromoteInteger;
287
2.93M
  }
288
289
  // There are two general methods for expanding a BUILD_VECTOR node:
290
  //  1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
291
  //     them together.
292
  //  2. Build the vector on the stack and then load it.
293
  // If this function returns true, then method (1) will be used, subject to
294
  // the constraint that all of the necessary shuffles are legal (as determined
295
  // by isShuffleMaskLegal). If this function returns false, then method (2) is
296
  // always used. The vector type, and the number of defined values, are
297
  // provided.
298
  virtual bool
299
  shouldExpandBuildVectorWithShuffles(EVT /* VT */,
300
1.93k
                                      unsigned DefinedValues) const {
301
1.93k
    return DefinedValues < 3;
302
1.93k
  }
303
304
  /// Return true if integer divide is usually cheaper than a sequence of
305
  /// several shifts, adds, and multiplies for this target.
306
  /// The definition of "cheaper" may depend on whether we're optimizing
307
  /// for speed or for size.
308
634
  virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
309
310
  /// Return true if the target can handle a standalone remainder operation.
311
0
  virtual bool hasStandaloneRem(EVT VT) const {
312
0
    return true;
313
0
  }
314
315
  /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
316
82
  virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
317
82
    // Default behavior is to replace SQRT(X) with X*RSQRT(X).
318
82
    return false;
319
82
  }
320
321
  /// Reciprocal estimate status values used by the functions below.
322
  enum ReciprocalEstimate : int {
323
    Unspecified = -1,
324
    Disabled = 0,
325
    Enabled = 1
326
  };
327
328
  /// Return a ReciprocalEstimate enum value for a square root of the given type
329
  /// based on the function's attributes. If the operation is not overridden by
330
  /// the function's attributes, "Unspecified" is returned and target defaults
331
  /// are expected to be used for instruction selection.
332
  int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
333
334
  /// Return a ReciprocalEstimate enum value for a division of the given type
335
  /// based on the function's attributes. If the operation is not overridden by
336
  /// the function's attributes, "Unspecified" is returned and target defaults
337
  /// are expected to be used for instruction selection.
338
  int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
339
340
  /// Return the refinement step count for a square root of the given type based
341
  /// on the function's attributes. If the operation is not overridden by
342
  /// the function's attributes, "Unspecified" is returned and target defaults
343
  /// are expected to be used for instruction selection.
344
  int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
345
346
  /// Return the refinement step count for a division of the given type based
347
  /// on the function's attributes. If the operation is not overridden by
348
  /// the function's attributes, "Unspecified" is returned and target defaults
349
  /// are expected to be used for instruction selection.
350
  int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
351
352
  /// Returns true if target has indicated at least one type should be bypassed.
353
441k
  bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
354
355
  /// Returns map of slow types for division or remainder with corresponding
356
  /// fast types
357
17.3k
  const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
358
17.3k
    return BypassSlowDivWidths;
359
17.3k
  }
360
361
  /// Return true if Flow Control is an expensive operation that should be
362
  /// avoided.
363
61.9k
  bool isJumpExpensive() const { return JumpIsExpensive; }
364
365
  /// Return true if selects are only cheaper than branches if the branch is
366
  /// unlikely to be predicted right.
367
259k
  bool isPredictableSelectExpensive() const {
368
259k
    return PredictableSelectIsExpensive;
369
259k
  }
370
371
  /// If a branch or a select condition is skewed in one direction by more than
372
  /// this factor, it is very likely to be predicted correctly.
373
  virtual BranchProbability getPredictableBranchThreshold() const;
374
375
  /// Return true if the following transform is beneficial:
376
  /// fold (conv (load x)) -> (load (conv*)x)
377
  /// On architectures that don't natively support some vector loads
378
  /// efficiently, casting the load to a smaller vector of larger types and
379
  /// loading is more efficient, however, this can be undone by optimizations in
380
  /// dag combiner.
381
  virtual bool isLoadBitCastBeneficial(EVT LoadVT,
382
17.0k
                                       EVT BitcastVT) const {
383
17.0k
    // Don't do if we could do an indexed load on the original type, but not on
384
17.0k
    // the new one.
385
17.0k
    if (!LoadVT.isSimple() || 
!BitcastVT.isSimple()17.0k
)
386
67
      return true;
387
17.0k
388
17.0k
    MVT LoadMVT = LoadVT.getSimpleVT();
389
17.0k
390
17.0k
    // Don't bother doing this if it's just going to be promoted again later, as
391
17.0k
    // doing so might interfere with other combines.
392
17.0k
    if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
393
17.0k
        
getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT()7.47k
)
394
6.05k
      return false;
395
10.9k
396
10.9k
    return true;
397
10.9k
  }
398
399
  /// Return true if the following transform is beneficial:
400
  /// (store (y (conv x)), y*)) -> (store x, (x*))
401
20.9k
  virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {
402
20.9k
    // Default to the same logic as loads.
403
20.9k
    return isLoadBitCastBeneficial(StoreVT, BitcastVT);
404
20.9k
  }
405
406
  /// Return true if it is expected to be cheaper to do a store of a non-zero
407
  /// vector constant with the given size and type for the address space than to
408
  /// store the individual scalar element constants.
409
  virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
410
                                            unsigned NumElem,
411
201k
                                            unsigned AddrSpace) const {
412
201k
    return false;
413
201k
  }
414
415
  /// Allow store merging after legalization in addition to before legalization.
416
  /// This may catch stores that do not exist earlier (eg, stores created from
417
  /// intrinsics).
418
1.29M
  virtual bool mergeStoresAfterLegalization() const { return true; }
419
420
  /// Returns if it's reasonable to merge stores to MemVT size.
421
  virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
422
7.73k
                                const SelectionDAG &DAG) const {
423
7.73k
    return true;
424
7.73k
  }
425
426
  /// Return true if it is cheap to speculate a call to intrinsic cttz.
427
8
  virtual bool isCheapToSpeculateCttz() const {
428
8
    return false;
429
8
  }
430
431
  /// Return true if it is cheap to speculate a call to intrinsic ctlz.
432
5
  virtual bool isCheapToSpeculateCtlz() const {
433
5
    return false;
434
5
  }
435
436
  /// Return true if ctlz instruction is fast.
437
0
  virtual bool isCtlzFast() const {
438
0
    return false;
439
0
  }
440
441
  /// Return true if it is safe to transform an integer-domain bitwise operation
442
  /// into the equivalent floating-point operation. This should be set to true
443
  /// if the target has IEEE-754-compliant fabs/fneg operations for the input
444
  /// type.
445
19.9k
  virtual bool hasBitPreservingFPLogic(EVT VT) const {
446
19.9k
    return false;
447
19.9k
  }
448
449
  /// Return true if it is cheaper to split the store of a merged int val
450
  /// from a pair of smaller values into multiple stores.
451
506
  virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
452
506
    return false;
453
506
  }
454
455
  /// Return if the target supports combining a
456
  /// chain like:
457
  /// \code
458
  ///   %andResult = and %val1, #mask
459
  ///   %icmpResult = icmp %andResult, 0
460
  /// \endcode
461
  /// into a single machine instruction of a form like:
462
  /// \code
463
  ///   cc = test %register, #mask
464
  /// \endcode
465
89
  virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
466
89
    return false;
467
89
  }
468
469
  /// Use bitwise logic to make pairs of compares more efficient. For example:
470
  /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
471
  /// This should be true when it takes more than one instruction to lower
472
  /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
473
  /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
474
7.03k
  virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
475
7.03k
    return false;
476
7.03k
  }
477
478
  /// Return the preferred operand type if the target has a quick way to compare
479
  /// integer values of the given size. Assume that any legal integer type can
480
  /// be compared efficiently. Targets may override this to allow illegal wide
481
  /// types to return a vector type if there is support to compare that type.
482
29
  virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
483
29
    MVT VT = MVT::getIntegerVT(NumBits);
484
29
    return isTypeLegal(VT) ? 
VT10
:
MVT::INVALID_SIMPLE_VALUE_TYPE19
;
485
29
  }
486
487
  /// Return true if the target should transform:
488
  /// (X & Y) == Y ---> (~X & Y) == 0
489
  /// (X & Y) != Y ---> (~X & Y) != 0
490
  ///
491
  /// This may be profitable if the target has a bitwise and-not operation that
492
  /// sets comparison flags. A target may want to limit the transformation based
493
  /// on the type of Y or if Y is a constant.
494
  ///
495
  /// Note that the transform will not occur if Y is known to be a power-of-2
496
  /// because a mask and compare of a single bit can be handled by inverting the
497
  /// predicate, for example:
498
  /// (X & 8) == 8 ---> (X & 8) != 0
499
619
  virtual bool hasAndNotCompare(SDValue Y) const {
500
619
    return false;
501
619
  }
502
503
  /// Return true if the target has a bitwise and-not operation:
504
  /// X = ~A & B
505
  /// This can be used to simplify select or other instructions.
506
710
  virtual bool hasAndNot(SDValue X) const {
507
710
    // If the target has the more complex version of this operation, assume that
508
710
    // it has this operation too.
509
710
    return hasAndNotCompare(X);
510
710
  }
511
512
  /// There are two ways to clear extreme bits (either low or high):
513
  /// Mask:    x &  (-1 << y)  (the instcombine canonical form)
514
  /// Shifts:  x >> y << y
515
  /// Return true if the variant with 2 shifts is preferred.
516
  /// Return false if there is no preference.
517
276k
  virtual bool preferShiftsToClearExtremeBits(SDValue X) const {
518
276k
    // By default, let's assume that no one prefers shifts.
519
276k
    return false;
520
276k
  }
521
522
  /// Return true if the target wants to use the optimization that
523
  /// turns ext(promotableInst1(...(promotableInstN(load)))) into
524
  /// promotedInst1(...(promotedInstN(ext(load)))).
525
512k
  bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
526
527
  /// Return true if the target can combine store(extractelement VectorTy,
528
  /// Idx).
529
  /// \p Cost[out] gives the cost of that transformation when this is true.
530
  virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
531
40.8k
                                         unsigned &Cost) const {
532
40.8k
    return false;
533
40.8k
  }
534
535
  /// Return true if target supports floating point exceptions.
536
10.5M
  bool hasFloatingPointExceptions() const {
537
10.5M
    return HasFloatingPointExceptions;
538
10.5M
  }
539
540
  /// Return true if target always beneficiates from combining into FMA for a
541
  /// given value type. This must typically return false on targets where FMA
542
  /// takes more cycles to execute than FADD.
543
4.42k
  virtual bool enableAggressiveFMAFusion(EVT VT) const {
544
4.42k
    return false;
545
4.42k
  }
546
547
  /// Return the ValueType of the result of SETCC operations.
548
  virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
549
                                 EVT VT) const;
550
551
  /// Return the ValueType for comparison libcalls. Comparions libcalls include
552
  /// floating point comparion calls, and Ordered/Unordered check calls on
553
  /// floating point numbers.
554
  virtual
555
  MVT::SimpleValueType getCmpLibcallReturnType() const;
556
557
  /// For targets without i1 registers, this gives the nature of the high-bits
558
  /// of boolean values held in types wider than i1.
559
  ///
560
  /// "Boolean values" are special true/false values produced by nodes like
561
  /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
562
  /// Not to be confused with general values promoted from i1.  Some cpus
563
  /// distinguish between vectors of boolean and scalars; the isVec parameter
564
  /// selects between the two kinds.  For example on X86 a scalar boolean should
565
  /// be zero extended from i1, while the elements of a vector of booleans
566
  /// should be sign extended from i1.
567
  ///
568
  /// Some cpus also treat floating point types the same way as they treat
569
  /// vectors instead of the way they treat scalars.
570
1.76M
  BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
571
1.76M
    if (isVec)
572
258k
      return BooleanVectorContents;
573
1.50M
    return isFloat ? 
BooleanFloatContents36.4k
:
BooleanContents1.46M
;
574
1.50M
  }
575
576
1.74M
  BooleanContent getBooleanContents(EVT Type) const {
577
1.74M
    return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
578
1.74M
  }
579
580
  /// Return target scheduling preference.
581
306k
  Sched::Preference getSchedulingPreference() const {
582
306k
    return SchedPreferenceInfo;
583
306k
  }
584
585
  /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
586
  /// for different nodes. This function returns the preference (or none) for
587
  /// the given node.
588
14.8M
  virtual Sched::Preference getSchedulingPreference(SDNode *) const {
589
14.8M
    return Sched::None;
590
14.8M
  }
591
592
  /// Return the register class that should be used for the specified value
593
  /// type.
594
23.0M
  virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
595
23.0M
    const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
596
23.0M
    assert(RC && "This value type is not natively supported!");
597
23.0M
    return RC;
598
23.0M
  }
599
600
  /// Return the 'representative' register class for the specified value
601
  /// type.
602
  ///
603
  /// The 'representative' register class is the largest legal super-reg
604
  /// register class for the register class of the value type.  For example, on
605
  /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
606
  /// register class is GR64 on x86_64.
607
2.06M
  virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
608
2.06M
    const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
609
2.06M
    return RC;
610
2.06M
  }
611
612
  /// Return the cost of the 'representative' register class for the specified
613
  /// value type.
614
1.72M
  virtual uint8_t getRepRegClassCostFor(MVT VT) const {
615
1.72M
    return RepRegClassCostForVT[VT.SimpleTy];
616
1.72M
  }
617
618
  /// Return true if the target has native support for the specified value type.
619
  /// This means that it has a register that directly holds it without
620
  /// promotions or expansions.
621
569M
  bool isTypeLegal(EVT VT) const {
622
569M
    assert(!VT.isSimple() ||
623
569M
           (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
624
569M
    return VT.isSimple() && 
RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr568M
;
625
569M
  }
626
627
  class ValueTypeActionImpl {
628
    /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
629
    /// that indicates how instruction selection should deal with the type.
630
    LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
631
632
  public:
633
44.3k
    ValueTypeActionImpl() {
634
44.3k
      std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
635
44.3k
                TypeLegal);
636
44.3k
    }
637
638
110M
    LegalizeTypeAction getTypeAction(MVT VT) const {
639
110M
      return ValueTypeActions[VT.SimpleTy];
640
110M
    }
641
642
4.19M
    void setTypeAction(MVT VT, LegalizeTypeAction Action) {
643
4.19M
      ValueTypeActions[VT.SimpleTy] = Action;
644
4.19M
    }
645
  };
646
647
1.76M
  const ValueTypeActionImpl &getValueTypeActions() const {
648
1.76M
    return ValueTypeActions;
649
1.76M
  }
650
651
  /// Return how we should legalize values of this type, either it is already
652
  /// legal (return 'Legal') or we need to promote it to a larger type (return
653
  /// 'Promote'), or we need to expand it into multiple registers of smaller
654
  /// integer type (return 'Expand').  'Custom' is not an option.
655
103M
  LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
656
103M
    return getTypeConversion(Context, VT).first;
657
103M
  }
658
0
  LegalizeTypeAction getTypeAction(MVT VT) const {
659
0
    return ValueTypeActions.getTypeAction(VT);
660
0
  }
661
662
  /// For types supported by the target, this is an identity function.  For
663
  /// types that must be promoted to larger types, this returns the larger type
664
  /// to promote to.  For integer types that are larger than the largest integer
665
  /// register, this contains one step in the expansion to get to the smaller
666
  /// register. For illegal floating point types, this returns the integer type
667
  /// to transform to.
668
1.51M
  EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
669
1.51M
    return getTypeConversion(Context, VT).second;
670
1.51M
  }
671
672
  /// For types supported by the target, this is an identity function.  For
673
  /// types that must be expanded (i.e. integer types that are larger than the
674
  /// largest integer register or illegal floating point types), this returns
675
  /// the largest legal type it will be expanded to.
676
15.2k
  EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
677
15.2k
    assert(!VT.isVector());
678
16.6k
    while (true) {
679
16.6k
      switch (getTypeAction(Context, VT)) {
680
16.6k
      case TypeLegal:
681
15.2k
        return VT;
682
16.6k
      case TypeExpandInteger:
683
1.38k
        VT = getTypeToTransformTo(Context, VT);
684
1.38k
        break;
685
16.6k
      default:
686
0
        llvm_unreachable("Type is not legal nor is it to be expanded!");
687
16.6k
      }
688
16.6k
    }
689
15.2k
  }
690
691
  /// Vector types are broken down into some number of legal first class types.
692
  /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
693
  /// promoted EVT::f64 values with the X86 FP stack.  Similarly, EVT::v2i64
694
  /// turns into 4 EVT::i32 values with both PPC and X86.
695
  ///
696
  /// This method returns the number of registers needed, and the VT for each
697
  /// register.  It also returns the VT and quantity of the intermediate values
698
  /// before they are promoted/expanded.
699
  unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
700
                                  EVT &IntermediateVT,
701
                                  unsigned &NumIntermediates,
702
                                  MVT &RegisterVT) const;
703
704
  /// Certain targets such as MIPS require that some types such as vectors are
705
  /// always broken down into scalars in some contexts. This occurs even if the
706
  /// vector type is legal.
707
  virtual unsigned getVectorTypeBreakdownForCallingConv(
708
      LLVMContext &Context, EVT VT, EVT &IntermediateVT,
709
11.2k
      unsigned &NumIntermediates, MVT &RegisterVT) const {
710
11.2k
    return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
711
11.2k
                                  RegisterVT);
712
11.2k
  }
713
714
  struct IntrinsicInfo {
715
    unsigned     opc = 0;          // target opcode
716
    EVT          memVT;            // memory VT
717
718
    // value representing memory location
719
    PointerUnion<const Value *, const PseudoSourceValue *> ptrVal;
720
721
    int          offset = 0;       // offset off of ptrVal
722
    unsigned     size = 0;         // the size of the memory location
723
                                   // (taken from memVT if zero)
724
    unsigned     align = 1;        // alignment
725
726
    MachineMemOperand::Flags flags = MachineMemOperand::MONone;
727
294k
    IntrinsicInfo() = default;
728
  };
729
730
  /// Given an intrinsic, checks if on the target the intrinsic will need to map
731
  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
732
  /// true and store the intrinsic information into the IntrinsicInfo that was
733
  /// passed to the function.
734
  virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
735
                                  MachineFunction &,
736
3.91k
                                  unsigned /*Intrinsic*/) const {
737
3.91k
    return false;
738
3.91k
  }
739
740
  /// Returns true if the target can instruction select the specified FP
741
  /// immediate natively. If false, the legalizer will materialize the FP
742
  /// immediate as a load from a constant pool.
743
78
  virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
744
78
    return false;
745
78
  }
746
747
  /// Targets can use this to indicate that they only support *some*
748
  /// VECTOR_SHUFFLE operations, those with specific masks.  By default, if a
749
  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
750
  /// legal.
751
566
  virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
752
566
    return true;
753
566
  }
754
755
  /// Returns true if the operation can trap for the value type.
756
  ///
757
  /// VT must be a legal type. By default, we optimistically assume most
758
  /// operations don't trap except for integer divide and remainder.
759
  virtual bool canOpTrap(unsigned Op, EVT VT) const;
760
761
  /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
762
  /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
763
  /// constant pool entry.
764
  virtual bool isVectorClearMaskLegal(ArrayRef<int> /*Mask*/,
765
12.1k
                                      EVT /*VT*/) const {
766
12.1k
    return false;
767
12.1k
  }
768
769
  /// Return how this operation should be treated: either it is legal, needs to
770
  /// be promoted to a larger size, needs to be expanded to some other code
771
  /// sequence, or the target has a custom expander for it.
772
120M
  LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
773
120M
    if (VT.isExtended()) 
return Expand174k
;
774
120M
    // If a target-specific SDNode requires legalization, require the target
775
120M
    // to provide custom legalization for it.
776
120M
    if (Op >= array_lengthof(OpActions[0])) 
return Custom86
;
777
120M
    return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
778
120M
  }
779
780
182
  LegalizeAction getStrictFPOperationAction(unsigned Op, EVT VT) const {
781
182
    unsigned EqOpc;
782
182
    switch (Op) {
783
182
      
default: 0
llvm_unreachable0
("Unexpected FP pseudo-opcode");
784
182
      
case ISD::STRICT_FADD: EqOpc = ISD::FADD; break12
;
785
182
      
case ISD::STRICT_FSUB: EqOpc = ISD::FSUB; break20
;
786
182
      
case ISD::STRICT_FMUL: EqOpc = ISD::FMUL; break12
;
787
182
      
case ISD::STRICT_FDIV: EqOpc = ISD::FDIV; break12
;
788
182
      
case ISD::STRICT_FSQRT: EqOpc = ISD::FSQRT; break12
;
789
182
      
case ISD::STRICT_FPOW: EqOpc = ISD::FPOW; break8
;
790
182
      
case ISD::STRICT_FPOWI: EqOpc = ISD::FPOWI; break8
;
791
182
      
case ISD::STRICT_FMA: EqOpc = ISD::FMA; break22
;
792
182
      
case ISD::STRICT_FSIN: EqOpc = ISD::FSIN; break8
;
793
182
      
case ISD::STRICT_FCOS: EqOpc = ISD::FCOS; break8
;
794
182
      
case ISD::STRICT_FEXP: EqOpc = ISD::FEXP; break8
;
795
182
      
case ISD::STRICT_FEXP2: EqOpc = ISD::FEXP2; break8
;
796
182
      
case ISD::STRICT_FLOG: EqOpc = ISD::FLOG; break8
;
797
182
      
case ISD::STRICT_FLOG10: EqOpc = ISD::FLOG10; break8
;
798
182
      
case ISD::STRICT_FLOG2: EqOpc = ISD::FLOG2; break8
;
799
182
      
case ISD::STRICT_FRINT: EqOpc = ISD::FRINT; break10
;
800
182
      
case ISD::STRICT_FNEARBYINT: EqOpc = ISD::FNEARBYINT; break10
;
801
182
    }
802
182
803
182
    auto Action = getOperationAction(EqOpc, VT);
804
182
805
182
    // We don't currently handle Custom or Promote for strict FP pseudo-ops.
806
182
    // For now, we just expand for those cases.
807
182
    if (Action != Legal)
808
90
      Action = Expand;
809
182
810
182
    return Action;
811
182
  }
812
813
  /// Return true if the specified operation is legal on this target or can be
814
  /// made legal with custom lowering. This is used to help guide high-level
815
  /// lowering decisions.
816
26.4M
  bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
817
26.4M
    return (VT == MVT::Other || 
isTypeLegal(VT)26.2M
) &&
818
26.4M
      
(21.4M
getOperationAction(Op, VT) == Legal21.4M
||
819
21.4M
       
getOperationAction(Op, VT) == Custom12.9M
);
820
26.4M
  }
821
822
  /// Return true if the specified operation is legal on this target or can be
823
  /// made legal using promotion. This is used to help guide high-level lowering
824
  /// decisions.
825
548k
  bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
826
548k
    return (VT == MVT::Other || isTypeLegal(VT)) &&
827
548k
      
(548k
getOperationAction(Op, VT) == Legal548k
||
828
548k
       
getOperationAction(Op, VT) == Promote62.0k
);
829
548k
  }
830
831
  /// Return true if the specified operation is legal on this target or can be
832
  /// made legal with custom lowering or using promotion. This is used to help
833
  /// guide high-level lowering decisions.
834
636k
  bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
835
636k
    return (VT == MVT::Other || isTypeLegal(VT)) &&
836
636k
      
(630k
getOperationAction(Op, VT) == Legal630k
||
837
630k
       
getOperationAction(Op, VT) == Custom56.9k
||
838
630k
       
getOperationAction(Op, VT) == Promote46.0k
);
839
636k
  }
840
841
  /// Return true if the operation uses custom lowering, regardless of whether
842
  /// the type is legal or not.
843
991
  bool isOperationCustom(unsigned Op, EVT VT) const {
844
991
    return getOperationAction(Op, VT) == Custom;
845
991
  }
846
847
  /// Return true if lowering to a jump table is allowed.
848
49.4k
  virtual bool areJTsAllowed(const Function *Fn) const {
849
49.4k
    if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
850
2
      return false;
851
49.4k
852
49.4k
    return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
853
49.4k
           
isOperationLegalOrCustom(ISD::BRIND, MVT::Other)46.5k
;
854
49.4k
  }
855
856
  /// Check whether the range [Low,High] fits in a machine word.
857
  bool rangeFitsInWord(const APInt &Low, const APInt &High,
858
60.9k
                       const DataLayout &DL) const {
859
60.9k
    // FIXME: Using the pointer type doesn't seem ideal.
860
60.9k
    uint64_t BW = DL.getIndexSizeInBits(0u);
861
60.9k
    uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
862
60.9k
    return Range <= BW;
863
60.9k
  }
864
865
  /// Return true if lowering to a jump table is suitable for a set of case
866
  /// clusters which may contain \p NumCases cases, \p Range range of values.
867
  /// FIXME: This function check the maximum table size and density, but the
868
  /// minimum size is not checked. It would be nice if the minimum size is
869
  /// also combined within this function. Currently, the minimum size check is
870
  /// performed in findJumpTable() in SelectionDAGBuiler and
871
  /// getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
872
  virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
873
26.1k
                                      uint64_t Range) const {
874
26.1k
    const bool OptForSize = SI->getParent()->getParent()->optForSize();
875
26.1k
    const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
876
26.1k
    const unsigned MaxJumpTableSize =
877
26.1k
        OptForSize || 
getMaximumJumpTableSize() == 026.0k
878
26.1k
            ? UINT_MAX
879
26.1k
            : 
getMaximumJumpTableSize()461
;
880
26.1k
    // Check whether a range of clusters is dense enough for a jump table.
881
26.1k
    if (Range <= MaxJumpTableSize &&
882
26.1k
        
(NumCases * 100 >= Range * MinDensity)25.8k
) {
883
19.1k
      return true;
884
19.1k
    }
885
6.90k
    return false;
886
6.90k
  }
887
888
  /// Return true if lowering to a bit test is suitable for a set of case
889
  /// clusters which contains \p NumDests unique destinations, \p Low and
890
  /// \p High as its lowest and highest case values, and expects \p NumCmps
891
  /// case value comparisons. Check if the number of destinations, comparison
892
  /// metric, and range are all suitable.
893
  bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
894
                             const APInt &Low, const APInt &High,
895
47.9k
                             const DataLayout &DL) const {
896
47.9k
    // FIXME: I don't think NumCmps is the correct metric: a single case and a
897
47.9k
    // range of cases both require only one branch to lower. Just looking at the
898
47.9k
    // number of clusters and destinations should be enough to decide whether to
899
47.9k
    // build bit tests.
900
47.9k
901
47.9k
    // To lower a range with bit tests, the range must fit the bitwidth of a
902
47.9k
    // machine word.
903
47.9k
    if (!rangeFitsInWord(Low, High, DL))
904
7.67k
      return false;
905
40.3k
906
40.3k
    // Decide whether it's profitable to lower this range with bit tests. Each
907
40.3k
    // destination requires a bit test and branch, and there is an overall range
908
40.3k
    // check branch. For a small number of clusters, separate comparisons might
909
40.3k
    // be cheaper, and for many destinations, splitting the range might be
910
40.3k
    // better.
911
40.3k
    return (NumDests == 1 && 
NumCmps >= 38.92k
) ||
(35.6k
NumDests == 235.6k
&&
NumCmps >= 519.1k
) ||
912
40.3k
           
(35.0k
NumDests == 335.0k
&&
NumCmps >= 63.66k
);
913
40.3k
  }
914
915
  /// Return true if the specified operation is illegal on this target or
916
  /// unlikely to be made legal with custom lowering. This is used to help guide
917
  /// high-level lowering decisions.
918
251k
  bool isOperationExpand(unsigned Op, EVT VT) const {
919
251k
    return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
920
251k
  }
921
922
  /// Return true if the specified operation is legal on this target.
923
3.18M
  bool isOperationLegal(unsigned Op, EVT VT) const {
924
3.18M
    return (VT == MVT::Other || isTypeLegal(VT)) &&
925
3.18M
           
getOperationAction(Op, VT) == Legal3.14M
;
926
3.18M
  }
927
928
  /// Return how this load with extension should be treated: either it is legal,
929
  /// needs to be promoted to a larger size, needs to be expanded to some other
930
  /// code sequence, or the target has a custom expander for it.
931
  LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
932
1.40M
                                  EVT MemVT) const {
933
1.40M
    if (ValVT.isExtended() || 
MemVT.isExtended()1.40M
)
return Expand2.10k
;
934
1.40M
    unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
935
1.40M
    unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
936
1.40M
    assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
937
1.40M
           MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
938
1.40M
    unsigned Shift = 4 * ExtType;
939
1.40M
    return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
940
1.40M
  }
941
942
  /// Return true if the specified load with extension is legal on this target.
943
902k
  bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
944
902k
    return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
945
902k
  }
946
947
  /// Return true if the specified load with extension is legal or custom
948
  /// on this target.
949
2.03k
  bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
950
2.03k
    return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
951
2.03k
           
getLoadExtAction(ExtType, ValVT, MemVT) == Custom1.84k
;
952
2.03k
  }
953
954
  /// Return how this store with truncation should be treated: either it is
955
  /// legal, needs to be promoted to a larger size, needs to be expanded to some
956
  /// other code sequence, or the target has a custom expander for it.
957
576k
  LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
958
576k
    if (ValVT.isExtended() || MemVT.isExtended()) 
return Expand180k
;
959
395k
    unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
960
395k
    unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
961
395k
    assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
962
395k
           "Table isn't big enough!");
963
395k
    return TruncStoreActions[ValI][MemI];
964
395k
  }
965
966
  /// Return true if the specified store with truncation is legal on this
967
  /// target.
968
281k
  bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
969
281k
    return isTypeLegal(ValVT) && 
getTruncStoreAction(ValVT, MemVT) == Legal246k
;
970
281k
  }
971
972
  /// Return true if the specified store with truncation has solution on this
973
  /// target.
974
2.09k
  bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
975
2.09k
    return isTypeLegal(ValVT) &&
976
2.09k
      (getTruncStoreAction(ValVT, MemVT) == Legal ||
977
2.09k
       
getTruncStoreAction(ValVT, MemVT) == Custom1.19k
);
978
2.09k
  }
979
980
  /// Return how the indexed load should be treated: either it is legal, needs
981
  /// to be promoted to a larger size, needs to be expanded to some other code
982
  /// sequence, or the target has a custom expander for it.
983
  LegalizeAction
984
5.19M
  getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
985
5.19M
    assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
986
5.19M
           "Table isn't big enough!");
987
5.19M
    unsigned Ty = (unsigned)VT.SimpleTy;
988
5.19M
    return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
989
5.19M
  }
990
991
  /// Return true if the specified indexed load is legal on this target.
992
3.39M
  bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
993
3.39M
    return VT.isSimple() &&
994
3.39M
      (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
995
3.39M
       
getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom1.80M
);
996
3.39M
  }
997
998
  /// Return how the indexed store should be treated: either it is legal, needs
999
  /// to be promoted to a larger size, needs to be expanded to some other code
1000
  /// sequence, or the target has a custom expander for it.
1001
  LegalizeAction
1002
5.75M
  getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
1003
5.75M
    assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1004
5.75M
           "Table isn't big enough!");
1005
5.75M
    unsigned Ty = (unsigned)VT.SimpleTy;
1006
5.75M
    return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
1007
5.75M
  }
1008
1009
  /// Return true if the specified indexed load is legal on this target.
1010
3.65M
  bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
1011
3.65M
    return VT.isSimple() &&
1012
3.65M
      (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
1013
3.65M
       
getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom2.10M
);
1014
3.65M
  }
1015
1016
  /// Return how the condition code should be treated: either it is legal, needs
1017
  /// to be expanded to some other code sequence, or the target has a custom
1018
  /// expander for it.
1019
  LegalizeAction
1020
858k
  getCondCodeAction(ISD::CondCode CC, MVT VT) const {
1021
858k
    assert((unsigned)CC < array_lengthof(CondCodeActions) &&
1022
858k
           ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
1023
858k
           "Table isn't big enough!");
1024
858k
    // See setCondCodeAction for how this is encoded.
1025
858k
    uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1026
858k
    uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
1027
858k
    LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
1028
858k
    assert(Action != Promote && "Can't promote condition code!");
1029
858k
    return Action;
1030
858k
  }
1031
1032
  /// Return true if the specified condition code is legal on this target.
1033
26.6k
  bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
1034
26.6k
    return getCondCodeAction(CC, VT) == Legal;
1035
26.6k
  }
1036
1037
  /// Return true if the specified condition code is legal or custom on this
1038
  /// target.
1039
2.54k
  bool isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) const {
1040
2.54k
    return getCondCodeAction(CC, VT) == Legal ||
1041
2.54k
           
getCondCodeAction(CC, VT) == Custom803
;
1042
2.54k
  }
1043
1044
  /// If the action for this operation is to promote, this method returns the
1045
  /// ValueType to promote to.
1046
266k
  MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
1047
266k
    assert(getOperationAction(Op, VT) == Promote &&
1048
266k
           "This operation isn't promoted!");
1049
266k
1050
266k
    // See if this has an explicit type specified.
1051
266k
    std::map<std::pair<unsigned, MVT::SimpleValueType>,
1052
266k
             MVT::SimpleValueType>::const_iterator PTTI =
1053
266k
      PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1054
266k
    if (PTTI != PromoteToType.end()) 
return PTTI->second265k
;
1055
856
1056
856
    assert((VT.isInteger() || VT.isFloatingPoint()) &&
1057
856
           "Cannot autopromote this type, add it with AddPromotedToType.");
1058
856
1059
856
    MVT NVT = VT;
1060
920
    do {
1061
920
      NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1062
920
      assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1063
920
             "Didn't find type to promote to!");
1064
920
    } while (!isTypeLegal(NVT) ||
1065
920
              
getOperationAction(Op, NVT) == Promote914
);
1066
856
    return NVT;
1067
856
  }
1068
1069
  /// Return the EVT corresponding to this LLVM type.  This is fixed by the LLVM
1070
  /// operations except for the pointer size.  If AllowUnknown is true, this
1071
  /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1072
  /// otherwise it will assert.
1073
  EVT getValueType(const DataLayout &DL, Type *Ty,
1074
62.1M
                   bool AllowUnknown = false) const {
1075
62.1M
    // Lower scalar pointers to native pointer types.
1076
62.1M
    if (PointerType *PTy = dyn_cast<PointerType>(Ty))
1077
20.6M
      return getPointerTy(DL, PTy->getAddressSpace());
1078
41.4M
1079
41.4M
    if (Ty->isVectorTy()) {
1080
5.68M
      VectorType *VTy = cast<VectorType>(Ty);
1081
5.68M
      Type *Elm = VTy->getElementType();
1082
5.68M
      // Lower vectors of pointers to native pointer types.
1083
5.68M
      if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
1084
293k
        EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
1085
293k
        Elm = PointerTy.getTypeForEVT(Ty->getContext());
1086
293k
      }
1087
5.68M
1088
5.68M
      return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1089
5.68M
                       VTy->getNumElements());
1090
5.68M
    }
1091
35.7M
    return EVT::getEVT(Ty, AllowUnknown);
1092
35.7M
  }
1093
1094
  /// Return the MVT corresponding to this LLVM type. See getValueType.
1095
  MVT getSimpleValueType(const DataLayout &DL, Type *Ty,
1096
21.8k
                         bool AllowUnknown = false) const {
1097
21.8k
    return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1098
21.8k
  }
1099
1100
  /// Return the desired alignment for ByVal or InAlloca aggregate function
1101
  /// arguments in the caller parameter area.  This is the actual alignment, not
1102
  /// its logarithm.
1103
  virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1104
1105
  /// Return the type of registers that this ValueType will eventually require.
1106
3.63M
  MVT getRegisterType(MVT VT) const {
1107
3.63M
    assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
1108
3.63M
    return RegisterTypeForVT[VT.SimpleTy];
1109
3.63M
  }
1110
1111
  /// Return the type of registers that this ValueType will eventually require.
1112
11.0M
  MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1113
11.0M
    if (VT.isSimple()) {
1114
11.0M
      assert((unsigned)VT.getSimpleVT().SimpleTy <
1115
11.0M
                array_lengthof(RegisterTypeForVT));
1116
11.0M
      return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1117
11.0M
    }
1118
16.0k
    if (VT.isVector()) {
1119
3.29k
      EVT VT1;
1120
3.29k
      MVT RegisterVT;
1121
3.29k
      unsigned NumIntermediates;
1122
3.29k
      (void)getVectorTypeBreakdown(Context, VT, VT1,
1123
3.29k
                                   NumIntermediates, RegisterVT);
1124
3.29k
      return RegisterVT;
1125
3.29k
    }
1126
12.7k
    if (VT.isInteger()) {
1127
12.7k
      return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1128
12.7k
    }
1129
1
    llvm_unreachable("Unsupported extended type!");
1130
1
  }
1131
1132
  /// Return the number of registers that this ValueType will eventually
1133
  /// require.
1134
  ///
1135
  /// This is one for any types promoted to live in larger registers, but may be
1136
  /// more than one for types (like i64) that are split into pieces.  For types
1137
  /// like i140, which are first promoted then expanded, it is the number of
1138
  /// registers needed to hold all the bits of the original type.  For an i140
1139
  /// on a 32 bit machine this means 5 registers.
1140
12.2M
  unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1141
12.2M
    if (VT.isSimple()) {
1142
12.2M
      assert((unsigned)VT.getSimpleVT().SimpleTy <
1143
12.2M
                array_lengthof(NumRegistersForVT));
1144
12.2M
      return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1145
12.2M
    }
1146
8.86k
    if (VT.isVector()) {
1147
3.92k
      EVT VT1;
1148
3.92k
      MVT VT2;
1149
3.92k
      unsigned NumIntermediates;
1150
3.92k
      return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1151
3.92k
    }
1152
4.94k
    if (VT.isInteger()) {
1153
4.94k
      unsigned BitWidth = VT.getSizeInBits();
1154
4.94k
      unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1155
4.94k
      return (BitWidth + RegWidth - 1) / RegWidth;
1156
4.94k
    }
1157
0
    llvm_unreachable("Unsupported extended type!");
1158
0
  }
1159
1160
  /// Certain combinations of ABIs, Targets and features require that types
1161
  /// are legal for some operations and not for other operations.
1162
  /// For MIPS all vector types must be passed through the integer register set.
1163
  virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context,
1164
5.24M
                                            EVT VT) const {
1165
5.24M
    return getRegisterType(Context, VT);
1166
5.24M
  }
1167
1168
  /// Certain targets require unusual breakdowns of certain types. For MIPS,
1169
  /// this occurs when a vector type is used, as vector are passed through the
1170
  /// integer register set.
1171
  virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1172
4.89M
                                                 EVT VT) const {
1173
4.89M
    return getNumRegisters(Context, VT);
1174
4.89M
  }
1175
1176
  /// Certain targets have context senstive alignment requirements, where one
1177
  /// type has the alignment requirement of another type.
1178
  virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
1179
2.11M
                                                 DataLayout DL) const {
1180
2.11M
    return DL.getABITypeAlignment(ArgTy);
1181
2.11M
  }
1182
1183
  /// If true, then instruction selection should seek to shrink the FP constant
1184
  /// of the specified type to a smaller type in order to save space and / or
1185
  /// reduce runtime.
1186
286
  virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1187
1188
  // Return true if it is profitable to reduce the given load node to a smaller
1189
  // type.
1190
  //
1191
  // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
1192
  virtual bool shouldReduceLoadWidth(SDNode *Load,
1193
                                     ISD::LoadExtType ExtTy,
1194
1.22k
                                     EVT NewVT) const {
1195
1.22k
    return true;
1196
1.22k
  }
1197
1198
  /// When splitting a value of the specified type into parts, does the Lo
1199
  /// or Hi part come first?  This usually follows the endianness, except
1200
  /// for ppcf128, where the Hi part always comes first.
1201
177k
  bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1202
177k
    return DL.isBigEndian() || 
VT == MVT::ppcf128173k
;
1203
177k
  }
1204
1205
  /// If true, the target has custom DAG combine transformations that it can
1206
  /// perform for the specified node.
1207
88.5M
  bool hasTargetDAGCombine(ISD::NodeType NT) const {
1208
88.5M
    assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1209
88.5M
    return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1210
88.5M
  }
1211
1212
30.4M
  unsigned getGatherAllAliasesMaxDepth() const {
1213
30.4M
    return GatherAllAliasesMaxDepth;
1214
30.4M
  }
1215
1216
  /// Returns the size of the platform's va_list object.
1217
0
  virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1218
0
    return getPointerTy(DL).getSizeInBits();
1219
0
  }
1220
1221
  /// Get maximum # of store operations permitted for llvm.memset
1222
  ///
1223
  /// This function returns the maximum number of store operations permitted
1224
  /// to replace a call to llvm.memset. The value is set by the target at the
1225
  /// performance threshold for such a replacement. If OptSize is true,
1226
  /// return the limit for functions that have OptSize attribute.
1227
12.2k
  unsigned getMaxStoresPerMemset(bool OptSize) const {
1228
12.2k
    return OptSize ? 
MaxStoresPerMemsetOptSize21
:
MaxStoresPerMemset12.2k
;
1229
12.2k
  }
1230
1231
  /// Get maximum # of store operations permitted for llvm.memcpy
1232
  ///
1233
  /// This function returns the maximum number of store operations permitted
1234
  /// to replace a call to llvm.memcpy. The value is set by the target at the
1235
  /// performance threshold for such a replacement. If OptSize is true,
1236
  /// return the limit for functions that have OptSize attribute.
1237
11.7k
  unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1238
11.7k
    return OptSize ? 
MaxStoresPerMemcpyOptSize42
:
MaxStoresPerMemcpy11.6k
;
1239
11.7k
  }
1240
1241
  /// \brief Get maximum # of store operations to be glued together
1242
  ///
1243
  /// This function returns the maximum number of store operations permitted
1244
  /// to glue together during lowering of llvm.memcpy. The value is set by
1245
  //  the target at the performance threshold for such a replacement.
1246
10.5k
  virtual unsigned getMaxGluedStoresPerMemcpy() const {
1247
10.5k
    return MaxGluedStoresPerMemcpy;
1248
10.5k
  }
1249
1250
  /// Get maximum # of load operations permitted for memcmp
1251
  ///
1252
  /// This function returns the maximum number of load operations permitted
1253
  /// to replace a call to memcmp. The value is set by the target at the
1254
  /// performance threshold for such a replacement. If OptSize is true,
1255
  /// return the limit for functions that have OptSize attribute.
1256
391
  unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1257
391
    return OptSize ? 
MaxLoadsPerMemcmpOptSize108
:
MaxLoadsPerMemcmp283
;
1258
391
  }
1259
1260
  /// For memcmp expansion when the memcmp result is only compared equal or
1261
  /// not-equal to 0, allow up to this number of load pairs per block. As an
1262
  /// example, this may allow 'memcmp(a, b, 3) == 0' in a single block:
1263
  ///   a0 = load2bytes &a[0]
1264
  ///   b0 = load2bytes &b[0]
1265
  ///   a2 = load1byte  &a[2]
1266
  ///   b2 = load1byte  &b[2]
1267
  ///   r  = cmp eq (a0 ^ b0 | a2 ^ b2), 0
1268
22
  virtual unsigned getMemcmpEqZeroLoadsPerBlock() const {
1269
22
    return 1;
1270
22
  }
1271
1272
  /// Get maximum # of store operations permitted for llvm.memmove
1273
  ///
1274
  /// This function returns the maximum number of store operations permitted
1275
  /// to replace a call to llvm.memmove. The value is set by the target at the
1276
  /// performance threshold for such a replacement. If OptSize is true,
1277
  /// return the limit for functions that have OptSize attribute.
1278
103
  unsigned getMaxStoresPerMemmove(bool OptSize) const {
1279
103
    return OptSize ? 
MaxStoresPerMemmoveOptSize0
: MaxStoresPerMemmove;
1280
103
  }
1281
1282
  /// Determine if the target supports unaligned memory accesses.
1283
  ///
1284
  /// This function returns true if the target allows unaligned memory accesses
1285
  /// of the specified type in the given address space. If true, it also returns
1286
  /// whether the unaligned memory access is "fast" in the last argument by
1287
  /// reference. This is used, for example, in situations where an array
1288
  /// copy/move/set is converted to a sequence of store operations. Its use
1289
  /// helps to ensure that such replacements don't generate code that causes an
1290
  /// alignment error (trap) on the target machine.
1291
  virtual bool allowsMisalignedMemoryAccesses(EVT,
1292
                                              unsigned AddrSpace = 0,
1293
                                              unsigned Align = 1,
1294
1.15k
                                              bool * /*Fast*/ = nullptr) const {
1295
1.15k
    return false;
1296
1.15k
  }
1297
1298
  /// Return true if the target supports a memory access of this type for the
1299
  /// given address space and alignment. If the access is allowed, the optional
1300
  /// final parameter returns if the access is also fast (as defined by the
1301
  /// target).
1302
  bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1303
                          unsigned AddrSpace = 0, unsigned Alignment = 1,
1304
                          bool *Fast = nullptr) const;
1305
1306
  /// Returns the target specific optimal type for load and store operations as
1307
  /// a result of memset, memcpy, and memmove lowering.
1308
  ///
1309
  /// If DstAlign is zero that means it's safe to destination alignment can
1310
  /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1311
  /// a need to check it against alignment requirement, probably because the
1312
  /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1313
  /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1314
  /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1315
  /// does not need to be loaded.  It returns EVT::Other if the type should be
1316
  /// determined using generic target-independent logic.
1317
  virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
1318
                                  unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
1319
                                  bool /*IsMemset*/,
1320
                                  bool /*ZeroMemset*/,
1321
                                  bool /*MemcpyStrSrc*/,
1322
133
                                  MachineFunction &/*MF*/) const {
1323
133
    return MVT::Other;
1324
133
  }
1325
1326
  /// Returns true if it's safe to use load / store of the specified type to
1327
  /// expand memcpy / memset inline.
1328
  ///
1329
  /// This is mostly true for all types except for some special cases. For
1330
  /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1331
  /// fstpl which also does type conversion. Note the specified type doesn't
1332
  /// have to be legal as the hook is used before type legalization.
1333
5.70k
  virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1334
1335
  /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1336
0
  bool usesUnderscoreSetJmp() const {
1337
0
    return UseUnderscoreSetJmp;
1338
0
  }
1339
1340
  /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1341
0
  bool usesUnderscoreLongJmp() const {
1342
0
    return UseUnderscoreLongJmp;
1343
0
  }
1344
1345
  /// Return lower limit for number of blocks in a jump table.
1346
  virtual unsigned getMinimumJumpTableEntries() const;
1347
1348
  /// Return lower limit of the density in a jump table.
1349
  unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1350
1351
  /// Return upper limit for number of entries in a jump table.
1352
  /// Zero if no limit.
1353
  unsigned getMaximumJumpTableSize() const;
1354
1355
2.30k
  virtual bool isJumpTableRelative() const {
1356
2.30k
    return TM.isPositionIndependent();
1357
2.30k
  }
1358
1359
  /// If a physical register, this specifies the register that
1360
  /// llvm.savestack/llvm.restorestack should save and restore.
1361
19.9M
  unsigned getStackPointerRegisterToSaveRestore() const {
1362
19.9M
    return StackPointerRegisterToSaveRestore;
1363
19.9M
  }
1364
1365
  /// If a physical register, this returns the register that receives the
1366
  /// exception address on entry to an EH pad.
1367
  virtual unsigned
1368
0
  getExceptionPointerRegister(const Constant *PersonalityFn) const {
1369
0
    // 0 is guaranteed to be the NoRegister value on all targets
1370
0
    return 0;
1371
0
  }
1372
1373
  /// If a physical register, this returns the register that receives the
1374
  /// exception typeid on entry to a landing pad.
1375
  virtual unsigned
1376
0
  getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1377
0
    // 0 is guaranteed to be the NoRegister value on all targets
1378
0
    return 0;
1379
0
  }
1380
1381
0
  virtual bool needsFixedCatchObjects() const {
1382
0
    report_fatal_error("Funclet EH is not implemented for this target");
1383
0
  }
1384
1385
  /// Returns the target's jmp_buf size in bytes (if never set, the default is
1386
  /// 200)
1387
0
  unsigned getJumpBufSize() const {
1388
0
    return JumpBufSize;
1389
0
  }
1390
1391
  /// Returns the target's jmp_buf alignment in bytes (if never set, the default
1392
  /// is 0)
1393
0
  unsigned getJumpBufAlignment() const {
1394
0
    return JumpBufAlignment;
1395
0
  }
1396
1397
  /// Return the minimum stack alignment of an argument.
1398
169
  unsigned getMinStackArgumentAlignment() const {
1399
169
    return MinStackArgumentAlignment;
1400
169
  }
1401
1402
  /// Return the minimum function alignment.
1403
501k
  unsigned getMinFunctionAlignment() const {
1404
501k
    return MinFunctionAlignment;
1405
501k
  }
1406
1407
  /// Return the preferred function alignment.
1408
494k
  unsigned getPrefFunctionAlignment() const {
1409
494k
    return PrefFunctionAlignment;
1410
494k
  }
1411
1412
  /// Return the preferred loop alignment.
1413
626k
  virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1414
626k
    return PrefLoopAlignment;
1415
626k
  }
1416
1417
  /// If the target has a standard location for the stack protector guard,
1418
  /// returns the address of that location. Otherwise, returns nullptr.
1419
  /// DEPRECATED: please override useLoadStackGuardNode and customize
1420
  ///             LOAD_STACK_GUARD, or customize \@llvm.stackguard().
1421
  virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1422
1423
  /// Inserts necessary declarations for SSP (stack protection) purpose.
1424
  /// Should be used only when getIRStackGuard returns nullptr.
1425
  virtual void insertSSPDeclarations(Module &M) const;
1426
1427
  /// Return the variable that's previously inserted by insertSSPDeclarations,
1428
  /// if any, otherwise return nullptr. Should be used only when
1429
  /// getIRStackGuard returns nullptr.
1430
  virtual Value *getSDagStackGuard(const Module &M) const;
1431
1432
  /// If this function returns true, stack protection checks should XOR the
1433
  /// frame pointer (or whichever pointer is used to address locals) into the
1434
  /// stack guard value before checking it. getIRStackGuard must return nullptr
1435
  /// if this returns true.
1436
5.83k
  virtual bool useStackGuardXorFP() const { return false; }
1437
1438
  /// If the target has a standard stack protection check function that
1439
  /// performs validation and error handling, returns the function. Otherwise,
1440
  /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1441
  /// Should be used only when getIRStackGuard returns nullptr.
1442
  virtual Value *getSSPStackGuardCheck(const Module &M) const;
1443
1444
protected:
1445
  Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1446
                                            bool UseTLS) const;
1447
1448
public:
1449
  /// Returns the target-specific address of the unsafe stack pointer.
1450
  virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1451
1452
  /// Returns the name of the symbol used to emit stack probes or the empty
1453
  /// string if not applicable.
1454
0
  virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const {
1455
0
    return "";
1456
0
  }
1457
1458
  /// Returns true if a cast between SrcAS and DestAS is a noop.
1459
465
  virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1460
465
    return false;
1461
465
  }
1462
1463
  /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1464
  /// are happy to sink it into basic blocks.
1465
200
  virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1466
200
    return isNoopAddrSpaceCast(SrcAS, DestAS);
1467
200
  }
1468
1469
  /// Return true if the pointer arguments to CI should be aligned by aligning
1470
  /// the object whose address is being passed. If so then MinSize is set to the
1471
  /// minimum size the object must be to be aligned and PrefAlign is set to the
1472
  /// preferred alignment.
1473
  virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1474
3.76M
                                      unsigned & /*PrefAlign*/) const {
1475
3.76M
    return false;
1476
3.76M
  }
1477
1478
  //===--------------------------------------------------------------------===//
1479
  /// \name Helpers for TargetTransformInfo implementations
1480
  /// @{
1481
1482
  /// Get the ISD node that corresponds to the Instruction class opcode.
1483
  int InstructionOpcodeToISD(unsigned Opcode) const;
1484
1485
  /// Estimate the cost of type-legalization and the legalized type.
1486
  std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1487
                                              Type *Ty) const;
1488
1489
  /// @}
1490
1491
  //===--------------------------------------------------------------------===//
1492
  /// \name Helpers for atomic expansion.
1493
  /// @{
1494
1495
  /// Returns the maximum atomic operation size (in bits) supported by
1496
  /// the backend. Atomic operations greater than this size (as well
1497
  /// as ones that are not naturally aligned), will be expanded by
1498
  /// AtomicExpandPass into an __atomic_* library call.
1499
38.0k
  unsigned getMaxAtomicSizeInBitsSupported() const {
1500
38.0k
    return MaxAtomicSizeInBitsSupported;
1501
38.0k
  }
1502
1503
  /// Returns the size of the smallest cmpxchg or ll/sc instruction
1504
  /// the backend supports.  Any smaller operations are widened in
1505
  /// AtomicExpandPass.
1506
  ///
1507
  /// Note that *unlike* operations above the maximum size, atomic ops
1508
  /// are still natively supported below the minimum; they just
1509
  /// require a more complex expansion.
1510
26.4k
  unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1511
1512
  /// Whether the target supports unaligned atomic operations.
1513
968
  bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
1514
1515
  /// Whether AtomicExpandPass should automatically insert fences and reduce
1516
  /// ordering for this atomic. This should be true for most architectures with
1517
  /// weak memory ordering. Defaults to false.
1518
39.8k
  virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1519
39.8k
    return false;
1520
39.8k
  }
1521
1522
  /// Perform a load-linked operation on Addr, returning a "Value *" with the
1523
  /// corresponding pointee type. This may entail some non-trivial operations to
1524
  /// truncate or reconstruct types that will be illegal in the backend. See
1525
  /// ARMISelLowering for an example implementation.
1526
  virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1527
0
                                AtomicOrdering Ord) const {
1528
0
    llvm_unreachable("Load linked unimplemented on this target");
1529
0
  }
1530
1531
  /// Perform a store-conditional operation to Addr. Return the status of the
1532
  /// store. This should be 0 if the store succeeded, non-zero otherwise.
1533
  virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1534
0
                                      Value *Addr, AtomicOrdering Ord) const {
1535
0
    llvm_unreachable("Store conditional unimplemented on this target");
1536
0
  }
1537
1538
  /// Inserts in the IR a target-specific intrinsic specifying a fence.
1539
  /// It is called by AtomicExpandPass before expanding an
1540
  ///   AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1541
  ///   if shouldInsertFencesForAtomic returns true.
1542
  ///
1543
  /// Inst is the original atomic instruction, prior to other expansions that
1544
  /// may be performed.
1545
  ///
1546
  /// This function should either return a nullptr, or a pointer to an IR-level
1547
  ///   Instruction*. Even complex fence sequences can be represented by a
1548
  ///   single Instruction* through an intrinsic to be lowered later.
1549
  /// Backends should override this method to produce target-specific intrinsic
1550
  ///   for their fences.
1551
  /// FIXME: Please note that the default implementation here in terms of
1552
  ///   IR-level fences exists for historical/compatibility reasons and is
1553
  ///   *unsound* ! Fences cannot, in general, be used to restore sequential
1554
  ///   consistency. For example, consider the following example:
1555
  /// atomic<int> x = y = 0;
1556
  /// int r1, r2, r3, r4;
1557
  /// Thread 0:
1558
  ///   x.store(1);
1559
  /// Thread 1:
1560
  ///   y.store(1);
1561
  /// Thread 2:
1562
  ///   r1 = x.load();
1563
  ///   r2 = y.load();
1564
  /// Thread 3:
1565
  ///   r3 = y.load();
1566
  ///   r4 = x.load();
1567
  ///  r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1568
  ///  seq_cst. But if they are lowered to monotonic accesses, no amount of
1569
  ///  IR-level fences can prevent it.
1570
  /// @{
1571
  virtual Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
1572
125
                                        AtomicOrdering Ord) const {
1573
125
    if (isReleaseOrStronger(Ord) && 
Inst->hasAtomicStore()95
)
1574
92
      return Builder.CreateFence(Ord);
1575
33
    else
1576
33
      return nullptr;
1577
125
  }
1578
1579
  virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
1580
                                         Instruction *Inst,
1581
125
                                         AtomicOrdering Ord) const {
1582
125
    if (isAcquireOrStronger(Ord))
1583
102
      return Builder.CreateFence(Ord);
1584
23
    else
1585
23
      return nullptr;
1586
125
  }
1587
  /// @}
1588
1589
  // Emits code that executes when the comparison result in the ll/sc
1590
  // expansion of a cmpxchg instruction is such that the store-conditional will
1591
  // not execute.  This makes it possible to balance out the load-linked with
1592
  // a dedicated instruction, if desired.
1593
  // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1594
  // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1595
3
  virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1596
1597
  /// Returns true if the given (atomic) store should be expanded by the
1598
  /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1599
67
  virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1600
67
    return false;
1601
67
  }
1602
1603
  /// Returns true if arguments should be sign-extended in lib calls.
1604
32.4k
  virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1605
32.4k
    return IsSigned;
1606
32.4k
  }
1607
1608
  /// Returns how the given (atomic) load should be expanded by the
1609
  /// IR-level AtomicExpand pass.
1610
79
  virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const {
1611
79
    return AtomicExpansionKind::None;
1612
79
  }
1613
1614
  /// Returns true if the given atomic cmpxchg should be expanded by the
1615
  /// IR-level AtomicExpand pass into a load-linked/store-conditional sequence
1616
  /// (through emitLoadLinked() and emitStoreConditional()).
1617
1.04k
  virtual bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
1618
1.04k
    return false;
1619
1.04k
  }
1620
1621
  /// Returns how the IR-level AtomicExpand pass should expand the given
1622
  /// AtomicRMW, if at all. Default is to never expand.
1623
786
  virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
1624
786
    return AtomicExpansionKind::None;
1625
786
  }
1626
1627
  /// On some platforms, an AtomicRMW that never actually modifies the value
1628
  /// (such as fetch_add of 0) can be turned into a fence followed by an
1629
  /// atomic load. This may sound useless, but it makes it possible for the
1630
  /// processor to keep the cacheline shared, dramatically improving
1631
  /// performance. And such idempotent RMWs are useful for implementing some
1632
  /// kinds of locks, see for example (justification + benchmarks):
1633
  /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1634
  /// This method tries doing that transformation, returning the atomic load if
1635
  /// it succeeds, and nullptr otherwise.
1636
  /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1637
  /// another round of expansion.
1638
  virtual LoadInst *
1639
0
  lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1640
0
    return nullptr;
1641
0
  }
1642
1643
  /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1644
  /// SIGN_EXTEND, or ANY_EXTEND).
1645
1.46k
  virtual ISD::NodeType getExtendForAtomicOps() const {
1646
1.46k
    return ISD::ZERO_EXTEND;
1647
1.46k
  }
1648
1649
  /// @}
1650
1651
  /// Returns true if we should normalize
1652
  /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1653
  /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1654
  /// that it saves us from materializing N0 and N1 in an integer register.
1655
  /// Targets that are able to perform and/or on flags should return false here.
1656
  virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
1657
32.9k
                                               EVT VT) const {
1658
32.9k
    // If a target has multiple condition registers, then it likely has logical
1659
32.9k
    // operations on those registers.
1660
32.9k
    if (hasMultipleConditionRegisters())
1661
11.8k
      return false;
1662
21.1k
    // Only do the transform if the value won't be split into multiple
1663
21.1k
    // registers.
1664
21.1k
    LegalizeTypeAction Action = getTypeAction(Context, VT);
1665
21.1k
    return Action != TypeExpandInteger && 
Action != TypeExpandFloat20.6k
&&
1666
21.1k
      
Action != TypeSplitVector20.6k
;
1667
21.1k
  }
1668
1669
  /// Return true if a select of constants (select Cond, C1, C2) should be
1670
  /// transformed into simple math ops with the condition value. For example:
1671
  /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1672
7.87k
  virtual bool convertSelectOfConstantsToMath(EVT VT) const {
1673
7.87k
    return false;
1674
7.87k
  }
1675
1676
  //===--------------------------------------------------------------------===//
1677
  // TargetLowering Configuration Methods - These methods should be invoked by
1678
  // the derived class constructor to configure this object for the target.
1679
  //
1680
protected:
1681
  /// Specify how the target extends the result of integer and floating point
1682
  /// boolean values from i1 to a wider type.  See getBooleanContents.
1683
44.3k
  void setBooleanContents(BooleanContent Ty) {
1684
44.3k
    BooleanContents = Ty;
1685
44.3k
    BooleanFloatContents = Ty;
1686
44.3k
  }
1687
1688
  /// Specify how the target extends the result of integer and floating point
1689
  /// boolean values from i1 to a wider type.  See getBooleanContents.
1690
1.20k
  void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1691
1.20k
    BooleanContents = IntTy;
1692
1.20k
    BooleanFloatContents = FloatTy;
1693
1.20k
  }
1694
1695
  /// Specify how the target extends the result of a vector boolean value from a
1696
  /// vector of i1 to a wider type.  See getBooleanContents.
1697
43.6k
  void setBooleanVectorContents(BooleanContent Ty) {
1698
43.6k
    BooleanVectorContents = Ty;
1699
43.6k
  }
1700
1701
  /// Specify the target scheduling preference.
1702
36.5k
  void setSchedulingPreference(Sched::Preference Pref) {
1703
36.5k
    SchedPreferenceInfo = Pref;
1704
36.5k
  }
1705
1706
  /// Indicate whether this target prefers to use _setjmp to implement
1707
  /// llvm.setjmp or the version without _.  Defaults to false.
1708
13.7k
  void setUseUnderscoreSetJmp(bool Val) {
1709
13.7k
    UseUnderscoreSetJmp = Val;
1710
13.7k
  }
1711
1712
  /// Indicate whether this target prefers to use _longjmp to implement
1713
  /// llvm.longjmp or the version without _.  Defaults to false.
1714
13.7k
  void setUseUnderscoreLongJmp(bool Val) {
1715
13.7k
    UseUnderscoreLongJmp = Val;
1716
13.7k
  }
1717
1718
  /// Indicate the minimum number of blocks to generate jump tables.
1719
  void setMinimumJumpTableEntries(unsigned Val);
1720
1721
  /// Indicate the maximum number of entries in jump tables.
1722
  /// Set to zero to generate unlimited jump tables.
1723
  void setMaximumJumpTableSize(unsigned);
1724
1725
  /// If set to a physical register, this specifies the register that
1726
  /// llvm.savestack/llvm.restorestack should save and restore.
1727
41.1k
  void setStackPointerRegisterToSaveRestore(unsigned R) {
1728
41.1k
    StackPointerRegisterToSaveRestore = R;
1729
41.1k
  }
1730
1731
  /// Tells the code generator that the target has multiple (allocatable)
1732
  /// condition registers that can be used to store the results of comparisons
1733
  /// for use by selects and conditional branches. With multiple condition
1734
  /// registers, the code generator will not aggressively sink comparisons into
1735
  /// the blocks of their users.
1736
3.94k
  void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1737
3.94k
    HasMultipleConditionRegisters = hasManyRegs;
1738
3.94k
  }
1739
1740
  /// Tells the code generator that the target has BitExtract instructions.
1741
  /// The code generator will aggressively sink "shift"s into the blocks of
1742
  /// their users if the users will generate "and" instructions which can be
1743
  /// combined with "shift" to BitExtract instructions.
1744
10.9k
  void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1745
10.9k
    HasExtractBitsInsn = hasExtractInsn;
1746
10.9k
  }
1747
1748
  /// Tells the code generator not to expand logic operations on comparison
1749
  /// predicates into separate sequences that increase the amount of flow
1750
  /// control.
1751
  void setJumpIsExpensive(bool isExpensive = true);
1752
1753
  /// Tells the code generator that this target supports floating point
1754
  /// exceptions and cares about preserving floating point exception behavior.
1755
2.27k
  void setHasFloatingPointExceptions(bool FPExceptions = true) {
1756
2.27k
    HasFloatingPointExceptions = FPExceptions;
1757
2.27k
  }
1758
1759
  /// Tells the code generator which bitwidths to bypass.
1760
1.65k
  void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1761
1.65k
    BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1762
1.65k
  }
1763
1764
  /// Add the specified register class as an available regclass for the
1765
  /// specified value type. This indicates the selector can handle values of
1766
  /// that class natively.
1767
545k
  void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1768
545k
    assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1769
545k
    RegClassForVT[VT.SimpleTy] = RC;
1770
545k
  }
1771
1772
  /// Return the largest legal super-reg register class of the register class
1773
  /// for the specified type and its associated "cost".
1774
  virtual std::pair<const TargetRegisterClass *, uint8_t>
1775
  findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1776
1777
  /// Once all of the register classes are added, this allows us to compute
1778
  /// derived properties we expose.
1779
  void computeRegisterProperties(const TargetRegisterInfo *TRI);
1780
1781
  /// Indicate that the specified operation does not work with the specified
1782
  /// type and indicate what to do about it. Note that VT may refer to either
1783
  /// the type of a result or that of an operand of Op.
1784
  void setOperationAction(unsigned Op, MVT VT,
1785
290M
                          LegalizeAction Action) {
1786
290M
    assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1787
290M
    OpActions[(unsigned)VT.SimpleTy][Op] = Action;
1788
290M
  }
1789
1790
  /// Indicate that the specified load with extension does not work with the
1791
  /// specified type and indicate what to do about it.
1792
  void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1793
781M
                        LegalizeAction Action) {
1794
781M
    assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1795
781M
           MemVT.isValid() && "Table isn't big enough!");
1796
781M
    assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1797
781M
    unsigned Shift = 4 * ExtType;
1798
781M
    LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
1799
781M
    LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
1800
781M
  }
1801
1802
  /// Indicate that the specified truncating store does not work with the
1803
  /// specified type and indicate what to do about it.
1804
  void setTruncStoreAction(MVT ValVT, MVT MemVT,
1805
278M
                           LegalizeAction Action) {
1806
278M
    assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1807
278M
    TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
1808
278M
  }
1809
1810
  /// Indicate that the specified indexed load does or does not work with the
1811
  /// specified type and indicate what to do abort it.
1812
  ///
1813
  /// NOTE: All indexed mode loads are initialized to Expand in
1814
  /// TargetLowering.cpp
1815
  void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1816
20.8M
                            LegalizeAction Action) {
1817
20.8M
    assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1818
20.8M
           (unsigned)Action < 0xf && "Table isn't big enough!");
1819
20.8M
    // Load action are kept in the upper half.
1820
20.8M
    IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1821
20.8M
    IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1822
20.8M
  }
1823
1824
  /// Indicate that the specified indexed store does or does not work with the
1825
  /// specified type and indicate what to do about it.
1826
  ///
1827
  /// NOTE: All indexed mode stores are initialized to Expand in
1828
  /// TargetLowering.cpp
1829
  void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1830
20.8M
                             LegalizeAction Action) {
1831
20.8M
    assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1832
20.8M
           (unsigned)Action < 0xf && "Table isn't big enough!");
1833
20.8M
    // Store action are kept in the lower half.
1834
20.8M
    IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1835
20.8M
    IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1836
20.8M
  }
1837
1838
  /// Indicate that the specified condition code is or isn't supported on the
1839
  /// target and indicate what to do about it.
1840
  void setCondCodeAction(ISD::CondCode CC, MVT VT,
1841
276k
                         LegalizeAction Action) {
1842
276k
    assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1843
276k
           "Table isn't big enough!");
1844
276k
    assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1845
276k
    /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
1846
276k
    /// value and the upper 29 bits index into the second dimension of the array
1847
276k
    /// to select what 32-bit value to use.
1848
276k
    uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1849
276k
    CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
1850
276k
    CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
1851
276k
  }
1852
1853
  /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1854
  /// to trying a larger integer/fp until it can find one that works. If that
1855
  /// default is insufficient, this method can be used by the target to override
1856
  /// the default.
1857
1.58M
  void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1858
1.58M
    PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1859
1.58M
  }
1860
1861
  /// Convenience method to set an operation to Promote and specify the type
1862
  /// in a single call.
1863
438k
  void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1864
438k
    setOperationAction(Opc, OrigVT, Promote);
1865
438k
    AddPromotedToType(Opc, OrigVT, DestVT);
1866
438k
  }
1867
1868
  /// Targets should invoke this method for each target independent node that
1869
  /// they want to provide a custom DAG combiner for by implementing the
1870
  /// PerformDAGCombine virtual method.
1871
1.06M
  void setTargetDAGCombine(ISD::NodeType NT) {
1872
1.06M
    assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1873
1.06M
    TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1874
1.06M
  }
1875
1876
  /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1877
0
  void setJumpBufSize(unsigned Size) {
1878
0
    JumpBufSize = Size;
1879
0
  }
1880
1881
  /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1882
  /// 0
1883
0
  void setJumpBufAlignment(unsigned Align) {
1884
0
    JumpBufAlignment = Align;
1885
0
  }
1886
1887
  /// Set the target's minimum function alignment (in log2(bytes))
1888
29.0k
  void setMinFunctionAlignment(unsigned Align) {
1889
29.0k
    MinFunctionAlignment = Align;
1890
29.0k
  }
1891
1892
  /// Set the target's preferred function alignment.  This should be set if
1893
  /// there is a performance benefit to higher-than-minimum alignment (in
1894
  /// log2(bytes))
1895
23.9k
  void setPrefFunctionAlignment(unsigned Align) {
1896
23.9k
    PrefFunctionAlignment = Align;
1897
23.9k
  }
1898
1899
  /// Set the target's preferred loop alignment. Default alignment is zero, it
1900
  /// means the target does not care about loop alignment.  The alignment is
1901
  /// specified in log2(bytes). The target may also override
1902
  /// getPrefLoopAlignment to provide per-loop values.
1903
22.5k
  void setPrefLoopAlignment(unsigned Align) {
1904
22.5k
    PrefLoopAlignment = Align;
1905
22.5k
  }
1906
1907
  /// Set the minimum stack alignment of an argument (in log2(bytes)).
1908
18.0k
  void setMinStackArgumentAlignment(unsigned Align) {
1909
18.0k
    MinStackArgumentAlignment = Align;
1910
18.0k
  }
1911
1912
  /// Set the maximum atomic operation size supported by the
1913
  /// backend. Atomic operations greater than this size (as well as
1914
  /// ones that are not naturally aligned), will be expanded by
1915
  /// AtomicExpandPass into an __atomic_* library call.
1916
1.38k
  void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
1917
1.38k
    MaxAtomicSizeInBitsSupported = SizeInBits;
1918
1.38k
  }
1919
1920
  /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
1921
1.38k
  void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
1922
1.38k
    MinCmpXchgSizeInBits = SizeInBits;
1923
1.38k
  }
1924
1925
  /// Sets whether unaligned atomic operations are supported.
1926
0
  void setSupportsUnalignedAtomics(bool UnalignedSupported) {
1927
0
    SupportsUnalignedAtomics = UnalignedSupported;
1928
0
  }
1929
1930
public:
1931
  //===--------------------------------------------------------------------===//
1932
  // Addressing mode description hooks (used by LSR etc).
1933
  //
1934
1935
  /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1936
  /// instructions reading the address. This allows as much computation as
1937
  /// possible to be done in the address mode for that operand. This hook lets
1938
  /// targets also pass back when this should be done on intrinsics which
1939
  /// load/store.
1940
  virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
1941
                                    SmallVectorImpl<Value*> &/*Ops*/,
1942
774k
                                    Type *&/*AccessTy*/) const {
1943
774k
    return false;
1944
774k
  }
1945
1946
  /// This represents an addressing mode of:
1947
  ///    BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1948
  /// If BaseGV is null,  there is no BaseGV.
1949
  /// If BaseOffs is zero, there is no base offset.
1950
  /// If HasBaseReg is false, there is no base register.
1951
  /// If Scale is zero, there is no ScaleReg.  Scale of 1 indicates a reg with
1952
  /// no scale.
1953
  struct AddrMode {
1954
    GlobalValue *BaseGV = nullptr;
1955
    int64_t      BaseOffs = 0;
1956
    bool         HasBaseReg = false;
1957
    int64_t      Scale = 0;
1958
67.9M
    AddrMode() = default;
1959
  };
1960
1961
  /// Return true if the addressing mode represented by AM is legal for this
1962
  /// target, for a load/store of the specified type.
1963
  ///
1964
  /// The type may be VoidTy, in which case only return true if the addressing
1965
  /// mode is legal for a load/store of any legal type.  TODO: Handle
1966
  /// pre/postinc as well.
1967
  ///
1968
  /// If the address space cannot be determined, it will be -1.
1969
  ///
1970
  /// TODO: Remove default argument
1971
  virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
1972
                                     Type *Ty, unsigned AddrSpace,
1973
                                     Instruction *I = nullptr) const;
1974
1975
  /// Return the cost of the scaling factor used in the addressing mode
1976
  /// represented by AM for this target, for a load/store of the specified type.
1977
  ///
1978
  /// If the AM is supported, the return value must be >= 0.
1979
  /// If the AM is not supported, it returns a negative value.
1980
  /// TODO: Handle pre/postinc as well.
1981
  /// TODO: Remove default argument
1982
  virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
1983
6.77k
                                   Type *Ty, unsigned AS = 0) const {
1984
6.77k
    // Default: assume that any scaling factor used in a legal AM is free.
1985
6.77k
    if (isLegalAddressingMode(DL, AM, Ty, AS))
1986
6.77k
      return 0;
1987
0
    return -1;
1988
0
  }
1989
1990
  /// Return true if the specified immediate is legal icmp immediate, that is
1991
  /// the target has icmp instructions which can compare a register against the
1992
  /// immediate without having to materialize the immediate into a register.
1993
34.3k
  virtual bool isLegalICmpImmediate(int64_t) const {
1994
34.3k
    return true;
1995
34.3k
  }
1996
1997
  /// Return true if the specified immediate is legal add immediate, that is the
1998
  /// target has add instructions which can add a register with the immediate
1999
  /// without having to materialize the immediate into a register.
2000
1.57k
  virtual bool isLegalAddImmediate(int64_t) const {
2001
1.57k
    return true;
2002
1.57k
  }
2003
2004
  /// Return true if it's significantly cheaper to shift a vector by a uniform
2005
  /// scalar than by an amount which will vary across each lane. On x86, for
2006
  /// example, there is a "psllw" instruction for the former case, but no simple
2007
  /// instruction for a general "a << b" operation on vectors.
2008
163k
  virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
2009
163k
    return false;
2010
163k
  }
2011
2012
  /// Returns true if the opcode is a commutative binary operation.
2013
116M
  virtual bool isCommutativeBinOp(unsigned Opcode) const {
2014
116M
    // FIXME: This should get its info from the td file.
2015
116M
    switch (Opcode) {
2016
116M
    case ISD::ADD:
2017
17.5M
    case ISD::SMIN:
2018
17.5M
    case ISD::SMAX:
2019
17.5M
    case ISD::UMIN:
2020
17.5M
    case ISD::UMAX:
2021
17.5M
    case ISD::MUL:
2022
17.5M
    case ISD::MULHU:
2023
17.5M
    case ISD::MULHS:
2024
17.5M
    case ISD::SMUL_LOHI:
2025
17.5M
    case ISD::UMUL_LOHI:
2026
17.5M
    case ISD::FADD:
2027
17.5M
    case ISD::FMUL:
2028
17.5M
    case ISD::AND:
2029
17.5M
    case ISD::OR:
2030
17.5M
    case ISD::XOR:
2031
17.5M
    case ISD::SADDO:
2032
17.5M
    case ISD::UADDO:
2033
17.5M
    case ISD::ADDC:
2034
17.5M
    case ISD::ADDE:
2035
17.5M
    case ISD::FMINNUM:
2036
17.5M
    case ISD::FMAXNUM:
2037
17.5M
    case ISD::FMINNAN:
2038
17.5M
    case ISD::FMAXNAN:
2039
17.5M
      return true;
2040
98.6M
    default: return false;
2041
116M
    }
2042
116M
  }
2043
2044
  /// Return true if it's free to truncate a value of type FromTy to type
2045
  /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
2046
  /// by referencing its sub-register AX.
2047
  /// Targets must return false when FromTy <= ToTy.
2048
91
  virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
2049
91
    return false;
2050
91
  }
2051
2052
  /// Return true if a truncation from FromTy to ToTy is permitted when deciding
2053
  /// whether a call is in tail position. Typically this means that both results
2054
  /// would be assigned to the same register or stack slot, but it could mean
2055
  /// the target performs adequate checks of its own before proceeding with the
2056
  /// tail call.  Targets must return false when FromTy <= ToTy.
2057
2
  virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
2058
2
    return false;
2059
2
  }
2060
2061
5.80k
  virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
2062
5.80k
    return false;
2063
5.80k
  }
2064
2065
44.1k
  virtual bool isProfitableToHoist(Instruction *I) const { return true; }
2066
2067
  /// Return true if the extension represented by \p I is free.
2068
  /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2069
  /// this method can use the context provided by \p I to decide
2070
  /// whether or not \p I is free.
2071
  /// This method extends the behavior of the is[Z|FP]ExtFree family.
2072
  /// In other words, if is[Z|FP]Free returns true, then this method
2073
  /// returns true as well. The converse is not true.
2074
  /// The target can perform the adequate checks by overriding isExtFreeImpl.
2075
  /// \pre \p I must be a sign, zero, or fp extension.
2076
2.01M
  bool isExtFree(const Instruction *I) const {
2077
2.01M
    switch (I->getOpcode()) {
2078
2.01M
    case Instruction::FPExt:
2079
73.7k
      if (isFPExtFree(EVT::getEVT(I->getType()),
2080
73.7k
                      EVT::getEVT(I->getOperand(0)->getType())))
2081
6
        return true;
2082
73.7k
      break;
2083
793k
    case Instruction::ZExt:
2084
793k
      if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2085
366k
        return true;
2086
426k
      break;
2087
1.14M
    case Instruction::SExt:
2088
1.14M
      break;
2089
426k
    default:
2090
0
      llvm_unreachable("Instruction is not an extension");
2091
1.64M
    }
2092
1.64M
    return isExtFreeImpl(I);
2093
1.64M
  }
2094
2095
  /// Return true if \p Load and \p Ext can form an ExtLoad.
2096
  /// For example, in AArch64
2097
  ///   %L = load i8, i8* %ptr
2098
  ///   %E = zext i8 %L to i32
2099
  /// can be lowered into one load instruction
2100
  ///   ldrb w0, [x0]
2101
  bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2102
691k
                 const DataLayout &DL) const {
2103
691k
    EVT VT = getValueType(DL, Ext->getType());
2104
691k
    EVT LoadVT = getValueType(DL, Load->getType());
2105
691k
2106
691k
    // If the load has other users and the truncate is not free, the ext
2107
691k
    // probably isn't free.
2108
691k
    if (!Load->hasOneUse() && 
(292k
isTypeLegal(LoadVT)292k
||
!isTypeLegal(VT)133k
) &&
2109
691k
        
!isTruncateFree(Ext->getType(), Load->getType())160k
)
2110
422
      return false;
2111
690k
2112
690k
    // Check whether the target supports casts folded into loads.
2113
690k
    unsigned LType;
2114
690k
    if (isa<ZExtInst>(Ext))
2115
275k
      LType = ISD::ZEXTLOAD;
2116
415k
    else {
2117
415k
      assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
2118
415k
      LType = ISD::SEXTLOAD;
2119
415k
    }
2120
690k
2121
690k
    return isLoadExtLegal(LType, VT, LoadVT);
2122
690k
  }
2123
2124
  /// Return true if any actual instruction that defines a value of type FromTy
2125
  /// implicitly zero-extends the value to ToTy in the result register.
2126
  ///
2127
  /// The function should return true when it is likely that the truncate can
2128
  /// be freely folded with an instruction defining a value of FromTy. If
2129
  /// the defining instruction is unknown (because you're looking at a
2130
  /// function argument, PHI, etc.) then the target may require an
2131
  /// explicit truncate, which is not necessarily free, but this function
2132
  /// does not deal with those cases.
2133
  /// Targets must return false when FromTy >= ToTy.
2134
44.0k
  virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2135
44.0k
    return false;
2136
44.0k
  }
2137
2138
16.3k
  virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2139
16.3k
    return false;
2140
16.3k
  }
2141
2142
  /// Return true if the target supplies and combines to a paired load
2143
  /// two loaded values of type LoadedType next to each other in memory.
2144
  /// RequiredAlignment gives the minimal alignment constraints that must be met
2145
  /// to be able to select this paired load.
2146
  ///
2147
  /// This information is *not* used to generate actual paired loads, but it is
2148
  /// used to generate a sequence of loads that is easier to combine into a
2149
  /// paired load.
2150
  /// For instance, something like this:
2151
  /// a = load i64* addr
2152
  /// b = trunc i64 a to i32
2153
  /// c = lshr i64 a, 32
2154
  /// d = trunc i64 c to i32
2155
  /// will be optimized into:
2156
  /// b = load i32* addr1
2157
  /// d = load i32* addr2
2158
  /// Where addr1 = addr2 +/- sizeof(i32).
2159
  ///
2160
  /// In other words, unless the target performs a post-isel load combining,
2161
  /// this information should not be provided because it will generate more
2162
  /// loads.
2163
  virtual bool hasPairedLoad(EVT /*LoadedType*/,
2164
14.3k
                             unsigned & /*RequiredAlignment*/) const {
2165
14.3k
    return false;
2166
14.3k
  }
2167
2168
  /// Return true if the target has a vector blend instruction.
2169
36.8k
  virtual bool hasVectorBlend() const { return false; }
2170
2171
  /// Get the maximum supported factor for interleaved memory accesses.
2172
  /// Default to be the minimum interleave factor: 2.
2173
0
  virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2174
2175
  /// Lower an interleaved load to target specific intrinsics. Return
2176
  /// true on success.
2177
  ///
2178
  /// \p LI is the vector load instruction.
2179
  /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2180
  /// \p Indices is the corresponding indices for each shufflevector.
2181
  /// \p Factor is the interleave factor.
2182
  virtual bool lowerInterleavedLoad(LoadInst *LI,
2183
                                    ArrayRef<ShuffleVectorInst *> Shuffles,
2184
                                    ArrayRef<unsigned> Indices,
2185
0
                                    unsigned Factor) const {
2186
0
    return false;
2187
0
  }
2188
2189
  /// Lower an interleaved store to target specific intrinsics. Return
2190
  /// true on success.
2191
  ///
2192
  /// \p SI is the vector store instruction.
2193
  /// \p SVI is the shufflevector to RE-interleave the stored vector.
2194
  /// \p Factor is the interleave factor.
2195
  virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
2196
0
                                     unsigned Factor) const {
2197
0
    return false;
2198
0
  }
2199
2200
  /// Return true if zero-extending the specific node Val to type VT2 is free
2201
  /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2202
  /// because it's folded such as X86 zero-extending loads).
2203
13.9k
  virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2204
13.9k
    return isZExtFree(Val.getValueType(), VT2);
2205
13.9k
  }
2206
2207
  /// Return true if an fpext operation is free (for instance, because
2208
  /// single-precision floating-point numbers are implicitly extended to
2209
  /// double-precision).
2210
74.4k
  virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2211
74.4k
    assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2212
74.4k
           "invalid fpext types");
2213
74.4k
    return false;
2214
74.4k
  }
2215
2216
  /// Return true if an fpext operation input to an \p Opcode operation is free
2217
  /// (for instance, because half-precision floating-point numbers are
2218
  /// implicitly extended to float-precision) for an FMA instruction.
2219
44
  virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
2220
44
    assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2221
44
           "invalid fpext types");
2222
44
    return isFPExtFree(DestVT, SrcVT);
2223
44
  }
2224
2225
  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2226
  /// extend node) is profitable.
2227
7.65k
  virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2228
2229
  /// Return true if an fneg operation is free to the point where it is never
2230
  /// worthwhile to replace it with a bitwise operation.
2231
7.94k
  virtual bool isFNegFree(EVT VT) const {
2232
7.94k
    assert(VT.isFloatingPoint());
2233
7.94k
    return false;
2234
7.94k
  }
2235
2236
  /// Return true if an fabs operation is free to the point where it is never
2237
  /// worthwhile to replace it with a bitwise operation.
2238
7.34k
  virtual bool isFAbsFree(EVT VT) const {
2239
7.34k
    assert(VT.isFloatingPoint());
2240
7.34k
    return false;
2241
7.34k
  }
2242
2243
  /// Return true if an FMA operation is faster than a pair of fmul and fadd
2244
  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2245
  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2246
  ///
2247
  /// NOTE: This may be called before legalization on types for which FMAs are
2248
  /// not legal, but should return true if those types will eventually legalize
2249
  /// to types that support FMAs. After legalization, it will only be called on
2250
  /// types that support FMAs (via Legal or Custom actions)
2251
4.82k
  virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
2252
4.82k
    return false;
2253
4.82k
  }
2254
2255
  /// Return true if it's profitable to narrow operations of type VT1 to
2256
  /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2257
  /// i32 to i16.
2258
5.69k
  virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2259
5.69k
    return false;
2260
5.69k
  }
2261
2262
  /// Return true if it is beneficial to convert a load of a constant to
2263
  /// just the constant itself.
2264
  /// On some targets it might be more efficient to use a combination of
2265
  /// arithmetic instructions to materialize the constant instead of loading it
2266
  /// from a constant pool.
2267
  virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2268
12
                                                 Type *Ty) const {
2269
12
    return false;
2270
12
  }
2271
2272
  /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2273
  /// from this source type with this index. This is needed because
2274
  /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2275
  /// the first element, and only the target knows which lowering is cheap.
2276
  virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2277
35
                                       unsigned Index) const {
2278
35
    return false;
2279
35
  }
2280
2281
  // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2282
  // even if the vector itself has multiple uses.
2283
691
  virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2284
691
    return false;
2285
691
  }
2286
2287
  // Return true if CodeGenPrepare should consider splitting large offset of a
2288
  // GEP to make the GEP fit into the addressing mode and can be sunk into the
2289
  // same blocks of its users.
2290
22.1k
  virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
2291
2292
  //===--------------------------------------------------------------------===//
2293
  // Runtime Library hooks
2294
  //
2295
2296
  /// Rename the default libcall routine name for the specified libcall.
2297
22.3M
  void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2298
22.3M
    LibcallRoutineNames[Call] = Name;
2299
22.3M
  }
2300
2301
  /// Get the libcall routine name for the specified libcall.
2302
102k
  const char *getLibcallName(RTLIB::Libcall Call) const {
2303
102k
    return LibcallRoutineNames[Call];
2304
102k
  }
2305
2306
  /// Override the default CondCode to be used to test the result of the
2307
  /// comparison libcall against zero.
2308
73.4k
  void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
2309
73.4k
    CmpLibcallCCs[Call] = CC;
2310
73.4k
  }
2311
2312
  /// Get the CondCode that's to be used to test the result of the comparison
2313
  /// libcall against zero.
2314
1.11k
  ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
2315
1.11k
    return CmpLibcallCCs[Call];
2316
1.11k
  }
2317
2318
  /// Set the CallingConv that should be used for the specified libcall.
2319
23.0M
  void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
2320
23.0M
    LibcallCallingConvs[Call] = CC;
2321
23.0M
  }
2322
2323
  /// Get the CallingConv that should be used for the specified libcall.
2324
16.3k
  CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
2325
16.3k
    return LibcallCallingConvs[Call];
2326
16.3k
  }
2327
2328
  /// Execute target specific actions to finalize target lowering.
2329
  /// This is used to set extra flags in MachineFrameInformation and freezing
2330
  /// the set of reserved registers.
2331
  /// The default implementation just freezes the set of reserved registers.
2332
  virtual void finalizeLowering(MachineFunction &MF) const;
2333
2334
private:
2335
  const TargetMachine &TM;
2336
2337
  /// Tells the code generator that the target has multiple (allocatable)
2338
  /// condition registers that can be used to store the results of comparisons
2339
  /// for use by selects and conditional branches. With multiple condition
2340
  /// registers, the code generator will not aggressively sink comparisons into
2341
  /// the blocks of their users.
2342
  bool HasMultipleConditionRegisters;
2343
2344
  /// Tells the code generator that the target has BitExtract instructions.
2345
  /// The code generator will aggressively sink "shift"s into the blocks of
2346
  /// their users if the users will generate "and" instructions which can be
2347
  /// combined with "shift" to BitExtract instructions.
2348
  bool HasExtractBitsInsn;
2349
2350
  /// Tells the code generator to bypass slow divide or remainder
2351
  /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2352
  /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2353
  /// div/rem when the operands are positive and less than 256.
2354
  DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
2355
2356
  /// Tells the code generator that it shouldn't generate extra flow control
2357
  /// instructions and should attempt to combine flow control instructions via
2358
  /// predication.
2359
  bool JumpIsExpensive;
2360
2361
  /// Whether the target supports or cares about preserving floating point
2362
  /// exception behavior.
2363
  bool HasFloatingPointExceptions;
2364
2365
  /// This target prefers to use _setjmp to implement llvm.setjmp.
2366
  ///
2367
  /// Defaults to false.
2368
  bool UseUnderscoreSetJmp;
2369
2370
  /// This target prefers to use _longjmp to implement llvm.longjmp.
2371
  ///
2372
  /// Defaults to false.
2373
  bool UseUnderscoreLongJmp;
2374
2375
  /// Information about the contents of the high-bits in boolean values held in
2376
  /// a type wider than i1. See getBooleanContents.
2377
  BooleanContent BooleanContents;
2378
2379
  /// Information about the contents of the high-bits in boolean values held in
2380
  /// a type wider than i1. See getBooleanContents.
2381
  BooleanContent BooleanFloatContents;
2382
2383
  /// Information about the contents of the high-bits in boolean vector values
2384
  /// when the element type is wider than i1. See getBooleanContents.
2385
  BooleanContent BooleanVectorContents;
2386
2387
  /// The target scheduling preference: shortest possible total cycles or lowest
2388
  /// register usage.
2389
  Sched::Preference SchedPreferenceInfo;
2390
2391
  /// The size, in bytes, of the target's jmp_buf buffers
2392
  unsigned JumpBufSize;
2393
2394
  /// The alignment, in bytes, of the target's jmp_buf buffers
2395
  unsigned JumpBufAlignment;
2396
2397
  /// The minimum alignment that any argument on the stack needs to have.
2398
  unsigned MinStackArgumentAlignment;
2399
2400
  /// The minimum function alignment (used when optimizing for size, and to
2401
  /// prevent explicitly provided alignment from leading to incorrect code).
2402
  unsigned MinFunctionAlignment;
2403
2404
  /// The preferred function alignment (used when alignment unspecified and
2405
  /// optimizing for speed).
2406
  unsigned PrefFunctionAlignment;
2407
2408
  /// The preferred loop alignment.
2409
  unsigned PrefLoopAlignment;
2410
2411
  /// Size in bits of the maximum atomics size the backend supports.
2412
  /// Accesses larger than this will be expanded by AtomicExpandPass.
2413
  unsigned MaxAtomicSizeInBitsSupported;
2414
2415
  /// Size in bits of the minimum cmpxchg or ll/sc operation the
2416
  /// backend supports.
2417
  unsigned MinCmpXchgSizeInBits;
2418
2419
  /// This indicates if the target supports unaligned atomic operations.
2420
  bool SupportsUnalignedAtomics;
2421
2422
  /// If set to a physical register, this specifies the register that
2423
  /// llvm.savestack/llvm.restorestack should save and restore.
2424
  unsigned StackPointerRegisterToSaveRestore;
2425
2426
  /// This indicates the default register class to use for each ValueType the
2427
  /// target supports natively.
2428
  const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2429
  unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
2430
  MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2431
2432
  /// This indicates the "representative" register class to use for each
2433
  /// ValueType the target supports natively. This information is used by the
2434
  /// scheduler to track register pressure. By default, the representative
2435
  /// register class is the largest legal super-reg register class of the
2436
  /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2437
  /// representative class would be GR32.
2438
  const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2439
2440
  /// This indicates the "cost" of the "representative" register class for each
2441
  /// ValueType. The cost is used by the scheduler to approximate register
2442
  /// pressure.
2443
  uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2444
2445
  /// For any value types we are promoting or expanding, this contains the value
2446
  /// type that we are changing to.  For Expanded types, this contains one step
2447
  /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2448
  /// (e.g. i64 -> i16).  For types natively supported by the system, this holds
2449
  /// the same type (e.g. i32 -> i32).
2450
  MVT TransformToType[MVT::LAST_VALUETYPE];
2451
2452
  /// For each operation and each value type, keep a LegalizeAction that
2453
  /// indicates how instruction selection should deal with the operation.  Most
2454
  /// operations are Legal (aka, supported natively by the target), but
2455
  /// operations that are not should be described.  Note that operations on
2456
  /// non-legal value types are not described here.
2457
  LegalizeAction OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
2458
2459
  /// For each load extension type and each value type, keep a LegalizeAction
2460
  /// that indicates how instruction selection should deal with a load of a
2461
  /// specific value type and extension type. Uses 4-bits to store the action
2462
  /// for each of the 4 load ext types.
2463
  uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2464
2465
  /// For each value type pair keep a LegalizeAction that indicates whether a
2466
  /// truncating store of a specific value type and truncating type is legal.
2467
  LegalizeAction TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2468
2469
  /// For each indexed mode and each value type, keep a pair of LegalizeAction
2470
  /// that indicates how instruction selection should deal with the load /
2471
  /// store.
2472
  ///
2473
  /// The first dimension is the value_type for the reference. The second
2474
  /// dimension represents the various modes for load store.
2475
  uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2476
2477
  /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2478
  /// indicates how instruction selection should deal with the condition code.
2479
  ///
2480
  /// Because each CC action takes up 4 bits, we need to have the array size be
2481
  /// large enough to fit all of the value types. This can be done by rounding
2482
  /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2483
  uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2484
2485
protected:
2486
  ValueTypeActionImpl ValueTypeActions;
2487
2488
private:
2489
  LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2490
2491
  /// Targets can specify ISD nodes that they would like PerformDAGCombine
2492
  /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2493
  /// array.
2494
  unsigned char
2495
  TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2496
2497
  /// For operations that must be promoted to a specific type, this holds the
2498
  /// destination type.  This map should be sparse, so don't hold it as an
2499
  /// array.
2500
  ///
2501
  /// Targets add entries to this map with AddPromotedToType(..), clients access
2502
  /// this with getTypeToPromoteTo(..).
2503
  std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2504
    PromoteToType;
2505
2506
  /// Stores the name each libcall.
2507
  const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
2508
2509
  /// The ISD::CondCode that should be used to test the result of each of the
2510
  /// comparison libcall against zero.
2511
  ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2512
2513
  /// Stores the CallingConv that should be used for each libcall.
2514
  CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2515
2516
  /// Set default libcall names and calling conventions.
2517
  void InitLibcalls(const Triple &TT);
2518
2519
protected:
2520
  /// Return true if the extension represented by \p I is free.
2521
  /// \pre \p I is a sign, zero, or fp extension and
2522
  ///      is[Z|FP]ExtFree of the related types is not true.
2523
233k
  virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2524
2525
  /// Depth that GatherAllAliases should should continue looking for chain
2526
  /// dependencies when trying to find a more preferable chain. As an
2527
  /// approximation, this should be more than the number of consecutive stores
2528
  /// expected to be merged.
2529
  unsigned GatherAllAliasesMaxDepth;
2530
2531
  /// Specify maximum number of store instructions per memset call.
2532
  ///
2533
  /// When lowering \@llvm.memset this field specifies the maximum number of
2534
  /// store operations that may be substituted for the call to memset. Targets
2535
  /// must set this value based on the cost threshold for that target. Targets
2536
  /// should assume that the memset will be done using as many of the largest
2537
  /// store operations first, followed by smaller ones, if necessary, per
2538
  /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2539
  /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2540
  /// store.  This only applies to setting a constant array of a constant size.
2541
  unsigned MaxStoresPerMemset;
2542
2543
  /// Maximum number of stores operations that may be substituted for the call
2544
  /// to memset, used for functions with OptSize attribute.
2545
  unsigned MaxStoresPerMemsetOptSize;
2546
2547
  /// Specify maximum bytes of store instructions per memcpy call.
2548
  ///
2549
  /// When lowering \@llvm.memcpy this field specifies the maximum number of
2550
  /// store operations that may be substituted for a call to memcpy. Targets
2551
  /// must set this value based on the cost threshold for that target. Targets
2552
  /// should assume that the memcpy will be done using as many of the largest
2553
  /// store operations first, followed by smaller ones, if necessary, per
2554
  /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2555
  /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2556
  /// and one 1-byte store. This only applies to copying a constant array of
2557
  /// constant size.
2558
  unsigned MaxStoresPerMemcpy;
2559
2560
2561
  /// \brief Specify max number of store instructions to glue in inlined memcpy.
2562
  ///
2563
  /// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number
2564
  /// of store instructions to keep together. This helps in pairing and
2565
  //  vectorization later on.
2566
  unsigned MaxGluedStoresPerMemcpy = 0;
2567
2568
  /// Maximum number of store operations that may be substituted for a call to
2569
  /// memcpy, used for functions with OptSize attribute.
2570
  unsigned MaxStoresPerMemcpyOptSize;
2571
  unsigned MaxLoadsPerMemcmp;
2572
  unsigned MaxLoadsPerMemcmpOptSize;
2573
2574
  /// Specify maximum bytes of store instructions per memmove call.
2575
  ///
2576
  /// When lowering \@llvm.memmove this field specifies the maximum number of
2577
  /// store instructions that may be substituted for a call to memmove. Targets
2578
  /// must set this value based on the cost threshold for that target. Targets
2579
  /// should assume that the memmove will be done using as many of the largest
2580
  /// store operations first, followed by smaller ones, if necessary, per
2581
  /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2582
  /// with 8-bit alignment would result in nine 1-byte stores.  This only
2583
  /// applies to copying a constant array of constant size.
2584
  unsigned MaxStoresPerMemmove;
2585
2586
  /// Maximum number of store instructions that may be substituted for a call to
2587
  /// memmove, used for functions with OptSize attribute.
2588
  unsigned MaxStoresPerMemmoveOptSize;
2589
2590
  /// Tells the code generator that select is more expensive than a branch if
2591
  /// the branch is usually predicted right.
2592
  bool PredictableSelectIsExpensive;
2593
2594
  /// \see enableExtLdPromotion.
2595
  bool EnableExtLdPromotion;
2596
2597
  /// Return true if the value types that can be represented by the specified
2598
  /// register class are all legal.
2599
  bool isLegalRC(const TargetRegisterInfo &TRI,
2600
                 const TargetRegisterClass &RC) const;
2601
2602
  /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2603
  /// sequence of memory operands that is recognized by PrologEpilogInserter.
2604
  MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2605
                                    MachineBasicBlock *MBB) const;
2606
2607
  /// Replace/modify the XRay custom event operands with target-dependent
2608
  /// details.
2609
  MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
2610
                                         MachineBasicBlock *MBB) const;
2611
2612
  /// Replace/modify the XRay typed event operands with target-dependent
2613
  /// details.
2614
  MachineBasicBlock *emitXRayTypedEvent(MachineInstr &MI,
2615
                                        MachineBasicBlock *MBB) const;
2616
};
2617
2618
/// This class defines information used to lower LLVM code to legal SelectionDAG
2619
/// operators that the target instruction selector can accept natively.
2620
///
2621
/// This class also defines callbacks that targets must implement to lower
2622
/// target-specific constructs to SelectionDAG operators.
2623
class TargetLowering : public TargetLoweringBase {
2624
public:
2625
  struct DAGCombinerInfo;
2626
2627
  TargetLowering(const TargetLowering &) = delete;
2628
  TargetLowering &operator=(const TargetLowering &) = delete;
2629
2630
  /// NOTE: The TargetMachine owns TLOF.
2631
  explicit TargetLowering(const TargetMachine &TM);
2632
2633
  bool isPositionIndependent() const;
2634
2635
  virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
2636
                                          FunctionLoweringInfo *FLI,
2637
51.7M
                                          DivergenceAnalysis *DA) const {
2638
51.7M
    return false;
2639
51.7M
  }
2640
2641
43.5M
  virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
2642
43.5M
    return false;
2643
43.5M
  }
2644
2645
  /// Returns true by value, base pointer and offset pointer and addressing mode
2646
  /// by reference if the node's address can be legally represented as
2647
  /// pre-indexed load / store address.
2648
  virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2649
                                         SDValue &/*Offset*/,
2650
                                         ISD::MemIndexedMode &/*AM*/,
2651
0
                                         SelectionDAG &/*DAG*/) const {
2652
0
    return false;
2653
0
  }
2654
2655
  /// Returns true by value, base pointer and offset pointer and addressing mode
2656
  /// by reference if this node can be combined with a load / store to form a
2657
  /// post-indexed load / store.
2658
  virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2659
                                          SDValue &/*Base*/,
2660
                                          SDValue &/*Offset*/,
2661
                                          ISD::MemIndexedMode &/*AM*/,
2662
0
                                          SelectionDAG &/*DAG*/) const {
2663
0
    return false;
2664
0
  }
2665
2666
  /// Return the entry encoding for a jump table in the current function.  The
2667
  /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2668
  virtual unsigned getJumpTableEncoding() const;
2669
2670
  virtual const MCExpr *
2671
  LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
2672
                            const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2673
0
                            MCContext &/*Ctx*/) const {
2674
0
    llvm_unreachable("Need to implement this hook if target has custom JTIs");
2675
0
  }
2676
2677
  /// Returns relocation base for the given PIC jumptable.
2678
  virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2679
                                           SelectionDAG &DAG) const;
2680
2681
  /// This returns the relocation base for the given PIC jumptable, the same as
2682
  /// getPICJumpTableRelocBase, but as an MCExpr.
2683
  virtual const MCExpr *
2684
  getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2685
                               unsigned JTI, MCContext &Ctx) const;
2686
2687
  /// Return true if folding a constant offset with the given GlobalAddress is
2688
  /// legal.  It is frequently not legal in PIC relocation models.
2689
  virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2690
2691
  bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2692
                            SDValue &Chain) const;
2693
2694
  void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
2695
                           SDValue &NewRHS, ISD::CondCode &CCCode,
2696
                           const SDLoc &DL) const;
2697
2698
  /// Returns a pair of (return value, chain).
2699
  /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2700
  std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2701
                                          EVT RetVT, ArrayRef<SDValue> Ops,
2702
                                          bool isSigned, const SDLoc &dl,
2703
                                          bool doesNotReturn = false,
2704
                                          bool isReturnValueUsed = true) const;
2705
2706
  /// Check whether parameters to a call that are passed in callee saved
2707
  /// registers are the same as from the calling function.  This needs to be
2708
  /// checked for tail call eligibility.
2709
  bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
2710
      const uint32_t *CallerPreservedMask,
2711
      const SmallVectorImpl<CCValAssign> &ArgLocs,
2712
      const SmallVectorImpl<SDValue> &OutVals) const;
2713
2714
  //===--------------------------------------------------------------------===//
2715
  // TargetLowering Optimization Methods
2716
  //
2717
2718
  /// A convenience struct that encapsulates a DAG, and two SDValues for
2719
  /// returning information from TargetLowering to its clients that want to
2720
  /// combine.
2721
  struct TargetLoweringOpt {
2722
    SelectionDAG &DAG;
2723
    bool LegalTys;
2724
    bool LegalOps;
2725
    SDValue Old;
2726
    SDValue New;
2727
2728
    explicit TargetLoweringOpt(SelectionDAG &InDAG,
2729
                               bool LT, bool LO) :
2730
7.90M
      DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2731
2732
158k
    bool LegalTypes() const { return LegalTys; }
2733
113k
    bool LegalOperations() const { return LegalOps; }
2734
2735
384k
    bool CombineTo(SDValue O, SDValue N) {
2736
384k
      Old = O;
2737
384k
      New = N;
2738
384k
      return true;
2739
384k
    }
2740
  };
2741
2742
  /// Check to see if the specified operand of the specified instruction is a
2743
  /// constant integer.  If so, check to see if there are any bits set in the
2744
  /// constant that are not demanded.  If so, shrink the constant and return
2745
  /// true.
2746
  bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2747
                              TargetLoweringOpt &TLO) const;
2748
2749
  // Target hook to do target-specific const optimization, which is called by
2750
  // ShrinkDemandedConstant. This function should return true if the target
2751
  // doesn't want ShrinkDemandedConstant to further optimize the constant.
2752
  virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2753
342k
                                            TargetLoweringOpt &TLO) const {
2754
342k
    return false;
2755
342k
  }
2756
2757
  /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.  This
2758
  /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2759
  /// generalized for targets with other types of implicit widening casts.
2760
  bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2761
                        TargetLoweringOpt &TLO) const;
2762
2763
  /// Helper for SimplifyDemandedBits that can simplify an operation with
2764
  /// multiple uses.  This function simplifies operand \p OpIdx of \p User and
2765
  /// then updates \p User with the simplified version. No other uses of
2766
  /// \p OpIdx are updated. If \p User is the only user of \p OpIdx, this
2767
  /// function behaves exactly like function SimplifyDemandedBits declared
2768
  /// below except that it also updates the DAG by calling
2769
  /// DCI.CommitTargetLoweringOpt.
2770
  bool SimplifyDemandedBits(SDNode *User, unsigned OpIdx, const APInt &Demanded,
2771
                            DAGCombinerInfo &DCI, TargetLoweringOpt &TLO) const;
2772
2773
  /// Look at Op.  At this point, we know that only the DemandedMask bits of the
2774
  /// result of Op are ever used downstream.  If we can use this information to
2775
  /// simplify Op, create a new simplified DAG node and return true, returning
2776
  /// the original and new nodes in Old and New.  Otherwise, analyze the
2777
  /// expression and return a mask of KnownOne and KnownZero bits for the
2778
  /// expression (used to simplify the caller).  The KnownZero/One bits may only
2779
  /// be accurate for those bits in the DemandedMask.
2780
  /// \p AssumeSingleUse When this parameter is true, this function will
2781
  ///    attempt to simplify \p Op even if there are multiple uses.
2782
  ///    Callers are responsible for correctly updating the DAG based on the
2783
  ///    results of this function, because simply replacing replacing TLO.Old
2784
  ///    with TLO.New will be incorrect when this parameter is true and TLO.Old
2785
  ///    has multiple uses.
2786
  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2787
                            KnownBits &Known,
2788
                            TargetLoweringOpt &TLO,
2789
                            unsigned Depth = 0,
2790
                            bool AssumeSingleUse = false) const;
2791
2792
  /// Helper wrapper around SimplifyDemandedBits
2793
  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2794
                            DAGCombinerInfo &DCI) const;
2795
2796
  /// Look at Vector Op. At this point, we know that only the DemandedElts
2797
  /// elements of the result of Op are ever used downstream.  If we can use
2798
  /// this information to simplify Op, create a new simplified DAG node and
2799
  /// return true, storing the original and new nodes in TLO.
2800
  /// Otherwise, analyze the expression and return a mask of KnownUndef and
2801
  /// KnownZero elements for the expression (used to simplify the caller).
2802
  /// The KnownUndef/Zero elements may only be accurate for those bits
2803
  /// in the DemandedMask.
2804
  /// \p AssumeSingleUse When this parameter is true, this function will
2805
  ///    attempt to simplify \p Op even if there are multiple uses.
2806
  ///    Callers are responsible for correctly updating the DAG based on the
2807
  ///    results of this function, because simply replacing replacing TLO.Old
2808
  ///    with TLO.New will be incorrect when this parameter is true and TLO.Old
2809
  ///    has multiple uses.
2810
  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
2811
                                  APInt &KnownUndef, APInt &KnownZero,
2812
                                  TargetLoweringOpt &TLO, unsigned Depth = 0,
2813
                                  bool AssumeSingleUse = false) const;
2814
2815
  /// Helper wrapper around SimplifyDemandedVectorElts
2816
  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
2817
                                  APInt &KnownUndef, APInt &KnownZero,
2818
                                  DAGCombinerInfo &DCI) const;
2819
2820
  /// Determine which of the bits specified in Mask are known to be either zero
2821
  /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
2822
  /// argument allows us to only collect the known bits that are shared by the
2823
  /// requested vector elements.
2824
  virtual void computeKnownBitsForTargetNode(const SDValue Op,
2825
                                             KnownBits &Known,
2826
                                             const APInt &DemandedElts,
2827
                                             const SelectionDAG &DAG,
2828
                                             unsigned Depth = 0) const;
2829
2830
  /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
2831
  /// Default implementation computes low bits based on alignment
2832
  /// information. This should preserve known bits passed into it.
2833
  virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
2834
                                             KnownBits &Known,
2835
                                             const APInt &DemandedElts,
2836
                                             const SelectionDAG &DAG,
2837
                                             unsigned Depth = 0) const;
2838
2839
  /// This method can be implemented by targets that want to expose additional
2840
  /// information about sign bits to the DAG Combiner. The DemandedElts
2841
  /// argument allows us to only collect the minimum sign bits that are shared
2842
  /// by the requested vector elements.
2843
  virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2844
                                                   const APInt &DemandedElts,
2845
                                                   const SelectionDAG &DAG,
2846
                                                   unsigned Depth = 0) const;
2847
2848
  /// Attempt to simplify any target nodes based on the demanded vector
2849
  /// elements, returning true on success. Otherwise, analyze the expression and
2850
  /// return a mask of KnownUndef and KnownZero elements for the expression
2851
  /// (used to simplify the caller). The KnownUndef/Zero elements may only be
2852
  /// accurate for those bits in the DemandedMask
2853
  virtual bool SimplifyDemandedVectorEltsForTargetNode(
2854
      SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
2855
      APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2856
2857
  struct DAGCombinerInfo {
2858
    void *DC;  // The DAG Combiner object.
2859
    CombineLevel Level;
2860
    bool CalledByLegalizer;
2861
2862
  public:
2863
    SelectionDAG &DAG;
2864
2865
    DAGCombinerInfo(SelectionDAG &dag, CombineLevel level,  bool cl, void *dc)
2866
23.2M
      : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2867
2868
5.28M
    bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2869
5.76M
    bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2870
228k
    bool isAfterLegalizeDAG() const {
2871
228k
      return Level == AfterLegalizeDAG;
2872
228k
    }
2873
168k
    CombineLevel getDAGCombineLevel() { return Level; }
2874
44.8k
    bool isCalledByLegalizer() const { return CalledByLegalizer; }
2875
2876
    void AddToWorklist(SDNode *N);
2877
    SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
2878
    SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2879
    SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2880
2881
    void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2882
  };
2883
2884
  /// Return if the N is a constant or constant vector equal to the true value
2885
  /// from getBooleanContents().
2886
  bool isConstTrueVal(const SDNode *N) const;
2887
2888
  /// Return if the N is a constant or constant vector equal to the false value
2889
  /// from getBooleanContents().
2890
  bool isConstFalseVal(const SDNode *N) const;
2891
2892
  /// Return if \p N is a True value when extended to \p VT.
2893
  bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool Signed) const;
2894
2895
  /// Try to simplify a setcc built with the specified operands and cc. If it is
2896
  /// unable to simplify it, return a null SDValue.
2897
  SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
2898
                        bool foldBooleans, DAGCombinerInfo &DCI,
2899
                        const SDLoc &dl) const;
2900
2901
  // For targets which wrap address, unwrap for analysis.
2902
50.2M
  virtual SDValue unwrapAddress(SDValue N) const { return N; }
2903
2904
  /// Returns true (and the GlobalValue and the offset) if the node is a
2905
  /// GlobalAddress + offset.
2906
  virtual bool
2907
  isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2908
2909
  /// This method will be invoked for all target nodes and for any
2910
  /// target-independent nodes that the target has registered with invoke it
2911
  /// for.
2912
  ///
2913
  /// The semantics are as follows:
2914
  /// Return Value:
2915
  ///   SDValue.Val == 0   - No change was made
2916
  ///   SDValue.Val == N   - N was replaced, is dead, and is already handled.
2917
  ///   otherwise          - N should be replaced by the returned Operand.
2918
  ///
2919
  /// In addition, methods provided by DAGCombinerInfo may be used to perform
2920
  /// more complex transformations.
2921
  ///
2922
  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2923
2924
  /// Return true if it is profitable to move a following shift through this
2925
  //  node, adjusting any immediate operands as necessary to preserve semantics.
2926
  //  This transformation may not be desirable if it disrupts a particularly
2927
  //  auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2928
  //  By default, it returns true.
2929
959
  virtual bool isDesirableToCommuteWithShift(const SDNode *N) const {
2930
959
    return true;
2931
959
  }
2932
2933
  // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
2934
  // to a shuffle and a truncate.
2935
  // Example of such a combine:
2936
  // v4i32 build_vector((extract_elt V, 1),
2937
  //                    (extract_elt V, 3),
2938
  //                    (extract_elt V, 5),
2939
  //                    (extract_elt V, 7))
2940
  //  -->
2941
  // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
2942
  virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(
2943
0
      ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
2944
0
    return false;
2945
0
  }
2946
2947
  /// Return true if the target has native support for the specified value type
2948
  /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2949
  /// i16 is legal, but undesirable since i16 instruction encodings are longer
2950
  /// and some i16 instructions are slow.
2951
3.35M
  virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2952
3.35M
    // By default, assume all legal types are desirable.
2953
3.35M
    return isTypeLegal(VT);
2954
3.35M
  }
2955
2956
  /// Return true if it is profitable for dag combiner to transform a floating
2957
  /// point op of specified opcode to a equivalent op of an integer
2958
  /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2959
  virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2960
384
                                                 EVT /*VT*/) const {
2961
384
    return false;
2962
384
  }
2963
2964
  /// This method query the target whether it is beneficial for dag combiner to
2965
  /// promote the specified node. If true, it should return the desired
2966
  /// promotion type by reference.
2967
3.79k
  virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2968
3.79k
    return false;
2969
3.79k
  }
2970
2971
  /// Return true if the target supports swifterror attribute. It optimizes
2972
  /// loads and stores to reading and writing a specific register.
2973
391k
  virtual bool supportSwiftError() const {
2974
391k
    return false;
2975
391k
  }
2976
2977
  /// Return true if the target supports that a subset of CSRs for the given
2978
  /// machine function is handled explicitly via copies.
2979
27.2k
  virtual bool supportSplitCSR(MachineFunction *MF) const {
2980
27.2k
    return false;
2981
27.2k
  }
2982
2983
  /// Perform necessary initialization to handle a subset of CSRs explicitly
2984
  /// via copies. This function is called at the beginning of instruction
2985
  /// selection.
2986
0
  virtual void initializeSplitCSR(MachineBasicBlock *Entry) const {
2987
0
    llvm_unreachable("Not Implemented");
2988
0
  }
2989
2990
  /// Insert explicit copies in entry and exit blocks. We copy a subset of
2991
  /// CSRs to virtual registers in the entry block, and copy them back to
2992
  /// physical registers in the exit blocks. This function is called at the end
2993
  /// of instruction selection.
2994
  virtual void insertCopiesSplitCSR(
2995
      MachineBasicBlock *Entry,
2996
0
      const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
2997
0
    llvm_unreachable("Not Implemented");
2998
0
  }
2999
3000
  //===--------------------------------------------------------------------===//
3001
  // Lowering methods - These methods must be implemented by targets so that
3002
  // the SelectionDAGBuilder code knows how to lower these.
3003
  //
3004
3005
  /// This hook must be implemented to lower the incoming (formal) arguments,
3006
  /// described by the Ins array, into the specified DAG. The implementation
3007
  /// should fill in the InVals array with legal-type argument values, and
3008
  /// return the resulting token chain value.
3009
  virtual SDValue LowerFormalArguments(
3010
      SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
3011
      const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
3012
0
      SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
3013
0
    llvm_unreachable("Not Implemented");
3014
0
  }
3015
3016
  /// This structure contains all information that is necessary for lowering
3017
  /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
3018
  /// needs to lower a call, and targets will see this struct in their LowerCall
3019
  /// implementation.
3020
  struct CallLoweringInfo {
3021
    SDValue Chain;
3022
    Type *RetTy = nullptr;
3023
    bool RetSExt           : 1;
3024
    bool RetZExt           : 1;
3025
    bool IsVarArg          : 1;
3026
    bool IsInReg           : 1;
3027
    bool DoesNotReturn     : 1;
3028
    bool IsReturnValueUsed : 1;
3029
    bool IsConvergent      : 1;
3030
    bool IsPatchPoint      : 1;
3031
3032
    // IsTailCall should be modified by implementations of
3033
    // TargetLowering::LowerCall that perform tail call conversions.
3034
    bool IsTailCall = false;
3035
3036
    // Is Call lowering done post SelectionDAG type legalization.
3037
    bool IsPostTypeLegalization = false;
3038
3039
    unsigned NumFixedArgs = -1;
3040
    CallingConv::ID CallConv = CallingConv::C;
3041
    SDValue Callee;
3042
    ArgListTy Args;
3043
    SelectionDAG &DAG;
3044
    SDLoc DL;
3045
    ImmutableCallSite CS;
3046
    SmallVector<ISD::OutputArg, 32> Outs;
3047
    SmallVector<SDValue, 32> OutVals;
3048
    SmallVector<ISD::InputArg, 32> Ins;
3049
    SmallVector<SDValue, 4> InVals;
3050
3051
    CallLoweringInfo(SelectionDAG &DAG)
3052
        : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
3053
          DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
3054
754k
          IsPatchPoint(false), DAG(DAG) {}
3055
3056
754k
    CallLoweringInfo &setDebugLoc(const SDLoc &dl) {
3057
754k
      DL = dl;
3058
754k
      return *this;
3059
754k
    }
3060
3061
774k
    CallLoweringInfo &setChain(SDValue InChain) {
3062
774k
      Chain = InChain;
3063
774k
      return *this;
3064
774k
    }
3065
3066
    // setCallee with target/module-specific attributes
3067
    CallLoweringInfo &setLibCallee(CallingConv::ID CC, Type *ResultType,
3068
19.6k
                                   SDValue Target, ArgListTy &&ArgsList) {
3069
19.6k
      RetTy = ResultType;
3070
19.6k
      Callee = Target;
3071
19.6k
      CallConv = CC;
3072
19.6k
      NumFixedArgs = ArgsList.size();
3073
19.6k
      Args = std::move(ArgsList);
3074
19.6k
3075
19.6k
      DAG.getTargetLoweringInfo().markLibCallAttributes(
3076
19.6k
          &(DAG.getMachineFunction()), CC, Args);
3077
19.6k
      return *this;
3078
19.6k
    }
3079
3080
    CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
3081
595
                                SDValue Target, ArgListTy &&ArgsList) {
3082
595
      RetTy = ResultType;
3083
595
      Callee = Target;
3084
595
      CallConv = CC;
3085
595
      NumFixedArgs = ArgsList.size();
3086
595
      Args = std::move(ArgsList);
3087
595
      return *this;
3088
595
    }
3089
3090
    CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
3091
                                SDValue Target, ArgListTy &&ArgsList,
3092
734k
                                ImmutableCallSite Call) {
3093
734k
      RetTy = ResultType;
3094
734k
3095
734k
      IsInReg = Call.hasRetAttr(Attribute::InReg);
3096
734k
      DoesNotReturn =
3097
734k
          Call.doesNotReturn() ||
3098
734k
          
(706k
!Call.isInvoke()706k
&&
3099
706k
           
isa<UnreachableInst>(Call.getInstruction()->getNextNode())687k
);
3100
734k
      IsVarArg = FTy->isVarArg();
3101
734k
      IsReturnValueUsed = !Call.getInstruction()->use_empty();
3102
734k
      RetSExt = Call.hasRetAttr(Attribute::SExt);
3103
734k
      RetZExt = Call.hasRetAttr(Attribute::ZExt);
3104
734k
3105
734k
      Callee = Target;
3106
734k
3107
734k
      CallConv = Call.getCallingConv();
3108
734k
      NumFixedArgs = FTy->getNumParams();
3109
734k
      Args = std::move(ArgsList);
3110
734k
3111
734k
      CS = Call;
3112
734k
3113
734k
      return *this;
3114
734k
    }
3115
3116
197
    CallLoweringInfo &setInRegister(bool Value = true) {
3117
197
      IsInReg = Value;
3118
197
      return *this;
3119
197
    }
3120
3121
6.79k
    CallLoweringInfo &setNoReturn(bool Value = true) {
3122
6.79k
      DoesNotReturn = Value;
3123
6.79k
      return *this;
3124
6.79k
    }
3125
3126
    CallLoweringInfo &setVarArg(bool Value = true) {
3127
      IsVarArg = Value;
3128
      return *this;
3129
    }
3130
3131
740k
    CallLoweringInfo &setTailCall(bool Value = true) {
3132
740k
      IsTailCall = Value;
3133
740k
      return *this;
3134
740k
    }
3135
3136
15.2k
    CallLoweringInfo &setDiscardResult(bool Value = true) {
3137
15.2k
      IsReturnValueUsed = !Value;
3138
15.2k
      return *this;
3139
15.2k
    }
3140
3141
734k
    CallLoweringInfo &setConvergent(bool Value = true) {
3142
734k
      IsConvergent = Value;
3143
734k
      return *this;
3144
734k
    }
3145
3146
11.0k
    CallLoweringInfo &setSExtResult(bool Value = true) {
3147
11.0k
      RetSExt = Value;
3148
11.0k
      return *this;
3149
11.0k
    }
3150
3151
11.0k
    CallLoweringInfo &setZExtResult(bool Value = true) {
3152
11.0k
      RetZExt = Value;
3153
11.0k
      return *this;
3154
11.0k
    }
3155
3156
216
    CallLoweringInfo &setIsPatchPoint(bool Value = true) {
3157
216
      IsPatchPoint = Value;
3158
216
      return *this;
3159
216
    }
3160
3161
3.41k
    CallLoweringInfo &setIsPostTypeLegalization(bool Value=true) {
3162
3.41k
      IsPostTypeLegalization = Value;
3163
3.41k
      return *this;
3164
3.41k
    }
3165
3166
1.95M
    ArgListTy &getArgs() {
3167
1.95M
      return Args;
3168
1.95M
    }
3169
  };
3170
3171
  /// This function lowers an abstract call to a function into an actual call.
3172
  /// This returns a pair of operands.  The first element is the return value
3173
  /// for the function (if RetTy is not VoidTy).  The second element is the
3174
  /// outgoing token chain. It calls LowerCall to do the actual lowering.
3175
  std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
3176
3177
  /// This hook must be implemented to lower calls into the specified
3178
  /// DAG. The outgoing arguments to the call are described by the Outs array,
3179
  /// and the values to be returned by the call are described by the Ins
3180
  /// array. The implementation should fill in the InVals array with legal-type
3181
  /// return values from the call, and return the resulting token chain value.
3182
  virtual SDValue
3183
    LowerCall(CallLoweringInfo &/*CLI*/,
3184
0
              SmallVectorImpl<SDValue> &/*InVals*/) const {
3185
0
    llvm_unreachable("Not Implemented");
3186
0
  }
3187
3188
  /// Target-specific cleanup for formal ByVal parameters.
3189
1.06k
  virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
3190
3191
  /// This hook should be implemented to check whether the return values
3192
  /// described by the Outs array can fit into the return registers.  If false
3193
  /// is returned, an sret-demotion is performed.
3194
  virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
3195
                              MachineFunction &/*MF*/, bool /*isVarArg*/,
3196
               const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
3197
               LLVMContext &/*Context*/) const
3198
5.40k
  {
3199
5.40k
    // Return true by default to get preexisting behavior.
3200
5.40k
    return true;
3201
5.40k
  }
3202
3203
  /// This hook must be implemented to lower outgoing return values, described
3204
  /// by the Outs array, into the specified DAG. The implementation should
3205
  /// return the resulting token chain value.
3206
  virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
3207
                              bool /*isVarArg*/,
3208
                              const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
3209
                              const SmallVectorImpl<SDValue> & /*OutVals*/,
3210
                              const SDLoc & /*dl*/,
3211
0
                              SelectionDAG & /*DAG*/) const {
3212
0
    llvm_unreachable("Not Implemented");
3213
0
  }
3214
3215
  /// Return true if result of the specified node is used by a return node
3216
  /// only. It also compute and return the input chain for the tail call.
3217
  ///
3218
  /// This is used to determine whether it is possible to codegen a libcall as
3219
  /// tail call at legalization time.
3220
605
  virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
3221
605
    return false;
3222
605
  }
3223
3224
  /// Return true if the target may be able emit the call instruction as a tail
3225
  /// call. This is used by optimization passes to determine if it's profitable
3226
  /// to duplicate return instructions to enable tailcall optimization.
3227
147
  virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
3228
147
    return false;
3229
147
  }
3230
3231
  /// Return the builtin name for the __builtin___clear_cache intrinsic
3232
  /// Default is to invoke the clear cache library call
3233
2
  virtual const char * getClearCacheBuiltinName() const {
3234
2
    return "__clear_cache";
3235
2
  }
3236
3237
  /// Return the register ID of the name passed in. Used by named register
3238
  /// global variables extension. There is no target-independent behaviour
3239
  /// so the default action is to bail.
3240
  virtual unsigned getRegisterByName(const char* RegName, EVT VT,
3241
0
                                     SelectionDAG &DAG) const {
3242
0
    report_fatal_error("Named registers not implemented for this target");
3243
0
  }
3244
3245
  /// Return the type that should be used to zero or sign extend a
3246
  /// zeroext/signext integer return value.  FIXME: Some C calling conventions
3247
  /// require the return type to be promoted, but this is not true all the time,
3248
  /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3249
  /// conventions. The frontend should handle this and include all of the
3250
  /// necessary information.
3251
  virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
3252
6.16k
                                       ISD::NodeType /*ExtendKind*/) const {
3253
6.16k
    EVT MinVT = getRegisterType(Context, MVT::i32);
3254
6.16k
    return VT.bitsLT(MinVT) ? 
MinVT3.94k
:
VT2.22k
;
3255
6.16k
  }
3256
3257
  /// For some targets, an LLVM struct type must be broken down into multiple
3258
  /// simple types, but the calling convention specifies that the entire struct
3259
  /// must be passed in a block of consecutive registers.
3260
  virtual bool
3261
  functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
3262
691k
                                            bool isVarArg) const {
3263
691k
    return false;
3264
691k
  }
3265
3266
  /// Returns a 0 terminated array of registers that can be safely used as
3267
  /// scratch registers.
3268
0
  virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
3269
0
    return nullptr;
3270
0
  }
3271
3272
  /// This callback is used to prepare for a volatile or atomic load.
3273
  /// It takes a chain node as input and returns the chain for the load itself.
3274
  ///
3275
  /// Having a callback like this is necessary for targets like SystemZ,
3276
  /// which allows a CPU to reuse the result of a previous load indefinitely,
3277
  /// even if a cache-coherent store is performed by another CPU.  The default
3278
  /// implementation does nothing.
3279
  virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL,
3280
17.5k
                                              SelectionDAG &DAG) const {
3281
17.5k
    return Chain;
3282
17.5k
  }
3283
3284
  /// This callback is used to inspect load/store instructions and add
3285
  /// target-specific MachineMemOperand flags to them.  The default
3286
  /// implementation does nothing.
3287
488k
  virtual MachineMemOperand::Flags getMMOFlags(const Instruction &I) const {
3288
488k
    return MachineMemOperand::MONone;
3289
488k
  }
3290
3291
  /// This callback is invoked by the type legalizer to legalize nodes with an
3292
  /// illegal operand type but legal result types.  It replaces the
3293
  /// LowerOperation callback in the type Legalizer.  The reason we can not do
3294
  /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3295
  /// use this callback.
3296
  ///
3297
  /// TODO: Consider merging with ReplaceNodeResults.
3298
  ///
3299
  /// The target places new result values for the node in Results (their number
3300
  /// and types must exactly match those of the original return values of
3301
  /// the node), or leaves Results empty, which indicates that the node is not
3302
  /// to be custom lowered after all.
3303
  /// The default implementation calls LowerOperation.
3304
  virtual void LowerOperationWrapper(SDNode *N,
3305
                                     SmallVectorImpl<SDValue> &Results,
3306
                                     SelectionDAG &DAG) const;
3307
3308
  /// This callback is invoked for operations that are unsupported by the
3309
  /// target, which are registered to use 'custom' lowering, and whose defined
3310
  /// values are all legal.  If the target has no operations that require custom
3311
  /// lowering, it need not implement this.  The default implementation of this
3312
  /// aborts.
3313
  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
3314
3315
  /// This callback is invoked when a node result type is illegal for the
3316
  /// target, and the operation was registered to use 'custom' lowering for that
3317
  /// result type.  The target places new result values for the node in Results
3318
  /// (their number and types must exactly match those of the original return
3319
  /// values of the node), or leaves Results empty, which indicates that the
3320
  /// node is not to be custom lowered after all.
3321
  ///
3322
  /// If the target has no operations that require custom lowering, it need not
3323
  /// implement this.  The default implementation aborts.
3324
  virtual void ReplaceNodeResults(SDNode * /*N*/,
3325
                                  SmallVectorImpl<SDValue> &/*Results*/,
3326
0
                                  SelectionDAG &/*DAG*/) const {
3327
0
    llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3328
0
  }
3329
3330
  /// This method returns the name of a target specific DAG node.
3331
  virtual const char *getTargetNodeName(unsigned Opcode) const;
3332
3333
  /// This method returns a target specific FastISel object, or null if the
3334
  /// target does not support "fast" ISel.
3335
  virtual FastISel *createFastISel(FunctionLoweringInfo &,
3336
2.55k
                                   const TargetLibraryInfo *) const {
3337
2.55k
    return nullptr;
3338
2.55k
  }
3339
3340
  bool verifyReturnAddressArgumentIsConstant(SDValue Op,
3341
                                             SelectionDAG &DAG) const;
3342
3343
  //===--------------------------------------------------------------------===//
3344
  // Inline Asm Support hooks
3345
  //
3346
3347
  /// This hook allows the target to expand an inline asm call to be explicit
3348
  /// llvm code if it wants to.  This is useful for turning simple inline asms
3349
  /// into LLVM intrinsics, which gives the compiler more information about the
3350
  /// behavior of the code.
3351
4.92k
  virtual bool ExpandInlineAsm(CallInst *) const {
3352
4.92k
    return false;
3353
4.92k
  }
3354
3355
  enum ConstraintType {
3356
    C_Register,            // Constraint represents specific register(s).
3357
    C_RegisterClass,       // Constraint represents any of register(s) in class.
3358
    C_Memory,              // Memory constraint.
3359
    C_Other,               // Something else.
3360
    C_Unknown              // Unsupported constraint.
3361
  };
3362
3363
  enum ConstraintWeight {
3364
    // Generic weights.
3365
    CW_Invalid  = -1,     // No match.
3366
    CW_Okay     = 0,      // Acceptable.
3367
    CW_Good     = 1,      // Good weight.
3368
    CW_Better   = 2,      // Better weight.
3369
    CW_Best     = 3,      // Best weight.
3370
3371
    // Well-known weights.
3372
    CW_SpecificReg  = CW_Okay,    // Specific register operands.
3373
    CW_Register     = CW_Good,    // Register operands.
3374
    CW_Memory       = CW_Better,  // Memory operands.
3375
    CW_Constant     = CW_Best,    // Constant operand.
3376
    CW_Default      = CW_Okay     // Default or don't know type.
3377
  };
3378
3379
  /// This contains information for each constraint that we are lowering.
3380
  struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3381
    /// This contains the actual string for the code, like "m".  TargetLowering
3382
    /// picks the 'best' code from ConstraintInfo::Codes that most closely
3383
    /// matches the operand.
3384
    std::string ConstraintCode;
3385
3386
    /// Information about the constraint code, e.g. Register, RegisterClass,
3387
    /// Memory, Other, Unknown.
3388
    TargetLowering::ConstraintType ConstraintType = TargetLowering::C_Unknown;
3389
3390
    /// If this is the result output operand or a clobber, this is null,
3391
    /// otherwise it is the incoming operand to the CallInst.  This gets
3392
    /// modified as the asm is processed.
3393
    Value *CallOperandVal = nullptr;
3394
3395
    /// The ValueType for the operand value.
3396
    MVT ConstraintVT = MVT::Other;
3397
3398
    /// Copy constructor for copying from a ConstraintInfo.
3399
    AsmOperandInfo(InlineAsm::ConstraintInfo Info)
3400
334k
        : InlineAsm::ConstraintInfo(std::move(Info)) {}
3401
3402
    /// Return true of this is an input operand that is a matching constraint
3403
    /// like "4".
3404
    bool isMatchingInputConstraint() const;
3405
3406
    /// If this is an input matching constraint, this method returns the output
3407
    /// operand it matches.
3408
    unsigned getMatchedOperand() const;
3409
  };
3410
3411
  using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
3412
3413
  /// Split up the constraint string from the inline assembly value into the
3414
  /// specific constraints and their prefixes, and also tie in the associated
3415
  /// operand values.  If this returns an empty vector, and if the constraint
3416
  /// string itself isn't empty, there was an error parsing.
3417
  virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
3418
                                                const TargetRegisterInfo *TRI,
3419
                                                ImmutableCallSite CS) const;
3420
3421
  /// Examine constraint type and operand type and determine a weight value.
3422
  /// The operand object must already have been set up with the operand type.
3423
  virtual ConstraintWeight getMultipleConstraintMatchWeight(
3424
      AsmOperandInfo &info, int maIndex) const;
3425
3426
  /// Examine constraint string and operand type and determine a weight value.
3427
  /// The operand object must already have been set up with the operand type.
3428
  virtual ConstraintWeight getSingleConstraintMatchWeight(
3429
      AsmOperandInfo &info, const char *constraint) const;
3430
3431
  /// Determines the constraint code and constraint type to use for the specific
3432
  /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3433
  /// If the actual operand being passed in is available, it can be passed in as
3434
  /// Op, otherwise an empty SDValue can be passed.
3435
  virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3436
                                      SDValue Op,
3437
                                      SelectionDAG *DAG = nullptr) const;
3438
3439
  /// Given a constraint, return the type of constraint it is for this target.
3440
  virtual ConstraintType getConstraintType(StringRef Constraint) const;
3441
3442
  /// Given a physical register constraint (e.g.  {edx}), return the register
3443
  /// number and the register class for the register.
3444
  ///
3445
  /// Given a register class constraint, like 'r', if this corresponds directly
3446
  /// to an LLVM register class, return a register of 0 and the register class
3447
  /// pointer.
3448
  ///
3449
  /// This should only be used for C_Register constraints.  On error, this
3450
  /// returns a register number of 0 and a null register class pointer.
3451
  virtual std::pair<unsigned, const TargetRegisterClass *>
3452
  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3453
                               StringRef Constraint, MVT VT) const;
3454
3455
3.00k
  virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
3456
3.00k
    if (ConstraintCode == "i")
3457
0
      return InlineAsm::Constraint_i;
3458
3.00k
    else if (ConstraintCode == "m")
3459
3.00k
      return InlineAsm::Constraint_m;
3460
0
    return InlineAsm::Constraint_Unknown;
3461
0
  }
3462
3463
  /// Try to replace an X constraint, which matches anything, with another that
3464
  /// has more specific requirements based on the type of the corresponding
3465
  /// operand.  This returns null if there is no replacement to make.
3466
  virtual const char *LowerXConstraint(EVT ConstraintVT) const;
3467
3468
  /// Lower the specified operand into the Ops vector.  If it is invalid, don't
3469
  /// add anything to Ops.
3470
  virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
3471
                                            std::vector<SDValue> &Ops,
3472
                                            SelectionDAG &DAG) const;
3473
3474
  //===--------------------------------------------------------------------===//
3475
  // Div utility functions
3476
  //
3477
  SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
3478
                    bool IsAfterLegalization,
3479
                    std::vector<SDNode *> *Created) const;
3480
  SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
3481
                    bool IsAfterLegalization,
3482
                    std::vector<SDNode *> *Created) const;
3483
3484
  /// Targets may override this function to provide custom SDIV lowering for
3485
  /// power-of-2 denominators.  If the target returns an empty SDValue, LLVM
3486
  /// assumes SDIV is expensive and replaces it with a series of other integer
3487
  /// operations.
3488
  virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
3489
                                SelectionDAG &DAG,
3490
                                std::vector<SDNode *> *Created) const;
3491
3492
  /// Indicate whether this target prefers to combine FDIVs with the same
3493
  /// divisor. If the transform should never be done, return zero. If the
3494
  /// transform should be done, return the minimum number of divisor uses
3495
  /// that must exist.
3496
52
  virtual unsigned combineRepeatedFPDivisors() const {
3497
52
    return 0;
3498
52
  }
3499
3500
  /// Hooks for building estimates in place of slower divisions and square
3501
  /// roots.
3502
3503
  /// Return either a square root or its reciprocal estimate value for the input
3504
  /// operand.
3505
  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3506
  /// 'Enabled' as set by a potential default override attribute.
3507
  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3508
  /// refinement iterations required to generate a sufficient (though not
3509
  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3510
  /// The boolean UseOneConstNR output is used to select a Newton-Raphson
3511
  /// algorithm implementation that uses either one or two constants.
3512
  /// The boolean Reciprocal is used to select whether the estimate is for the
3513
  /// square root of the input operand or the reciprocal of its square root.
3514
  /// A target may choose to implement its own refinement within this function.
3515
  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3516
  /// any further refinement of the estimate.
3517
  /// An empty SDValue return means no estimate sequence can be created.
3518
  virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
3519
                                  int Enabled, int &RefinementSteps,
3520
0
                                  bool &UseOneConstNR, bool Reciprocal) const {
3521
0
    return SDValue();
3522
0
  }
3523
3524
  /// Return a reciprocal estimate value for the input operand.
3525
  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3526
  /// 'Enabled' as set by a potential default override attribute.
3527
  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3528
  /// refinement iterations required to generate a sufficient (though not
3529
  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3530
  /// A target may choose to implement its own refinement within this function.
3531
  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3532
  /// any further refinement of the estimate.
3533
  /// An empty SDValue return means no estimate sequence can be created.
3534
  virtual SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG,
3535
42
                                   int Enabled, int &RefinementSteps) const {
3536
42
    return SDValue();
3537
42
  }
3538
3539
  //===--------------------------------------------------------------------===//
3540
  // Legalization utility functions
3541
  //
3542
3543
  /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
3544
  /// respectively, each computing an n/2-bit part of the result.
3545
  /// \param Result A vector that will be filled with the parts of the result
3546
  ///        in little-endian order.
3547
  /// \param LL Low bits of the LHS of the MUL.  You can use this parameter
3548
  ///        if you want to control how low bits are extracted from the LHS.
3549
  /// \param LH High bits of the LHS of the MUL.  See LL for meaning.
3550
  /// \param RL Low bits of the RHS of the MUL.  See LL for meaning
3551
  /// \param RH High bits of the RHS of the MUL.  See LL for meaning.
3552
  /// \returns true if the node has been expanded, false if it has not
3553
  bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
3554
                      SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
3555
                      SelectionDAG &DAG, MulExpansionKind Kind,
3556
                      SDValue LL = SDValue(), SDValue LH = SDValue(),
3557
                      SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3558
3559
  /// Expand a MUL into two nodes.  One that computes the high bits of
3560
  /// the result and one that computes the low bits.
3561
  /// \param HiLoVT The value type to use for the Lo and Hi nodes.
3562
  /// \param LL Low bits of the LHS of the MUL.  You can use this parameter
3563
  ///        if you want to control how low bits are extracted from the LHS.
3564
  /// \param LH High bits of the LHS of the MUL.  See LL for meaning.
3565
  /// \param RL Low bits of the RHS of the MUL.  See LL for meaning
3566
  /// \param RH High bits of the RHS of the MUL.  See LL for meaning.
3567
  /// \returns true if the node has been expanded. false if it has not
3568
  bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
3569
                 SelectionDAG &DAG, MulExpansionKind Kind,
3570
                 SDValue LL = SDValue(), SDValue LH = SDValue(),
3571
                 SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3572
3573
  /// Expand float(f32) to SINT(i64) conversion
3574
  /// \param N Node to expand
3575
  /// \param Result output after conversion
3576
  /// \returns True, if the expansion was successful, false otherwise
3577
  bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3578
3579
  /// Turn load of vector type into a load of the individual elements.
3580
  /// \param LD load to expand
3581
  /// \returns MERGE_VALUEs of the scalar loads with their chains.
3582
  SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
3583
3584
  // Turn a store of a vector type into stores of the individual elements.
3585
  /// \param ST Store with a vector value type
3586
  /// \returns MERGE_VALUs of the individual store chains.
3587
  SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3588
3589
  /// Expands an unaligned load to 2 half-size loads for an integer, and
3590
  /// possibly more for vectors.
3591
  std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
3592
                                                  SelectionDAG &DAG) const;
3593
3594
  /// Expands an unaligned store to 2 half-size stores for integer values, and
3595
  /// possibly more for vectors.
3596
  SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3597
3598
  /// Increments memory address \p Addr according to the type of the value
3599
  /// \p DataVT that should be stored. If the data is stored in compressed
3600
  /// form, the memory address should be incremented according to the number of
3601
  /// the stored elements. This number is equal to the number of '1's bits
3602
  /// in the \p Mask.
3603
  /// \p DataVT is a vector type. \p Mask is a vector value.
3604
  /// \p DataVT and \p Mask have the same number of vector elements.
3605
  SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
3606
                                 EVT DataVT, SelectionDAG &DAG,
3607
                                 bool IsCompressedMemory) const;
3608
3609
  /// Get a pointer to vector element \p Idx located in memory for a vector of
3610
  /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
3611
  /// bounds the returned pointer is unspecified, but will be within the vector
3612
  /// bounds.
3613
  SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
3614
                                  SDValue Idx) const;
3615
3616
  //===--------------------------------------------------------------------===//
3617
  // Instruction Emitting Hooks
3618
  //
3619
3620
  /// This method should be implemented by targets that mark instructions with
3621
  /// the 'usesCustomInserter' flag.  These instructions are special in various
3622
  /// ways, which require special support to insert.  The specified MachineInstr
3623
  /// is created but not inserted into any basic blocks, and this method is
3624
  /// called to expand it into a sequence of instructions, potentially also
3625
  /// creating new basic blocks and control flow.
3626
  /// As long as the returned basic block is different (i.e., we created a new
3627
  /// one), the custom inserter is free to modify the rest of \p MBB.
3628
  virtual MachineBasicBlock *
3629
  EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
3630
3631
  /// This method should be implemented by targets that mark instructions with
3632
  /// the 'hasPostISelHook' flag. These instructions must be adjusted after
3633
  /// instruction selection by target hooks.  e.g. To fill in optional defs for
3634
  /// ARM 's' setting instructions.
3635
  virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
3636
                                             SDNode *Node) const;
3637
3638
  /// If this function returns true, SelectionDAGBuilder emits a
3639
  /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
3640
27
  virtual bool useLoadStackGuardNode() const {
3641
27
    return false;
3642
27
  }
3643
3644
  virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
3645
0
                                      const SDLoc &DL) const {
3646
0
    llvm_unreachable("not implemented for this target");
3647
0
  }
3648
3649
  /// Lower TLS global address SDNode for target independent emulated TLS model.
3650
  virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
3651
                                          SelectionDAG &DAG) const;
3652
3653
  /// Expands target specific indirect branch for the case of JumpTable
3654
  /// expanasion.
3655
  virtual SDValue expandIndirectJTBranch(const SDLoc& dl, SDValue Value, SDValue Addr,
3656
2.33k
                                         SelectionDAG &DAG) const {
3657
2.33k
    return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
3658
2.33k
  }
3659
3660
  // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
3661
  // If we're comparing for equality to zero and isCtlzFast is true, expose the
3662
  // fact that this can be implemented as a ctlz/srl pair, so that the dag
3663
  // combiner can fold the new nodes.
3664
  SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
3665
3666
private:
3667
  SDValue simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
3668
                               ISD::CondCode Cond, DAGCombinerInfo &DCI,
3669
                               const SDLoc &DL) const;
3670
};
3671
3672
/// Given an LLVM IR type and return type attributes, compute the return value
3673
/// EVTs and flags, and optionally also the offsets, if the return value is
3674
/// being lowered to memory.
3675
void GetReturnInfo(Type *ReturnType, AttributeList attr,
3676
                   SmallVectorImpl<ISD::OutputArg> &Outs,
3677
                   const TargetLowering &TLI, const DataLayout &DL);
3678
3679
} // end namespace llvm
3680
3681
#endif // LLVM_CODEGEN_TARGETLOWERING_H