Coverage Report

Created: 2018-09-19 08:35

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/TargetPassConfig.h
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//===- TargetPassConfig.h - Code Generation pass options --------*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// Target-Independent Code Generator Pass Configuration Options pass.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_TARGETPASSCONFIG_H
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#define LLVM_CODEGEN_TARGETPASSCONFIG_H
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#include "llvm/Pass.h"
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#include "llvm/Support/CodeGen.h"
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#include <cassert>
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#include <string>
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namespace llvm {
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class LLVMTargetMachine;
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struct MachineSchedContext;
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class PassConfigImpl;
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class ScheduleDAGInstrs;
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// The old pass manager infrastructure is hidden in a legacy namespace now.
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namespace legacy {
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class PassManagerBase;
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} // end namespace legacy
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using legacy::PassManagerBase;
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/// Discriminated union of Pass ID types.
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///
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/// The PassConfig API prefers dealing with IDs because they are safer and more
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/// efficient. IDs decouple configuration from instantiation. This way, when a
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/// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
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/// refer to a Pass pointer after adding it to a pass manager, which deletes
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/// redundant pass instances.
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///
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/// However, it is convient to directly instantiate target passes with
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/// non-default ctors. These often don't have a registered PassInfo. Rather than
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/// force all target passes to implement the pass registry boilerplate, allow
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/// the PassConfig API to handle either type.
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///
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/// AnalysisID is sadly char*, so PointerIntPair won't work.
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class IdentifyingPassPtr {
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  union {
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    AnalysisID ID;
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    Pass *P;
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  };
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  bool IsInstance = false;
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public:
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34.4k
  IdentifyingPassPtr() : P(nullptr) {}
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1.36M
  IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr) {}
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  IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
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1.36M
  bool isValid() const { return P; }
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1.36M
  bool isInstance() const { return IsInstance; }
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1.36M
  AnalysisID getID() const {
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1.36M
    assert(!IsInstance && "Not a Pass ID");
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1.36M
    return ID;
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1.36M
  }
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0
  Pass *getInstance() const {
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0
    assert(IsInstance && "Not a Pass Instance");
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0
    return P;
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0
  }
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};
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template <> struct isPodLike<IdentifyingPassPtr> {
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  static const bool value = true;
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};
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/// Target-Independent Code Generator Pass Configuration Options.
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///
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/// This is an ImmutablePass solely for the purpose of exposing CodeGen options
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/// to the internals of other CodeGen passes.
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class TargetPassConfig : public ImmutablePass {
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private:
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  PassManagerBase *PM = nullptr;
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  AnalysisID StartBefore = nullptr;
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  AnalysisID StartAfter = nullptr;
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  AnalysisID StopBefore = nullptr;
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  AnalysisID StopAfter = nullptr;
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  bool Started = true;
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  bool Stopped = false;
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  bool AddingMachinePasses = false;
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  /// Set the StartAfter, StartBefore and StopAfter passes to allow running only
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  /// a portion of the normal code-gen pass sequence.
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  ///
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  /// If the StartAfter and StartBefore pass ID is zero, then compilation will
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  /// begin at the normal point; otherwise, clear the Started flag to indicate
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  /// that passes should not be added until the starting pass is seen.  If the
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  /// Stop pass ID is zero, then compilation will continue to the end.
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  ///
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  /// This function expects that at least one of the StartAfter or the
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  /// StartBefore pass IDs is null.
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  void setStartStopPasses();
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protected:
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  LLVMTargetMachine *TM;
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  PassConfigImpl *Impl = nullptr; // Internal data structures
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  bool Initialized = false; // Flagged after all passes are configured.
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  // Target Pass Options
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  // Targets provide a default setting, user flags override.
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  bool DisableVerify = false;
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  /// Default setting for -enable-tail-merge on this target.
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  bool EnableTailMerge = true;
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  /// Require processing of functions such that callees are generated before
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  /// callers.
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  bool RequireCodeGenSCCOrder = false;
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  /// Add the actual instruction selection passes. This does not include
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  /// preparation passes on IR.
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  bool addCoreISelPasses();
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public:
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  TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm);
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  // Dummy constructor.
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  TargetPassConfig();
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  ~TargetPassConfig() override;
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  static char ID;
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  /// Get the right type of TargetMachine for this target.
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3.22M
  template<typename TMC> TMC &getTM() const {
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    return *static_cast<TMC*>(TM);
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  }
llvm::AArch64TargetMachine& llvm::TargetPassConfig::getTM<llvm::AArch64TargetMachine>() const
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262k
  template<typename TMC> TMC &getTM() const {
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    return *static_cast<TMC*>(TM);
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  }
llvm::TargetMachine& llvm::TargetPassConfig::getTM<llvm::TargetMachine>() const
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2.87M
  template<typename TMC> TMC &getTM() const {
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    return *static_cast<TMC*>(TM);
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  }
llvm::AMDGPUTargetMachine& llvm::TargetPassConfig::getTM<llvm::AMDGPUTargetMachine>() const
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23.7k
  template<typename TMC> TMC &getTM() const {
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    return *static_cast<TMC*>(TM);
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  }
Unexecuted instantiation: llvm::GCNTargetMachine& llvm::TargetPassConfig::getTM<llvm::GCNTargetMachine>() const
llvm::ARMBaseTargetMachine& llvm::TargetPassConfig::getTM<llvm::ARMBaseTargetMachine>() const
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4.88k
  template<typename TMC> TMC &getTM() const {
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    return *static_cast<TMC*>(TM);
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  }
llvm::BPFTargetMachine& llvm::TargetPassConfig::getTM<llvm::BPFTargetMachine>() const
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  template<typename TMC> TMC &getTM() const {
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    return *static_cast<TMC*>(TM);
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  }
llvm::HexagonTargetMachine& llvm::TargetPassConfig::getTM<llvm::HexagonTargetMachine>() const
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  template<typename TMC> TMC &getTM() const {
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    return *static_cast<TMC*>(TM);
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  }
llvm::LanaiTargetMachine& llvm::TargetPassConfig::getTM<llvm::LanaiTargetMachine>() const
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  template<typename TMC> TMC &getTM() const {
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    return *static_cast<TMC*>(TM);
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  }
llvm::MipsTargetMachine& llvm::TargetPassConfig::getTM<llvm::MipsTargetMachine>() const
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22.4k
  template<typename TMC> TMC &getTM() const {
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    return *static_cast<TMC*>(TM);
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  }
llvm::MSP430TargetMachine& llvm::TargetPassConfig::getTM<llvm::MSP430TargetMachine>() const
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  template<typename TMC> TMC &getTM() const {
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    return *static_cast<TMC*>(TM);
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  }
llvm::NVPTXTargetMachine& llvm::TargetPassConfig::getTM<llvm::NVPTXTargetMachine>() const
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  template<typename TMC> TMC &getTM() const {
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    return *static_cast<TMC*>(TM);
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984
  }
llvm::PPCTargetMachine& llvm::TargetPassConfig::getTM<llvm::PPCTargetMachine>() const
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21.8k
  template<typename TMC> TMC &getTM() const {
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    return *static_cast<TMC*>(TM);
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  }
llvm::SparcTargetMachine& llvm::TargetPassConfig::getTM<llvm::SparcTargetMachine>() const
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  template<typename TMC> TMC &getTM() const {
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    return *static_cast<TMC*>(TM);
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  }
llvm::SystemZTargetMachine& llvm::TargetPassConfig::getTM<llvm::SystemZTargetMachine>() const
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5.31k
  template<typename TMC> TMC &getTM() const {
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    return *static_cast<TMC*>(TM);
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  }
llvm::X86TargetMachine& llvm::TargetPassConfig::getTM<llvm::X86TargetMachine>() const
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11.3k
  template<typename TMC> TMC &getTM() const {
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    return *static_cast<TMC*>(TM);
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  }
llvm::XCoreTargetMachine& llvm::TargetPassConfig::getTM<llvm::XCoreTargetMachine>() const
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  template<typename TMC> TMC &getTM() const {
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    return *static_cast<TMC*>(TM);
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  }
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  //
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  void setInitialized() { Initialized = true; }
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  CodeGenOpt::Level getOptLevel() const;
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  /// Describe the status of the codegen
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  /// pipeline set by this target pass config.
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  /// Having a limited codegen pipeline means that options
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  /// have been used to restrict what codegen is doing.
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  /// In particular, that means that codegen won't emit
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  /// assembly code.
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  bool hasLimitedCodeGenPipeline() const;
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  /// If hasLimitedCodeGenPipeline is true, this method
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  /// returns a string with the name of the options, separated
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  /// by \p Separator that caused this pipeline to be limited.
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  std::string
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  getLimitedCodeGenPipelineReason(const char *Separator = "/") const;
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  /// Check if the codegen pipeline is limited in such a way that it
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  /// won't be complete. When the codegen pipeline is not complete,
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  /// this means it may not be possible to generate assembly from it.
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32.9k
  bool willCompleteCodeGenPipeline() const {
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    return !hasLimitedCodeGenPipeline() || 
(247
!StopAfter247
&&
!StopBefore82
);
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  }
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33.9k
  void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
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  bool getEnableTailMerge() const { return EnableTailMerge; }
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  void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
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32.9k
  bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; }
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  void setRequiresCodeGenSCCOrder(bool Enable = true) {
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    setOpt(RequireCodeGenSCCOrder, Enable);
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  }
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  /// Allow the target to override a specific pass without overriding the pass
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  /// pipeline. When passes are added to the standard pipeline at the
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  /// point where StandardID is expected, add TargetID in its place.
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  void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
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  /// Insert InsertedPassID pass after TargetPassID pass.
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  void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
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                  bool VerifyAfter = true, bool PrintAfter = true);
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  /// Allow the target to enable a specific standard pass by default.
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0
  void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
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  /// Allow the target to disable a specific standard pass by default.
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14.2k
  void disablePass(AnalysisID PassID) {
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    substitutePass(PassID, IdentifyingPassPtr());
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14.2k
  }
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  /// Return the pass substituted for StandardID by the target.
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  /// If no substitution exists, return StandardID.
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  IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const;
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  /// Return true if the pass has been substituted by the target or
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  /// overridden on the command line.
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  bool isPassSubstitutedOrOverridden(AnalysisID ID) const;
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  /// Return true if the optimized regalloc pipeline is enabled.
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  bool getOptimizeRegAlloc() const;
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  /// Return true if the default global register allocator is in use and
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  /// has not be overriden on the command line with '-regalloc=...'
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  bool usingDefaultRegAlloc() const;
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  /// High level function that adds all passes necessary to go from llvm IR
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  /// representation to the MI representation.
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  /// Adds IR based lowering and target specific optimization passes and finally
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  /// the core instruction selection passes.
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  /// \returns true if an error occurred, false otherwise.
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  bool addISelPasses();
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  /// Add common target configurable passes that perform LLVM IR to IR
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  /// transforms following machine independent optimization.
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  virtual void addIRPasses();
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  /// Add passes to lower exception handling for the code generator.
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  void addPassesToHandleExceptions();
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  /// Add pass to prepare the LLVM IR for code generation. This should be done
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  /// before exception handling preparation passes.
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  virtual void addCodeGenPrepare();
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  /// Add common passes that perform LLVM IR to IR transforms in preparation for
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  /// instruction selection.
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  virtual void addISelPrepare();
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  /// addInstSelector - This method should install an instruction selector pass,
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  /// which converts from LLVM code to machine instructions.
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0
  virtual bool addInstSelector() {
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0
    return true;
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0
  }
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  /// This method should install an IR translator pass, which converts from
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  /// LLVM code to machine instructions with possibly generic opcodes.
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0
  virtual bool addIRTranslator() { return true; }
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  /// This method may be implemented by targets that want to run passes
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  /// immediately before legalization.
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6.82k
  virtual void addPreLegalizeMachineIR() {}
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  /// This method should install a legalize pass, which converts the instruction
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  /// sequence into one that can be selected by the target.
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0
  virtual bool addLegalizeMachineIR() { return true; }
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  /// This method may be implemented by targets that want to run passes
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  /// immediately before the register bank selection.
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6.82k
  virtual void addPreRegBankSelect() {}
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  /// This method should install a register bank selector pass, which
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  /// assigns register banks to virtual registers without a register
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  /// class or register banks.
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0
  virtual bool addRegBankSelect() { return true; }
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  /// This method may be implemented by targets that want to run passes
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  /// immediately before the (global) instruction selection.
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125
  virtual void addPreGlobalInstructionSelect() {}
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  /// This method should install a (global) instruction selector pass, which
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  /// converts possibly generic instructions to fully target-specific
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  /// instructions, thereby constraining all generic virtual registers to
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  /// register classes.
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0
  virtual bool addGlobalInstructionSelect() { return true; }
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  /// Add the complete, standard set of LLVM CodeGen passes.
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  /// Fully developed targets will not generally override this.
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  virtual void addMachinePasses();
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  /// Create an instance of ScheduleDAGInstrs to be run within the standard
275
  /// MachineScheduler pass for this function and target at the current
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  /// optimization level.
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  ///
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  /// This can also be used to plug a new MachineSchedStrategy into an instance
279
  /// of the standard ScheduleDAGMI:
280
  ///   return new ScheduleDAGMI(C, make_unique<MyStrategy>(C), /*RemoveKillFlags=*/false)
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  ///
282
  /// Return NULL to select the default (generic) machine scheduler.
283
  virtual ScheduleDAGInstrs *
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16.4k
  createMachineScheduler(MachineSchedContext *C) const {
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16.4k
    return nullptr;
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16.4k
  }
287
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  /// Similar to createMachineScheduler but used when postRA machine scheduling
289
  /// is enabled.
290
  virtual ScheduleDAGInstrs *
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8.72k
  createPostMachineScheduler(MachineSchedContext *C) const {
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8.72k
    return nullptr;
293
8.72k
  }
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295
  /// printAndVerify - Add a pass to dump then verify the machine function, if
296
  /// those steps are enabled.
297
  void printAndVerify(const std::string &Banner);
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299
  /// Add a pass to print the machine function if printing is enabled.
300
  void addPrintPass(const std::string &Banner);
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302
  /// Add a pass to perform basic verification of the machine function if
303
  /// verification is enabled.
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  void addVerifyPass(const std::string &Banner);
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  /// Check whether or not GlobalISel should abort on error.
307
  /// When this is disabled, GlobalISel will fall back on SDISel instead of
308
  /// erroring out.
309
  bool isGlobalISelAbortEnabled() const;
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311
  /// Check whether or not a diagnostic should be emitted when GlobalISel
312
  /// uses the fallback path. In other words, it will emit a diagnostic
313
  /// when GlobalISel failed and isGlobalISelAbortEnabled is false.
314
  virtual bool reportDiagnosticWhenGlobalISelFallback() const;
315
316
protected:
317
  // Helper to verify the analysis is really immutable.
318
  void setOpt(bool &Opt, bool Val);
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320
  /// Methods with trivial inline returns are convenient points in the common
321
  /// codegen pass pipeline where targets may insert passes. Methods with
322
  /// out-of-line standard implementations are major CodeGen stages called by
323
  /// addMachinePasses. Some targets may override major stages when inserting
324
  /// passes is insufficient, but maintaining overriden stages is more work.
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  ///
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327
  /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
328
  /// passes (which are run just before instruction selector).
329
4.33k
  virtual bool addPreISel() {
330
4.33k
    return true;
331
4.33k
  }
332
333
  /// addMachineSSAOptimization - Add standard passes that optimize machine
334
  /// instructions in SSA form.
335
  virtual void addMachineSSAOptimization();
336
337
  /// Add passes that optimize instruction level parallelism for out-of-order
338
  /// targets. These passes are run while the machine code is still in SSA
339
  /// form, so they can use MachineTraceMetrics to control their heuristics.
340
  ///
341
  /// All passes added here should preserve the MachineDominatorTree,
342
  /// MachineLoopInfo, and MachineTraceMetrics analyses.
343
10.0k
  virtual bool addILPOpts() {
344
10.0k
    return false;
345
10.0k
  }
346
347
  /// This method may be implemented by targets that want to run passes
348
  /// immediately before register allocation.
349
1.54k
  virtual void addPreRegAlloc() { }
350
351
  /// createTargetRegisterAllocator - Create the register allocator pass for
352
  /// this target at the current optimization level.
353
  virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
354
355
  /// addFastRegAlloc - Add the minimum set of target-independent passes that
356
  /// are required for fast register allocation.
357
  virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
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359
  /// addOptimizedRegAlloc - Add passes related to register allocation.
360
  /// LLVMTargetMachine provides standard regalloc passes for most targets.
361
  virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
362
363
  /// addPreRewrite - Add passes to the optimized register allocation pipeline
364
  /// after register allocation is complete, but before virtual registers are
365
  /// rewritten to physical registers.
366
  ///
367
  /// These passes must preserve VirtRegMap and LiveIntervals, and when running
368
  /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
369
  /// When these passes run, VirtRegMap contains legal physreg assignments for
370
  /// all virtual registers.
371
31.1k
  virtual bool addPreRewrite() {
372
31.1k
    return false;
373
31.1k
  }
374
375
  /// This method may be implemented by targets that want to run passes after
376
  /// register allocation pass pipeline but before prolog-epilog insertion.
377
11.9k
  virtual void addPostRegAlloc() { }
378
379
  /// Add passes that optimize machine instructions after register allocation.
380
  virtual void addMachineLateOptimization();
381
382
  /// This method may be implemented by targets that want to run passes after
383
  /// prolog-epilog insertion and before the second instruction scheduling pass.
384
2.59k
  virtual void addPreSched2() { }
385
386
  /// addGCPasses - Add late codegen passes that analyze code for garbage
387
  /// collection. This should return true if GC info should be printed after
388
  /// these passes.
389
  virtual bool addGCPasses();
390
391
  /// Add standard basic block placement passes.
392
  virtual void addBlockPlacement();
393
394
  /// This pass may be implemented by targets that want to run passes
395
  /// immediately before machine code is emitted.
396
246
  virtual void addPreEmitPass() { }
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398
  /// Targets may add passes immediately before machine code is emitted in this
399
  /// callback. This is called even later than `addPreEmitPass`.
400
  // FIXME: Rename `addPreEmitPass` to something more sensible given its actual
401
  // position and remove the `2` suffix here as this callback is what
402
  // `addPreEmitPass` *should* be but in reality isn't.
403
21.5k
  virtual void addPreEmitPass2() {}
404
405
  /// Utilities for targets to add passes to the pass manager.
406
  ///
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408
  /// Add a CodeGen pass at this point in the pipeline after checking overrides.
409
  /// Return the pass that was added, or zero if no pass was added.
410
  /// @p printAfter    if true and adding a machine function pass add an extra
411
  ///                  machine printer pass afterwards
412
  /// @p verifyAfter   if true and adding a machine function pass add an extra
413
  ///                  machine verification pass afterwards.
414
  AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true,
415
                     bool printAfter = true);
416
417
  /// Add a pass to the PassManager if that pass is supposed to be run, as
418
  /// determined by the StartAfter and StopAfter options. Takes ownership of the
419
  /// pass.
420
  /// @p printAfter    if true and adding a machine function pass add an extra
421
  ///                  machine printer pass afterwards
422
  /// @p verifyAfter   if true and adding a machine function pass add an extra
423
  ///                  machine verification pass afterwards.
424
  void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
425
426
  /// addMachinePasses helper to create the target-selected or overriden
427
  /// regalloc pass.
428
  FunctionPass *createRegAllocPass(bool Optimized);
429
};
430
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} // end namespace llvm
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#endif // LLVM_CODEGEN_TARGETPASSCONFIG_H