Coverage Report

Created: 2018-09-17 19:50

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
Line
Count
Source (jump to first uncovered line)
1
//==- CodeGen/TargetRegisterInfo.h - Target Register Information -*- C++ -*-==//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
//
10
// This file describes an abstract interface used to get information about a
11
// target machines register file.  This information is used for a variety of
12
// purposed, especially register allocation.
13
//
14
//===----------------------------------------------------------------------===//
15
16
#ifndef LLVM_CODEGEN_TARGETREGISTERINFO_H
17
#define LLVM_CODEGEN_TARGETREGISTERINFO_H
18
19
#include "llvm/ADT/ArrayRef.h"
20
#include "llvm/ADT/SmallVector.h"
21
#include "llvm/ADT/StringRef.h"
22
#include "llvm/ADT/iterator_range.h"
23
#include "llvm/CodeGen/MachineBasicBlock.h"
24
#include "llvm/IR/CallingConv.h"
25
#include "llvm/MC/LaneBitmask.h"
26
#include "llvm/MC/MCRegisterInfo.h"
27
#include "llvm/Support/ErrorHandling.h"
28
#include "llvm/Support/MachineValueType.h"
29
#include "llvm/Support/MathExtras.h"
30
#include "llvm/Support/Printable.h"
31
#include <cassert>
32
#include <cstdint>
33
#include <functional>
34
35
namespace llvm {
36
37
class BitVector;
38
class LiveRegMatrix;
39
class MachineFunction;
40
class MachineInstr;
41
class RegScavenger;
42
class VirtRegMap;
43
class LiveIntervals;
44
45
class TargetRegisterClass {
46
public:
47
  using iterator = const MCPhysReg *;
48
  using const_iterator = const MCPhysReg *;
49
  using sc_iterator = const TargetRegisterClass* const *;
50
51
  // Instance variables filled by tablegen, do not use!
52
  const MCRegisterClass *MC;
53
  const uint32_t *SubClassMask;
54
  const uint16_t *SuperRegIndices;
55
  const LaneBitmask LaneMask;
56
  /// Classes with a higher priority value are assigned first by register
57
  /// allocators using a greedy heuristic. The value is in the range [0,63].
58
  const uint8_t AllocationPriority;
59
  /// Whether the class supports two (or more) disjunct subregister indices.
60
  const bool HasDisjunctSubRegs;
61
  /// Whether a combination of subregisters can cover every register in the
62
  /// class. See also the CoveredBySubRegs description in Target.td.
63
  const bool CoveredBySubRegs;
64
  const sc_iterator SuperClasses;
65
  ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
66
67
  /// Return the register class ID number.
68
521M
  unsigned getID() const { return MC->getID(); }
69
70
  /// begin/end - Return all of the registers in this class.
71
  ///
72
16.4M
  iterator       begin() const { return MC->begin(); }
73
15.7M
  iterator         end() const { return MC->end(); }
74
75
  /// Return the number of registers in this class.
76
568M
  unsigned getNumRegs() const { return MC->getNumRegs(); }
77
78
  iterator_range<SmallVectorImpl<MCPhysReg>::const_iterator>
79
37.6k
  getRegisters() const {
80
37.6k
    return make_range(MC->begin(), MC->end());
81
37.6k
  }
82
83
  /// Return the specified register in the class.
84
17.7M
  unsigned getRegister(unsigned i) const {
85
17.7M
    return MC->getRegister(i);
86
17.7M
  }
87
88
  /// Return true if the specified register is included in this register class.
89
  /// This does not include virtual registers.
90
1.04G
  bool contains(unsigned Reg) const {
91
1.04G
    return MC->contains(Reg);
92
1.04G
  }
93
94
  /// Return true if both registers are in this class.
95
661k
  bool contains(unsigned Reg1, unsigned Reg2) const {
96
661k
    return MC->contains(Reg1, Reg2);
97
661k
  }
98
99
  /// Return the cost of copying a value between two registers in this class.
100
  /// A negative number means the register class is very expensive
101
  /// to copy e.g. status flag register classes.
102
1.32M
  int getCopyCost() const { return MC->getCopyCost(); }
103
104
  /// Return true if this register class may be used to create virtual
105
  /// registers.
106
14.5M
  bool isAllocatable() const { return MC->isAllocatable(); }
107
108
  /// Return true if the specified TargetRegisterClass
109
  /// is a proper sub-class of this TargetRegisterClass.
110
12.5M
  bool hasSubClass(const TargetRegisterClass *RC) const {
111
12.5M
    return RC != this && hasSubClassEq(RC);
112
12.5M
  }
113
114
  /// Returns true if RC is a sub-class of or equal to this class.
115
29.8M
  bool hasSubClassEq(const TargetRegisterClass *RC) const {
116
29.8M
    unsigned ID = RC->getID();
117
29.8M
    return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
118
29.8M
  }
119
120
  /// Return true if the specified TargetRegisterClass is a
121
  /// proper super-class of this TargetRegisterClass.
122
0
  bool hasSuperClass(const TargetRegisterClass *RC) const {
123
0
    return RC->hasSubClass(this);
124
0
  }
125
126
  /// Returns true if RC is a super-class of or equal to this class.
127
13.7M
  bool hasSuperClassEq(const TargetRegisterClass *RC) const {
128
13.7M
    return RC->hasSubClassEq(this);
129
13.7M
  }
130
131
  /// Returns a bit vector of subclasses, including this one.
132
  /// The vector is indexed by class IDs.
133
  ///
134
  /// To use it, consider the returned array as a chunk of memory that
135
  /// contains an array of bits of size NumRegClasses. Each 32-bit chunk
136
  /// contains a bitset of the ID of the subclasses in big-endian style.
137
138
  /// I.e., the representation of the memory from left to right at the
139
  /// bit level looks like:
140
  /// [31 30 ... 1 0] [ 63 62 ... 33 32] ...
141
  ///                     [ XXX NumRegClasses NumRegClasses - 1 ... ]
142
  /// Where the number represents the class ID and XXX bits that
143
  /// should be ignored.
144
  ///
145
  /// See the implementation of hasSubClassEq for an example of how it
146
  /// can be used.
147
42.5M
  const uint32_t *getSubClassMask() const {
148
42.5M
    return SubClassMask;
149
42.5M
  }
150
151
  /// Returns a 0-terminated list of sub-register indices that project some
152
  /// super-register class into this register class. The list has an entry for
153
  /// each Idx such that:
154
  ///
155
  ///   There exists SuperRC where:
156
  ///     For all Reg in SuperRC:
157
  ///       this->contains(Reg:Idx)
158
3.38M
  const uint16_t *getSuperRegIndices() const {
159
3.38M
    return SuperRegIndices;
160
3.38M
  }
161
162
  /// Returns a NULL-terminated list of super-classes.  The
163
  /// classes are ordered by ID which is also a topological ordering from large
164
  /// to small classes.  The list does NOT include the current class.
165
580k
  sc_iterator getSuperClasses() const {
166
580k
    return SuperClasses;
167
580k
  }
168
169
  /// Return true if this TargetRegisterClass is a subset
170
  /// class of at least one other TargetRegisterClass.
171
0
  bool isASubClass() const {
172
0
    return SuperClasses[0] != nullptr;
173
0
  }
174
175
  /// Returns the preferred order for allocating registers from this register
176
  /// class in MF. The raw order comes directly from the .td file and may
177
  /// include reserved registers that are not allocatable.
178
  /// Register allocators should also make sure to allocate
179
  /// callee-saved registers only after all the volatiles are used. The
180
  /// RegisterClassInfo class provides filtered allocation orders with
181
  /// callee-saved registers moved to the end.
182
  ///
183
  /// The MachineFunction argument can be used to tune the allocatable
184
  /// registers based on the characteristics of the function, subtarget, or
185
  /// other criteria.
186
  ///
187
  /// By default, this method returns all registers in the class.
188
870k
  ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
189
870k
    return OrderFunc ? 
OrderFunc(MF)157k
:
makeArrayRef(begin(), getNumRegs())712k
;
190
870k
  }
191
192
  /// Returns the combination of all lane masks of register in this class.
193
  /// The lane masks of the registers are the combination of all lane masks
194
  /// of their subregisters. Returns 1 if there are no subregisters.
195
12.5M
  LaneBitmask getLaneMask() const {
196
12.5M
    return LaneMask;
197
12.5M
  }
198
};
199
200
/// Extra information, not in MCRegisterDesc, about registers.
201
/// These are used by codegen, not by MC.
202
struct TargetRegisterInfoDesc {
203
  unsigned CostPerUse;          // Extra cost of instructions using register.
204
  bool inAllocatableClass;      // Register belongs to an allocatable regclass.
205
};
206
207
/// Each TargetRegisterClass has a per register weight, and weight
208
/// limit which must be less than the limits of its pressure sets.
209
struct RegClassWeight {
210
  unsigned RegWeight;
211
  unsigned WeightLimit;
212
};
213
214
/// TargetRegisterInfo base class - We assume that the target defines a static
215
/// array of TargetRegisterDesc objects that represent all of the machine
216
/// registers that the target has.  As such, we simply have to track a pointer
217
/// to this array so that we can turn register number into a register
218
/// descriptor.
219
///
220
class TargetRegisterInfo : public MCRegisterInfo {
221
public:
222
  using regclass_iterator = const TargetRegisterClass * const *;
223
  using vt_iterator = const MVT::SimpleValueType *;
224
  struct RegClassInfo {
225
    unsigned RegSize, SpillSize, SpillAlignment;
226
    vt_iterator VTList;
227
  };
228
private:
229
  const TargetRegisterInfoDesc *InfoDesc;     // Extra desc array for codegen
230
  const char *const *SubRegIndexNames;        // Names of subreg indexes.
231
  // Pointer to array of lane masks, one per sub-reg index.
232
  const LaneBitmask *SubRegIndexLaneMasks;
233
234
  regclass_iterator RegClassBegin, RegClassEnd;   // List of regclasses
235
  LaneBitmask CoveringLanes;
236
  const RegClassInfo *const RCInfos;
237
  unsigned HwMode;
238
239
protected:
240
  TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
241
                     regclass_iterator RCB,
242
                     regclass_iterator RCE,
243
                     const char *const *SRINames,
244
                     const LaneBitmask *SRILaneMasks,
245
                     LaneBitmask CoveringLanes,
246
                     const RegClassInfo *const RCIs,
247
                     unsigned Mode = 0);
248
  virtual ~TargetRegisterInfo();
249
250
public:
251
  // Register numbers can represent physical registers, virtual registers, and
252
  // sometimes stack slots. The unsigned values are divided into these ranges:
253
  //
254
  //   0           Not a register, can be used as a sentinel.
255
  //   [1;2^30)    Physical registers assigned by TableGen.
256
  //   [2^30;2^31) Stack slots. (Rarely used.)
257
  //   [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
258
  //
259
  // Further sentinels can be allocated from the small negative integers.
260
  // DenseMapInfo<unsigned> uses -1u and -2u.
261
262
  /// isStackSlot - Sometimes it is useful the be able to store a non-negative
263
  /// frame index in a variable that normally holds a register. isStackSlot()
264
  /// returns true if Reg is in the range used for stack slots.
265
  ///
266
  /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
267
  /// slots, so if a variable may contains a stack slot, always check
268
  /// isStackSlot() first.
269
  ///
270
4.09M
  static bool isStackSlot(unsigned Reg) {
271
4.09M
    return int(Reg) >= (1 << 30);
272
4.09M
  }
273
274
  /// Compute the frame index from a register value representing a stack slot.
275
735k
  static int stackSlot2Index(unsigned Reg) {
276
735k
    assert(isStackSlot(Reg) && "Not a stack slot");
277
735k
    return int(Reg - (1u << 30));
278
735k
  }
279
280
  /// Convert a non-negative frame index to a stack slot register value.
281
353k
  static unsigned index2StackSlot(int FI) {
282
353k
    assert(FI >= 0 && "Cannot hold a negative frame index.");
283
353k
    return FI + (1u << 30);
284
353k
  }
285
286
  /// Return true if the specified register number is in
287
  /// the physical register namespace.
288
1.06G
  static bool isPhysicalRegister(unsigned Reg) {
289
1.06G
    assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
290
1.06G
    return int(Reg) > 0;
291
1.06G
  }
292
293
  /// Return true if the specified register number is in
294
  /// the virtual register namespace.
295
1.88G
  static bool isVirtualRegister(unsigned Reg) {
296
1.88G
    assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
297
1.88G
    return int(Reg) < 0;
298
1.88G
  }
299
300
  /// Convert a virtual register number to a 0-based index.
301
  /// The first virtual register in a function will get the index 0.
302
2.20G
  static unsigned virtReg2Index(unsigned Reg) {
303
2.20G
    assert(isVirtualRegister(Reg) && "Not a virtual register");
304
2.20G
    return Reg & ~(1u << 31);
305
2.20G
  }
306
307
  /// Convert a 0-based index to a virtual register number.
308
  /// This is the inverse operation of VirtReg2IndexFunctor below.
309
241M
  static unsigned index2VirtReg(unsigned Index) {
310
241M
    return Index | (1u << 31);
311
241M
  }
312
313
  /// Return the size in bits of a register from class RC.
314
28.1M
  unsigned getRegSizeInBits(const TargetRegisterClass &RC) const {
315
28.1M
    return getRegClassInfo(RC).RegSize;
316
28.1M
  }
317
318
  /// Return the size in bytes of the stack slot allocated to hold a spilled
319
  /// copy of a register from class RC.
320
25.1M
  unsigned getSpillSize(const TargetRegisterClass &RC) const {
321
25.1M
    return getRegClassInfo(RC).SpillSize / 8;
322
25.1M
  }
323
324
  /// Return the minimum required alignment in bytes for a spill slot for
325
  /// a register of this class.
326
1.43M
  unsigned getSpillAlignment(const TargetRegisterClass &RC) const {
327
1.43M
    return getRegClassInfo(RC).SpillAlignment / 8;
328
1.43M
  }
329
330
  /// Return true if the given TargetRegisterClass has the ValueType T.
331
199M
  bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const {
332
492M
    for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; 
++I293M
)
333
318M
      if (MVT(*I) == T)
334
25.2M
        return true;
335
199M
    
return false174M
;
336
199M
  }
337
338
  /// Loop over all of the value types that can be represented by values
339
  /// in the given register class.
340
226M
  vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const {
341
226M
    return getRegClassInfo(RC).VTList;
342
226M
  }
343
344
0
  vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const {
345
0
    vt_iterator I = legalclasstypes_begin(RC);
346
0
    while (*I != MVT::Other)
347
0
      ++I;
348
0
    return I;
349
0
  }
350
351
  /// Returns the Register Class of a physical register of the given type,
352
  /// picking the most sub register class of the right type that contains this
353
  /// physreg.
354
  const TargetRegisterClass *
355
    getMinimalPhysRegClass(unsigned Reg, MVT VT = MVT::Other) const;
356
357
  /// Return the maximal subclass of the given register class that is
358
  /// allocatable or NULL.
359
  const TargetRegisterClass *
360
    getAllocatableClass(const TargetRegisterClass *RC) const;
361
362
  /// Returns a bitset indexed by register number indicating if a register is
363
  /// allocatable or not. If a register class is specified, returns the subset
364
  /// for the class.
365
  BitVector getAllocatableSet(const MachineFunction &MF,
366
                              const TargetRegisterClass *RC = nullptr) const;
367
368
  /// Return the additional cost of using this register instead
369
  /// of other registers in its class.
370
48.5M
  unsigned getCostPerUse(unsigned RegNo) const {
371
48.5M
    return InfoDesc[RegNo].CostPerUse;
372
48.5M
  }
373
374
  /// Return true if the register is in the allocation of any register class.
375
38.1M
  bool isInAllocatableClass(unsigned RegNo) const {
376
38.1M
    return InfoDesc[RegNo].inAllocatableClass;
377
38.1M
  }
378
379
  /// Return the human-readable symbolic target-specific
380
  /// name for the specified SubRegIndex.
381
9.98k
  const char *getSubRegIndexName(unsigned SubIdx) const {
382
9.98k
    assert(SubIdx && SubIdx < getNumSubRegIndices() &&
383
9.98k
           "This is not a subregister index");
384
9.98k
    return SubRegIndexNames[SubIdx-1];
385
9.98k
  }
386
387
  /// Return a bitmask representing the parts of a register that are covered by
388
  /// SubIdx \see LaneBitmask.
389
  ///
390
  /// SubIdx == 0 is allowed, it has the lane mask ~0u.
391
32.4M
  LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const {
392
32.4M
    assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
393
32.4M
    return SubRegIndexLaneMasks[SubIdx];
394
32.4M
  }
395
396
  /// The lane masks returned by getSubRegIndexLaneMask() above can only be
397
  /// used to determine if sub-registers overlap - they can't be used to
398
  /// determine if a set of sub-registers completely cover another
399
  /// sub-register.
400
  ///
401
  /// The X86 general purpose registers have two lanes corresponding to the
402
  /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
403
  /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
404
  /// sub_32bit sub-register.
405
  ///
406
  /// On the other hand, the ARM NEON lanes fully cover their registers: The
407
  /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
408
  /// This is related to the CoveredBySubRegs property on register definitions.
409
  ///
410
  /// This function returns a bit mask of lanes that completely cover their
411
  /// sub-registers. More precisely, given:
412
  ///
413
  ///   Covering = getCoveringLanes();
414
  ///   MaskA = getSubRegIndexLaneMask(SubA);
415
  ///   MaskB = getSubRegIndexLaneMask(SubB);
416
  ///
417
  /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
418
  /// SubB.
419
0
  LaneBitmask getCoveringLanes() const { return CoveringLanes; }
420
421
  /// Returns true if the two registers are equal or alias each other.
422
  /// The registers may be virtual registers.
423
16.5M
  bool regsOverlap(unsigned regA, unsigned regB) const {
424
16.5M
    if (regA == regB) 
return true776k
;
425
15.7M
    if (isVirtualRegister(regA) || 
isVirtualRegister(regB)15.5M
)
426
209k
      return false;
427
15.5M
428
15.5M
    // Regunits are numerically ordered. Find a common unit.
429
15.5M
    MCRegUnitIterator RUA(regA, this);
430
15.5M
    MCRegUnitIterator RUB(regB, this);
431
19.4M
    do {
432
19.4M
      if (*RUA == *RUB) 
return true54.7k
;
433
19.4M
      if (*RUA < *RUB) 
++RUA8.35M
;
434
11.0M
      else             ++RUB;
435
19.4M
    } while (RUA.isValid() && 
RUB.isValid()12.9M
);
436
15.5M
    
return false15.4M
;
437
15.5M
  }
438
439
  /// Returns true if Reg contains RegUnit.
440
2.29M
  bool hasRegUnit(unsigned Reg, unsigned RegUnit) const {
441
4.44M
    for (MCRegUnitIterator Units(Reg, this); Units.isValid(); 
++Units2.15M
)
442
2.38M
      if (*Units == RegUnit)
443
231k
        return true;
444
2.29M
    
return false2.06M
;
445
2.29M
  }
446
447
  /// Returns the original SrcReg unless it is the target of a copy-like
448
  /// operation, in which case we chain backwards through all such operations
449
  /// to the ultimate source register.  If a physical register is encountered,
450
  /// we stop the search.
451
  virtual unsigned lookThruCopyLike(unsigned SrcReg,
452
                                    const MachineRegisterInfo *MRI) const;
453
454
  /// Return a null-terminated list of all of the callee-saved registers on
455
  /// this target. The register should be in the order of desired callee-save
456
  /// stack frame offset. The first register is closest to the incoming stack
457
  /// pointer if stack grows down, and vice versa.
458
  /// Notice: This function does not take into account disabled CSRs.
459
  ///         In most cases you will want to use instead the function
460
  ///         getCalleeSavedRegs that is implemented in MachineRegisterInfo.
461
  virtual const MCPhysReg*
462
  getCalleeSavedRegs(const MachineFunction *MF) const = 0;
463
464
  /// Return a mask of call-preserved registers for the given calling convention
465
  /// on the current function. The mask should include all call-preserved
466
  /// aliases. This is used by the register allocator to determine which
467
  /// registers can be live across a call.
468
  ///
469
  /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
470
  /// A set bit indicates that all bits of the corresponding register are
471
  /// preserved across the function call.  The bit mask is expected to be
472
  /// sub-register complete, i.e. if A is preserved, so are all its
473
  /// sub-registers.
474
  ///
475
  /// Bits are numbered from the LSB, so the bit for physical register Reg can
476
  /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
477
  ///
478
  /// A NULL pointer means that no register mask will be used, and call
479
  /// instructions should use implicit-def operands to indicate call clobbered
480
  /// registers.
481
  ///
482
  virtual const uint32_t *getCallPreservedMask(const MachineFunction &MF,
483
0
                                               CallingConv::ID) const {
484
0
    // The default mask clobbers everything.  All targets should override.
485
0
    return nullptr;
486
0
  }
487
488
  /// Return a register mask that clobbers everything.
489
0
  virtual const uint32_t *getNoPreservedMask() const {
490
0
    llvm_unreachable("target does not provide no preserved mask");
491
0
  }
492
493
  /// Return true if all bits that are set in mask \p mask0 are also set in
494
  /// \p mask1.
495
  bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
496
497
  /// Return all the call-preserved register masks defined for this target.
498
  virtual ArrayRef<const uint32_t *> getRegMasks() const = 0;
499
  virtual ArrayRef<const char *> getRegMaskNames() const = 0;
500
501
  /// Returns a bitset indexed by physical register number indicating if a
502
  /// register is a special register that has particular uses and should be
503
  /// considered unavailable at all times, e.g. stack pointer, return address.
504
  /// A reserved register:
505
  /// - is not allocatable
506
  /// - is considered always live
507
  /// - is ignored by liveness tracking
508
  /// It is often necessary to reserve the super registers of a reserved
509
  /// register as well, to avoid them getting allocated indirectly. You may use
510
  /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
511
  virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
512
513
  /// Returns false if we can't guarantee that Physreg, specified as an IR asm
514
  /// clobber constraint, will be preserved across the statement.
515
  virtual bool isAsmClobberable(const MachineFunction &MF,
516
40.6k
                               unsigned PhysReg) const {
517
40.6k
    return true;
518
40.6k
  }
519
520
  /// Returns true if PhysReg is unallocatable and constant throughout the
521
  /// function.  Used by MachineRegisterInfo::isConstantPhysReg().
522
6.48M
  virtual bool isConstantPhysReg(unsigned PhysReg) const { return false; }
523
524
  /// Physical registers that may be modified within a function but are
525
  /// guaranteed to be restored before any uses. This is useful for targets that
526
  /// have call sequences where a GOT register may be updated by the caller
527
  /// prior to a call and is guaranteed to be restored (also by the caller)
528
  /// after the call.
529
  virtual bool isCallerPreservedPhysReg(unsigned PhysReg,
530
1.09M
                                        const MachineFunction &MF) const {
531
1.09M
    return false;
532
1.09M
  }
533
534
  /// Prior to adding the live-out mask to a stackmap or patchpoint
535
  /// instruction, provide the target the opportunity to adjust it (mainly to
536
  /// remove pseudo-registers that should be ignored).
537
74
  virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const {}
538
539
  /// Return a super-register of the specified register
540
  /// Reg so its sub-register of index SubIdx is Reg.
541
  unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
542
664k
                               const TargetRegisterClass *RC) const {
543
664k
    return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
544
664k
  }
545
546
  /// Return a subclass of the specified register
547
  /// class A so that each register in it has a sub-register of the
548
  /// specified sub-register index which is in the specified register class B.
549
  ///
550
  /// TableGen will synthesize missing A sub-classes.
551
  virtual const TargetRegisterClass *
552
  getMatchingSuperRegClass(const TargetRegisterClass *A,
553
                           const TargetRegisterClass *B, unsigned Idx) const;
554
555
  // For a copy-like instruction that defines a register of class DefRC with
556
  // subreg index DefSubReg, reading from another source with class SrcRC and
557
  // subregister SrcSubReg return true if this is a preferable copy
558
  // instruction or an earlier use should be used.
559
  virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
560
                                    unsigned DefSubReg,
561
                                    const TargetRegisterClass *SrcRC,
562
                                    unsigned SrcSubReg) const;
563
564
  /// Returns the largest legal sub-class of RC that
565
  /// supports the sub-register index Idx.
566
  /// If no such sub-class exists, return NULL.
567
  /// If all registers in RC already have an Idx sub-register, return RC.
568
  ///
569
  /// TableGen generates a version of this function that is good enough in most
570
  /// cases.  Targets can override if they have constraints that TableGen
571
  /// doesn't understand.  For example, the x86 sub_8bit sub-register index is
572
  /// supported by the full GR32 register class in 64-bit mode, but only by the
573
  /// GR32_ABCD regiister class in 32-bit mode.
574
  ///
575
  /// TableGen will synthesize missing RC sub-classes.
576
  virtual const TargetRegisterClass *
577
0
  getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
578
0
    assert(Idx == 0 && "Target has no sub-registers");
579
0
    return RC;
580
0
  }
581
582
  /// Return the subregister index you get from composing
583
  /// two subregister indices.
584
  ///
585
  /// The special null sub-register index composes as the identity.
586
  ///
587
  /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
588
  /// returns c. Note that composeSubRegIndices does not tell you about illegal
589
  /// compositions. If R does not have a subreg a, or R:a does not have a subreg
590
  /// b, composeSubRegIndices doesn't tell you.
591
  ///
592
  /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
593
  /// ssub_0:S0 - ssub_3:S3 subregs.
594
  /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
595
28.8M
  unsigned composeSubRegIndices(unsigned a, unsigned b) const {
596
28.8M
    if (!a) 
return b26.4M
;
597
2.42M
    if (!b) 
return a1.90M
;
598
520k
    return composeSubRegIndicesImpl(a, b);
599
520k
  }
600
601
  /// Transforms a LaneMask computed for one subregister to the lanemask that
602
  /// would have been computed when composing the subsubregisters with IdxA
603
  /// first. @sa composeSubRegIndices()
604
  LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA,
605
328k
                                         LaneBitmask Mask) const {
606
328k
    if (!IdxA)
607
13.8k
      return Mask;
608
314k
    return composeSubRegIndexLaneMaskImpl(IdxA, Mask);
609
314k
  }
610
611
  /// Transform a lanemask given for a virtual register to the corresponding
612
  /// lanemask before using subregister with index \p IdxA.
613
  /// This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a
614
  /// valie lane mask (no invalid bits set) the following holds:
615
  /// X0 = composeSubRegIndexLaneMask(Idx, Mask)
616
  /// X1 = reverseComposeSubRegIndexLaneMask(Idx, X0)
617
  /// => X1 == Mask
618
  LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA,
619
615k
                                                LaneBitmask LaneMask) const {
620
615k
    if (!IdxA)
621
205k
      return LaneMask;
622
409k
    return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask);
623
409k
  }
624
625
  /// Debugging helper: dump register in human readable form to dbgs() stream.
626
  static void dumpReg(unsigned Reg, unsigned SubRegIndex = 0,
627
                      const TargetRegisterInfo* TRI = nullptr);
628
629
protected:
630
  /// Overridden by TableGen in targets that have sub-registers.
631
0
  virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
632
0
    llvm_unreachable("Target has no sub-registers");
633
0
  }
634
635
  /// Overridden by TableGen in targets that have sub-registers.
636
  virtual LaneBitmask
637
0
  composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const {
638
0
    llvm_unreachable("Target has no sub-registers");
639
0
  }
640
641
  virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned,
642
0
                                                            LaneBitmask) const {
643
0
    llvm_unreachable("Target has no sub-registers");
644
0
  }
645
646
public:
647
  /// Find a common super-register class if it exists.
648
  ///
649
  /// Find a register class, SuperRC and two sub-register indices, PreA and
650
  /// PreB, such that:
651
  ///
652
  ///   1. PreA + SubA == PreB + SubB  (using composeSubRegIndices()), and
653
  ///
654
  ///   2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
655
  ///
656
  ///   3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
657
  ///
658
  /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
659
  /// requirements, and there is no register class with a smaller spill size
660
  /// that satisfies the requirements.
661
  ///
662
  /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
663
  ///
664
  /// Either of the PreA and PreB sub-register indices may be returned as 0. In
665
  /// that case, the returned register class will be a sub-class of the
666
  /// corresponding argument register class.
667
  ///
668
  /// The function returns NULL if no register class can be found.
669
  const TargetRegisterClass*
670
  getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
671
                         const TargetRegisterClass *RCB, unsigned SubB,
672
                         unsigned &PreA, unsigned &PreB) const;
673
674
  //===--------------------------------------------------------------------===//
675
  // Register Class Information
676
  //
677
protected:
678
281M
  const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const {
679
281M
    return RCInfos[getNumRegClasses() * HwMode + RC.getID()];
680
281M
  }
681
682
public:
683
  /// Register class iterators
684
313M
  regclass_iterator regclass_begin() const { return RegClassBegin; }
685
313M
  regclass_iterator regclass_end() const { return RegClassEnd; }
686
5.85M
  iterator_range<regclass_iterator> regclasses() const {
687
5.85M
    return make_range(regclass_begin(), regclass_end());
688
5.85M
  }
689
690
307M
  unsigned getNumRegClasses() const {
691
307M
    return (unsigned)(regclass_end()-regclass_begin());
692
307M
  }
693
694
  /// Returns the register class associated with the enumeration value.
695
  /// See class MCOperandInfo.
696
101M
  const TargetRegisterClass *getRegClass(unsigned i) const {
697
101M
    assert(i < getNumRegClasses() && "Register Class ID out of range");
698
101M
    return RegClassBegin[i];
699
101M
  }
700
701
  /// Returns the name of the register class.
702
132k
  const char *getRegClassName(const TargetRegisterClass *Class) const {
703
132k
    return MCRegisterInfo::getRegClassName(Class->MC);
704
132k
  }
705
706
  /// Find the largest common subclass of A and B.
707
  /// Return NULL if there is no common subclass.
708
  /// The common subclass should contain
709
  /// simple value type SVT if it is not the Any type.
710
  const TargetRegisterClass *
711
  getCommonSubClass(const TargetRegisterClass *A,
712
                    const TargetRegisterClass *B,
713
                    const MVT::SimpleValueType SVT =
714
                    MVT::SimpleValueType::Any) const;
715
716
  /// Returns a TargetRegisterClass used for pointer values.
717
  /// If a target supports multiple different pointer register classes,
718
  /// kind specifies which one is indicated.
719
  virtual const TargetRegisterClass *
720
0
  getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
721
0
    llvm_unreachable("Target didn't implement getPointerRegClass!");
722
0
  }
723
724
  /// Returns a legal register class to copy a register in the specified class
725
  /// to or from. If it is possible to copy the register directly without using
726
  /// a cross register class copy, return the specified RC. Returns NULL if it
727
  /// is not possible to copy between two registers of the specified class.
728
  virtual const TargetRegisterClass *
729
0
  getCrossCopyRegClass(const TargetRegisterClass *RC) const {
730
0
    return RC;
731
0
  }
732
733
  /// Returns the largest super class of RC that is legal to use in the current
734
  /// sub-target and has the same spill size.
735
  /// The returned register class can be used to create virtual registers which
736
  /// means that all its registers can be copied and spilled.
737
  virtual const TargetRegisterClass *
738
  getLargestLegalSuperClass(const TargetRegisterClass *RC,
739
1.94M
                            const MachineFunction &) const {
740
1.94M
    /// The default implementation is very conservative and doesn't allow the
741
1.94M
    /// register allocator to inflate register classes.
742
1.94M
    return RC;
743
1.94M
  }
744
745
  /// Return the register pressure "high water mark" for the specific register
746
  /// class. The scheduler is in high register pressure mode (for the specific
747
  /// register class) if it goes over the limit.
748
  ///
749
  /// Note: this is the old register pressure model that relies on a manually
750
  /// specified representative register class per value type.
751
  virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
752
1.31k
                                       MachineFunction &MF) const {
753
1.31k
    return 0;
754
1.31k
  }
755
756
  /// Return a heuristic for the machine scheduler to compare the profitability
757
  /// of increasing one register pressure set versus another.  The scheduler
758
  /// will prefer increasing the register pressure of the set which returns
759
  /// the largest value for this function.
760
  virtual unsigned getRegPressureSetScore(const MachineFunction &MF,
761
3.97M
                                          unsigned PSetID) const {
762
3.97M
    return PSetID;
763
3.97M
  }
764
765
  /// Get the weight in units of pressure for this register class.
766
  virtual const RegClassWeight &getRegClassWeight(
767
    const TargetRegisterClass *RC) const = 0;
768
769
  /// Returns size in bits of a phys/virtual/generic register.
770
  unsigned getRegSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI) const;
771
772
  /// Get the weight in units of pressure for this register unit.
773
  virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
774
775
  /// Get the number of dimensions of register pressure.
776
  virtual unsigned getNumRegPressureSets() const = 0;
777
778
  /// Get the name of this register unit pressure set.
779
  virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
780
781
  /// Get the register unit pressure limit for this dimension.
782
  /// This limit must be adjusted dynamically for reserved registers.
783
  virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
784
                                          unsigned Idx) const = 0;
785
786
  /// Get the dimensions of register pressure impacted by this register class.
787
  /// Returns a -1 terminated array of pressure set IDs.
788
  virtual const int *getRegClassPressureSets(
789
    const TargetRegisterClass *RC) const = 0;
790
791
  /// Get the dimensions of register pressure impacted by this register unit.
792
  /// Returns a -1 terminated array of pressure set IDs.
793
  virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
794
795
  /// Get a list of 'hint' registers that the register allocator should try
796
  /// first when allocating a physical register for the virtual register
797
  /// VirtReg. These registers are effectively moved to the front of the
798
  /// allocation order. If true is returned, regalloc will try to only use
799
  /// hints to the greatest extent possible even if it means spilling.
800
  ///
801
  /// The Order argument is the allocation order for VirtReg's register class
802
  /// as returned from RegisterClassInfo::getOrder(). The hint registers must
803
  /// come from Order, and they must not be reserved.
804
  ///
805
  /// The default implementation of this function will only add target
806
  /// independent register allocation hints. Targets that override this
807
  /// function should typically call this default implementation as well and
808
  /// expect to see generic copy hints added.
809
  virtual bool getRegAllocationHints(unsigned VirtReg,
810
                                     ArrayRef<MCPhysReg> Order,
811
                                     SmallVectorImpl<MCPhysReg> &Hints,
812
                                     const MachineFunction &MF,
813
                                     const VirtRegMap *VRM = nullptr,
814
                                     const LiveRegMatrix *Matrix = nullptr)
815
    const;
816
817
  /// A callback to allow target a chance to update register allocation hints
818
  /// when a register is "changed" (e.g. coalesced) to another register.
819
  /// e.g. On ARM, some virtual registers should target register pairs,
820
  /// if one of pair is coalesced to another register, the allocation hint of
821
  /// the other half of the pair should be changed to point to the new register.
822
  virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg,
823
4.13M
                                  MachineFunction &MF) const {
824
4.13M
    // Do nothing.
825
4.13M
  }
826
827
  /// The creation of multiple copy hints have been implemented in
828
  /// weightCalcHelper(), but since this affects so many tests for many
829
  /// targets, this is temporarily disabled per default. THIS SHOULD BE
830
  /// "GENERAL GOODNESS" and hopefully all targets will update their tests
831
  /// and enable this soon. This hook should then be removed.
832
2.20M
  virtual bool enableMultipleCopyHints() const { return false; }
833
834
  /// Allow the target to reverse allocation order of local live ranges. This
835
  /// will generally allocate shorter local live ranges first. For targets with
836
  /// many registers, this could reduce regalloc compile time by a large
837
  /// factor. It is disabled by default for three reasons:
838
  /// (1) Top-down allocation is simpler and easier to debug for targets that
839
  /// don't benefit from reversing the order.
840
  /// (2) Bottom-up allocation could result in poor evicition decisions on some
841
  /// targets affecting the performance of compiled code.
842
  /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
843
8.33M
  virtual bool reverseLocalAssignment() const { return false; }
844
845
  /// Allow the target to override the cost of using a callee-saved register for
846
  /// the first time. Default value of 0 means we will use a callee-saved
847
  /// register if it is available.
848
182k
  virtual unsigned getCSRFirstUseCost() const { return 0; }
849
850
  /// Returns true if the target requires (and can make use of) the register
851
  /// scavenger.
852
312k
  virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
853
312k
    return false;
854
312k
  }
855
856
  /// Returns true if the target wants to use frame pointer based accesses to
857
  /// spill to the scavenger emergency spill slot.
858
36.3k
  virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
859
36.3k
    return true;
860
36.3k
  }
861
862
  /// Returns true if the target requires post PEI scavenging of registers for
863
  /// materializing frame index constants.
864
131k
  virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
865
131k
    return false;
866
131k
  }
867
868
  /// Returns true if the target requires using the RegScavenger directly for
869
  /// frame elimination despite using requiresFrameIndexScavenging.
870
  virtual bool requiresFrameIndexReplacementScavenging(
871
443k
      const MachineFunction &MF) const {
872
443k
    return false;
873
443k
  }
874
875
  /// Returns true if the target wants the LocalStackAllocation pass to be run
876
  /// and virtual base registers used for more efficient stack access.
877
157k
  virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
878
157k
    return false;
879
157k
  }
880
881
  /// Return true if target has reserved a spill slot in the stack frame of
882
  /// the given function for the specified register. e.g. On x86, if the frame
883
  /// register is required, the first fixed stack object is reserved as its
884
  /// spill slot. This tells PEI not to create a new stack frame
885
  /// object for the given register. It should be called only after
886
  /// determineCalleeSaves().
887
  virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
888
1.28M
                                    int &FrameIdx) const {
889
1.28M
    return false;
890
1.28M
  }
891
892
  /// Returns true if the live-ins should be tracked after register allocation.
893
4.32k
  virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
894
4.32k
    return false;
895
4.32k
  }
896
897
  /// True if the stack can be realigned for the target.
898
  virtual bool canRealignStack(const MachineFunction &MF) const;
899
900
  /// True if storage within the function requires the stack pointer to be
901
  /// aligned more than the normal calling convention calls for.
902
  /// This cannot be overriden by the target, but canRealignStack can be
903
  /// overridden.
904
  bool needsStackRealignment(const MachineFunction &MF) const;
905
906
  /// Get the offset from the referenced frame index in the instruction,
907
  /// if there is one.
908
  virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
909
1.93k
                                           int Idx) const {
910
1.93k
    return 0;
911
1.93k
  }
912
913
  /// Returns true if the instruction's frame index reference would be better
914
  /// served by a base register other than FP or SP.
915
  /// Used by LocalStackFrameAllocation to determine which frame index
916
  /// references it should create new base registers for.
917
0
  virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
918
0
    return false;
919
0
  }
920
921
  /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
922
  /// before insertion point I.
923
  virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
924
                                            unsigned BaseReg, int FrameIdx,
925
0
                                            int64_t Offset) const {
926
0
    llvm_unreachable("materializeFrameBaseRegister does not exist on this "
927
0
                     "target");
928
0
  }
929
930
  /// Resolve a frame index operand of an instruction
931
  /// to reference the indicated base register plus offset instead.
932
  virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
933
0
                                 int64_t Offset) const {
934
0
    llvm_unreachable("resolveFrameIndex does not exist on this target");
935
0
  }
936
937
  /// Determine whether a given base register plus offset immediate is
938
  /// encodable to resolve a frame index.
939
  virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
940
0
                                  int64_t Offset) const {
941
0
    llvm_unreachable("isFrameOffsetLegal does not exist on this target");
942
0
  }
943
944
  /// Spill the register so it can be used by the register scavenger.
945
  /// Return true if the register was spilled, false otherwise.
946
  /// If this function does not spill the register, the scavenger
947
  /// will instead spill it to the emergency spill slot.
948
  virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
949
                                     MachineBasicBlock::iterator I,
950
                                     MachineBasicBlock::iterator &UseMI,
951
                                     const TargetRegisterClass *RC,
952
28
                                     unsigned Reg) const {
953
28
    return false;
954
28
  }
955
956
  /// This method must be overriden to eliminate abstract frame indices from
957
  /// instructions which may use them. The instruction referenced by the
958
  /// iterator contains an MO_FrameIndex operand which must be eliminated by
959
  /// this method. This method may modify or replace the specified instruction,
960
  /// as long as it keeps the iterator pointing at the finished product.
961
  /// SPAdj is the SP adjustment due to call frame setup instruction.
962
  /// FIOperandNum is the FI operand number.
963
  virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
964
                                   int SPAdj, unsigned FIOperandNum,
965
                                   RegScavenger *RS = nullptr) const = 0;
966
967
  /// Return the assembly name for \p Reg.
968
104M
  virtual StringRef getRegAsmName(unsigned Reg) const {
969
104M
    // FIXME: We are assuming that the assembly name is equal to the TableGen
970
104M
    // name converted to lower case
971
104M
    //
972
104M
    // The TableGen name is the name of the definition for this register in the
973
104M
    // target's tablegen files.  For example, the TableGen name of
974
104M
    // def EAX : Register <...>; is "EAX"
975
104M
    return StringRef(getName(Reg));
976
104M
  }
977
978
  //===--------------------------------------------------------------------===//
979
  /// Subtarget Hooks
980
981
  /// SrcRC and DstRC will be morphed into NewRC if this returns true.
982
  virtual bool shouldCoalesce(MachineInstr *MI,
983
                              const TargetRegisterClass *SrcRC,
984
                              unsigned SubReg,
985
                              const TargetRegisterClass *DstRC,
986
                              unsigned DstSubReg,
987
                              const TargetRegisterClass *NewRC,
988
                              LiveIntervals &LIS) const
989
3.98M
  { return true; }
990
991
  //===--------------------------------------------------------------------===//
992
  /// Debug information queries.
993
994
  /// getFrameRegister - This method should return the register used as a base
995
  /// for values allocated in the current stack frame.
996
  virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
997
998
  /// Mark a register and all its aliases as reserved in the given set.
999
  void markSuperRegs(BitVector &RegisterSet, unsigned Reg) const;
1000
1001
  /// Returns true if for every register in the set all super registers are part
1002
  /// of the set as well.
1003
  bool checkAllSuperRegsMarked(const BitVector &RegisterSet,
1004
      ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
1005
1006
  virtual const TargetRegisterClass *
1007
  getConstrainedRegClassForOperand(const MachineOperand &MO,
1008
0
                                   const MachineRegisterInfo &MRI) const {
1009
0
    return nullptr;
1010
0
  }
1011
};
1012
1013
//===----------------------------------------------------------------------===//
1014
//                           SuperRegClassIterator
1015
//===----------------------------------------------------------------------===//
1016
//
1017
// Iterate over the possible super-registers for a given register class. The
1018
// iterator will visit a list of pairs (Idx, Mask) corresponding to the
1019
// possible classes of super-registers.
1020
//
1021
// Each bit mask will have at least one set bit, and each set bit in Mask
1022
// corresponds to a SuperRC such that:
1023
//
1024
//   For all Reg in SuperRC: Reg:Idx is in RC.
1025
//
1026
// The iterator can include (O, RC->getSubClassMask()) as the first entry which
1027
// also satisfies the above requirement, assuming Reg:0 == Reg.
1028
//
1029
class SuperRegClassIterator {
1030
  const unsigned RCMaskWords;
1031
  unsigned SubReg = 0;
1032
  const uint16_t *Idx;
1033
  const uint32_t *Mask;
1034
1035
public:
1036
  /// Create a SuperRegClassIterator that visits all the super-register classes
1037
  /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
1038
  SuperRegClassIterator(const TargetRegisterClass *RC,
1039
                        const TargetRegisterInfo *TRI,
1040
                        bool IncludeSelf = false)
1041
    : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
1042
3.38M
      Idx(RC->getSuperRegIndices()), Mask(RC->getSubClassMask()) {
1043
3.38M
    if (!IncludeSelf)
1044
3.10M
      ++*this;
1045
3.38M
  }
1046
1047
  /// Returns true if this iterator is still pointing at a valid entry.
1048
8.12M
  bool isValid() const { return Idx; }
1049
1050
  /// Returns the current sub-register index.
1051
5.80M
  unsigned getSubReg() const { return SubReg; }
1052
1053
  /// Returns the bit mask of register classes that getSubReg() projects into
1054
  /// RC.
1055
  /// See TargetRegisterClass::getSubClassMask() for how to use it.
1056
5.89M
  const uint32_t *getMask() const { return Mask; }
1057
1058
  /// Advance iterator to the next entry.
1059
7.83M
  void operator++() {
1060
7.83M
    assert(isValid() && "Cannot move iterator past end.");
1061
7.83M
    Mask += RCMaskWords;
1062
7.83M
    SubReg = *Idx++;
1063
7.83M
    if (!SubReg)
1064
417k
      Idx = nullptr;
1065
7.83M
  }
1066
};
1067
1068
//===----------------------------------------------------------------------===//
1069
//                           BitMaskClassIterator
1070
//===----------------------------------------------------------------------===//
1071
/// This class encapuslates the logic to iterate over bitmask returned by
1072
/// the various RegClass related APIs.
1073
/// E.g., this class can be used to iterate over the subclasses provided by
1074
/// TargetRegisterClass::getSubClassMask or SuperRegClassIterator::getMask.
1075
class BitMaskClassIterator {
1076
  /// Total number of register classes.
1077
  const unsigned NumRegClasses;
1078
  /// Base index of CurrentChunk.
1079
  /// In other words, the number of bit we read to get at the
1080
  /// beginning of that chunck.
1081
  unsigned Base = 0;
1082
  /// Adjust base index of CurrentChunk.
1083
  /// Base index + how many bit we read within CurrentChunk.
1084
  unsigned Idx = 0;
1085
  /// Current register class ID.
1086
  unsigned ID = 0;
1087
  /// Mask we are iterating over.
1088
  const uint32_t *Mask;
1089
  /// Current chunk of the Mask we are traversing.
1090
  uint32_t CurrentChunk;
1091
1092
  /// Move ID to the next set bit.
1093
281k
  void moveToNextID() {
1094
281k
    // If the current chunk of memory is empty, move to the next one,
1095
281k
    // while making sure we do not go pass the number of register
1096
281k
    // classes.
1097
703k
    while (!CurrentChunk) {
1098
562k
      // Move to the next chunk.
1099
562k
      Base += 32;
1100
562k
      if (Base >= NumRegClasses) {
1101
140k
        ID = NumRegClasses;
1102
140k
        return;
1103
140k
      }
1104
421k
      CurrentChunk = *++Mask;
1105
421k
      Idx = Base;
1106
421k
    }
1107
281k
    // Otherwise look for the first bit set from the right
1108
281k
    // (representation of the class ID is big endian).
1109
281k
    // See getSubClassMask for more details on the representation.
1110
281k
    unsigned Offset = countTrailingZeros(CurrentChunk);
1111
141k
    // Add the Offset to the adjusted base number of this chunk: Idx.
1112
141k
    // This is the ID of the register class.
1113
141k
    ID = Idx + Offset;
1114
141k
1115
141k
    // Consume the zeros, if any, and the bit we just read
1116
141k
    // so that we are at the right spot for the next call.
1117
141k
    // Do not do Offset + 1 because Offset may be 31 and 32
1118
141k
    // will be UB for the shift, though in that case we could
1119
141k
    // have make the chunk being equal to 0, but that would
1120
141k
    // have introduced a if statement.
1121
141k
    moveNBits(Offset);
1122
141k
    moveNBits(1);
1123
141k
  }
1124
1125
  /// Move \p NumBits Bits forward in CurrentChunk.
1126
282k
  void moveNBits(unsigned NumBits) {
1127
282k
    assert(NumBits < 32 && "Undefined behavior spotted!");
1128
282k
    // Consume the bit we read for the next call.
1129
282k
    CurrentChunk >>= NumBits;
1130
282k
    // Adjust the base for the chunk.
1131
282k
    Idx += NumBits;
1132
282k
  }
1133
1134
public:
1135
  /// Create a BitMaskClassIterator that visits all the register classes
1136
  /// represented by \p Mask.
1137
  ///
1138
  /// \pre \p Mask != nullptr
1139
  BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
1140
140k
      : NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) {
1141
140k
    // Move to the first ID.
1142
140k
    moveToNextID();
1143
140k
  }
1144
1145
  /// Returns true if this iterator is still pointing at a valid entry.
1146
281k
  bool isValid() const { return getID() != NumRegClasses; }
1147
1148
  /// Returns the current register class ID.
1149
423k
  unsigned getID() const { return ID; }
1150
1151
  /// Advance iterator to the next entry.
1152
140k
  void operator++() {
1153
140k
    assert(isValid() && "Cannot move iterator past end.");
1154
140k
    moveToNextID();
1155
140k
  }
1156
};
1157
1158
// This is useful when building IndexedMaps keyed on virtual registers
1159
struct VirtReg2IndexFunctor {
1160
  using argument_type = unsigned;
1161
2.12G
  unsigned operator()(unsigned Reg) const {
1162
2.12G
    return TargetRegisterInfo::virtReg2Index(Reg);
1163
2.12G
  }
1164
};
1165
1166
/// Prints virtual and physical registers with or without a TRI instance.
1167
///
1168
/// The format is:
1169
///   %noreg          - NoRegister
1170
///   %5              - a virtual register.
1171
///   %5:sub_8bit     - a virtual register with sub-register index (with TRI).
1172
///   %eax            - a physical register
1173
///   %physreg17      - a physical register when no TRI instance given.
1174
///
1175
/// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
1176
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr,
1177
                   unsigned SubIdx = 0,
1178
                   const MachineRegisterInfo *MRI = nullptr);
1179
1180
/// Create Printable object to print register units on a \ref raw_ostream.
1181
///
1182
/// Register units are named after their root registers:
1183
///
1184
///   al      - Single root.
1185
///   fp0~st7 - Dual roots.
1186
///
1187
/// Usage: OS << printRegUnit(Unit, TRI) << '\n';
1188
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
1189
1190
/// Create Printable object to print virtual registers and physical
1191
/// registers on a \ref raw_ostream.
1192
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
1193
1194
/// Create Printable object to print register classes or register banks
1195
/// on a \ref raw_ostream.
1196
Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo,
1197
                              const TargetRegisterInfo *TRI);
1198
1199
} // end namespace llvm
1200
1201
#endif // LLVM_CODEGEN_TARGETREGISTERINFO_H