Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
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//==- CodeGen/TargetRegisterInfo.h - Target Register Information -*- C++ -*-==//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file describes an abstract interface used to get information about a
10
// target machines register file.  This information is used for a variety of
11
// purposed, especially register allocation.
12
//
13
//===----------------------------------------------------------------------===//
14
15
#ifndef LLVM_CODEGEN_TARGETREGISTERINFO_H
16
#define LLVM_CODEGEN_TARGETREGISTERINFO_H
17
18
#include "llvm/ADT/ArrayRef.h"
19
#include "llvm/ADT/SmallVector.h"
20
#include "llvm/ADT/StringRef.h"
21
#include "llvm/ADT/iterator_range.h"
22
#include "llvm/CodeGen/MachineBasicBlock.h"
23
#include "llvm/IR/CallingConv.h"
24
#include "llvm/MC/LaneBitmask.h"
25
#include "llvm/MC/MCRegisterInfo.h"
26
#include "llvm/Support/ErrorHandling.h"
27
#include "llvm/Support/MachineValueType.h"
28
#include "llvm/Support/MathExtras.h"
29
#include "llvm/Support/Printable.h"
30
#include <cassert>
31
#include <cstdint>
32
#include <functional>
33
34
namespace llvm {
35
36
class BitVector;
37
class LiveRegMatrix;
38
class MachineFunction;
39
class MachineInstr;
40
class RegScavenger;
41
class VirtRegMap;
42
class LiveIntervals;
43
44
class TargetRegisterClass {
45
public:
46
  using iterator = const MCPhysReg *;
47
  using const_iterator = const MCPhysReg *;
48
  using sc_iterator = const TargetRegisterClass* const *;
49
50
  // Instance variables filled by tablegen, do not use!
51
  const MCRegisterClass *MC;
52
  const uint32_t *SubClassMask;
53
  const uint16_t *SuperRegIndices;
54
  const LaneBitmask LaneMask;
55
  /// Classes with a higher priority value are assigned first by register
56
  /// allocators using a greedy heuristic. The value is in the range [0,63].
57
  const uint8_t AllocationPriority;
58
  /// Whether the class supports two (or more) disjunct subregister indices.
59
  const bool HasDisjunctSubRegs;
60
  /// Whether a combination of subregisters can cover every register in the
61
  /// class. See also the CoveredBySubRegs description in Target.td.
62
  const bool CoveredBySubRegs;
63
  const sc_iterator SuperClasses;
64
  ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
65
66
  /// Return the register class ID number.
67
622M
  unsigned getID() const { return MC->getID(); }
68
69
  /// begin/end - Return all of the registers in this class.
70
  ///
71
20.2M
  iterator       begin() const { return MC->begin(); }
72
18.6M
  iterator         end() const { return MC->end(); }
73
74
  /// Return the number of registers in this class.
75
499M
  unsigned getNumRegs() const { return MC->getNumRegs(); }
76
77
  iterator_range<SmallVectorImpl<MCPhysReg>::const_iterator>
78
49.8k
  getRegisters() const {
79
49.8k
    return make_range(MC->begin(), MC->end());
80
49.8k
  }
81
82
  /// Return the specified register in the class.
83
15.9M
  unsigned getRegister(unsigned i) const {
84
15.9M
    return MC->getRegister(i);
85
15.9M
  }
86
87
  /// Return true if the specified register is included in this register class.
88
  /// This does not include virtual registers.
89
589M
  bool contains(unsigned Reg) const {
90
589M
    return MC->contains(Reg);
91
589M
  }
92
93
  /// Return true if both registers are in this class.
94
728k
  bool contains(unsigned Reg1, unsigned Reg2) const {
95
728k
    return MC->contains(Reg1, Reg2);
96
728k
  }
97
98
  /// Return the cost of copying a value between two registers in this class.
99
  /// A negative number means the register class is very expensive
100
  /// to copy e.g. status flag register classes.
101
793k
  int getCopyCost() const { return MC->getCopyCost(); }
102
103
  /// Return true if this register class may be used to create virtual
104
  /// registers.
105
15.9M
  bool isAllocatable() const { return MC->isAllocatable(); }
106
107
  /// Return true if the specified TargetRegisterClass
108
  /// is a proper sub-class of this TargetRegisterClass.
109
22.0M
  bool hasSubClass(const TargetRegisterClass *RC) const {
110
22.0M
    return RC != this && hasSubClassEq(RC);
111
22.0M
  }
112
113
  /// Returns true if RC is a sub-class of or equal to this class.
114
44.7M
  bool hasSubClassEq(const TargetRegisterClass *RC) const {
115
44.7M
    unsigned ID = RC->getID();
116
44.7M
    return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
117
44.7M
  }
118
119
  /// Return true if the specified TargetRegisterClass is a
120
  /// proper super-class of this TargetRegisterClass.
121
0
  bool hasSuperClass(const TargetRegisterClass *RC) const {
122
0
    return RC->hasSubClass(this);
123
0
  }
124
125
  /// Returns true if RC is a super-class of or equal to this class.
126
20.5M
  bool hasSuperClassEq(const TargetRegisterClass *RC) const {
127
20.5M
    return RC->hasSubClassEq(this);
128
20.5M
  }
129
130
  /// Returns a bit vector of subclasses, including this one.
131
  /// The vector is indexed by class IDs.
132
  ///
133
  /// To use it, consider the returned array as a chunk of memory that
134
  /// contains an array of bits of size NumRegClasses. Each 32-bit chunk
135
  /// contains a bitset of the ID of the subclasses in big-endian style.
136
137
  /// I.e., the representation of the memory from left to right at the
138
  /// bit level looks like:
139
  /// [31 30 ... 1 0] [ 63 62 ... 33 32] ...
140
  ///                     [ XXX NumRegClasses NumRegClasses - 1 ... ]
141
  /// Where the number represents the class ID and XXX bits that
142
  /// should be ignored.
143
  ///
144
  /// See the implementation of hasSubClassEq for an example of how it
145
  /// can be used.
146
56.8M
  const uint32_t *getSubClassMask() const {
147
56.8M
    return SubClassMask;
148
56.8M
  }
149
150
  /// Returns a 0-terminated list of sub-register indices that project some
151
  /// super-register class into this register class. The list has an entry for
152
  /// each Idx such that:
153
  ///
154
  ///   There exists SuperRC where:
155
  ///     For all Reg in SuperRC:
156
  ///       this->contains(Reg:Idx)
157
4.32M
  const uint16_t *getSuperRegIndices() const {
158
4.32M
    return SuperRegIndices;
159
4.32M
  }
160
161
  /// Returns a NULL-terminated list of super-classes.  The
162
  /// classes are ordered by ID which is also a topological ordering from large
163
  /// to small classes.  The list does NOT include the current class.
164
524k
  sc_iterator getSuperClasses() const {
165
524k
    return SuperClasses;
166
524k
  }
167
168
  /// Return true if this TargetRegisterClass is a subset
169
  /// class of at least one other TargetRegisterClass.
170
0
  bool isASubClass() const {
171
0
    return SuperClasses[0] != nullptr;
172
0
  }
173
174
  /// Returns the preferred order for allocating registers from this register
175
  /// class in MF. The raw order comes directly from the .td file and may
176
  /// include reserved registers that are not allocatable.
177
  /// Register allocators should also make sure to allocate
178
  /// callee-saved registers only after all the volatiles are used. The
179
  /// RegisterClassInfo class provides filtered allocation orders with
180
  /// callee-saved registers moved to the end.
181
  ///
182
  /// The MachineFunction argument can be used to tune the allocatable
183
  /// registers based on the characteristics of the function, subtarget, or
184
  /// other criteria.
185
  ///
186
  /// By default, this method returns all registers in the class.
187
1.63M
  ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
188
1.63M
    return OrderFunc ? 
OrderFunc(MF)168k
:
makeArrayRef(begin(), getNumRegs())1.46M
;
189
1.63M
  }
190
191
  /// Returns the combination of all lane masks of register in this class.
192
  /// The lane masks of the registers are the combination of all lane masks
193
  /// of their subregisters. Returns 1 if there are no subregisters.
194
15.8M
  LaneBitmask getLaneMask() const {
195
15.8M
    return LaneMask;
196
15.8M
  }
197
};
198
199
/// Extra information, not in MCRegisterDesc, about registers.
200
/// These are used by codegen, not by MC.
201
struct TargetRegisterInfoDesc {
202
  unsigned CostPerUse;          // Extra cost of instructions using register.
203
  bool inAllocatableClass;      // Register belongs to an allocatable regclass.
204
};
205
206
/// Each TargetRegisterClass has a per register weight, and weight
207
/// limit which must be less than the limits of its pressure sets.
208
struct RegClassWeight {
209
  unsigned RegWeight;
210
  unsigned WeightLimit;
211
};
212
213
/// TargetRegisterInfo base class - We assume that the target defines a static
214
/// array of TargetRegisterDesc objects that represent all of the machine
215
/// registers that the target has.  As such, we simply have to track a pointer
216
/// to this array so that we can turn register number into a register
217
/// descriptor.
218
///
219
class TargetRegisterInfo : public MCRegisterInfo {
220
public:
221
  using regclass_iterator = const TargetRegisterClass * const *;
222
  using vt_iterator = const MVT::SimpleValueType *;
223
  struct RegClassInfo {
224
    unsigned RegSize, SpillSize, SpillAlignment;
225
    vt_iterator VTList;
226
  };
227
private:
228
  const TargetRegisterInfoDesc *InfoDesc;     // Extra desc array for codegen
229
  const char *const *SubRegIndexNames;        // Names of subreg indexes.
230
  // Pointer to array of lane masks, one per sub-reg index.
231
  const LaneBitmask *SubRegIndexLaneMasks;
232
233
  regclass_iterator RegClassBegin, RegClassEnd;   // List of regclasses
234
  LaneBitmask CoveringLanes;
235
  const RegClassInfo *const RCInfos;
236
  unsigned HwMode;
237
238
protected:
239
  TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
240
                     regclass_iterator RCB,
241
                     regclass_iterator RCE,
242
                     const char *const *SRINames,
243
                     const LaneBitmask *SRILaneMasks,
244
                     LaneBitmask CoveringLanes,
245
                     const RegClassInfo *const RCIs,
246
                     unsigned Mode = 0);
247
  virtual ~TargetRegisterInfo();
248
249
public:
250
  // Register numbers can represent physical registers, virtual registers, and
251
  // sometimes stack slots. The unsigned values are divided into these ranges:
252
  //
253
  //   0           Not a register, can be used as a sentinel.
254
  //   [1;2^30)    Physical registers assigned by TableGen.
255
  //   [2^30;2^31) Stack slots. (Rarely used.)
256
  //   [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
257
  //
258
  // Further sentinels can be allocated from the small negative integers.
259
  // DenseMapInfo<unsigned> uses -1u and -2u.
260
261
  /// isStackSlot - Sometimes it is useful the be able to store a non-negative
262
  /// frame index in a variable that normally holds a register. isStackSlot()
263
  /// returns true if Reg is in the range used for stack slots.
264
  ///
265
  /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
266
  /// slots, so if a variable may contains a stack slot, always check
267
  /// isStackSlot() first.
268
  ///
269
4.76M
  static bool isStackSlot(unsigned Reg) {
270
4.76M
    return int(Reg) >= (1 << 30);
271
4.76M
  }
272
273
  /// Compute the frame index from a register value representing a stack slot.
274
698k
  static int stackSlot2Index(unsigned Reg) {
275
698k
    assert(isStackSlot(Reg) && "Not a stack slot");
276
698k
    return int(Reg - (1u << 30));
277
698k
  }
278
279
  /// Convert a non-negative frame index to a stack slot register value.
280
339k
  static unsigned index2StackSlot(int FI) {
281
339k
    assert(FI >= 0 && "Cannot hold a negative frame index.");
282
339k
    return FI + (1u << 30);
283
339k
  }
284
285
  /// Return true if the specified register number is in
286
  /// the physical register namespace.
287
1.15G
  static bool isPhysicalRegister(unsigned Reg) {
288
1.15G
    assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
289
1.15G
    return int(Reg) > 0;
290
1.15G
  }
291
292
  /// Return true if the specified register number is in
293
  /// the virtual register namespace.
294
2.69G
  static bool isVirtualRegister(unsigned Reg) {
295
2.69G
    assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
296
2.69G
    return int(Reg) < 0;
297
2.69G
  }
298
299
  /// Convert a virtual register number to a 0-based index.
300
  /// The first virtual register in a function will get the index 0.
301
2.60G
  static unsigned virtReg2Index(unsigned Reg) {
302
2.60G
    assert(isVirtualRegister(Reg) && "Not a virtual register");
303
2.60G
    return Reg & ~(1u << 31);
304
2.60G
  }
305
306
  /// Convert a 0-based index to a virtual register number.
307
  /// This is the inverse operation of VirtReg2IndexFunctor below.
308
280M
  static unsigned index2VirtReg(unsigned Index) {
309
280M
    return Index | (1u << 31);
310
280M
  }
311
312
  /// Return the size in bits of a register from class RC.
313
40.6M
  unsigned getRegSizeInBits(const TargetRegisterClass &RC) const {
314
40.6M
    return getRegClassInfo(RC).RegSize;
315
40.6M
  }
316
317
  /// Return the size in bytes of the stack slot allocated to hold a spilled
318
  /// copy of a register from class RC.
319
32.2M
  unsigned getSpillSize(const TargetRegisterClass &RC) const {
320
32.2M
    return getRegClassInfo(RC).SpillSize / 8;
321
32.2M
  }
322
323
  /// Return the minimum required alignment in bytes for a spill slot for
324
  /// a register of this class.
325
1.44M
  unsigned getSpillAlignment(const TargetRegisterClass &RC) const {
326
1.44M
    return getRegClassInfo(RC).SpillAlignment / 8;
327
1.44M
  }
328
329
  /// Return true if the given TargetRegisterClass has the ValueType T.
330
130M
  bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const {
331
300M
    for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; 
++I169M
)
332
191M
      if (MVT(*I) == T)
333
21.8M
        return true;
334
130M
    
return false108M
;
335
130M
  }
336
337
  /// Loop over all of the value types that can be represented by values
338
  /// in the given register class.
339
163M
  vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const {
340
163M
    return getRegClassInfo(RC).VTList;
341
163M
  }
342
343
0
  vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const {
344
0
    vt_iterator I = legalclasstypes_begin(RC);
345
0
    while (*I != MVT::Other)
346
0
      ++I;
347
0
    return I;
348
0
  }
349
350
  /// Returns the Register Class of a physical register of the given type,
351
  /// picking the most sub register class of the right type that contains this
352
  /// physreg.
353
  const TargetRegisterClass *
354
    getMinimalPhysRegClass(unsigned Reg, MVT VT = MVT::Other) const;
355
356
  /// Return the maximal subclass of the given register class that is
357
  /// allocatable or NULL.
358
  const TargetRegisterClass *
359
    getAllocatableClass(const TargetRegisterClass *RC) const;
360
361
  /// Returns a bitset indexed by register number indicating if a register is
362
  /// allocatable or not. If a register class is specified, returns the subset
363
  /// for the class.
364
  BitVector getAllocatableSet(const MachineFunction &MF,
365
                              const TargetRegisterClass *RC = nullptr) const;
366
367
  /// Return the additional cost of using this register instead
368
  /// of other registers in its class.
369
60.4M
  unsigned getCostPerUse(unsigned RegNo) const {
370
60.4M
    return InfoDesc[RegNo].CostPerUse;
371
60.4M
  }
372
373
  /// Return true if the register is in the allocation of any register class.
374
39.9M
  bool isInAllocatableClass(unsigned RegNo) const {
375
39.9M
    return InfoDesc[RegNo].inAllocatableClass;
376
39.9M
  }
377
378
  /// Return the human-readable symbolic target-specific
379
  /// name for the specified SubRegIndex.
380
20.6k
  const char *getSubRegIndexName(unsigned SubIdx) const {
381
20.6k
    assert(SubIdx && SubIdx < getNumSubRegIndices() &&
382
20.6k
           "This is not a subregister index");
383
20.6k
    return SubRegIndexNames[SubIdx-1];
384
20.6k
  }
385
386
  /// Return a bitmask representing the parts of a register that are covered by
387
  /// SubIdx \see LaneBitmask.
388
  ///
389
  /// SubIdx == 0 is allowed, it has the lane mask ~0u.
390
35.9M
  LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const {
391
35.9M
    assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
392
35.9M
    return SubRegIndexLaneMasks[SubIdx];
393
35.9M
  }
394
395
  /// The lane masks returned by getSubRegIndexLaneMask() above can only be
396
  /// used to determine if sub-registers overlap - they can't be used to
397
  /// determine if a set of sub-registers completely cover another
398
  /// sub-register.
399
  ///
400
  /// The X86 general purpose registers have two lanes corresponding to the
401
  /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
402
  /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
403
  /// sub_32bit sub-register.
404
  ///
405
  /// On the other hand, the ARM NEON lanes fully cover their registers: The
406
  /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
407
  /// This is related to the CoveredBySubRegs property on register definitions.
408
  ///
409
  /// This function returns a bit mask of lanes that completely cover their
410
  /// sub-registers. More precisely, given:
411
  ///
412
  ///   Covering = getCoveringLanes();
413
  ///   MaskA = getSubRegIndexLaneMask(SubA);
414
  ///   MaskB = getSubRegIndexLaneMask(SubB);
415
  ///
416
  /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
417
  /// SubB.
418
0
  LaneBitmask getCoveringLanes() const { return CoveringLanes; }
419
420
  /// Returns true if the two registers are equal or alias each other.
421
  /// The registers may be virtual registers.
422
19.4M
  bool regsOverlap(unsigned regA, unsigned regB) const {
423
19.4M
    if (regA == regB) 
return true620k
;
424
18.8M
    if (isVirtualRegister(regA) || 
isVirtualRegister(regB)17.9M
)
425
960k
      return false;
426
17.9M
427
17.9M
    // Regunits are numerically ordered. Find a common unit.
428
17.9M
    MCRegUnitIterator RUA(regA, this);
429
17.9M
    MCRegUnitIterator RUB(regB, this);
430
23.2M
    do {
431
23.2M
      if (*RUA == *RUB) 
return true85.9k
;
432
23.1M
      if (*RUA < *RUB) 
++RUA10.8M
;
433
12.3M
      else             ++RUB;
434
23.1M
    } while (RUA.isValid() && 
RUB.isValid()15.1M
);
435
17.9M
    
return false17.8M
;
436
17.9M
  }
437
438
  /// Returns true if Reg contains RegUnit.
439
6.87M
  bool hasRegUnit(unsigned Reg, unsigned RegUnit) const {
440
13.5M
    for (MCRegUnitIterator Units(Reg, this); Units.isValid(); 
++Units6.65M
)
441
6.97M
      if (*Units == RegUnit)
442
323k
        return true;
443
6.87M
    
return false6.55M
;
444
6.87M
  }
445
446
  /// Returns the original SrcReg unless it is the target of a copy-like
447
  /// operation, in which case we chain backwards through all such operations
448
  /// to the ultimate source register.  If a physical register is encountered,
449
  /// we stop the search.
450
  virtual unsigned lookThruCopyLike(unsigned SrcReg,
451
                                    const MachineRegisterInfo *MRI) const;
452
453
  /// Return a null-terminated list of all of the callee-saved registers on
454
  /// this target. The register should be in the order of desired callee-save
455
  /// stack frame offset. The first register is closest to the incoming stack
456
  /// pointer if stack grows down, and vice versa.
457
  /// Notice: This function does not take into account disabled CSRs.
458
  ///         In most cases you will want to use instead the function
459
  ///         getCalleeSavedRegs that is implemented in MachineRegisterInfo.
460
  virtual const MCPhysReg*
461
  getCalleeSavedRegs(const MachineFunction *MF) const = 0;
462
463
  /// Return a mask of call-preserved registers for the given calling convention
464
  /// on the current function. The mask should include all call-preserved
465
  /// aliases. This is used by the register allocator to determine which
466
  /// registers can be live across a call.
467
  ///
468
  /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
469
  /// A set bit indicates that all bits of the corresponding register are
470
  /// preserved across the function call.  The bit mask is expected to be
471
  /// sub-register complete, i.e. if A is preserved, so are all its
472
  /// sub-registers.
473
  ///
474
  /// Bits are numbered from the LSB, so the bit for physical register Reg can
475
  /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
476
  ///
477
  /// A NULL pointer means that no register mask will be used, and call
478
  /// instructions should use implicit-def operands to indicate call clobbered
479
  /// registers.
480
  ///
481
  virtual const uint32_t *getCallPreservedMask(const MachineFunction &MF,
482
0
                                               CallingConv::ID) const {
483
0
    // The default mask clobbers everything.  All targets should override.
484
0
    return nullptr;
485
0
  }
486
487
  /// Return a register mask that clobbers everything.
488
0
  virtual const uint32_t *getNoPreservedMask() const {
489
0
    llvm_unreachable("target does not provide no preserved mask");
490
0
  }
491
492
  /// Return true if all bits that are set in mask \p mask0 are also set in
493
  /// \p mask1.
494
  bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
495
496
  /// Return all the call-preserved register masks defined for this target.
497
  virtual ArrayRef<const uint32_t *> getRegMasks() const = 0;
498
  virtual ArrayRef<const char *> getRegMaskNames() const = 0;
499
500
  /// Returns a bitset indexed by physical register number indicating if a
501
  /// register is a special register that has particular uses and should be
502
  /// considered unavailable at all times, e.g. stack pointer, return address.
503
  /// A reserved register:
504
  /// - is not allocatable
505
  /// - is considered always live
506
  /// - is ignored by liveness tracking
507
  /// It is often necessary to reserve the super registers of a reserved
508
  /// register as well, to avoid them getting allocated indirectly. You may use
509
  /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
510
  virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
511
512
  /// Returns false if we can't guarantee that Physreg, specified as an IR asm
513
  /// clobber constraint, will be preserved across the statement.
514
  virtual bool isAsmClobberable(const MachineFunction &MF,
515
55.4k
                               unsigned PhysReg) const {
516
55.4k
    return true;
517
55.4k
  }
518
519
  /// Returns true if PhysReg is unallocatable and constant throughout the
520
  /// function.  Used by MachineRegisterInfo::isConstantPhysReg().
521
6.71M
  virtual bool isConstantPhysReg(unsigned PhysReg) const { return false; }
522
523
  /// Returns true if the register class is considered divergent.
524
4.83M
  virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const {
525
4.83M
    return false;
526
4.83M
  }
527
528
  /// Physical registers that may be modified within a function but are
529
  /// guaranteed to be restored before any uses. This is useful for targets that
530
  /// have call sequences where a GOT register may be updated by the caller
531
  /// prior to a call and is guaranteed to be restored (also by the caller)
532
  /// after the call.
533
  virtual bool isCallerPreservedPhysReg(unsigned PhysReg,
534
851k
                                        const MachineFunction &MF) const {
535
851k
    return false;
536
851k
  }
537
538
  /// Prior to adding the live-out mask to a stackmap or patchpoint
539
  /// instruction, provide the target the opportunity to adjust it (mainly to
540
  /// remove pseudo-registers that should be ignored).
541
75
  virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const {}
542
543
  /// Return a super-register of the specified register
544
  /// Reg so its sub-register of index SubIdx is Reg.
545
  unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
546
732k
                               const TargetRegisterClass *RC) const {
547
732k
    return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
548
732k
  }
549
550
  /// Return a subclass of the specified register
551
  /// class A so that each register in it has a sub-register of the
552
  /// specified sub-register index which is in the specified register class B.
553
  ///
554
  /// TableGen will synthesize missing A sub-classes.
555
  virtual const TargetRegisterClass *
556
  getMatchingSuperRegClass(const TargetRegisterClass *A,
557
                           const TargetRegisterClass *B, unsigned Idx) const;
558
559
  // For a copy-like instruction that defines a register of class DefRC with
560
  // subreg index DefSubReg, reading from another source with class SrcRC and
561
  // subregister SrcSubReg return true if this is a preferable copy
562
  // instruction or an earlier use should be used.
563
  virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
564
                                    unsigned DefSubReg,
565
                                    const TargetRegisterClass *SrcRC,
566
                                    unsigned SrcSubReg) const;
567
568
  /// Returns the largest legal sub-class of RC that
569
  /// supports the sub-register index Idx.
570
  /// If no such sub-class exists, return NULL.
571
  /// If all registers in RC already have an Idx sub-register, return RC.
572
  ///
573
  /// TableGen generates a version of this function that is good enough in most
574
  /// cases.  Targets can override if they have constraints that TableGen
575
  /// doesn't understand.  For example, the x86 sub_8bit sub-register index is
576
  /// supported by the full GR32 register class in 64-bit mode, but only by the
577
  /// GR32_ABCD regiister class in 32-bit mode.
578
  ///
579
  /// TableGen will synthesize missing RC sub-classes.
580
  virtual const TargetRegisterClass *
581
0
  getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
582
0
    assert(Idx == 0 && "Target has no sub-registers");
583
0
    return RC;
584
0
  }
585
586
  /// Return the subregister index you get from composing
587
  /// two subregister indices.
588
  ///
589
  /// The special null sub-register index composes as the identity.
590
  ///
591
  /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
592
  /// returns c. Note that composeSubRegIndices does not tell you about illegal
593
  /// compositions. If R does not have a subreg a, or R:a does not have a subreg
594
  /// b, composeSubRegIndices doesn't tell you.
595
  ///
596
  /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
597
  /// ssub_0:S0 - ssub_3:S3 subregs.
598
  /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
599
28.6M
  unsigned composeSubRegIndices(unsigned a, unsigned b) const {
600
28.6M
    if (!a) 
return b24.5M
;
601
4.13M
    if (!b) 
return a2.11M
;
602
2.02M
    return composeSubRegIndicesImpl(a, b);
603
2.02M
  }
604
605
  /// Transforms a LaneMask computed for one subregister to the lanemask that
606
  /// would have been computed when composing the subsubregisters with IdxA
607
  /// first. @sa composeSubRegIndices()
608
  LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA,
609
378k
                                         LaneBitmask Mask) const {
610
378k
    if (!IdxA)
611
14.1k
      return Mask;
612
364k
    return composeSubRegIndexLaneMaskImpl(IdxA, Mask);
613
364k
  }
614
615
  /// Transform a lanemask given for a virtual register to the corresponding
616
  /// lanemask before using subregister with index \p IdxA.
617
  /// This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a
618
  /// valie lane mask (no invalid bits set) the following holds:
619
  /// X0 = composeSubRegIndexLaneMask(Idx, Mask)
620
  /// X1 = reverseComposeSubRegIndexLaneMask(Idx, X0)
621
  /// => X1 == Mask
622
  LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA,
623
723k
                                                LaneBitmask LaneMask) const {
624
723k
    if (!IdxA)
625
255k
      return LaneMask;
626
468k
    return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask);
627
468k
  }
628
629
  /// Debugging helper: dump register in human readable form to dbgs() stream.
630
  static void dumpReg(unsigned Reg, unsigned SubRegIndex = 0,
631
                      const TargetRegisterInfo* TRI = nullptr);
632
633
protected:
634
  /// Overridden by TableGen in targets that have sub-registers.
635
0
  virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
636
0
    llvm_unreachable("Target has no sub-registers");
637
0
  }
638
639
  /// Overridden by TableGen in targets that have sub-registers.
640
  virtual LaneBitmask
641
0
  composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const {
642
0
    llvm_unreachable("Target has no sub-registers");
643
0
  }
644
645
  virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned,
646
0
                                                            LaneBitmask) const {
647
0
    llvm_unreachable("Target has no sub-registers");
648
0
  }
649
650
public:
651
  /// Find a common super-register class if it exists.
652
  ///
653
  /// Find a register class, SuperRC and two sub-register indices, PreA and
654
  /// PreB, such that:
655
  ///
656
  ///   1. PreA + SubA == PreB + SubB  (using composeSubRegIndices()), and
657
  ///
658
  ///   2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
659
  ///
660
  ///   3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
661
  ///
662
  /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
663
  /// requirements, and there is no register class with a smaller spill size
664
  /// that satisfies the requirements.
665
  ///
666
  /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
667
  ///
668
  /// Either of the PreA and PreB sub-register indices may be returned as 0. In
669
  /// that case, the returned register class will be a sub-class of the
670
  /// corresponding argument register class.
671
  ///
672
  /// The function returns NULL if no register class can be found.
673
  const TargetRegisterClass*
674
  getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
675
                         const TargetRegisterClass *RCB, unsigned SubB,
676
                         unsigned &PreA, unsigned &PreB) const;
677
678
  //===--------------------------------------------------------------------===//
679
  // Register Class Information
680
  //
681
protected:
682
237M
  const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const {
683
237M
    return RCInfos[getNumRegClasses() * HwMode + RC.getID()];
684
237M
  }
685
686
public:
687
  /// Register class iterators
688
279M
  regclass_iterator regclass_begin() const { return RegClassBegin; }
689
279M
  regclass_iterator regclass_end() const { return RegClassEnd; }
690
6.54M
  iterator_range<regclass_iterator> regclasses() const {
691
6.54M
    return make_range(regclass_begin(), regclass_end());
692
6.54M
  }
693
694
272M
  unsigned getNumRegClasses() const {
695
272M
    return (unsigned)(regclass_end()-regclass_begin());
696
272M
  }
697
698
  /// Returns the register class associated with the enumeration value.
699
  /// See class MCOperandInfo.
700
121M
  const TargetRegisterClass *getRegClass(unsigned i) const {
701
121M
    assert(i < getNumRegClasses() && "Register Class ID out of range");
702
121M
    return RegClassBegin[i];
703
121M
  }
704
705
  /// Returns the name of the register class.
706
336k
  const char *getRegClassName(const TargetRegisterClass *Class) const {
707
336k
    return MCRegisterInfo::getRegClassName(Class->MC);
708
336k
  }
709
710
  /// Find the largest common subclass of A and B.
711
  /// Return NULL if there is no common subclass.
712
  /// The common subclass should contain
713
  /// simple value type SVT if it is not the Any type.
714
  const TargetRegisterClass *
715
  getCommonSubClass(const TargetRegisterClass *A,
716
                    const TargetRegisterClass *B,
717
                    const MVT::SimpleValueType SVT =
718
                    MVT::SimpleValueType::Any) const;
719
720
  /// Returns a TargetRegisterClass used for pointer values.
721
  /// If a target supports multiple different pointer register classes,
722
  /// kind specifies which one is indicated.
723
  virtual const TargetRegisterClass *
724
0
  getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
725
0
    llvm_unreachable("Target didn't implement getPointerRegClass!");
726
0
  }
727
728
  /// Returns a legal register class to copy a register in the specified class
729
  /// to or from. If it is possible to copy the register directly without using
730
  /// a cross register class copy, return the specified RC. Returns NULL if it
731
  /// is not possible to copy between two registers of the specified class.
732
  virtual const TargetRegisterClass *
733
0
  getCrossCopyRegClass(const TargetRegisterClass *RC) const {
734
0
    return RC;
735
0
  }
736
737
  /// Returns the largest super class of RC that is legal to use in the current
738
  /// sub-target and has the same spill size.
739
  /// The returned register class can be used to create virtual registers which
740
  /// means that all its registers can be copied and spilled.
741
  virtual const TargetRegisterClass *
742
  getLargestLegalSuperClass(const TargetRegisterClass *RC,
743
3.45M
                            const MachineFunction &) const {
744
3.45M
    /// The default implementation is very conservative and doesn't allow the
745
3.45M
    /// register allocator to inflate register classes.
746
3.45M
    return RC;
747
3.45M
  }
748
749
  /// Return the register pressure "high water mark" for the specific register
750
  /// class. The scheduler is in high register pressure mode (for the specific
751
  /// register class) if it goes over the limit.
752
  ///
753
  /// Note: this is the old register pressure model that relies on a manually
754
  /// specified representative register class per value type.
755
  virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
756
45.2k
                                       MachineFunction &MF) const {
757
45.2k
    return 0;
758
45.2k
  }
759
760
  /// Return a heuristic for the machine scheduler to compare the profitability
761
  /// of increasing one register pressure set versus another.  The scheduler
762
  /// will prefer increasing the register pressure of the set which returns
763
  /// the largest value for this function.
764
  virtual unsigned getRegPressureSetScore(const MachineFunction &MF,
765
6.37M
                                          unsigned PSetID) const {
766
6.37M
    return PSetID;
767
6.37M
  }
768
769
  /// Get the weight in units of pressure for this register class.
770
  virtual const RegClassWeight &getRegClassWeight(
771
    const TargetRegisterClass *RC) const = 0;
772
773
  /// Returns size in bits of a phys/virtual/generic register.
774
  unsigned getRegSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI) const;
775
776
  /// Get the weight in units of pressure for this register unit.
777
  virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
778
779
  /// Get the number of dimensions of register pressure.
780
  virtual unsigned getNumRegPressureSets() const = 0;
781
782
  /// Get the name of this register unit pressure set.
783
  virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
784
785
  /// Get the register unit pressure limit for this dimension.
786
  /// This limit must be adjusted dynamically for reserved registers.
787
  virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
788
                                          unsigned Idx) const = 0;
789
790
  /// Get the dimensions of register pressure impacted by this register class.
791
  /// Returns a -1 terminated array of pressure set IDs.
792
  virtual const int *getRegClassPressureSets(
793
    const TargetRegisterClass *RC) const = 0;
794
795
  /// Get the dimensions of register pressure impacted by this register unit.
796
  /// Returns a -1 terminated array of pressure set IDs.
797
  virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
798
799
  /// Get a list of 'hint' registers that the register allocator should try
800
  /// first when allocating a physical register for the virtual register
801
  /// VirtReg. These registers are effectively moved to the front of the
802
  /// allocation order. If true is returned, regalloc will try to only use
803
  /// hints to the greatest extent possible even if it means spilling.
804
  ///
805
  /// The Order argument is the allocation order for VirtReg's register class
806
  /// as returned from RegisterClassInfo::getOrder(). The hint registers must
807
  /// come from Order, and they must not be reserved.
808
  ///
809
  /// The default implementation of this function will only add target
810
  /// independent register allocation hints. Targets that override this
811
  /// function should typically call this default implementation as well and
812
  /// expect to see generic copy hints added.
813
  virtual bool getRegAllocationHints(unsigned VirtReg,
814
                                     ArrayRef<MCPhysReg> Order,
815
                                     SmallVectorImpl<MCPhysReg> &Hints,
816
                                     const MachineFunction &MF,
817
                                     const VirtRegMap *VRM = nullptr,
818
                                     const LiveRegMatrix *Matrix = nullptr)
819
    const;
820
821
  /// A callback to allow target a chance to update register allocation hints
822
  /// when a register is "changed" (e.g. coalesced) to another register.
823
  /// e.g. On ARM, some virtual registers should target register pairs,
824
  /// if one of pair is coalesced to another register, the allocation hint of
825
  /// the other half of the pair should be changed to point to the new register.
826
  virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg,
827
3.53M
                                  MachineFunction &MF) const {
828
3.53M
    // Do nothing.
829
3.53M
  }
830
831
  /// Allow the target to reverse allocation order of local live ranges. This
832
  /// will generally allocate shorter local live ranges first. For targets with
833
  /// many registers, this could reduce regalloc compile time by a large
834
  /// factor. It is disabled by default for three reasons:
835
  /// (1) Top-down allocation is simpler and easier to debug for targets that
836
  /// don't benefit from reversing the order.
837
  /// (2) Bottom-up allocation could result in poor evicition decisions on some
838
  /// targets affecting the performance of compiled code.
839
  /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
840
8.81M
  virtual bool reverseLocalAssignment() const { return false; }
841
842
  /// Allow the target to override the cost of using a callee-saved register for
843
  /// the first time. Default value of 0 means we will use a callee-saved
844
  /// register if it is available.
845
201k
  virtual unsigned getCSRFirstUseCost() const { return 0; }
846
847
  /// Returns true if the target requires (and can make use of) the register
848
  /// scavenger.
849
351k
  virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
850
351k
    return false;
851
351k
  }
852
853
  /// Returns true if the target wants to use frame pointer based accesses to
854
  /// spill to the scavenger emergency spill slot.
855
25.8k
  virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
856
25.8k
    return true;
857
25.8k
  }
858
859
  /// Returns true if the target requires post PEI scavenging of registers for
860
  /// materializing frame index constants.
861
146k
  virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
862
146k
    return false;
863
146k
  }
864
865
  /// Returns true if the target requires using the RegScavenger directly for
866
  /// frame elimination despite using requiresFrameIndexScavenging.
867
  virtual bool requiresFrameIndexReplacementScavenging(
868
259k
      const MachineFunction &MF) const {
869
259k
    return false;
870
259k
  }
871
872
  /// Returns true if the target wants the LocalStackAllocation pass to be run
873
  /// and virtual base registers used for more efficient stack access.
874
177k
  virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
875
177k
    return false;
876
177k
  }
877
878
  /// Return true if target has reserved a spill slot in the stack frame of
879
  /// the given function for the specified register. e.g. On x86, if the frame
880
  /// register is required, the first fixed stack object is reserved as its
881
  /// spill slot. This tells PEI not to create a new stack frame
882
  /// object for the given register. It should be called only after
883
  /// determineCalleeSaves().
884
  virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
885
1.30M
                                    int &FrameIdx) const {
886
1.30M
    return false;
887
1.30M
  }
888
889
  /// Returns true if the live-ins should be tracked after register allocation.
890
8.75k
  virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
891
8.75k
    return false;
892
8.75k
  }
893
894
  /// True if the stack can be realigned for the target.
895
  virtual bool canRealignStack(const MachineFunction &MF) const;
896
897
  /// True if storage within the function requires the stack pointer to be
898
  /// aligned more than the normal calling convention calls for.
899
  /// This cannot be overriden by the target, but canRealignStack can be
900
  /// overridden.
901
  bool needsStackRealignment(const MachineFunction &MF) const;
902
903
  /// Get the offset from the referenced frame index in the instruction,
904
  /// if there is one.
905
  virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
906
1.79k
                                           int Idx) const {
907
1.79k
    return 0;
908
1.79k
  }
909
910
  /// Returns true if the instruction's frame index reference would be better
911
  /// served by a base register other than FP or SP.
912
  /// Used by LocalStackFrameAllocation to determine which frame index
913
  /// references it should create new base registers for.
914
0
  virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
915
0
    return false;
916
0
  }
917
918
  /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
919
  /// before insertion point I.
920
  virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
921
                                            unsigned BaseReg, int FrameIdx,
922
0
                                            int64_t Offset) const {
923
0
    llvm_unreachable("materializeFrameBaseRegister does not exist on this "
924
0
                     "target");
925
0
  }
926
927
  /// Resolve a frame index operand of an instruction
928
  /// to reference the indicated base register plus offset instead.
929
  virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
930
0
                                 int64_t Offset) const {
931
0
    llvm_unreachable("resolveFrameIndex does not exist on this target");
932
0
  }
933
934
  /// Determine whether a given base register plus offset immediate is
935
  /// encodable to resolve a frame index.
936
  virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
937
0
                                  int64_t Offset) const {
938
0
    llvm_unreachable("isFrameOffsetLegal does not exist on this target");
939
0
  }
940
941
  /// Spill the register so it can be used by the register scavenger.
942
  /// Return true if the register was spilled, false otherwise.
943
  /// If this function does not spill the register, the scavenger
944
  /// will instead spill it to the emergency spill slot.
945
  virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
946
                                     MachineBasicBlock::iterator I,
947
                                     MachineBasicBlock::iterator &UseMI,
948
                                     const TargetRegisterClass *RC,
949
33
                                     unsigned Reg) const {
950
33
    return false;
951
33
  }
952
953
  /// This method must be overriden to eliminate abstract frame indices from
954
  /// instructions which may use them. The instruction referenced by the
955
  /// iterator contains an MO_FrameIndex operand which must be eliminated by
956
  /// this method. This method may modify or replace the specified instruction,
957
  /// as long as it keeps the iterator pointing at the finished product.
958
  /// SPAdj is the SP adjustment due to call frame setup instruction.
959
  /// FIOperandNum is the FI operand number.
960
  virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
961
                                   int SPAdj, unsigned FIOperandNum,
962
                                   RegScavenger *RS = nullptr) const = 0;
963
964
  /// Return the assembly name for \p Reg.
965
121M
  virtual StringRef getRegAsmName(unsigned Reg) const {
966
121M
    // FIXME: We are assuming that the assembly name is equal to the TableGen
967
121M
    // name converted to lower case
968
121M
    //
969
121M
    // The TableGen name is the name of the definition for this register in the
970
121M
    // target's tablegen files.  For example, the TableGen name of
971
121M
    // def EAX : Register <...>; is "EAX"
972
121M
    return StringRef(getName(Reg));
973
121M
  }
974
975
  //===--------------------------------------------------------------------===//
976
  /// Subtarget Hooks
977
978
  /// SrcRC and DstRC will be morphed into NewRC if this returns true.
979
  virtual bool shouldCoalesce(MachineInstr *MI,
980
                              const TargetRegisterClass *SrcRC,
981
                              unsigned SubReg,
982
                              const TargetRegisterClass *DstRC,
983
                              unsigned DstSubReg,
984
                              const TargetRegisterClass *NewRC,
985
                              LiveIntervals &LIS) const
986
3.59M
  { return true; }
987
988
  //===--------------------------------------------------------------------===//
989
  /// Debug information queries.
990
991
  /// getFrameRegister - This method should return the register used as a base
992
  /// for values allocated in the current stack frame.
993
  virtual Register getFrameRegister(const MachineFunction &MF) const = 0;
994
995
  /// Mark a register and all its aliases as reserved in the given set.
996
  void markSuperRegs(BitVector &RegisterSet, unsigned Reg) const;
997
998
  /// Returns true if for every register in the set all super registers are part
999
  /// of the set as well.
1000
  bool checkAllSuperRegsMarked(const BitVector &RegisterSet,
1001
      ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
1002
1003
  virtual const TargetRegisterClass *
1004
  getConstrainedRegClassForOperand(const MachineOperand &MO,
1005
0
                                   const MachineRegisterInfo &MRI) const {
1006
0
    return nullptr;
1007
0
  }
1008
};
1009
1010
//===----------------------------------------------------------------------===//
1011
//                           SuperRegClassIterator
1012
//===----------------------------------------------------------------------===//
1013
//
1014
// Iterate over the possible super-registers for a given register class. The
1015
// iterator will visit a list of pairs (Idx, Mask) corresponding to the
1016
// possible classes of super-registers.
1017
//
1018
// Each bit mask will have at least one set bit, and each set bit in Mask
1019
// corresponds to a SuperRC such that:
1020
//
1021
//   For all Reg in SuperRC: Reg:Idx is in RC.
1022
//
1023
// The iterator can include (O, RC->getSubClassMask()) as the first entry which
1024
// also satisfies the above requirement, assuming Reg:0 == Reg.
1025
//
1026
class SuperRegClassIterator {
1027
  const unsigned RCMaskWords;
1028
  unsigned SubReg = 0;
1029
  const uint16_t *Idx;
1030
  const uint32_t *Mask;
1031
1032
public:
1033
  /// Create a SuperRegClassIterator that visits all the super-register classes
1034
  /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
1035
  SuperRegClassIterator(const TargetRegisterClass *RC,
1036
                        const TargetRegisterInfo *TRI,
1037
                        bool IncludeSelf = false)
1038
    : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
1039
4.32M
      Idx(RC->getSuperRegIndices()), Mask(RC->getSubClassMask()) {
1040
4.32M
    if (!IncludeSelf)
1041
3.97M
      ++*this;
1042
4.32M
  }
1043
1044
  /// Returns true if this iterator is still pointing at a valid entry.
1045
13.4M
  bool isValid() const { return Idx; }
1046
1047
  /// Returns the current sub-register index.
1048
9.42M
  unsigned getSubReg() const { return SubReg; }
1049
1050
  /// Returns the bit mask of register classes that getSubReg() projects into
1051
  /// RC.
1052
  /// See TargetRegisterClass::getSubClassMask() for how to use it.
1053
11.2M
  const uint32_t *getMask() const { return Mask; }
1054
1055
  /// Advance iterator to the next entry.
1056
13.1M
  void operator++() {
1057
13.1M
    assert(isValid() && "Cannot move iterator past end.");
1058
13.1M
    Mask += RCMaskWords;
1059
13.1M
    SubReg = *Idx++;
1060
13.1M
    if (!SubReg)
1061
567k
      Idx = nullptr;
1062
13.1M
  }
1063
};
1064
1065
//===----------------------------------------------------------------------===//
1066
//                           BitMaskClassIterator
1067
//===----------------------------------------------------------------------===//
1068
/// This class encapuslates the logic to iterate over bitmask returned by
1069
/// the various RegClass related APIs.
1070
/// E.g., this class can be used to iterate over the subclasses provided by
1071
/// TargetRegisterClass::getSubClassMask or SuperRegClassIterator::getMask.
1072
class BitMaskClassIterator {
1073
  /// Total number of register classes.
1074
  const unsigned NumRegClasses;
1075
  /// Base index of CurrentChunk.
1076
  /// In other words, the number of bit we read to get at the
1077
  /// beginning of that chunck.
1078
  unsigned Base = 0;
1079
  /// Adjust base index of CurrentChunk.
1080
  /// Base index + how many bit we read within CurrentChunk.
1081
  unsigned Idx = 0;
1082
  /// Current register class ID.
1083
  unsigned ID = 0;
1084
  /// Mask we are iterating over.
1085
  const uint32_t *Mask;
1086
  /// Current chunk of the Mask we are traversing.
1087
  uint32_t CurrentChunk;
1088
1089
  /// Move ID to the next set bit.
1090
253k
  void moveToNextID() {
1091
253k
    // If the current chunk of memory is empty, move to the next one,
1092
253k
    // while making sure we do not go pass the number of register
1093
253k
    // classes.
1094
631k
    while (!CurrentChunk) {
1095
504k
      // Move to the next chunk.
1096
504k
      Base += 32;
1097
504k
      if (Base >= NumRegClasses) {
1098
126k
        ID = NumRegClasses;
1099
126k
        return;
1100
126k
      }
1101
378k
      CurrentChunk = *++Mask;
1102
378k
      Idx = Base;
1103
378k
    }
1104
253k
    // Otherwise look for the first bit set from the right
1105
253k
    // (representation of the class ID is big endian).
1106
253k
    // See getSubClassMask for more details on the representation.
1107
253k
    unsigned Offset = countTrailingZeros(CurrentChunk);
1108
127k
    // Add the Offset to the adjusted base number of this chunk: Idx.
1109
127k
    // This is the ID of the register class.
1110
127k
    ID = Idx + Offset;
1111
127k
1112
127k
    // Consume the zeros, if any, and the bit we just read
1113
127k
    // so that we are at the right spot for the next call.
1114
127k
    // Do not do Offset + 1 because Offset may be 31 and 32
1115
127k
    // will be UB for the shift, though in that case we could
1116
127k
    // have make the chunk being equal to 0, but that would
1117
127k
    // have introduced a if statement.
1118
127k
    moveNBits(Offset);
1119
127k
    moveNBits(1);
1120
127k
  }
1121
1122
  /// Move \p NumBits Bits forward in CurrentChunk.
1123
254k
  void moveNBits(unsigned NumBits) {
1124
254k
    assert(NumBits < 32 && "Undefined behavior spotted!");
1125
254k
    // Consume the bit we read for the next call.
1126
254k
    CurrentChunk >>= NumBits;
1127
254k
    // Adjust the base for the chunk.
1128
254k
    Idx += NumBits;
1129
254k
  }
1130
1131
public:
1132
  /// Create a BitMaskClassIterator that visits all the register classes
1133
  /// represented by \p Mask.
1134
  ///
1135
  /// \pre \p Mask != nullptr
1136
  BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
1137
126k
      : NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) {
1138
126k
    // Move to the first ID.
1139
126k
    moveToNextID();
1140
126k
  }
1141
1142
  /// Returns true if this iterator is still pointing at a valid entry.
1143
253k
  bool isValid() const { return getID() != NumRegClasses; }
1144
1145
  /// Returns the current register class ID.
1146
380k
  unsigned getID() const { return ID; }
1147
1148
  /// Advance iterator to the next entry.
1149
126k
  void operator++() {
1150
126k
    assert(isValid() && "Cannot move iterator past end.");
1151
126k
    moveToNextID();
1152
126k
  }
1153
};
1154
1155
// This is useful when building IndexedMaps keyed on virtual registers
1156
struct VirtReg2IndexFunctor {
1157
  using argument_type = unsigned;
1158
2.51G
  unsigned operator()(unsigned Reg) const {
1159
2.51G
    return TargetRegisterInfo::virtReg2Index(Reg);
1160
2.51G
  }
1161
};
1162
1163
/// Prints virtual and physical registers with or without a TRI instance.
1164
///
1165
/// The format is:
1166
///   %noreg          - NoRegister
1167
///   %5              - a virtual register.
1168
///   %5:sub_8bit     - a virtual register with sub-register index (with TRI).
1169
///   %eax            - a physical register
1170
///   %physreg17      - a physical register when no TRI instance given.
1171
///
1172
/// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
1173
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr,
1174
                   unsigned SubIdx = 0,
1175
                   const MachineRegisterInfo *MRI = nullptr);
1176
1177
/// Create Printable object to print register units on a \ref raw_ostream.
1178
///
1179
/// Register units are named after their root registers:
1180
///
1181
///   al      - Single root.
1182
///   fp0~st7 - Dual roots.
1183
///
1184
/// Usage: OS << printRegUnit(Unit, TRI) << '\n';
1185
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
1186
1187
/// Create Printable object to print virtual registers and physical
1188
/// registers on a \ref raw_ostream.
1189
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
1190
1191
/// Create Printable object to print register classes or register banks
1192
/// on a \ref raw_ostream.
1193
Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo,
1194
                              const TargetRegisterInfo *TRI);
1195
1196
} // end namespace llvm
1197
1198
#endif // LLVM_CODEGEN_TARGETREGISTERINFO_H