Coverage Report

Created: 2018-09-17 19:50

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/TargetSchedule.h
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//===- llvm/CodeGen/TargetSchedule.h - Sched Machine Model ------*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a wrapper around MCSchedModel that allows the interface to
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// benefit from information currently only available in TargetInstrInfo.
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// Ideally, the scheduling interface would be fully defined in the MC layer.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_TARGETSCHEDULE_H
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#define LLVM_CODEGEN_TARGETSCHEDULE_H
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/Config/llvm-config.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/MC/MCSchedule.h"
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namespace llvm {
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class MachineInstr;
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class TargetInstrInfo;
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/// Provide an instruction scheduling machine model to CodeGen passes.
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class TargetSchedModel {
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  // For efficiency, hold a copy of the statically defined MCSchedModel for this
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  // processor.
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  MCSchedModel SchedModel;
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  InstrItineraryData InstrItins;
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  const TargetSubtargetInfo *STI = nullptr;
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  const TargetInstrInfo *TII = nullptr;
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  SmallVector<unsigned, 16> ResourceFactors;
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  unsigned MicroOpFactor; // Multiply to normalize microops to resource units.
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  unsigned ResourceLCM;   // Resource units per cycle. Latency normalization factor.
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  unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
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public:
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731k
  TargetSchedModel() : SchedModel(MCSchedModel::GetDefaultSchedModel()) {}
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  /// Initialize the machine model for instruction scheduling.
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  ///
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  /// The machine model API keeps a copy of the top-level MCSchedModel table
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  /// indices and may query TargetSubtargetInfo and TargetInstrInfo to resolve
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  /// dynamic properties.
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  void init(const TargetSubtargetInfo *TSInfo);
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  /// Return the MCSchedClassDesc for this instruction.
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  const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
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  /// TargetSubtargetInfo getter.
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  const TargetSubtargetInfo *getSubtargetInfo() const { return STI; }
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  /// TargetInstrInfo getter.
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  const TargetInstrInfo *getInstrInfo() const { return TII; }
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  /// Return true if this machine model includes an instruction-level
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  /// scheduling model.
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  ///
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  /// This is more detailed than the course grain IssueWidth and default
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  /// latency properties, but separate from the per-cycle itinerary data.
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  bool hasInstrSchedModel() const;
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  const MCSchedModel *getMCSchedModel() const { return &SchedModel; }
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  /// Return true if this machine model includes cycle-to-cycle itinerary
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  /// data.
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  ///
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  /// This models scheduling at each stage in the processor pipeline.
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  bool hasInstrItineraries() const;
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  const InstrItineraryData *getInstrItineraries() const {
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    if (hasInstrItineraries())
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      return &InstrItins;
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    return nullptr;
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  }
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  /// Return true if this machine model includes an instruction-level
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  /// scheduling model or cycle-to-cycle itinerary data.
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  bool hasInstrSchedModelOrItineraries() const {
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    return hasInstrSchedModel() || 
hasInstrItineraries()2.42k
;
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  }
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  /// Identify the processor corresponding to the current subtarget.
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  unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
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  /// Maximum number of micro-ops that may be scheduled per cycle.
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  unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
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  /// Return true if new group must begin.
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  bool mustBeginGroup(const MachineInstr *MI,
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                          const MCSchedClassDesc *SC = nullptr) const;
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  /// Return true if current group must end.
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  bool mustEndGroup(const MachineInstr *MI,
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                          const MCSchedClassDesc *SC = nullptr) const;
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  /// Return the number of issue slots required for this MI.
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  unsigned getNumMicroOps(const MachineInstr *MI,
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                          const MCSchedClassDesc *SC = nullptr) const;
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  /// Get the number of kinds of resources for this target.
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  unsigned getNumProcResourceKinds() const {
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    return SchedModel.getNumProcResourceKinds();
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  }
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  /// Get a processor resource by ID for convenience.
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  const MCProcResourceDesc *getProcResource(unsigned PIdx) const {
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    return SchedModel.getProcResource(PIdx);
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  }
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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  const char *getResourceName(unsigned PIdx) const {
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    if (!PIdx)
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      return "MOps";
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    return SchedModel.getProcResource(PIdx)->Name;
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  }
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#endif
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  using ProcResIter = const MCWriteProcResEntry *;
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  // Get an iterator into the processor resources consumed by this
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  // scheduling class.
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  ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const {
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    // The subtarget holds a single resource table for all processors.
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    return STI->getWriteProcResBegin(SC);
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  }
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  ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const {
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    return STI->getWriteProcResEnd(SC);
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  }
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  /// Multiply the number of units consumed for a resource by this factor
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  /// to normalize it relative to other resources.
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  unsigned getResourceFactor(unsigned ResIdx) const {
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    return ResourceFactors[ResIdx];
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  }
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  /// Multiply number of micro-ops by this factor to normalize it
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  /// relative to other resources.
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  unsigned getMicroOpFactor() const {
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    return MicroOpFactor;
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  }
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  /// Multiply cycle count by this factor to normalize it relative to
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  /// other resources. This is the number of resource units per cycle.
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  unsigned getLatencyFactor() const {
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    return ResourceLCM;
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  }
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  /// Number of micro-ops that may be buffered for OOO execution.
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  unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; }
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  /// Number of resource units that may be buffered for OOO execution.
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  /// \return The buffer size in resource units or -1 for unlimited.
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  int getResourceBufferSize(unsigned PIdx) const {
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    return SchedModel.getProcResource(PIdx)->BufferSize;
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  }
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  /// Compute operand latency based on the available machine model.
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  ///
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  /// Compute and return the latency of the given data dependent def and use
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  /// when the operand indices are already known. UseMI may be NULL for an
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  /// unknown user.
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  unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
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                                 const MachineInstr *UseMI, unsigned UseOperIdx)
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    const;
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  /// Compute the instruction latency based on the available machine
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  /// model.
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  ///
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  /// Compute and return the expected latency of this instruction independent of
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  /// a particular use. computeOperandLatency is the preferred API, but this is
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  /// occasionally useful to help estimate instruction cost.
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  ///
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  /// If UseDefaultDefLatency is false and no new machine sched model is
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  /// present this method falls back to TII->getInstrLatency with an empty
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  /// instruction itinerary (this is so we preserve the previous behavior of the
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  /// if converter after moving it to TargetSchedModel).
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  unsigned computeInstrLatency(const MachineInstr *MI,
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                               bool UseDefaultDefLatency = true) const;
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  unsigned computeInstrLatency(const MCInst &Inst) const;
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  unsigned computeInstrLatency(unsigned Opcode) const;
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  /// Output dependency latency of a pair of defs of the same register.
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  ///
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  /// This is typically one cycle.
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  unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
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                                const MachineInstr *DepMI) const;
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  /// Compute the reciprocal throughput of the given instruction.
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  double computeReciprocalThroughput(const MachineInstr *MI) const;
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  double computeReciprocalThroughput(const MCInst &MI) const;
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  double computeReciprocalThroughput(unsigned Opcode) const;
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};
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} // end namespace llvm
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#endif // LLVM_CODEGEN_TARGETSCHEDULE_H