Coverage Report

Created: 2019-02-20 07:29

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
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//===- llvm/CodeGen/TargetSubtargetInfo.h - Target Information --*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the subtarget options of a Target machine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_TARGETSUBTARGETINFO_H
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#define LLVM_CODEGEN_TARGETSUBTARGETINFO_H
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/PBQPRAConstraint.h"
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#include "llvm/CodeGen/ScheduleDAGMutation.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/CodeGen.h"
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#include <memory>
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#include <vector>
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namespace llvm {
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class CallLowering;
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class InstrItineraryData;
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struct InstrStage;
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class InstructionSelector;
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class LegalizerInfo;
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class MachineInstr;
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struct MachineSchedPolicy;
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struct MCReadAdvanceEntry;
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struct MCWriteLatencyEntry;
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struct MCWriteProcResEntry;
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class RegisterBankInfo;
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class SDep;
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class SelectionDAGTargetInfo;
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struct SubtargetFeatureKV;
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struct SubtargetInfoKV;
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class SUnit;
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class TargetFrameLowering;
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class TargetInstrInfo;
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class TargetLowering;
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class TargetRegisterClass;
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class TargetRegisterInfo;
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class TargetSchedModel;
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class Triple;
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//===----------------------------------------------------------------------===//
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///
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/// TargetSubtargetInfo - Generic base class for all target subtargets.  All
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/// Target-specific options that control code generation and printing should
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/// be exposed through a TargetSubtargetInfo-derived class.
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///
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class TargetSubtargetInfo : public MCSubtargetInfo {
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protected: // Can only create subclasses...
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  TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
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                      ArrayRef<SubtargetFeatureKV> PF,
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                      ArrayRef<SubtargetFeatureKV> PD,
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                      const SubtargetInfoKV *ProcSched,
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                      const MCWriteProcResEntry *WPR,
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                      const MCWriteLatencyEntry *WL,
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                      const MCReadAdvanceEntry *RA, const InstrStage *IS,
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                      const unsigned *OC, const unsigned *FP);
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public:
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  // AntiDepBreakMode - Type of anti-dependence breaking that should
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  // be performed before post-RA scheduling.
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  using AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL };
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  using RegClassVector = SmallVectorImpl<const TargetRegisterClass *>;
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  TargetSubtargetInfo() = delete;
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  TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
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  TargetSubtargetInfo &operator=(const TargetSubtargetInfo &) = delete;
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  ~TargetSubtargetInfo() override;
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  virtual bool isXRaySupported() const { return false; }
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  // Interfaces to the major aspects of target machine information:
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  //
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  // -- Instruction opcode and operand information
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  // -- Pipelines and scheduling information
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  // -- Stack frame information
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  // -- Selection DAG lowering information
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  // -- Call lowering information
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  //
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  // N.B. These objects may change during compilation. It's not safe to cache
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  // them between functions.
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  virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; }
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  virtual const TargetFrameLowering *getFrameLowering() const {
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    return nullptr;
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  }
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  virtual const TargetLowering *getTargetLowering() const { return nullptr; }
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  virtual const SelectionDAGTargetInfo *getSelectionDAGInfo() const {
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    return nullptr;
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  }
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  virtual const CallLowering *getCallLowering() const { return nullptr; }
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  // FIXME: This lets targets specialize the selector by subtarget (which lets
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  // us do things like a dedicated avx512 selector).  However, we might want
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  // to also specialize selectors by MachineFunction, which would let us be
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  // aware of optsize/optnone and such.
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  virtual const InstructionSelector *getInstructionSelector() const {
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    return nullptr;
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  }
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  virtual unsigned getHwMode() const { return 0; }
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  /// Target can subclass this hook to select a different DAG scheduler.
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  virtual RegisterScheduler::FunctionPassCtor
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      getDAGScheduler(CodeGenOpt::Level) const {
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    return nullptr;
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  }
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  virtual const LegalizerInfo *getLegalizerInfo() const { return nullptr; }
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  /// getRegisterInfo - If register information is available, return it.  If
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  /// not, return null.
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  virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
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  /// If the information for the register banks is available, return it.
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  /// Otherwise return nullptr.
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  virtual const RegisterBankInfo *getRegBankInfo() const { return nullptr; }
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  /// getInstrItineraryData - Returns instruction itinerary data for the target
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  /// or specific subtarget.
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  virtual const InstrItineraryData *getInstrItineraryData() const {
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    return nullptr;
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  }
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  /// Resolve a SchedClass at runtime, where SchedClass identifies an
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  /// MCSchedClassDesc with the isVariant property. This may return the ID of
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  /// another variant SchedClass, but repeated invocation must quickly terminate
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  /// in a nonvariant SchedClass.
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  virtual unsigned resolveSchedClass(unsigned SchedClass,
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                                     const MachineInstr *MI,
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                                     const TargetSchedModel *SchedModel) const {
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    return 0;
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  }
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  /// Returns true if MI is a dependency breaking zero-idiom instruction for the
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  /// subtarget.
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  ///
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  /// This function also sets bits in Mask related to input operands that
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  /// are not in a data dependency relationship.  There is one bit for each
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  /// machine operand; implicit operands follow explicit operands in the bit
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  /// representation used for Mask.  An empty (i.e. a mask with all bits
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  /// cleared) means: data dependencies are "broken" for all the explicit input
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  /// machine operands of MI.
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  virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const {
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    return false;
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  }
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  /// Returns true if MI is a dependency breaking instruction for the subtarget.
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  ///
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  /// Similar in behavior to `isZeroIdiom`. However, it knows how to identify
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  /// all dependency breaking instructions (i.e. not just zero-idioms).
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  /// 
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  /// As for `isZeroIdiom`, this method returns a mask of "broken" dependencies.
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  /// (See method `isZeroIdiom` for a detailed description of Mask).
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  virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const {
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    return isZeroIdiom(MI, Mask);
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  }
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  /// Returns true if MI is a candidate for move elimination.
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  ///
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  /// A candidate for move elimination may be optimized out at register renaming
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  /// stage. Subtargets can specify the set of optimizable moves by
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  /// instantiating tablegen class `IsOptimizableRegisterMove` (see
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  /// llvm/Target/TargetInstrPredicate.td).
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  ///
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  /// SubtargetEmitter is responsible for processing all the definitions of class
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  /// IsOptimizableRegisterMove, and auto-generate an override for this method.
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  virtual bool isOptimizableRegisterMove(const MachineInstr *MI) const {
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    return false;
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  }
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  /// True if the subtarget should run MachineScheduler after aggressive
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  /// coalescing.
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  ///
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  /// This currently replaces the SelectionDAG scheduler with the "source" order
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  /// scheduler (though see below for an option to turn this off and use the
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  /// TargetLowering preference). It does not yet disable the postRA scheduler.
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  virtual bool enableMachineScheduler() const;
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  /// True if the machine scheduler should disable the TLI preference
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  /// for preRA scheduling with the source level scheduler.
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  virtual bool enableMachineSchedDefaultSched() const { return true; }
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  /// True if the subtarget should enable joining global copies.
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  ///
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  /// By default this is enabled if the machine scheduler is enabled, but
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  /// can be overridden.
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  virtual bool enableJoinGlobalCopies() const;
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  /// True if the subtarget should run a scheduler after register allocation.
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  ///
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  /// By default this queries the PostRAScheduling bit in the scheduling model
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  /// which is the preferred way to influence this.
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  virtual bool enablePostRAScheduler() const;
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  /// True if the subtarget should run the atomic expansion pass.
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  virtual bool enableAtomicExpand() const;
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  /// True if the subtarget should run the indirectbr expansion pass.
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  virtual bool enableIndirectBrExpand() const;
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  /// Override generic scheduling policy within a region.
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  ///
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  /// This is a convenient way for targets that don't provide any custom
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  /// scheduling heuristics (no custom MachineSchedStrategy) to make
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  /// changes to the generic scheduling policy.
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  virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
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                                   unsigned NumRegionInstrs) const {}
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  // Perform target specific adjustments to the latency of a schedule
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  // dependency.
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  virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const {}
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  // For use with PostRAScheduling: get the anti-dependence breaking that should
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  // be performed before post-RA scheduling.
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  virtual AntiDepBreakMode getAntiDepBreakMode() const { return ANTIDEP_NONE; }
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  // For use with PostRAScheduling: in CriticalPathRCs, return any register
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  // classes that should only be considered for anti-dependence breaking if they
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  // are on the critical path.
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  virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
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    return CriticalPathRCs.clear();
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  }
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  // Provide an ordered list of schedule DAG mutations for the post-RA
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  // scheduler.
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  virtual void getPostRAMutations(
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      std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
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  }
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  // Provide an ordered list of schedule DAG mutations for the machine
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  // pipeliner.
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  virtual void getSMSMutations(
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      std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
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  }
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  // For use with PostRAScheduling: get the minimum optimization level needed
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  // to enable post-RA scheduling.
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  virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const {
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    return CodeGenOpt::Default;
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  }
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  /// True if the subtarget should run the local reassignment
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  /// heuristic of the register allocator.
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  /// This heuristic may be compile time intensive, \p OptLevel provides
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  /// a finer grain to tune the register allocator.
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  virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const;
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  /// True if the subtarget should consider the cost of local intervals
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  /// created by a split candidate when choosing the best split candidate. This
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  /// heuristic may be compile time intensive.
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  virtual bool enableAdvancedRASplitCost() const;
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  /// Enable use of alias analysis during code generation (during MI
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  /// scheduling, DAGCombine, etc.).
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  virtual bool useAA() const;
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  /// Enable the use of the early if conversion pass.
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  virtual bool enableEarlyIfConversion() const { return false; }
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  /// Return PBQPConstraint(s) for the target.
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  ///
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  /// Override to provide custom PBQP constraints.
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  virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const {
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    return nullptr;
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  }
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  /// Enable tracking of subregister liveness in register allocator.
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  /// Please use MachineRegisterInfo::subRegLivenessEnabled() instead where
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  /// possible.
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  virtual bool enableSubRegLiveness() const { return false; }
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  /// This is called after a .mir file was loaded.
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  virtual void mirFileLoaded(MachineFunction &MF) const;
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};
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} // end namespace llvm
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#endif // LLVM_CODEGEN_TARGETSUBTARGETINFO_H