Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/IR/InlineAsm.h
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//===- llvm/InlineAsm.h - Class to represent inline asm strings -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This class represents the inline asm strings, which are Value*'s that are
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// used as the callee operand of call instructions.  InlineAsm's are uniqued
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// like constants, and created via InlineAsm::get(...).
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_IR_INLINEASM_H
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#define LLVM_IR_INLINEASM_H
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#include "llvm/ADT/StringRef.h"
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#include "llvm/IR/Value.h"
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#include <cassert>
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#include <string>
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#include <vector>
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namespace llvm {
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class FunctionType;
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class PointerType;
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template <class ConstantClass> class ConstantUniqueMap;
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class InlineAsm final : public Value {
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public:
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  enum AsmDialect {
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    AD_ATT,
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    AD_Intel
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  };
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private:
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  friend struct InlineAsmKeyType;
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  friend class ConstantUniqueMap<InlineAsm>;
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  std::string AsmString, Constraints;
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  FunctionType *FTy;
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  bool HasSideEffects;
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  bool IsAlignStack;
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  AsmDialect Dialect;
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  InlineAsm(FunctionType *Ty, const std::string &AsmString,
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            const std::string &Constraints, bool hasSideEffects,
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            bool isAlignStack, AsmDialect asmDialect);
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  /// When the ConstantUniqueMap merges two types and makes two InlineAsms
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  /// identical, it destroys one of them with this method.
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  void destroyConstant();
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public:
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  InlineAsm(const InlineAsm &) = delete;
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  InlineAsm &operator=(const InlineAsm &) = delete;
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  /// InlineAsm::get - Return the specified uniqued inline asm string.
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  ///
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  static InlineAsm *get(FunctionType *Ty, StringRef AsmString,
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                        StringRef Constraints, bool hasSideEffects,
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                        bool isAlignStack = false,
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                        AsmDialect asmDialect = AD_ATT);
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59.5k
  bool hasSideEffects() const { return HasSideEffects; }
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38.8k
  bool isAlignStack() const { return IsAlignStack; }
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38.8k
  AsmDialect getDialect() const { return Dialect; }
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  /// getType - InlineAsm's are always pointers.
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  ///
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16.8k
  PointerType *getType() const {
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16.8k
    return reinterpret_cast<PointerType*>(Value::getType());
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16.8k
  }
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  /// getFunctionType - InlineAsm's are always pointers to functions.
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  ///
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  FunctionType *getFunctionType() const;
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  const std::string &getAsmString() const { return AsmString; }
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17.9k
  const std::string &getConstraintString() const { return Constraints; }
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  /// Verify - This static method can be used by the parser to check to see if
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  /// the specified constraint string is legal for the type.  This returns true
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  /// if legal, false if not.
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  ///
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  static bool Verify(FunctionType *Ty, StringRef Constraints);
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  // Constraint String Parsing
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  enum ConstraintPrefix {
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    isInput,            // 'x'
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    isOutput,           // '=x'
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    isClobber           // '~x'
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  };
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  using ConstraintCodeVector = std::vector<std::string>;
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  struct SubConstraintInfo {
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    /// MatchingInput - If this is not -1, this is an output constraint where an
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    /// input constraint is required to match it (e.g. "0").  The value is the
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    /// constraint number that matches this one (for example, if this is
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    /// constraint #0 and constraint #4 has the value "0", this will be 4).
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    int MatchingInput = -1;
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    /// Code - The constraint code, either the register name (in braces) or the
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    /// constraint letter/number.
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    ConstraintCodeVector Codes;
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    /// Default constructor.
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2.35k
    SubConstraintInfo() = default;
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  };
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  using SubConstraintInfoVector = std::vector<SubConstraintInfo>;
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  struct ConstraintInfo;
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  using ConstraintInfoVector = std::vector<ConstraintInfo>;
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  struct ConstraintInfo {
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    /// Type - The basic type of the constraint: input/output/clobber
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    ///
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    ConstraintPrefix Type = isInput;
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    /// isEarlyClobber - "&": output operand writes result before inputs are all
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    /// read.  This is only ever set for an output operand.
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    bool isEarlyClobber = false;
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    /// MatchingInput - If this is not -1, this is an output constraint where an
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    /// input constraint is required to match it (e.g. "0").  The value is the
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    /// constraint number that matches this one (for example, if this is
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    /// constraint #0 and constraint #4 has the value "0", this will be 4).
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    int MatchingInput = -1;
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    /// hasMatchingInput - Return true if this is an output constraint that has
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    /// a matching input constraint.
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    bool hasMatchingInput() const { return MatchingInput != -1; }
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    /// isCommutative - This is set to true for a constraint that is commutative
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    /// with the next operand.
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    bool isCommutative = false;
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    /// isIndirect - True if this operand is an indirect operand.  This means
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    /// that the address of the source or destination is present in the call
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    /// instruction, instead of it being returned or passed in explicitly.  This
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    /// is represented with a '*' in the asm string.
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    bool isIndirect = false;
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    /// Code - The constraint code, either the register name (in braces) or the
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    /// constraint letter/number.
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    ConstraintCodeVector Codes;
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    /// isMultipleAlternative - '|': has multiple-alternative constraints.
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    bool isMultipleAlternative = false;
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    /// multipleAlternatives - If there are multiple alternative constraints,
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    /// this array will contain them.  Otherwise it will be empty.
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    SubConstraintInfoVector multipleAlternatives;
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    /// The currently selected alternative constraint index.
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    unsigned currentAlternativeIndex = 0;
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    /// Default constructor.
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    ConstraintInfo() = default;
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    /// Parse - Analyze the specified string (e.g. "=*&{eax}") and fill in the
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    /// fields in this structure.  If the constraint string is not understood,
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    /// return true, otherwise return false.
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    bool Parse(StringRef Str, ConstraintInfoVector &ConstraintsSoFar);
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    /// selectAlternative - Point this constraint to the alternative constraint
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    /// indicated by the index.
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    void selectAlternative(unsigned index);
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  };
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  /// ParseConstraints - Split up the constraint string into the specific
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  /// constraints and their prefixes.  If this returns an empty vector, and if
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  /// the constraint string itself isn't empty, there was an error parsing.
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  static ConstraintInfoVector ParseConstraints(StringRef ConstraintString);
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  /// ParseConstraints - Parse the constraints of this inlineasm object,
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  /// returning them the same way that ParseConstraints(str) does.
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  ConstraintInfoVector ParseConstraints() const {
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    return ParseConstraints(Constraints);
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  }
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  // Methods for support type inquiry through isa, cast, and dyn_cast:
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  static bool classof(const Value *V) {
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    return V->getValueID() == Value::InlineAsmVal;
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  }
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  // These are helper methods for dealing with flags in the INLINEASM SDNode
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  // in the backend.
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  //
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  // The encoding of the flag word is currently:
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  //   Bits 2-0 - A Kind_* value indicating the kind of the operand.
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  //   Bits 15-3 - The number of SDNode operands associated with this inline
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  //               assembly operand.
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  //   If bit 31 is set:
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  //     Bit 30-16 - The operand number that this operand must match.
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  //                 When bits 2-0 are Kind_Mem, the Constraint_* value must be
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  //                 obtained from the flags for this operand number.
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  //   Else if bits 2-0 are Kind_Mem:
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  //     Bit 30-16 - A Constraint_* value indicating the original constraint
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  //                 code.
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  //   Else:
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  //     Bit 30-16 - The register class ID to use for the operand.
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  enum : uint32_t {
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    // Fixed operands on an INLINEASM SDNode.
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    Op_InputChain = 0,
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    Op_AsmString = 1,
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    Op_MDNode = 2,
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    Op_ExtraInfo = 3,    // HasSideEffects, IsAlignStack, AsmDialect.
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    Op_FirstOperand = 4,
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    // Fixed operands on an INLINEASM MachineInstr.
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    MIOp_AsmString = 0,
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    MIOp_ExtraInfo = 1,    // HasSideEffects, IsAlignStack, AsmDialect.
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    MIOp_FirstOperand = 2,
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    // Interpretation of the MIOp_ExtraInfo bit field.
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    Extra_HasSideEffects = 1,
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    Extra_IsAlignStack = 2,
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    Extra_AsmDialect = 4,
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    Extra_MayLoad = 8,
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    Extra_MayStore = 16,
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    Extra_IsConvergent = 32,
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    // Inline asm operands map to multiple SDNode / MachineInstr operands.
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    // The first operand is an immediate describing the asm operand, the low
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    // bits is the kind:
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    Kind_RegUse = 1,             // Input register, "r".
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    Kind_RegDef = 2,             // Output register, "=r".
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    Kind_RegDefEarlyClobber = 3, // Early-clobber output register, "=&r".
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    Kind_Clobber = 4,            // Clobbered register, "~r".
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    Kind_Imm = 5,                // Immediate.
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    Kind_Mem = 6,                // Memory operand, "m".
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    // Memory constraint codes.
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    // These could be tablegenerated but there's little need to do that since
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    // there's plenty of space in the encoding to support the union of all
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    // constraint codes for all targets.
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    Constraint_Unknown = 0,
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    Constraint_es,
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    Constraint_i,
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    Constraint_m,
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    Constraint_o,
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    Constraint_v,
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    Constraint_Q,
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    Constraint_R,
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    Constraint_S,
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    Constraint_T,
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    Constraint_Um,
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    Constraint_Un,
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    Constraint_Uq,
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    Constraint_Us,
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    Constraint_Ut,
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    Constraint_Uv,
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    Constraint_Uy,
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    Constraint_X,
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    Constraint_Z,
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    Constraint_ZC,
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    Constraint_Zy,
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    Constraints_Max = Constraint_Zy,
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    Constraints_ShiftAmount = 16,
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    Flag_MatchingOperand = 0x80000000
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  };
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  static unsigned getFlagWord(unsigned Kind, unsigned NumOps) {
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    assert(((NumOps << 3) & ~0xffff) == 0 && "Too many inline asm operands!");
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    assert(Kind >= Kind_RegUse && Kind <= Kind_Mem && "Invalid Kind");
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    return Kind | (NumOps << 3);
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  }
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  static bool isRegDefKind(unsigned Flag){ return getKind(Flag) == Kind_RegDef;}
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0
  static bool isImmKind(unsigned Flag) { return getKind(Flag) == Kind_Imm; }
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  static bool isMemKind(unsigned Flag) { return getKind(Flag) == Kind_Mem; }
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  static bool isRegDefEarlyClobberKind(unsigned Flag) {
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    return getKind(Flag) == Kind_RegDefEarlyClobber;
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  }
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  static bool isClobberKind(unsigned Flag) {
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    return getKind(Flag) == Kind_Clobber;
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  }
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  /// getFlagWordForMatchingOp - Augment an existing flag word returned by
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  /// getFlagWord with information indicating that this input operand is tied
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  /// to a previous output operand.
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  static unsigned getFlagWordForMatchingOp(unsigned InputFlag,
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                                           unsigned MatchedOperandNo) {
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    assert(MatchedOperandNo <= 0x7fff && "Too big matched operand");
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    assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
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    return InputFlag | Flag_MatchingOperand | (MatchedOperandNo << 16);
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  }
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  /// getFlagWordForRegClass - Augment an existing flag word returned by
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  /// getFlagWord with the required register class for the following register
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  /// operands.
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  /// A tied use operand cannot have a register class, use the register class
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  /// from the def operand instead.
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  static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC) {
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    // Store RC + 1, reserve the value 0 to mean 'no register class'.
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    ++RC;
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    assert(!isImmKind(InputFlag) && "Immediates cannot have a register class");
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    assert(!isMemKind(InputFlag) && "Memory operand cannot have a register class");
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    assert(RC <= 0x7fff && "Too large register class ID");
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    assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
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    return InputFlag | (RC << 16);
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  }
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  /// Augment an existing flag word returned by getFlagWord with the constraint
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  /// code for a memory constraint.
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  static unsigned getFlagWordForMem(unsigned InputFlag, unsigned Constraint) {
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    assert(isMemKind(InputFlag) && "InputFlag is not a memory constraint!");
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    assert(Constraint <= 0x7fff && "Too large a memory constraint ID");
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    assert(Constraint <= Constraints_Max && "Unknown constraint ID");
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    assert((InputFlag & ~0xffff) == 0 && "High bits already contain data");
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    return InputFlag | (Constraint << Constraints_ShiftAmount);
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  }
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  static unsigned convertMemFlagWordToMatchingFlagWord(unsigned InputFlag) {
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    assert(isMemKind(InputFlag));
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    return InputFlag & ~(0x7fff << Constraints_ShiftAmount);
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  }
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274k
  static unsigned getKind(unsigned Flags) {
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    return Flags & 7;
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  }
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  static unsigned getMemoryConstraintID(unsigned Flag) {
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    assert(isMemKind(Flag));
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    return (Flag >> Constraints_ShiftAmount) & 0x7fff;
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  }
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  /// getNumOperandRegisters - Extract the number of registers field from the
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  /// inline asm operand flag.
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2.79M
  static unsigned getNumOperandRegisters(unsigned Flag) {
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2.79M
    return (Flag & 0xffff) >> 3;
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2.79M
  }
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  /// isUseOperandTiedToDef - Return true if the flag of the inline asm
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  /// operand indicates it is an use operand that's matched to a def operand.
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1.61M
  static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx) {
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    if ((Flag & Flag_MatchingOperand) == 0)
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1.05M
      return false;
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562k
    Idx = (Flag & ~Flag_MatchingOperand) >> 16;
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562k
    return true;
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562k
  }
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  /// hasRegClassConstraint - Returns true if the flag contains a register
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  /// class constraint.  Sets RC to the register class ID.
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2.06k
  static bool hasRegClassConstraint(unsigned Flag, unsigned &RC) {
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2.06k
    if (Flag & Flag_MatchingOperand)
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      return false;
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1.93k
    unsigned High = Flag >> 16;
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1.93k
    // getFlagWordForRegClass() uses 0 to mean no register class, and otherwise
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    // stores RC + 1.
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1.93k
    if (!High)
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      return false;
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1.67k
    RC = High - 1;
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1.67k
    return true;
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  }
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};
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} // end namespace llvm
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#endif // LLVM_IR_INLINEASM_H