Coverage Report

Created: 2019-02-20 07:29

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/MC/MCInstrDesc.h
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//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
8
//
9
// This file defines the MCOperandInfo and MCInstrDesc classes, which
10
// are used to describe target instructions and their operands.
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//
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//===----------------------------------------------------------------------===//
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14
#ifndef LLVM_MC_MCINSTRDESC_H
15
#define LLVM_MC_MCINSTRDESC_H
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/DataTypes.h"
19
#include <string>
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namespace llvm {
22
  class MCInst;
23
  class MCSubtargetInfo;
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  class FeatureBitset;
25
26
//===----------------------------------------------------------------------===//
27
// Machine Operand Flags and Description
28
//===----------------------------------------------------------------------===//
29
30
namespace MCOI {
31
// Operand constraints
32
enum OperandConstraint {
33
  TIED_TO = 0,  // Must be allocated the same register as.
34
  EARLY_CLOBBER // Operand is an early clobber register operand
35
};
36
37
/// These are flags set on operands, but should be considered
38
/// private, all access should go through the MCOperandInfo accessors.
39
/// See the accessors for a description of what these are.
40
enum OperandFlags { LookupPtrRegClass = 0, Predicate, OptionalDef };
41
42
/// Operands are tagged with one of the values of this enum.
43
enum OperandType {
44
  OPERAND_UNKNOWN = 0,
45
  OPERAND_IMMEDIATE = 1,
46
  OPERAND_REGISTER = 2,
47
  OPERAND_MEMORY = 3,
48
  OPERAND_PCREL = 4,
49
50
  OPERAND_FIRST_GENERIC = 6,
51
  OPERAND_GENERIC_0 = 6,
52
  OPERAND_GENERIC_1 = 7,
53
  OPERAND_GENERIC_2 = 8,
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  OPERAND_GENERIC_3 = 9,
55
  OPERAND_GENERIC_4 = 10,
56
  OPERAND_GENERIC_5 = 11,
57
  OPERAND_LAST_GENERIC = 11,
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59
  OPERAND_FIRST_TARGET = 12,
60
};
61
62
}
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64
/// This holds information about one operand of a machine instruction,
65
/// indicating the register class for register operands, etc.
66
class MCOperandInfo {
67
public:
68
  /// This specifies the register class enumeration of the operand
69
  /// if the operand is a register.  If isLookupPtrRegClass is set, then this is
70
  /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
71
  /// get a dynamic register class.
72
  int16_t RegClass;
73
74
  /// These are flags from the MCOI::OperandFlags enum.
75
  uint8_t Flags;
76
77
  /// Information about the type of the operand.
78
  uint8_t OperandType;
79
  /// The lower 16 bits are used to specify which constraints are set.
80
  /// The higher 16 bits are used to specify the value of constraints (4 bits
81
  /// each).
82
  uint32_t Constraints;
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84
  /// Set if this operand is a pointer value and it requires a callback
85
  /// to look up its register class.
86
78.6M
  bool isLookupPtrRegClass() const {
87
78.6M
    return Flags & (1 << MCOI::LookupPtrRegClass);
88
78.6M
  }
89
90
  /// Set if this is one of the operands that made up of the predicate
91
  /// operand that controls an isPredicable() instruction.
92
33.2M
  bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
93
94
  /// Set if this operand is a optional def.
95
10.9M
  bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
96
97
32.2M
  bool isGenericType() const {
98
32.2M
    return OperandType >= MCOI::OPERAND_FIRST_GENERIC &&
99
32.2M
           
OperandType <= MCOI::OPERAND_LAST_GENERIC26.0M
;
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32.2M
  }
101
102
26.1M
  unsigned getGenericTypeIndex() const {
103
26.1M
    assert(isGenericType() && "non-generic types don't have an index");
104
26.1M
    return OperandType - MCOI::OPERAND_FIRST_GENERIC;
105
26.1M
  }
106
};
107
108
//===----------------------------------------------------------------------===//
109
// Machine Instruction Flags and Description
110
//===----------------------------------------------------------------------===//
111
112
namespace MCID {
113
/// These should be considered private to the implementation of the
114
/// MCInstrDesc class.  Clients should use the predicate methods on MCInstrDesc,
115
/// not use these directly.  These all correspond to bitfields in the
116
/// MCInstrDesc::Flags field.
117
enum Flag {
118
  Variadic = 0,
119
  HasOptionalDef,
120
  Pseudo,
121
  Return,
122
  EHScopeReturn,
123
  Call,
124
  Barrier,
125
  Terminator,
126
  Branch,
127
  IndirectBranch,
128
  Compare,
129
  MoveImm,
130
  MoveReg,
131
  Bitcast,
132
  Select,
133
  DelaySlot,
134
  FoldableAsLoad,
135
  MayLoad,
136
  MayStore,
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  Predicable,
138
  NotDuplicable,
139
  UnmodeledSideEffects,
140
  Commutable,
141
  ConvertibleTo3Addr,
142
  UsesCustomInserter,
143
  HasPostISelHook,
144
  Rematerializable,
145
  CheapAsAMove,
146
  ExtraSrcRegAllocReq,
147
  ExtraDefRegAllocReq,
148
  RegSequence,
149
  ExtractSubreg,
150
  InsertSubreg,
151
  Convergent,
152
  Add,
153
  Trap,
154
  VariadicOpsAreDefs,
155
};
156
}
157
158
/// Describe properties that are true of each instruction in the target
159
/// description file.  This captures information about side effects, register
160
/// use and many other things.  There is one instance of this struct for each
161
/// target instruction class, and the MachineInstr class points to this struct
162
/// directly to describe itself.
163
class MCInstrDesc {
164
public:
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  unsigned short Opcode;         // The opcode number
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  unsigned short NumOperands;    // Num of args (may be more if variable_ops)
167
  unsigned char NumDefs;         // Num of args that are definitions
168
  unsigned char Size;            // Number of bytes in encoding.
169
  unsigned short SchedClass;     // enum identifying instr sched class
170
  uint64_t Flags;                // Flags identifying machine instr class
171
  uint64_t TSFlags;              // Target Specific Flag values
172
  const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr
173
  const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
174
  const MCOperandInfo *OpInfo;   // 'NumOperands' entries about operands
175
  // Subtarget feature that this is deprecated on, if any
176
  // -1 implies this is not deprecated by any single feature. It may still be
177
  // deprecated due to a "complex" reason, below.
178
  int64_t DeprecatedFeature;
179
180
  // A complex method to determine if a certain instruction is deprecated or
181
  // not, and return the reason for deprecation.
182
  bool (*ComplexDeprecationInfo)(MCInst &, const MCSubtargetInfo &,
183
                                 std::string &);
184
185
  /// Returns the value of the specific constraint if
186
  /// it is set. Returns -1 if it is not set.
187
  int getOperandConstraint(unsigned OpNum,
188
280M
                           MCOI::OperandConstraint Constraint) const {
189
280M
    if (OpNum < NumOperands &&
190
280M
        
(OpInfo[OpNum].Constraints & (1 << Constraint))274M
) {
191
4.44M
      unsigned Pos = 16 + Constraint * 4;
192
4.44M
      return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
193
4.44M
    }
194
276M
    return -1;
195
276M
  }
196
197
  /// Returns true if a certain instruction is deprecated and if so
198
  /// returns the reason in \p Info.
199
  bool getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI,
200
                         std::string &Info) const;
201
202
  /// Return the opcode number for this descriptor.
203
287M
  unsigned getOpcode() const { return Opcode; }
204
205
  /// Return the number of declared MachineOperands for this
206
  /// MachineInstruction.  Note that variadic (isVariadic() returns true)
207
  /// instructions may have additional operands at the end of the list, and note
208
  /// that the machine instruction may include implicit register def/uses as
209
  /// well.
210
601M
  unsigned getNumOperands() const { return NumOperands; }
211
212
  using const_opInfo_iterator = const MCOperandInfo *;
213
214
8.54k
  const_opInfo_iterator opInfo_begin() const { return OpInfo; }
215
2
  const_opInfo_iterator opInfo_end() const { return OpInfo + NumOperands; }
216
217
2
  iterator_range<const_opInfo_iterator> operands() const {
218
2
    return make_range(opInfo_begin(), opInfo_end());
219
2
  }
220
221
  /// Return the number of MachineOperands that are register
222
  /// definitions.  Register definitions always occur at the start of the
223
  /// machine operand list.  This is the number of "outs" in the .td file,
224
  /// and does not include implicit defs.
225
239M
  unsigned getNumDefs() const { return NumDefs; }
226
227
  /// Return flags of this instruction.
228
2.56G
  uint64_t getFlags() const { return Flags; }
229
230
  /// Return true if this instruction can have a variable number of
231
  /// operands.  In this case, the variable operands will be after the normal
232
  /// operands but before the implicit definitions and uses (if any are
233
  /// present).
234
162M
  bool isVariadic() const { return Flags & (1ULL << MCID::Variadic); }
235
236
  /// Set if this instruction has an optional definition, e.g.
237
  /// ARM instructions which can set condition code if 's' bit is set.
238
8.08M
  bool hasOptionalDef() const { return Flags & (1ULL << MCID::HasOptionalDef); }
239
240
  /// Return true if this is a pseudo instruction that doesn't
241
  /// correspond to a real machine instruction.
242
4.05k
  bool isPseudo() const { return Flags & (1ULL << MCID::Pseudo); }
243
244
  /// Return true if the instruction is a return.
245
591k
  bool isReturn() const { return Flags & (1ULL << MCID::Return); }
246
247
  /// Return true if the instruction is an add instruction.
248
1.57k
  bool isAdd() const { return Flags & (1ULL << MCID::Add); }
249
250
  /// Return true if this instruction is a trap.
251
  bool isTrap() const { return Flags & (1ULL << MCID::Trap); }
252
253
  /// Return true if the instruction is a register to register move.
254
0
  bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); }
255
256
  ///  Return true if the instruction is a call.
257
14.4M
  bool isCall() const { return Flags & (1ULL << MCID::Call); }
258
259
  /// Returns true if the specified instruction stops control flow
260
  /// from executing the instruction immediately following it.  Examples include
261
  /// unconditional branches and return instructions.
262
380k
  bool isBarrier() const { return Flags & (1ULL << MCID::Barrier); }
263
264
  /// Returns true if this instruction part of the terminator for
265
  /// a basic block.  Typically this is things like return and branch
266
  /// instructions.
267
  ///
268
  /// Various passes use this to insert code into the bottom of a basic block,
269
  /// but before control flow occurs.
270
138k
  bool isTerminator() const { return Flags & (1ULL << MCID::Terminator); }
271
272
  /// Returns true if this is a conditional, unconditional, or
273
  /// indirect branch.  Predicates below can be used to discriminate between
274
  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
275
  /// get more information.
276
438k
  bool isBranch() const { return Flags & (1ULL << MCID::Branch); }
277
278
  /// Return true if this is an indirect branch, such as a
279
  /// branch through a register.
280
384k
  bool isIndirectBranch() const { return Flags & (1ULL << MCID::IndirectBranch); }
281
282
  /// Return true if this is a branch which may fall
283
  /// through to the next instruction or may transfer control flow to some other
284
  /// block.  The TargetInstrInfo::AnalyzeBranch method can be used to get more
285
  /// information about this branch.
286
187k
  bool isConditionalBranch() const {
287
187k
    return isBranch() & !isBarrier() & !isIndirectBranch();
288
187k
  }
289
290
  /// Return true if this is a branch which always
291
  /// transfers control flow to some other block.  The
292
  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
293
  /// about this branch.
294
193k
  bool isUnconditionalBranch() const {
295
193k
    return isBranch() & isBarrier() & !isIndirectBranch();
296
193k
  }
297
298
  /// Return true if this is a branch or an instruction which directly
299
  /// writes to the program counter. Considered 'may' affect rather than
300
  /// 'does' affect as things like predication are not taken into account.
301
  bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
302
303
  /// Return true if this instruction has a predicate operand
304
  /// that controls execution. It may be set to 'always', or may be set to other
305
  /// values. There are various methods in TargetInstrInfo that can be used to
306
  /// control and modify the predicate in this instruction.
307
13.3M
  bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); }
308
309
  /// Return true if this instruction is a comparison.
310
0
  bool isCompare() const { return Flags & (1ULL << MCID::Compare); }
311
312
  /// Return true if this instruction is a move immediate
313
  /// (including conditional moves) instruction.
314
0
  bool isMoveImmediate() const { return Flags & (1ULL << MCID::MoveImm); }
315
316
  /// Return true if this instruction is a bitcast instruction.
317
0
  bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); }
318
319
  /// Return true if this is a select instruction.
320
0
  bool isSelect() const { return Flags & (1ULL << MCID::Select); }
321
322
  /// Return true if this instruction cannot be safely
323
  /// duplicated.  For example, if the instruction has a unique labels attached
324
  /// to it, duplicating it would cause multiple definition errors.
325
0
  bool isNotDuplicable() const { return Flags & (1ULL << MCID::NotDuplicable); }
326
327
  /// Returns true if the specified instruction has a delay slot which
328
  /// must be filled by the code generator.
329
36.4k
  bool hasDelaySlot() const { return Flags & (1ULL << MCID::DelaySlot); }
330
331
  /// Return true for instructions that can be folded as memory operands
332
  /// in other instructions. The most common use for this is instructions that
333
  /// are simple loads from memory that don't modify the loaded value in any
334
  /// way, but it can also be used for instructions that can be expressed as
335
  /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be
336
  /// folded when it is beneficial.  This should only be set on instructions
337
  /// that return a value in their only virtual register definition.
338
0
  bool canFoldAsLoad() const { return Flags & (1ULL << MCID::FoldableAsLoad); }
339
340
  /// Return true if this instruction behaves
341
  /// the same way as the generic REG_SEQUENCE instructions.
342
  /// E.g., on ARM,
343
  /// dX VMOVDRR rY, rZ
344
  /// is equivalent to
345
  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
346
  ///
347
  /// Note that for the optimizers to be able to take advantage of
348
  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
349
  /// override accordingly.
350
0
  bool isRegSequenceLike() const { return Flags & (1ULL << MCID::RegSequence); }
351
352
  /// Return true if this instruction behaves
353
  /// the same way as the generic EXTRACT_SUBREG instructions.
354
  /// E.g., on ARM,
355
  /// rX, rY VMOVRRD dZ
356
  /// is equivalent to two EXTRACT_SUBREG:
357
  /// rX = EXTRACT_SUBREG dZ, ssub_0
358
  /// rY = EXTRACT_SUBREG dZ, ssub_1
359
  ///
360
  /// Note that for the optimizers to be able to take advantage of
361
  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
362
  /// override accordingly.
363
0
  bool isExtractSubregLike() const {
364
0
    return Flags & (1ULL << MCID::ExtractSubreg);
365
0
  }
366
367
  /// Return true if this instruction behaves
368
  /// the same way as the generic INSERT_SUBREG instructions.
369
  /// E.g., on ARM,
370
  /// dX = VSETLNi32 dY, rZ, Imm
371
  /// is equivalent to a INSERT_SUBREG:
372
  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
373
  ///
374
  /// Note that for the optimizers to be able to take advantage of
375
  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
376
  /// override accordingly.
377
0
  bool isInsertSubregLike() const { return Flags & (1ULL << MCID::InsertSubreg); }
378
379
380
  /// Return true if this instruction is convergent.
381
  ///
382
  /// Convergent instructions may not be made control-dependent on any
383
  /// additional values.
384
0
  bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); }
385
386
  /// Return true if variadic operands of this instruction are definitions.
387
1.94k
  bool variadicOpsAreDefs() const {
388
1.94k
    return Flags & (1ULL << MCID::VariadicOpsAreDefs);
389
1.94k
  }
390
391
  //===--------------------------------------------------------------------===//
392
  // Side Effect Analysis
393
  //===--------------------------------------------------------------------===//
394
395
  /// Return true if this instruction could possibly read memory.
396
  /// Instructions with this flag set are not necessarily simple load
397
  /// instructions, they may load a value and modify it, for example.
398
11.9M
  bool mayLoad() const { return Flags & (1ULL << MCID::MayLoad); }
399
400
  /// Return true if this instruction could possibly modify memory.
401
  /// Instructions with this flag set are not necessarily simple store
402
  /// instructions, they may store a modified value based on their operands, or
403
  /// may not actually modify anything, for example.
404
2.17M
  bool mayStore() const { return Flags & (1ULL << MCID::MayStore); }
405
406
  /// Return true if this instruction has side
407
  /// effects that are not modeled by other flags.  This does not return true
408
  /// for instructions whose effects are captured by:
409
  ///
410
  ///  1. Their operand list and implicit definition/use list.  Register use/def
411
  ///     info is explicit for instructions.
412
  ///  2. Memory accesses.  Use mayLoad/mayStore.
413
  ///  3. Calling, branching, returning: use isCall/isReturn/isBranch.
414
  ///
415
  /// Examples of side effects would be modifying 'invisible' machine state like
416
  /// a control register, flushing a cache, modifying a register invisible to
417
  /// LLVM, etc.
418
  bool hasUnmodeledSideEffects() const {
419
    return Flags & (1ULL << MCID::UnmodeledSideEffects);
420
  }
421
422
  //===--------------------------------------------------------------------===//
423
  // Flags that indicate whether an instruction can be modified by a method.
424
  //===--------------------------------------------------------------------===//
425
426
  /// Return true if this may be a 2- or 3-address instruction (of the
427
  /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are
428
  /// exchanged.  If this flag is set, then the
429
  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
430
  /// instruction.
431
  ///
432
  /// Note that this flag may be set on instructions that are only commutable
433
  /// sometimes.  In these cases, the call to commuteInstruction will fail.
434
  /// Also note that some instructions require non-trivial modification to
435
  /// commute them.
436
9.90M
  bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); }
437
438
  /// Return true if this is a 2-address instruction which can be changed
439
  /// into a 3-address instruction if needed.  Doing this transformation can be
440
  /// profitable in the register allocator, because it means that the
441
  /// instruction can use a 2-address form if possible, but degrade into a less
442
  /// efficient form if the source and dest register cannot be assigned to the
443
  /// same register.  For example, this allows the x86 backend to turn a "shl
444
  /// reg, 3" instruction into an LEA instruction, which is the same speed as
445
  /// the shift but has bigger code size.
446
  ///
447
  /// If this returns true, then the target must implement the
448
  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
449
  /// is allowed to fail if the transformation isn't valid for this specific
450
  /// instruction (e.g. shl reg, 4 on x86).
451
  ///
452
0
  bool isConvertibleTo3Addr() const {
453
0
    return Flags & (1ULL << MCID::ConvertibleTo3Addr);
454
0
  }
455
456
  /// Return true if this instruction requires custom insertion support
457
  /// when the DAG scheduler is inserting it into a machine basic block.  If
458
  /// this is true for the instruction, it basically means that it is a pseudo
459
  /// instruction used at SelectionDAG time that is expanded out into magic code
460
  /// by the target when MachineInstrs are formed.
461
  ///
462
  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
463
  /// is used to insert this into the MachineBasicBlock.
464
0
  bool usesCustomInsertionHook() const {
465
0
    return Flags & (1ULL << MCID::UsesCustomInserter);
466
0
  }
467
468
  /// Return true if this instruction requires *adjustment* after
469
  /// instruction selection by calling a target hook. For example, this can be
470
  /// used to fill in ARM 's' optional operand depending on whether the
471
  /// conditional flag register is used.
472
8.29M
  bool hasPostISelHook() const { return Flags & (1ULL << MCID::HasPostISelHook); }
473
474
  /// Returns true if this instruction is a candidate for remat. This
475
  /// flag is only used in TargetInstrInfo method isTriviallyRematerializable.
476
  ///
477
  /// If this flag is set, the isReallyTriviallyReMaterializable()
478
  /// or isReallyTriviallyReMaterializableGeneric methods are called to verify
479
  /// the instruction is really rematable.
480
6.76M
  bool isRematerializable() const {
481
6.76M
    return Flags & (1ULL << MCID::Rematerializable);
482
6.76M
  }
483
484
  /// Returns true if this instruction has the same cost (or less) than a
485
  /// move instruction. This is useful during certain types of optimizations
486
  /// (e.g., remat during two-address conversion or machine licm) where we would
487
  /// like to remat or hoist the instruction, but not if it costs more than
488
  /// moving the instruction into the appropriate register. Note, we are not
489
  /// marking copies from and to the same register class with this flag.
490
  ///
491
  /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
492
  /// for different subtargets.
493
0
  bool isAsCheapAsAMove() const { return Flags & (1ULL << MCID::CheapAsAMove); }
494
495
  /// Returns true if this instruction source operands have special
496
  /// register allocation requirements that are not captured by the operand
497
  /// register classes. e.g. ARM::STRD's two source registers must be an even /
498
  /// odd pair, ARM::STM registers have to be in ascending order.  Post-register
499
  /// allocation passes should not attempt to change allocations for sources of
500
  /// instructions with this flag.
501
0
  bool hasExtraSrcRegAllocReq() const {
502
0
    return Flags & (1ULL << MCID::ExtraSrcRegAllocReq);
503
0
  }
504
505
  /// Returns true if this instruction def operands have special register
506
  /// allocation requirements that are not captured by the operand register
507
  /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
508
  /// ARM::LDM registers have to be in ascending order.  Post-register
509
  /// allocation passes should not attempt to change allocations for definitions
510
  /// of instructions with this flag.
511
0
  bool hasExtraDefRegAllocReq() const {
512
0
    return Flags & (1ULL << MCID::ExtraDefRegAllocReq);
513
0
  }
514
515
  /// Return a list of registers that are potentially read by any
516
  /// instance of this machine instruction.  For example, on X86, the "adc"
517
  /// instruction adds two register operands and adds the carry bit in from the
518
  /// flags register.  In this case, the instruction is marked as implicitly
519
  /// reading the flags.  Likewise, the variable shift instruction on X86 is
520
  /// marked as implicitly reading the 'CL' register, which it always does.
521
  ///
522
  /// This method returns null if the instruction has no implicit uses.
523
13.1M
  const MCPhysReg *getImplicitUses() const { return ImplicitUses; }
524
525
  /// Return the number of implicit uses this instruction has.
526
68.4M
  unsigned getNumImplicitUses() const {
527
68.4M
    if (!ImplicitUses)
528
55.9M
      return 0;
529
12.4M
    unsigned i = 0;
530
25.6M
    for (; ImplicitUses[i]; 
++i13.1M
) /*empty*/
531
13.1M
      ;
532
12.4M
    return i;
533
12.4M
  }
534
535
  /// Return a list of registers that are potentially written by any
536
  /// instance of this machine instruction.  For example, on X86, many
537
  /// instructions implicitly set the flags register.  In this case, they are
538
  /// marked as setting the FLAGS.  Likewise, many instructions always deposit
539
  /// their result in a physical register.  For example, the X86 divide
540
  /// instruction always deposits the quotient and remainder in the EAX/EDX
541
  /// registers.  For that instruction, this will return a list containing the
542
  /// EAX/EDX/EFLAGS registers.
543
  ///
544
  /// This method returns null if the instruction has no implicit defs.
545
29.2M
  const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; }
546
547
  /// Return the number of implicit defs this instruct has.
548
68.0M
  unsigned getNumImplicitDefs() const {
549
68.0M
    if (!ImplicitDefs)
550
60.1M
      return 0;
551
7.85M
    unsigned i = 0;
552
16.4M
    for (; ImplicitDefs[i]; 
++i8.62M
) /*empty*/
553
8.62M
      ;
554
7.85M
    return i;
555
7.85M
  }
556
557
  /// Return true if this instruction implicitly
558
  /// uses the specified physical register.
559
424k
  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
560
424k
    if (const MCPhysReg *ImpUses = ImplicitUses)
561
458k
      
for (; 378k
*ImpUses;
++ImpUses79.3k
)
562
395k
        if (*ImpUses == Reg)
563
315k
          return true;
564
424k
    
return false109k
;
565
424k
  }
566
567
  /// Return true if this instruction implicitly
568
  /// defines the specified physical register.
569
  bool hasImplicitDefOfPhysReg(unsigned Reg,
570
                               const MCRegisterInfo *MRI = nullptr) const;
571
572
  /// Return the scheduling class for this instruction.  The
573
  /// scheduling class is an index into the InstrItineraryData table.  This
574
  /// returns zero if there is no known scheduling information for the
575
  /// instruction.
576
201M
  unsigned getSchedClass() const { return SchedClass; }
577
578
  /// Return the number of bytes in the encoding of this instruction,
579
  /// or zero if the encoding size cannot be known from the opcode.
580
8.15M
  unsigned getSize() const { return Size; }
581
582
  /// Find the index of the first operand in the
583
  /// operand list that is used to represent the predicate. It returns -1 if
584
  /// none is found.
585
17.1k
  int findFirstPredOperandIdx() const {
586
17.1k
    if (isPredicable()) {
587
62.0k
      for (unsigned i = 0, e = getNumOperands(); i != e; 
++i44.9k
)
588
62.0k
        if (OpInfo[i].isPredicate())
589
17.1k
          return i;
590
17.1k
    }
591
17.1k
    
return -10
;
592
17.1k
  }
593
594
  /// Return true if this instruction defines the specified physical
595
  /// register, either explicitly or implicitly.
596
  bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
597
                       const MCRegisterInfo &RI) const;
598
};
599
600
} // end namespace llvm
601
602
#endif