Coverage Report

Created: 2018-09-17 19:50

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
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//===- llvm/MC/MCTargetAsmParser.h - Target Assembly Parser -----*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_MC_MCPARSER_MCTARGETASMPARSER_H
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#define LLVM_MC_MCPARSER_MCTARGETASMPARSER_H
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#include "llvm/ADT/StringRef.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCParser/MCAsmLexer.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/MC/MCParser/MCAsmParserExtension.h"
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#include "llvm/MC/MCTargetOptions.h"
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#include "llvm/Support/SMLoc.h"
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#include <cstdint>
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#include <memory>
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namespace llvm {
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class MCInst;
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class MCParsedAsmOperand;
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class MCStreamer;
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class MCSubtargetInfo;
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template <typename T> class SmallVectorImpl;
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using OperandVector = SmallVectorImpl<std::unique_ptr<MCParsedAsmOperand>>;
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enum AsmRewriteKind {
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  AOK_Align,          // Rewrite align as .align.
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  AOK_EVEN,           // Rewrite even as .even.
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  AOK_Emit,           // Rewrite _emit as .byte.
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  AOK_Input,          // Rewrite in terms of $N.
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  AOK_Output,         // Rewrite in terms of $N.
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  AOK_SizeDirective,  // Add a sizing directive (e.g., dword ptr).
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  AOK_Label,          // Rewrite local labels.
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  AOK_EndOfStatement, // Add EndOfStatement (e.g., "\n\t").
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  AOK_Skip,           // Skip emission (e.g., offset/type operators).
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  AOK_IntelExpr       // SizeDirective SymDisp [BaseReg + IndexReg * Scale + ImmDisp]
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};
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const char AsmRewritePrecedence [] = {
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  2, // AOK_Align
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  2, // AOK_EVEN
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  2, // AOK_Emit
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  3, // AOK_Input
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  3, // AOK_Output
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  5, // AOK_SizeDirective
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  1, // AOK_Label
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  5, // AOK_EndOfStatement
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  2, // AOK_Skip
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  2  // AOK_IntelExpr
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};
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// Represnt the various parts which makes up an intel expression,
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// used for emitting compound intel expressions
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0
struct IntelExpr {
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  bool NeedBracs;
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  int64_t Imm;
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  StringRef BaseReg;
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  StringRef IndexReg;
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  unsigned Scale;
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  IntelExpr(bool needBracs = false) : NeedBracs(needBracs), Imm(0),
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    BaseReg(StringRef()), IndexReg(StringRef()),
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743
    Scale(1) {}
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  // Compund immediate expression
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202
  IntelExpr(int64_t imm, bool needBracs) : IntelExpr(needBracs) {
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202
    Imm = imm;
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202
  }
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  // [Reg + ImmediateExpression]
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  // We don't bother to emit an immediate expression evaluated to zero
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  IntelExpr(StringRef reg, int64_t imm = 0, unsigned scale = 0,
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    bool needBracs = true) :
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202
    IntelExpr(imm, needBracs) {
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202
    IndexReg = reg;
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202
    if (scale)
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3
      Scale = scale;
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202
  }
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  // [BaseReg + IndexReg * ScaleExpression + ImmediateExpression]
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  IntelExpr(StringRef baseReg, StringRef indexReg, unsigned scale = 0,
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    int64_t imm = 0, bool needBracs = true) :
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202
    IntelExpr(indexReg, imm, scale, needBracs) {
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202
    BaseReg = baseReg;
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202
  }
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420
  bool hasBaseReg() const {
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420
    return BaseReg.size();
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420
  }
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366
  bool hasIndexReg() const {
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366
    return IndexReg.size();
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366
  }
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215
  bool hasRegs() const {
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215
    return hasBaseReg() || 
hasIndexReg()165
;
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215
  }
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0
  bool isValid() const {
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0
    return (Scale == 1) ||
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0
           (hasIndexReg() && (Scale == 2 || Scale == 4 || Scale == 8));
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0
  }
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};
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struct AsmRewrite {
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  AsmRewriteKind Kind;
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  SMLoc Loc;
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  unsigned Len;
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  int64_t Val;
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  StringRef Label;
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  IntelExpr IntelExp;
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public:
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  AsmRewrite(AsmRewriteKind kind, SMLoc loc, unsigned len = 0, int64_t val = 0)
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541
    : Kind(kind), Loc(loc), Len(len), Val(val) {}
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  AsmRewrite(AsmRewriteKind kind, SMLoc loc, unsigned len, StringRef label)
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    : AsmRewrite(kind, loc, len) { Label = label; }
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  AsmRewrite(SMLoc loc, unsigned len, IntelExpr exp)
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    : AsmRewrite(AOK_IntelExpr, loc, len) { IntelExp = exp; }
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};
122
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struct ParseInstructionInfo {
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  SmallVectorImpl<AsmRewrite> *AsmRewrites = nullptr;
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  ParseInstructionInfo() = default;
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  ParseInstructionInfo(SmallVectorImpl<AsmRewrite> *rewrites)
128
464k
    : AsmRewrites(rewrites) {}
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};
130
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enum OperandMatchResultTy {
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  MatchOperand_Success,  // operand matched successfully
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  MatchOperand_NoMatch,  // operand did not match
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  MatchOperand_ParseFail // operand matched but had errors
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};
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enum class DiagnosticPredicateTy {
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  Match,
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  NearMatch,
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  NoMatch,
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};
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// When an operand is parsed, the assembler will try to iterate through a set of
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// possible operand classes that the operand might match and call the
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// corresponding PredicateMethod to determine that.
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//
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// If there are two AsmOperands that would give a specific diagnostic if there
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// is no match, there is currently no mechanism to distinguish which operand is
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// a closer match. The DiagnosticPredicate distinguishes between 'completely
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// no match' and 'near match', so the assembler can decide whether to give a
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// specific diagnostic, or use 'InvalidOperand' and continue to find a
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// 'better matching' diagnostic.
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//
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// For example:
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//    opcode opnd0, onpd1, opnd2
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//
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// where:
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//    opnd2 could be an 'immediate of range [-8, 7]'
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//    opnd2 could be a  'register + shift/extend'.
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//
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// If opnd2 is a valid register, but with a wrong shift/extend suffix, it makes
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// little sense to give a diagnostic that the operand should be an immediate
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// in range [-8, 7].
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//
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// This is a light-weight alternative to the 'NearMissInfo' approach
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// below which collects *all* possible diagnostics. This alternative
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// is optional and fully backward compatible with existing
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// PredicateMethods that return a 'bool' (match or no match).
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struct DiagnosticPredicate {
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  DiagnosticPredicateTy Type;
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  explicit DiagnosticPredicate(bool Match)
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      : Type(Match ? DiagnosticPredicateTy::Match
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2.38M
                   : DiagnosticPredicateTy::NearMatch) {}
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344k
  DiagnosticPredicate(DiagnosticPredicateTy T) : Type(T) {}
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  DiagnosticPredicate(const DiagnosticPredicate &) = default;
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4.37k
  operator bool() const { return Type == DiagnosticPredicateTy::Match; }
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2.72M
  bool isMatch() const { return Type == DiagnosticPredicateTy::Match; }
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260k
  bool isNearMatch() const { return Type == DiagnosticPredicateTy::NearMatch; }
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0
  bool isNoMatch() const { return Type == DiagnosticPredicateTy::NoMatch; }
182
};
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// When matching of an assembly instruction fails, there may be multiple
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// encodings that are close to being a match. It's often ambiguous which one
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// the programmer intended to use, so we want to report an error which mentions
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// each of these "near-miss" encodings. This struct contains information about
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// one such encoding, and why it did not match the parsed instruction.
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class NearMissInfo {
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public:
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  enum NearMissKind {
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    NoNearMiss,
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    NearMissOperand,
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    NearMissFeature,
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    NearMissPredicate,
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    NearMissTooFewOperands,
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  };
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  // The encoding is valid for the parsed assembly string. This is only used
200
  // internally to the table-generated assembly matcher.
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1.65M
  static NearMissInfo getSuccess() { return NearMissInfo(); }
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  // The instruction encoding is not valid because it requires some target
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  // features that are not currently enabled. MissingFeatures has a bit set for
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  // each feature that the encoding needs but which is not enabled.
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34.6k
  static NearMissInfo getMissedFeature(uint64_t MissingFeatures) {
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34.6k
    NearMissInfo Result;
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34.6k
    Result.Kind = NearMissFeature;
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34.6k
    Result.Features = MissingFeatures;
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34.6k
    return Result;
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34.6k
  }
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  // The instruction encoding is not valid because the target-specific
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  // predicate function returned an error code. FailureCode is the
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  // target-specific error code returned by the predicate.
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  static NearMissInfo getMissedPredicate(unsigned FailureCode) {
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    NearMissInfo Result;
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    Result.Kind = NearMissPredicate;
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    Result.PredicateError = FailureCode;
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    return Result;
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  }
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  // The instruction encoding is not valid because one (and only one) parsed
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  // operand is not of the correct type. OperandError is the error code
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  // relating to the operand class expected by the encoding. OperandClass is
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  // the type of the expected operand. Opcode is the opcode of the encoding.
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  // OperandIndex is the index into the parsed operand list.
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  static NearMissInfo getMissedOperand(unsigned OperandError,
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                                       unsigned OperandClass, unsigned Opcode,
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369k
                                       unsigned OperandIndex) {
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369k
    NearMissInfo Result;
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369k
    Result.Kind = NearMissOperand;
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369k
    Result.MissedOperand.Error = OperandError;
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369k
    Result.MissedOperand.Class = OperandClass;
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369k
    Result.MissedOperand.Opcode = Opcode;
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369k
    Result.MissedOperand.Index = OperandIndex;
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    return Result;
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  }
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  // The instruction encoding is not valid because it expects more operands
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  // than were parsed. OperandClass is the class of the expected operand that
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  // was not provided. Opcode is the instruction encoding.
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  static NearMissInfo getTooFewOperands(unsigned OperandClass,
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823
                                        unsigned Opcode) {
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823
    NearMissInfo Result;
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823
    Result.Kind = NearMissTooFewOperands;
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823
    Result.TooFewOperands.Class = OperandClass;
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823
    Result.TooFewOperands.Opcode = Opcode;
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823
    return Result;
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823
  }
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1.08M
  operator bool() const { return Kind != NoNearMiss; }
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11.2k
  NearMissKind getKind() const { return Kind; }
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  // Feature flags required by the instruction, that the current target does
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  // not have.
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2.39k
  uint64_t getFeatures() const {
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2.39k
    assert(Kind == NearMissFeature);
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2.39k
    return Features;
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2.39k
  }
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  // Error code returned by the target predicate when validating this
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  // instruction encoding.
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  unsigned getPredicateError() const {
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    assert(Kind == NearMissPredicate);
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    return PredicateError;
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  }
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  // MatchClassKind of the operand that we expected to see.
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3.44k
  unsigned getOperandClass() const {
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3.44k
    assert(Kind == NearMissOperand || Kind == NearMissTooFewOperands);
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3.44k
    return MissedOperand.Class;
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3.44k
  }
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  // Opcode of the encoding we were trying to match.
274
  unsigned getOpcode() const {
275
    assert(Kind == NearMissOperand || Kind == NearMissTooFewOperands);
276
    return MissedOperand.Opcode;
277
  }
278
  // Error code returned when validating the operand.
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4.93k
  unsigned getOperandError() const {
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4.93k
    assert(Kind == NearMissOperand);
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4.93k
    return MissedOperand.Error;
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4.93k
  }
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  // Index of the actual operand we were trying to match in the list of parsed
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  // operands.
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13.2k
  unsigned getOperandIndex() const {
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13.2k
    assert(Kind == NearMissOperand);
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    return MissedOperand.Index;
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13.2k
  }
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private:
291
  NearMissKind Kind;
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  // These two structs share a common prefix, so we can safely rely on the fact
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  // that they overlap in the union.
295
  struct MissedOpInfo {
296
    unsigned Class;
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    unsigned Opcode;
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    unsigned Error;
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    unsigned Index;
300
  };
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302
  struct TooFewOperandsInfo {
303
    unsigned Class;
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    unsigned Opcode;
305
  };
306
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  union {
308
    uint64_t Features;
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    unsigned PredicateError;
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    MissedOpInfo MissedOperand;
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    TooFewOperandsInfo TooFewOperands;
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  };
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2.05M
  NearMissInfo() : Kind(NoNearMiss) {}
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};
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/// MCTargetAsmParser - Generic interface to target specific assembly parsers.
318
class MCTargetAsmParser : public MCAsmParserExtension {
319
public:
320
  enum MatchResultTy {
321
    Match_InvalidOperand,
322
    Match_InvalidTiedOperand,
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    Match_MissingFeature,
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    Match_MnemonicFail,
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    Match_Success,
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    Match_NearMisses,
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    FIRST_TARGET_MATCH_RESULT_TY
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  };
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protected: // Can only create subclasses.
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  MCTargetAsmParser(MCTargetOptions const &, const MCSubtargetInfo &STI,
332
                    const MCInstrInfo &MII);
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  /// Create a copy of STI and return a non-const reference to it.
335
  MCSubtargetInfo &copySTI();
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  /// AvailableFeatures - The current set of available features.
338
  uint64_t AvailableFeatures = 0;
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  /// ParsingInlineAsm - Are we parsing ms-style inline assembly?
341
  bool ParsingInlineAsm = false;
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343
  /// SemaCallback - The Sema callback implementation.  Must be set when parsing
344
  /// ms-style inline assembly.
345
  MCAsmParserSemaCallback *SemaCallback;
346
347
  /// Set of options which affects instrumentation of inline assembly.
348
  MCTargetOptions MCOptions;
349
350
  /// Current STI.
351
  const MCSubtargetInfo *STI;
352
353
  const MCInstrInfo &MII;
354
355
public:
356
  MCTargetAsmParser(const MCTargetAsmParser &) = delete;
357
  MCTargetAsmParser &operator=(const MCTargetAsmParser &) = delete;
358
359
  ~MCTargetAsmParser() override;
360
361
  const MCSubtargetInfo &getSTI() const;
362
363
1.58M
  uint64_t getAvailableFeatures() const { return AvailableFeatures; }
364
163k
  void setAvailableFeatures(uint64_t Value) { AvailableFeatures = Value; }
365
366
854k
  bool isParsingInlineAsm () { return ParsingInlineAsm; }
367
225
  void setParsingInlineAsm (bool Value) { ParsingInlineAsm = Value; }
368
369
43.3k
  MCTargetOptions getTargetOptions() const { return MCOptions; }
370
371
225
  void setSemaCallback(MCAsmParserSemaCallback *Callback) {
372
225
    SemaCallback = Callback;
373
225
  }
374
375
  // Target-specific parsing of expression.
376
454k
  virtual bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
377
454k
    return getParser().parsePrimaryExpr(Res, EndLoc);
378
454k
  }
379
380
  virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
381
                             SMLoc &EndLoc) = 0;
382
383
  /// Sets frame register corresponding to the current MachineFunction.
384
858
  virtual void SetFrameRegister(unsigned RegNo) {}
385
386
  /// ParseInstruction - Parse one assembly instruction.
387
  ///
388
  /// The parser is positioned following the instruction name. The target
389
  /// specific instruction parser should parse the entire instruction and
390
  /// construct the appropriate MCInst, or emit an error. On success, the entire
391
  /// line should be parsed up to and including the end-of-statement token. On
392
  /// failure, the parser is not required to read to the end of the line.
393
  //
394
  /// \param Name - The instruction name.
395
  /// \param NameLoc - The source location of the name.
396
  /// \param Operands [out] - The list of parsed operands, this returns
397
  ///        ownership of them to the caller.
398
  /// \return True on failure.
399
  virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
400
                                SMLoc NameLoc, OperandVector &Operands) = 0;
401
  virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
402
459k
                                AsmToken Token, OperandVector &Operands) {
403
459k
    return ParseInstruction(Info, Name, Token.getLoc(), Operands);
404
459k
  }
405
406
  /// ParseDirective - Parse a target specific assembler directive
407
  ///
408
  /// The parser is positioned following the directive name.  The target
409
  /// specific directive parser should parse the entire directive doing or
410
  /// recording any target specific work, or return true and do nothing if the
411
  /// directive is not target specific. If the directive is specific for
412
  /// the target, the entire line is parsed up to and including the
413
  /// end-of-statement token and false is returned.
414
  ///
415
  /// \param DirectiveID - the identifier token of the directive.
416
  virtual bool ParseDirective(AsmToken DirectiveID) = 0;
417
418
  /// MatchAndEmitInstruction - Recognize a series of operands of a parsed
419
  /// instruction as an actual MCInst and emit it to the specified MCStreamer.
420
  /// This returns false on success and returns true on failure to match.
421
  ///
422
  /// On failure, the target parser is responsible for emitting a diagnostic
423
  /// explaining the match failure.
424
  virtual bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
425
                                       OperandVector &Operands, MCStreamer &Out,
426
                                       uint64_t &ErrorInfo,
427
                                       bool MatchingInlineAsm) = 0;
428
429
  /// Allows targets to let registers opt out of clobber lists.
430
0
  virtual bool OmitRegisterFromClobberLists(unsigned RegNo) { return false; }
431
432
  /// Allow a target to add special case operand matching for things that
433
  /// tblgen doesn't/can't handle effectively. For example, literal
434
  /// immediates on ARM. TableGen expects a token operand, but the parser
435
  /// will recognize them as immediates.
436
  virtual unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
437
1.01M
                                              unsigned Kind) {
438
1.01M
    return Match_InvalidOperand;
439
1.01M
  }
440
441
  /// Validate the instruction match against any complex target predicates
442
  /// before rendering any operands to it.
443
  virtual unsigned
444
468k
  checkEarlyTargetMatchPredicate(MCInst &Inst, const OperandVector &Operands) {
445
468k
    return Match_Success;
446
468k
  }
447
448
  /// checkTargetMatchPredicate - Validate the instruction match against
449
  /// any complex target predicates not expressible via match classes.
450
197k
  virtual unsigned checkTargetMatchPredicate(MCInst &Inst) {
451
197k
    return Match_Success;
452
197k
  }
453
454
  virtual void convertToMapAndConstraints(unsigned Kind,
455
                                          const OperandVector &Operands) = 0;
456
457
  /// Returns whether two registers are equal and is used by the tied-operands
458
  /// checks in the AsmMatcher. This method can be overridden allow e.g. a
459
  /// sub- or super-register as the tied operand.
460
  virtual bool regsEqual(const MCParsedAsmOperand &Op1,
461
2.07k
                         const MCParsedAsmOperand &Op2) const {
462
2.07k
    assert(Op1.isReg() && Op2.isReg() && "Operands not all regs");
463
2.07k
    return Op1.getReg() == Op2.getReg();
464
2.07k
  }
465
466
  // Return whether this parser uses assignment statements with equals tokens
467
584
  virtual bool equalIsAsmAssignment() { return true; };
468
  // Return whether this start of statement identifier is a label
469
22.5k
  virtual bool isLabel(AsmToken &Token) { return true; };
470
  // Return whether this parser accept star as start of statement
471
0
  virtual bool starIsStartOfStatement() { return false; };
472
473
  virtual const MCExpr *applyModifierToExpr(const MCExpr *E,
474
                                            MCSymbolRefExpr::VariantKind,
475
26
                                            MCContext &Ctx) {
476
26
    return nullptr;
477
26
  }
478
479
19.5k
  virtual void onLabelParsed(MCSymbol *Symbol) {}
480
481
  /// Ensure that all previously parsed instructions have been emitted to the
482
  /// output streamer, if the target does not emit them immediately.
483
674k
  virtual void flushPendingInstructions(MCStreamer &Out) {}
484
485
  virtual const MCExpr *createTargetUnaryExpr(const MCExpr *E,
486
                                              AsmToken::TokenKind OperatorToken,
487
0
                                              MCContext &Ctx) {
488
0
    return nullptr;
489
0
  }
490
};
491
492
} // end namespace llvm
493
494
#endif // LLVM_MC_MCPARSER_MCTARGETASMPARSER_H