/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/MC/MCRegisterInfo.h
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1 | | //===- MC/MCRegisterInfo.h - Target Register Description --------*- C++ -*-===// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | // |
9 | | // This file describes an abstract interface used to get information about a |
10 | | // target machines register file. This information is used for a variety of |
11 | | // purposed, especially register allocation. |
12 | | // |
13 | | //===----------------------------------------------------------------------===// |
14 | | |
15 | | #ifndef LLVM_MC_MCREGISTERINFO_H |
16 | | #define LLVM_MC_MCREGISTERINFO_H |
17 | | |
18 | | #include "llvm/ADT/DenseMap.h" |
19 | | #include "llvm/ADT/iterator_range.h" |
20 | | #include "llvm/MC/LaneBitmask.h" |
21 | | #include <cassert> |
22 | | #include <cstdint> |
23 | | #include <utility> |
24 | | |
25 | | namespace llvm { |
26 | | |
27 | | /// An unsigned integer type large enough to represent all physical registers, |
28 | | /// but not necessarily virtual registers. |
29 | | using MCPhysReg = uint16_t; |
30 | | |
31 | | /// MCRegisterClass - Base class of TargetRegisterClass. |
32 | | class MCRegisterClass { |
33 | | public: |
34 | | using iterator = const MCPhysReg*; |
35 | | using const_iterator = const MCPhysReg*; |
36 | | |
37 | | const iterator RegsBegin; |
38 | | const uint8_t *const RegSet; |
39 | | const uint32_t NameIdx; |
40 | | const uint16_t RegsSize; |
41 | | const uint16_t RegSetSize; |
42 | | const uint16_t ID; |
43 | | const int8_t CopyCost; |
44 | | const bool Allocatable; |
45 | | |
46 | | /// getID() - Return the register class ID number. |
47 | | /// |
48 | 622M | unsigned getID() const { return ID; } |
49 | | |
50 | | /// begin/end - Return all of the registers in this class. |
51 | | /// |
52 | 21.9M | iterator begin() const { return RegsBegin; } |
53 | 20.2M | iterator end() const { return RegsBegin + RegsSize; } |
54 | | |
55 | | /// getNumRegs - Return the number of registers in this class. |
56 | | /// |
57 | 501M | unsigned getNumRegs() const { return RegsSize; } |
58 | | |
59 | | /// getRegister - Return the specified register in the class. |
60 | | /// |
61 | 17.1M | unsigned getRegister(unsigned i) const { |
62 | 17.1M | assert(i < getNumRegs() && "Register number out of range!"); |
63 | 17.1M | return RegsBegin[i]; |
64 | 17.1M | } |
65 | | |
66 | | /// contains - Return true if the specified register is included in this |
67 | | /// register class. This does not include virtual registers. |
68 | 595M | bool contains(unsigned Reg) const { |
69 | 595M | unsigned InByte = Reg % 8; |
70 | 595M | unsigned Byte = Reg / 8; |
71 | 595M | if (Byte >= RegSetSize) |
72 | 146M | return false; |
73 | 448M | return (RegSet[Byte] & (1 << InByte)) != 0; |
74 | 448M | } |
75 | | |
76 | | /// contains - Return true if both registers are in this class. |
77 | 728k | bool contains(unsigned Reg1, unsigned Reg2) const { |
78 | 728k | return contains(Reg1) && contains(Reg2)358k ; |
79 | 728k | } |
80 | | |
81 | | /// getCopyCost - Return the cost of copying a value between two registers in |
82 | | /// this class. A negative number means the register class is very expensive |
83 | | /// to copy e.g. status flag register classes. |
84 | 793k | int getCopyCost() const { return CopyCost; } |
85 | | |
86 | | /// isAllocatable - Return true if this register class may be used to create |
87 | | /// virtual registers. |
88 | 15.9M | bool isAllocatable() const { return Allocatable; } |
89 | | }; |
90 | | |
91 | | /// MCRegisterDesc - This record contains information about a particular |
92 | | /// register. The SubRegs field is a zero terminated array of registers that |
93 | | /// are sub-registers of the specific register, e.g. AL, AH are sub-registers |
94 | | /// of AX. The SuperRegs field is a zero terminated array of registers that are |
95 | | /// super-registers of the specific register, e.g. RAX, EAX, are |
96 | | /// super-registers of AX. |
97 | | /// |
98 | | struct MCRegisterDesc { |
99 | | uint32_t Name; // Printable name for the reg (for debugging) |
100 | | uint32_t SubRegs; // Sub-register set, described above |
101 | | uint32_t SuperRegs; // Super-register set, described above |
102 | | |
103 | | // Offset into MCRI::SubRegIndices of a list of sub-register indices for each |
104 | | // sub-register in SubRegs. |
105 | | uint32_t SubRegIndices; |
106 | | |
107 | | // RegUnits - Points to the list of register units. The low 4 bits holds the |
108 | | // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator. |
109 | | uint32_t RegUnits; |
110 | | |
111 | | /// Index into list with lane mask sequences. The sequence contains a lanemask |
112 | | /// for every register unit. |
113 | | uint16_t RegUnitLaneMasks; |
114 | | }; |
115 | | |
116 | | /// MCRegisterInfo base class - We assume that the target defines a static |
117 | | /// array of MCRegisterDesc objects that represent all of the machine |
118 | | /// registers that the target has. As such, we simply have to track a pointer |
119 | | /// to this array so that we can turn register number into a register |
120 | | /// descriptor. |
121 | | /// |
122 | | /// Note this class is designed to be a base class of TargetRegisterInfo, which |
123 | | /// is the interface used by codegen. However, specific targets *should never* |
124 | | /// specialize this class. MCRegisterInfo should only contain getters to access |
125 | | /// TableGen generated physical register data. It must not be extended with |
126 | | /// virtual methods. |
127 | | /// |
128 | | class MCRegisterInfo { |
129 | | public: |
130 | | using regclass_iterator = const MCRegisterClass *; |
131 | | |
132 | | /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be |
133 | | /// performed with a binary search. |
134 | | struct DwarfLLVMRegPair { |
135 | | unsigned FromReg; |
136 | | unsigned ToReg; |
137 | | |
138 | 7.13M | bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; } |
139 | | }; |
140 | | |
141 | | /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg |
142 | | /// index, -1 in any being invalid. |
143 | | struct SubRegCoveredBits { |
144 | | uint16_t Offset; |
145 | | uint16_t Size; |
146 | | }; |
147 | | |
148 | | private: |
149 | | const MCRegisterDesc *Desc; // Pointer to the descriptor array |
150 | | unsigned NumRegs; // Number of entries in the array |
151 | | unsigned RAReg; // Return address register |
152 | | unsigned PCReg; // Program counter register |
153 | | const MCRegisterClass *Classes; // Pointer to the regclass array |
154 | | unsigned NumClasses; // Number of entries in the array |
155 | | unsigned NumRegUnits; // Number of regunits. |
156 | | const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table. |
157 | | const MCPhysReg *DiffLists; // Pointer to the difflists array |
158 | | const LaneBitmask *RegUnitMaskSequences; // Pointer to lane mask sequences |
159 | | // for register units. |
160 | | const char *RegStrings; // Pointer to the string table. |
161 | | const char *RegClassStrings; // Pointer to the class strings. |
162 | | const uint16_t *SubRegIndices; // Pointer to the subreg lookup |
163 | | // array. |
164 | | const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered |
165 | | // bit ranges array. |
166 | | unsigned NumSubRegIndices; // Number of subreg indices. |
167 | | const uint16_t *RegEncodingTable; // Pointer to array of register |
168 | | // encodings. |
169 | | |
170 | | unsigned L2DwarfRegsSize; |
171 | | unsigned EHL2DwarfRegsSize; |
172 | | unsigned Dwarf2LRegsSize; |
173 | | unsigned EHDwarf2LRegsSize; |
174 | | const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping |
175 | | const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH |
176 | | const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping |
177 | | const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH |
178 | | DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping |
179 | | DenseMap<unsigned, int> L2CVRegs; // LLVM to CV regs mapping |
180 | | |
181 | | public: |
182 | | /// DiffListIterator - Base iterator class that can traverse the |
183 | | /// differentially encoded register and regunit lists in DiffLists. |
184 | | /// Don't use this class directly, use one of the specialized sub-classes |
185 | | /// defined below. |
186 | | class DiffListIterator { |
187 | | uint16_t Val = 0; |
188 | | const MCPhysReg *List = nullptr; |
189 | | |
190 | | protected: |
191 | | /// Create an invalid iterator. Call init() to point to something useful. |
192 | 1.67G | DiffListIterator() = default; |
193 | | |
194 | | /// init - Point the iterator to InitVal, decoding subsequent values from |
195 | | /// DiffList. The iterator will initially point to InitVal, sub-classes are |
196 | | /// responsible for skipping the seed value if it is not part of the list. |
197 | 1.33G | void init(MCPhysReg InitVal, const MCPhysReg *DiffList) { |
198 | 1.33G | Val = InitVal; |
199 | 1.33G | List = DiffList; |
200 | 1.33G | } |
201 | | |
202 | | /// advance - Move to the next list position, return the applied |
203 | | /// differential. This function does not detect the end of the list, that |
204 | | /// is the caller's responsibility (by checking for a 0 return value). |
205 | 3.93G | unsigned advance() { |
206 | 3.93G | assert(isValid() && "Cannot move off the end of the list."); |
207 | 3.93G | MCPhysReg D = *List++; |
208 | 3.93G | Val += D; |
209 | 3.93G | return D; |
210 | 3.93G | } |
211 | | |
212 | | public: |
213 | | /// isValid - returns true if this iterator is not yet at the end. |
214 | 6.12G | bool isValid() const { return List; } |
215 | | |
216 | | /// Dereference the iterator to get the value at the current position. |
217 | 3.53G | unsigned operator*() const { return Val; } |
218 | | |
219 | | /// Pre-increment to move to the next position. |
220 | 3.18G | void operator++() { |
221 | 3.18G | // The end of the list is encoded as a 0 differential. |
222 | 3.18G | if (!advance()) |
223 | 1.02G | List = nullptr; |
224 | 3.18G | } |
225 | | }; |
226 | | |
227 | | // These iterators are allowed to sub-class DiffListIterator and access |
228 | | // internal list pointers. |
229 | | friend class MCSubRegIterator; |
230 | | friend class MCSubRegIndexIterator; |
231 | | friend class MCSuperRegIterator; |
232 | | friend class MCRegUnitIterator; |
233 | | friend class MCRegUnitMaskIterator; |
234 | | friend class MCRegUnitRootIterator; |
235 | | |
236 | | /// Initialize MCRegisterInfo, called by TableGen |
237 | | /// auto-generated routines. *DO NOT USE*. |
238 | | void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, |
239 | | unsigned PC, |
240 | | const MCRegisterClass *C, unsigned NC, |
241 | | const MCPhysReg (*RURoots)[2], |
242 | | unsigned NRU, |
243 | | const MCPhysReg *DL, |
244 | | const LaneBitmask *RUMS, |
245 | | const char *Strings, |
246 | | const char *ClassStrings, |
247 | | const uint16_t *SubIndices, |
248 | | unsigned NumIndices, |
249 | | const SubRegCoveredBits *SubIdxRanges, |
250 | 122k | const uint16_t *RET) { |
251 | 122k | Desc = D; |
252 | 122k | NumRegs = NR; |
253 | 122k | RAReg = RA; |
254 | 122k | PCReg = PC; |
255 | 122k | Classes = C; |
256 | 122k | DiffLists = DL; |
257 | 122k | RegUnitMaskSequences = RUMS; |
258 | 122k | RegStrings = Strings; |
259 | 122k | RegClassStrings = ClassStrings; |
260 | 122k | NumClasses = NC; |
261 | 122k | RegUnitRoots = RURoots; |
262 | 122k | NumRegUnits = NRU; |
263 | 122k | SubRegIndices = SubIndices; |
264 | 122k | NumSubRegIndices = NumIndices; |
265 | 122k | SubRegIdxRanges = SubIdxRanges; |
266 | 122k | RegEncodingTable = RET; |
267 | 122k | |
268 | 122k | // Initialize DWARF register mapping variables |
269 | 122k | EHL2DwarfRegs = nullptr; |
270 | 122k | EHL2DwarfRegsSize = 0; |
271 | 122k | L2DwarfRegs = nullptr; |
272 | 122k | L2DwarfRegsSize = 0; |
273 | 122k | EHDwarf2LRegs = nullptr; |
274 | 122k | EHDwarf2LRegsSize = 0; |
275 | 122k | Dwarf2LRegs = nullptr; |
276 | 122k | Dwarf2LRegsSize = 0; |
277 | 122k | } |
278 | | |
279 | | /// Used to initialize LLVM register to Dwarf |
280 | | /// register number mapping. Called by TableGen auto-generated routines. |
281 | | /// *DO NOT USE*. |
282 | | void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, |
283 | 238k | bool isEH) { |
284 | 238k | if (isEH) { |
285 | 119k | EHL2DwarfRegs = Map; |
286 | 119k | EHL2DwarfRegsSize = Size; |
287 | 119k | } else { |
288 | 119k | L2DwarfRegs = Map; |
289 | 119k | L2DwarfRegsSize = Size; |
290 | 119k | } |
291 | 238k | } |
292 | | |
293 | | /// Used to initialize Dwarf register to LLVM |
294 | | /// register number mapping. Called by TableGen auto-generated routines. |
295 | | /// *DO NOT USE*. |
296 | | void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, |
297 | 238k | bool isEH) { |
298 | 238k | if (isEH) { |
299 | 119k | EHDwarf2LRegs = Map; |
300 | 119k | EHDwarf2LRegsSize = Size; |
301 | 119k | } else { |
302 | 119k | Dwarf2LRegs = Map; |
303 | 119k | Dwarf2LRegsSize = Size; |
304 | 119k | } |
305 | 238k | } |
306 | | |
307 | | /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register |
308 | | /// number mapping. By default the SEH register number is just the same |
309 | | /// as the LLVM register number. |
310 | | /// FIXME: TableGen these numbers. Currently this requires target specific |
311 | | /// initialization code. |
312 | 12.2M | void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) { |
313 | 12.2M | L2SEHRegs[LLVMReg] = SEHReg; |
314 | 12.2M | } |
315 | | |
316 | 12.0M | void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg) { |
317 | 12.0M | L2CVRegs[LLVMReg] = CVReg; |
318 | 12.0M | } |
319 | | |
320 | | /// This method should return the register where the return |
321 | | /// address can be found. |
322 | 64.3k | unsigned getRARegister() const { |
323 | 64.3k | return RAReg; |
324 | 64.3k | } |
325 | | |
326 | | /// Return the register which is the program counter. |
327 | 2.16k | unsigned getProgramCounter() const { |
328 | 2.16k | return PCReg; |
329 | 2.16k | } |
330 | | |
331 | 1.47G | const MCRegisterDesc &operator[](unsigned RegNo) const { |
332 | 1.47G | assert(RegNo < NumRegs && |
333 | 1.47G | "Attempting to access record for invalid register number!"); |
334 | 1.47G | return Desc[RegNo]; |
335 | 1.47G | } |
336 | | |
337 | | /// Provide a get method, equivalent to [], but more useful with a |
338 | | /// pointer to this object. |
339 | 1.47G | const MCRegisterDesc &get(unsigned RegNo) const { |
340 | 1.47G | return operator[](RegNo); |
341 | 1.47G | } |
342 | | |
343 | | /// Returns the physical register number of sub-register "Index" |
344 | | /// for physical register RegNo. Return zero if the sub-register does not |
345 | | /// exist. |
346 | | unsigned getSubReg(unsigned Reg, unsigned Idx) const; |
347 | | |
348 | | /// Return a super-register of the specified register |
349 | | /// Reg so its sub-register of index SubIdx is Reg. |
350 | | unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, |
351 | | const MCRegisterClass *RC) const; |
352 | | |
353 | | /// For a given register pair, return the sub-register index |
354 | | /// if the second register is a sub-register of the first. Return zero |
355 | | /// otherwise. |
356 | | unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const; |
357 | | |
358 | | /// Get the size of the bit range covered by a sub-register index. |
359 | | /// If the index isn't continuous, return the sum of the sizes of its parts. |
360 | | /// If the index is used to access subregisters of different sizes, return -1. |
361 | | unsigned getSubRegIdxSize(unsigned Idx) const; |
362 | | |
363 | | /// Get the offset of the bit range covered by a sub-register index. |
364 | | /// If an Offset doesn't make sense (the index isn't continuous, or is used to |
365 | | /// access sub-registers at different offsets), return -1. |
366 | | unsigned getSubRegIdxOffset(unsigned Idx) const; |
367 | | |
368 | | /// Return the human-readable symbolic target-specific name for the |
369 | | /// specified physical register. |
370 | 125M | const char *getName(unsigned RegNo) const { |
371 | 125M | return RegStrings + get(RegNo).Name; |
372 | 125M | } |
373 | | |
374 | | /// Return the number of registers this target has (useful for |
375 | | /// sizing arrays holding per register information) |
376 | 78.2M | unsigned getNumRegs() const { |
377 | 78.2M | return NumRegs; |
378 | 78.2M | } |
379 | | |
380 | | /// Return the number of sub-register indices |
381 | | /// understood by the target. Index 0 is reserved for the no-op sub-register, |
382 | | /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers. |
383 | 1.49k | unsigned getNumSubRegIndices() const { |
384 | 1.49k | return NumSubRegIndices; |
385 | 1.49k | } |
386 | | |
387 | | /// Return the number of (native) register units in the |
388 | | /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They |
389 | | /// can be accessed through MCRegUnitIterator defined below. |
390 | 10.7M | unsigned getNumRegUnits() const { |
391 | 10.7M | return NumRegUnits; |
392 | 10.7M | } |
393 | | |
394 | | /// Map a target register to an equivalent dwarf register |
395 | | /// number. Returns -1 if there is no equivalent value. The second |
396 | | /// parameter allows targets to use different numberings for EH info and |
397 | | /// debugging info. |
398 | | int getDwarfRegNum(unsigned RegNum, bool isEH) const; |
399 | | |
400 | | /// Map a dwarf register back to a target register. |
401 | | int getLLVMRegNum(unsigned RegNum, bool isEH) const; |
402 | | |
403 | | /// Map a DWARF EH register back to a target register (same as |
404 | | /// getLLVMRegNum(RegNum, true)) but return -1 if there is no mapping, |
405 | | /// rather than asserting that there must be one. |
406 | | int getLLVMRegNumFromEH(unsigned RegNum) const; |
407 | | |
408 | | /// Map a target EH register number to an equivalent DWARF register |
409 | | /// number. |
410 | | int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const; |
411 | | |
412 | | /// Map a target register to an equivalent SEH register |
413 | | /// number. Returns LLVM register number if there is no equivalent value. |
414 | | int getSEHRegNum(unsigned RegNum) const; |
415 | | |
416 | | /// Map a target register to an equivalent CodeView register |
417 | | /// number. |
418 | | int getCodeViewRegNum(unsigned RegNum) const; |
419 | | |
420 | 0 | regclass_iterator regclass_begin() const { return Classes; } |
421 | 0 | regclass_iterator regclass_end() const { return Classes+NumClasses; } |
422 | 0 | iterator_range<regclass_iterator> regclasses() const { |
423 | 0 | return make_range(regclass_begin(), regclass_end()); |
424 | 0 | } |
425 | | |
426 | 0 | unsigned getNumRegClasses() const { |
427 | 0 | return (unsigned)(regclass_end()-regclass_begin()); |
428 | 0 | } |
429 | | |
430 | | /// Returns the register class associated with the enumeration |
431 | | /// value. See class MCOperandInfo. |
432 | 2.68M | const MCRegisterClass& getRegClass(unsigned i) const { |
433 | 2.68M | assert(i < getNumRegClasses() && "Register Class ID out of range"); |
434 | 2.68M | return Classes[i]; |
435 | 2.68M | } |
436 | | |
437 | 336k | const char *getRegClassName(const MCRegisterClass *Class) const { |
438 | 336k | return RegClassStrings + Class->NameIdx; |
439 | 336k | } |
440 | | |
441 | | /// Returns the encoding for RegNo |
442 | 58.4M | uint16_t getEncodingValue(unsigned RegNo) const { |
443 | 58.4M | assert(RegNo < NumRegs && |
444 | 58.4M | "Attempting to get encoding for invalid register number!"); |
445 | 58.4M | return RegEncodingTable[RegNo]; |
446 | 58.4M | } |
447 | | |
448 | | /// Returns true if RegB is a sub-register of RegA. |
449 | 35.0M | bool isSubRegister(unsigned RegA, unsigned RegB) const { |
450 | 35.0M | return isSuperRegister(RegB, RegA); |
451 | 35.0M | } |
452 | | |
453 | | /// Returns true if RegB is a super-register of RegA. |
454 | | bool isSuperRegister(unsigned RegA, unsigned RegB) const; |
455 | | |
456 | | /// Returns true if RegB is a sub-register of RegA or if RegB == RegA. |
457 | 1.83M | bool isSubRegisterEq(unsigned RegA, unsigned RegB) const { |
458 | 1.83M | return isSuperRegisterEq(RegB, RegA); |
459 | 1.83M | } |
460 | | |
461 | | /// Returns true if RegB is a super-register of RegA or if |
462 | | /// RegB == RegA. |
463 | 1.90M | bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const { |
464 | 1.90M | return RegA == RegB || isSuperRegister(RegA, RegB)212k ; |
465 | 1.90M | } |
466 | | |
467 | | /// Returns true if RegB is a super-register or sub-register of RegA |
468 | | /// or if RegB == RegA. |
469 | 758 | bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const { |
470 | 758 | return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB)544 ; |
471 | 758 | } |
472 | | }; |
473 | | |
474 | | //===----------------------------------------------------------------------===// |
475 | | // Register List Iterators |
476 | | //===----------------------------------------------------------------------===// |
477 | | |
478 | | // MCRegisterInfo provides lists of super-registers, sub-registers, and |
479 | | // aliasing registers. Use these iterator classes to traverse the lists. |
480 | | |
481 | | /// MCSubRegIterator enumerates all sub-registers of Reg. |
482 | | /// If IncludeSelf is set, Reg itself is included in the list. |
483 | | class MCSubRegIterator : public MCRegisterInfo::DiffListIterator { |
484 | | public: |
485 | | MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI, |
486 | 233M | bool IncludeSelf = false) { |
487 | 233M | init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs); |
488 | 233M | // Initially, the iterator points to Reg itself. |
489 | 233M | if (!IncludeSelf) |
490 | 95.5M | ++*this; |
491 | 233M | } |
492 | | }; |
493 | | |
494 | | /// Iterator that enumerates the sub-registers of a Reg and the associated |
495 | | /// sub-register indices. |
496 | | class MCSubRegIndexIterator { |
497 | | MCSubRegIterator SRIter; |
498 | | const uint16_t *SRIndex; |
499 | | |
500 | | public: |
501 | | /// Constructs an iterator that traverses subregisters and their |
502 | | /// associated subregister indices. |
503 | | MCSubRegIndexIterator(unsigned Reg, const MCRegisterInfo *MCRI) |
504 | 4.22M | : SRIter(Reg, MCRI) { |
505 | 4.22M | SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices; |
506 | 4.22M | } |
507 | | |
508 | | /// Returns current sub-register. |
509 | 20.3k | unsigned getSubReg() const { |
510 | 20.3k | return *SRIter; |
511 | 20.3k | } |
512 | | |
513 | | /// Returns sub-register index of the current sub-register. |
514 | 27.5k | unsigned getSubRegIndex() const { |
515 | 27.5k | return *SRIndex; |
516 | 27.5k | } |
517 | | |
518 | | /// Returns true if this iterator is not yet at the end. |
519 | 131k | bool isValid() const { return SRIter.isValid(); } |
520 | | |
521 | | /// Moves to the next position. |
522 | 27.5k | void operator++() { |
523 | 27.5k | ++SRIter; |
524 | 27.5k | ++SRIndex; |
525 | 27.5k | } |
526 | | }; |
527 | | |
528 | | /// MCSuperRegIterator enumerates all super-registers of Reg. |
529 | | /// If IncludeSelf is set, Reg itself is included in the list. |
530 | | class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator { |
531 | | public: |
532 | 169M | MCSuperRegIterator() = default; |
533 | | |
534 | | MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI, |
535 | 357M | bool IncludeSelf = false) { |
536 | 357M | init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs); |
537 | 357M | // Initially, the iterator points to Reg itself. |
538 | 357M | if (!IncludeSelf) |
539 | 84.0M | ++*this; |
540 | 357M | } |
541 | | }; |
542 | | |
543 | | // Definition for isSuperRegister. Put it down here since it needs the |
544 | | // iterator defined above in addition to the MCRegisterInfo class itself. |
545 | 71.7M | inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{ |
546 | 239M | for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I168M ) |
547 | 182M | if (*I == RegB) |
548 | 14.1M | return true; |
549 | 71.7M | return false57.6M ; |
550 | 71.7M | } |
551 | | |
552 | | //===----------------------------------------------------------------------===// |
553 | | // Register Units |
554 | | //===----------------------------------------------------------------------===// |
555 | | |
556 | | // Register units are used to compute register aliasing. Every register has at |
557 | | // least one register unit, but it can have more. Two registers overlap if and |
558 | | // only if they have a common register unit. |
559 | | // |
560 | | // A target with a complicated sub-register structure will typically have many |
561 | | // fewer register units than actual registers. MCRI::getNumRegUnits() returns |
562 | | // the number of register units in the target. |
563 | | |
564 | | // MCRegUnitIterator enumerates a list of register units for Reg. The list is |
565 | | // in ascending numerical order. |
566 | | class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator { |
567 | | public: |
568 | | /// MCRegUnitIterator - Create an iterator that traverses the register units |
569 | | /// in Reg. |
570 | 169M | MCRegUnitIterator() = default; |
571 | | |
572 | 746M | MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) { |
573 | 746M | assert(Reg && "Null register has no regunits"); |
574 | 746M | // Decode the RegUnits MCRegisterDesc field. |
575 | 746M | unsigned RU = MCRI->get(Reg).RegUnits; |
576 | 746M | unsigned Scale = RU & 15; |
577 | 746M | unsigned Offset = RU >> 4; |
578 | 746M | |
579 | 746M | // Initialize the iterator to Reg * Scale, and the List pointer to |
580 | 746M | // DiffLists + Offset. |
581 | 746M | init(Reg * Scale, MCRI->DiffLists + Offset); |
582 | 746M | |
583 | 746M | // That may not be a valid unit, we need to advance by one to get the real |
584 | 746M | // unit number. The first differential can be 0 which would normally |
585 | 746M | // terminate the list, but since we know every register has at least one |
586 | 746M | // unit, we can allow a 0 differential here. |
587 | 746M | advance(); |
588 | 746M | } |
589 | | }; |
590 | | |
591 | | /// MCRegUnitMaskIterator enumerates a list of register units and their |
592 | | /// associated lane masks for Reg. The register units are in ascending |
593 | | /// numerical order. |
594 | | class MCRegUnitMaskIterator { |
595 | | MCRegUnitIterator RUIter; |
596 | | const LaneBitmask *MaskListIter; |
597 | | |
598 | | public: |
599 | | MCRegUnitMaskIterator() = default; |
600 | | |
601 | | /// Constructs an iterator that traverses the register units and their |
602 | | /// associated LaneMasks in Reg. |
603 | | MCRegUnitMaskIterator(unsigned Reg, const MCRegisterInfo *MCRI) |
604 | 7.60M | : RUIter(Reg, MCRI) { |
605 | 7.60M | uint16_t Idx = MCRI->get(Reg).RegUnitLaneMasks; |
606 | 7.60M | MaskListIter = &MCRI->RegUnitMaskSequences[Idx]; |
607 | 7.60M | } |
608 | | |
609 | | /// Returns a (RegUnit, LaneMask) pair. |
610 | 16.6M | std::pair<unsigned,LaneBitmask> operator*() const { |
611 | 16.6M | return std::make_pair(*RUIter, *MaskListIter); |
612 | 16.6M | } |
613 | | |
614 | | /// Returns true if this iterator is not yet at the end. |
615 | 16.6M | bool isValid() const { return RUIter.isValid(); } |
616 | | |
617 | | /// Moves to the next position. |
618 | 8.73M | void operator++() { |
619 | 8.73M | ++MaskListIter; |
620 | 8.73M | ++RUIter; |
621 | 8.73M | } |
622 | | }; |
623 | | |
624 | | // Each register unit has one or two root registers. The complete set of |
625 | | // registers containing a register unit is the union of the roots and their |
626 | | // super-registers. All registers aliasing Unit can be visited like this: |
627 | | // |
628 | | // for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) { |
629 | | // for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI) |
630 | | // visit(*SI); |
631 | | // } |
632 | | |
633 | | /// MCRegUnitRootIterator enumerates the root registers of a register unit. |
634 | | class MCRegUnitRootIterator { |
635 | | uint16_t Reg0 = 0; |
636 | | uint16_t Reg1 = 0; |
637 | | |
638 | | public: |
639 | 169M | MCRegUnitRootIterator() = default; |
640 | | |
641 | 359M | MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { |
642 | 359M | assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit"); |
643 | 359M | Reg0 = MCRI->RegUnitRoots[RegUnit][0]; |
644 | 359M | Reg1 = MCRI->RegUnitRoots[RegUnit][1]; |
645 | 359M | } |
646 | | |
647 | | /// Dereference to get the current root register. |
648 | 359M | unsigned operator*() const { |
649 | 359M | return Reg0; |
650 | 359M | } |
651 | | |
652 | | /// Check if the iterator is at the end of the list. |
653 | 645M | bool isValid() const { |
654 | 645M | return Reg0; |
655 | 645M | } |
656 | | |
657 | | /// Preincrement to move to the next root register. |
658 | 318M | void operator++() { |
659 | 318M | assert(isValid() && "Cannot move off the end of the list."); |
660 | 318M | Reg0 = Reg1; |
661 | 318M | Reg1 = 0; |
662 | 318M | } |
663 | | }; |
664 | | |
665 | | /// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is |
666 | | /// set, Reg itself is included in the list. This iterator does not guarantee |
667 | | /// any ordering or that entries are unique. |
668 | | class MCRegAliasIterator { |
669 | | private: |
670 | | unsigned Reg; |
671 | | const MCRegisterInfo *MCRI; |
672 | | bool IncludeSelf; |
673 | | |
674 | | MCRegUnitIterator RI; |
675 | | MCRegUnitRootIterator RRI; |
676 | | MCSuperRegIterator SI; |
677 | | |
678 | | public: |
679 | | MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI, |
680 | | bool IncludeSelf) |
681 | 169M | : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) { |
682 | 169M | // Initialize the iterators. |
683 | 171M | for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI2.01M ) { |
684 | 171M | for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI2.02M ) { |
685 | 185M | for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI16.6M ) { |
686 | 183M | if (!(!IncludeSelf && Reg == *SI47.7M )) |
687 | 167M | return; |
688 | 183M | } |
689 | 169M | } |
690 | 169M | } |
691 | 169M | } |
692 | | |
693 | 1.75G | bool isValid() const { return RI.isValid(); } |
694 | | |
695 | 1.67G | unsigned operator*() const { |
696 | 1.67G | assert(SI.isValid() && "Cannot dereference an invalid iterator."); |
697 | 1.67G | return *SI; |
698 | 1.67G | } |
699 | | |
700 | 1.57G | void advance() { |
701 | 1.57G | // Assuming SI is valid. |
702 | 1.57G | ++SI; |
703 | 1.57G | if (SI.isValid()) return1.41G ; |
704 | 157M | |
705 | 157M | ++RRI; |
706 | 157M | if (RRI.isValid()) { |
707 | 46.4k | SI = MCSuperRegIterator(*RRI, MCRI, true); |
708 | 46.4k | return; |
709 | 46.4k | } |
710 | 157M | |
711 | 157M | ++RI; |
712 | 157M | if (RI.isValid()) { |
713 | 31.4M | RRI = MCRegUnitRootIterator(*RI, MCRI); |
714 | 31.4M | SI = MCSuperRegIterator(*RRI, MCRI, true); |
715 | 31.4M | } |
716 | 157M | } |
717 | | |
718 | 1.57G | void operator++() { |
719 | 1.57G | assert(isValid() && "Cannot move off the end of the list."); |
720 | 1.57G | do advance(); |
721 | 1.57G | while (!IncludeSelf && isValid()11.2M && *SI == Reg10.1M ); |
722 | 1.57G | } |
723 | | }; |
724 | | |
725 | | } // end namespace llvm |
726 | | |
727 | | #endif // LLVM_MC_MCREGISTERINFO_H |