Coverage Report

Created: 2018-07-19 03:59

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/MC/MCRegisterInfo.h
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//===- MC/MCRegisterInfo.h - Target Register Description --------*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
9
//
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// This file describes an abstract interface used to get information about a
11
// target machines register file.  This information is used for a variety of
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// purposed, especially register allocation.
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//
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//===----------------------------------------------------------------------===//
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16
#ifndef LLVM_MC_MCREGISTERINFO_H
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#define LLVM_MC_MCREGISTERINFO_H
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19
#include "llvm/ADT/DenseMap.h"
20
#include "llvm/ADT/iterator_range.h"
21
#include "llvm/MC/LaneBitmask.h"
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#include <cassert>
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#include <cstdint>
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#include <utility>
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26
namespace llvm {
27
28
/// An unsigned integer type large enough to represent all physical registers,
29
/// but not necessarily virtual registers.
30
using MCPhysReg = uint16_t;
31
32
/// MCRegisterClass - Base class of TargetRegisterClass.
33
class MCRegisterClass {
34
public:
35
  using iterator = const MCPhysReg*;
36
  using const_iterator = const MCPhysReg*;
37
38
  const iterator RegsBegin;
39
  const uint8_t *const RegSet;
40
  const uint32_t NameIdx;
41
  const uint16_t RegsSize;
42
  const uint16_t RegSetSize;
43
  const uint16_t ID;
44
  const uint16_t PhysRegSize;
45
  const int8_t CopyCost;
46
  const bool Allocatable;
47
48
  /// getID() - Return the register class ID number.
49
  ///
50
480M
  unsigned getID() const { return ID; }
51
52
  /// begin/end - Return all of the registers in this class.
53
  ///
54
13.5M
  iterator       begin() const { return RegsBegin; }
55
12.6M
  iterator         end() const { return RegsBegin + RegsSize; }
56
57
  /// getNumRegs - Return the number of registers in this class.
58
  ///
59
13.2M
  unsigned getNumRegs() const { return RegsSize; }
60
61
  /// getRegister - Return the specified register in the class.
62
  ///
63
1.11M
  unsigned getRegister(unsigned i) const {
64
1.11M
    assert(i < getNumRegs() && "Register number out of range!");
65
1.11M
    return RegsBegin[i];
66
1.11M
  }
67
68
  /// contains - Return true if the specified register is included in this
69
  /// register class.  This does not include virtual registers.
70
624M
  bool contains(unsigned Reg) const {
71
624M
    unsigned InByte = Reg % 8;
72
624M
    unsigned Byte = Reg / 8;
73
624M
    if (Byte >= RegSetSize)
74
176M
      return false;
75
447M
    return (RegSet[Byte] & (1 << InByte)) != 0;
76
447M
  }
77
78
  /// contains - Return true if both registers are in this class.
79
653k
  bool contains(unsigned Reg1, unsigned Reg2) const {
80
653k
    return contains(Reg1) && 
contains(Reg2)329k
;
81
653k
  }
82
83
  /// Return the size of the physical register in bytes.
84
0
  unsigned getPhysRegSize() const { return PhysRegSize; }
85
  /// Temporary function to allow out-of-tree targets to switch.
86
0
  unsigned getSize() const { return getPhysRegSize(); }
87
88
  /// getCopyCost - Return the cost of copying a value between two registers in
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  /// this class. A negative number means the register class is very expensive
90
  /// to copy e.g. status flag register classes.
91
1.29M
  int getCopyCost() const { return CopyCost; }
92
93
  /// isAllocatable - Return true if this register class may be used to create
94
  /// virtual registers.
95
14.2M
  bool isAllocatable() const { return Allocatable; }
96
};
97
98
/// MCRegisterDesc - This record contains information about a particular
99
/// register.  The SubRegs field is a zero terminated array of registers that
100
/// are sub-registers of the specific register, e.g. AL, AH are sub-registers
101
/// of AX. The SuperRegs field is a zero terminated array of registers that are
102
/// super-registers of the specific register, e.g. RAX, EAX, are
103
/// super-registers of AX.
104
///
105
struct MCRegisterDesc {
106
  uint32_t Name;      // Printable name for the reg (for debugging)
107
  uint32_t SubRegs;   // Sub-register set, described above
108
  uint32_t SuperRegs; // Super-register set, described above
109
110
  // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
111
  // sub-register in SubRegs.
112
  uint32_t SubRegIndices;
113
114
  // RegUnits - Points to the list of register units. The low 4 bits holds the
115
  // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
116
  uint32_t RegUnits;
117
118
  /// Index into list with lane mask sequences. The sequence contains a lanemask
119
  /// for every register unit.
120
  uint16_t RegUnitLaneMasks;
121
};
122
123
/// MCRegisterInfo base class - We assume that the target defines a static
124
/// array of MCRegisterDesc objects that represent all of the machine
125
/// registers that the target has.  As such, we simply have to track a pointer
126
/// to this array so that we can turn register number into a register
127
/// descriptor.
128
///
129
/// Note this class is designed to be a base class of TargetRegisterInfo, which
130
/// is the interface used by codegen. However, specific targets *should never*
131
/// specialize this class. MCRegisterInfo should only contain getters to access
132
/// TableGen generated physical register data. It must not be extended with
133
/// virtual methods.
134
///
135
class MCRegisterInfo {
136
public:
137
  using regclass_iterator = const MCRegisterClass *;
138
139
  /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
140
  /// performed with a binary search.
141
  struct DwarfLLVMRegPair {
142
    unsigned FromReg;
143
    unsigned ToReg;
144
145
6.73M
    bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
146
  };
147
148
  /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
149
  /// index, -1 in any being invalid.
150
  struct SubRegCoveredBits {
151
    uint16_t Offset;
152
    uint16_t Size;
153
  };
154
155
private:
156
  const MCRegisterDesc *Desc;                 // Pointer to the descriptor array
157
  unsigned NumRegs;                           // Number of entries in the array
158
  unsigned RAReg;                             // Return address register
159
  unsigned PCReg;                             // Program counter register
160
  const MCRegisterClass *Classes;             // Pointer to the regclass array
161
  unsigned NumClasses;                        // Number of entries in the array
162
  unsigned NumRegUnits;                       // Number of regunits.
163
  const MCPhysReg (*RegUnitRoots)[2];         // Pointer to regunit root table.
164
  const MCPhysReg *DiffLists;                 // Pointer to the difflists array
165
  const LaneBitmask *RegUnitMaskSequences;    // Pointer to lane mask sequences
166
                                              // for register units.
167
  const char *RegStrings;                     // Pointer to the string table.
168
  const char *RegClassStrings;                // Pointer to the class strings.
169
  const uint16_t *SubRegIndices;              // Pointer to the subreg lookup
170
                                              // array.
171
  const SubRegCoveredBits *SubRegIdxRanges;   // Pointer to the subreg covered
172
                                              // bit ranges array.
173
  unsigned NumSubRegIndices;                  // Number of subreg indices.
174
  const uint16_t *RegEncodingTable;           // Pointer to array of register
175
                                              // encodings.
176
177
  unsigned L2DwarfRegsSize;
178
  unsigned EHL2DwarfRegsSize;
179
  unsigned Dwarf2LRegsSize;
180
  unsigned EHDwarf2LRegsSize;
181
  const DwarfLLVMRegPair *L2DwarfRegs;        // LLVM to Dwarf regs mapping
182
  const DwarfLLVMRegPair *EHL2DwarfRegs;      // LLVM to Dwarf regs mapping EH
183
  const DwarfLLVMRegPair *Dwarf2LRegs;        // Dwarf to LLVM regs mapping
184
  const DwarfLLVMRegPair *EHDwarf2LRegs;      // Dwarf to LLVM regs mapping EH
185
  DenseMap<unsigned, int> L2SEHRegs;          // LLVM to SEH regs mapping
186
  DenseMap<unsigned, int> L2CVRegs;           // LLVM to CV regs mapping
187
188
public:
189
  /// DiffListIterator - Base iterator class that can traverse the
190
  /// differentially encoded register and regunit lists in DiffLists.
191
  /// Don't use this class directly, use one of the specialized sub-classes
192
  /// defined below.
193
0
  class DiffListIterator {
194
    uint16_t Val = 0;
195
    const MCPhysReg *List = nullptr;
196
197
  protected:
198
    /// Create an invalid iterator. Call init() to point to something useful.
199
1.68G
    DiffListIterator() = default;
200
201
    /// init - Point the iterator to InitVal, decoding subsequent values from
202
    /// DiffList. The iterator will initially point to InitVal, sub-classes are
203
    /// responsible for skipping the seed value if it is not part of the list.
204
1.20G
    void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
205
1.20G
      Val = InitVal;
206
1.20G
      List = DiffList;
207
1.20G
    }
208
209
    /// advance - Move to the next list position, return the applied
210
    /// differential. This function does not detect the end of the list, that
211
    /// is the caller's responsibility (by checking for a 0 return value).
212
3.31G
    unsigned advance() {
213
3.31G
      assert(isValid() && "Cannot move off the end of the list.");
214
3.31G
      MCPhysReg D = *List++;
215
3.31G
      Val += D;
216
3.31G
      return D;
217
3.31G
    }
218
219
  public:
220
    /// isValid - returns true if this iterator is not yet at the end.
221
5.44G
    bool isValid() const { return List; }
222
223
    /// Dereference the iterator to get the value at the current position.
224
3.59G
    unsigned operator*() const { return Val; }
225
226
    /// Pre-increment to move to the next position.
227
2.72G
    void operator++() {
228
2.72G
      // The end of the list is encoded as a 0 differential.
229
2.72G
      if (!advance())
230
910M
        List = nullptr;
231
2.72G
    }
232
  };
233
234
  // These iterators are allowed to sub-class DiffListIterator and access
235
  // internal list pointers.
236
  friend class MCSubRegIterator;
237
  friend class MCSubRegIndexIterator;
238
  friend class MCSuperRegIterator;
239
  friend class MCRegUnitIterator;
240
  friend class MCRegUnitMaskIterator;
241
  friend class MCRegUnitRootIterator;
242
243
  /// Initialize MCRegisterInfo, called by TableGen
244
  /// auto-generated routines. *DO NOT USE*.
245
  void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
246
                          unsigned PC,
247
                          const MCRegisterClass *C, unsigned NC,
248
                          const MCPhysReg (*RURoots)[2],
249
                          unsigned NRU,
250
                          const MCPhysReg *DL,
251
                          const LaneBitmask *RUMS,
252
                          const char *Strings,
253
                          const char *ClassStrings,
254
                          const uint16_t *SubIndices,
255
                          unsigned NumIndices,
256
                          const SubRegCoveredBits *SubIdxRanges,
257
101k
                          const uint16_t *RET) {
258
101k
    Desc = D;
259
101k
    NumRegs = NR;
260
101k
    RAReg = RA;
261
101k
    PCReg = PC;
262
101k
    Classes = C;
263
101k
    DiffLists = DL;
264
101k
    RegUnitMaskSequences = RUMS;
265
101k
    RegStrings = Strings;
266
101k
    RegClassStrings = ClassStrings;
267
101k
    NumClasses = NC;
268
101k
    RegUnitRoots = RURoots;
269
101k
    NumRegUnits = NRU;
270
101k
    SubRegIndices = SubIndices;
271
101k
    NumSubRegIndices = NumIndices;
272
101k
    SubRegIdxRanges = SubIdxRanges;
273
101k
    RegEncodingTable = RET;
274
101k
275
101k
    // Initialize DWARF register mapping variables
276
101k
    EHL2DwarfRegs = nullptr;
277
101k
    EHL2DwarfRegsSize = 0;
278
101k
    L2DwarfRegs = nullptr;
279
101k
    L2DwarfRegsSize = 0;
280
101k
    EHDwarf2LRegs = nullptr;
281
101k
    EHDwarf2LRegsSize = 0;
282
101k
    Dwarf2LRegs = nullptr;
283
101k
    Dwarf2LRegsSize = 0;
284
101k
  }
285
286
  /// Used to initialize LLVM register to Dwarf
287
  /// register number mapping. Called by TableGen auto-generated routines.
288
  /// *DO NOT USE*.
289
  void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
290
199k
                              bool isEH) {
291
199k
    if (isEH) {
292
99.5k
      EHL2DwarfRegs = Map;
293
99.5k
      EHL2DwarfRegsSize = Size;
294
99.5k
    } else {
295
99.5k
      L2DwarfRegs = Map;
296
99.5k
      L2DwarfRegsSize = Size;
297
99.5k
    }
298
199k
  }
299
300
  /// Used to initialize Dwarf register to LLVM
301
  /// register number mapping. Called by TableGen auto-generated routines.
302
  /// *DO NOT USE*.
303
  void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
304
199k
                              bool isEH) {
305
199k
    if (isEH) {
306
99.5k
      EHDwarf2LRegs = Map;
307
99.5k
      EHDwarf2LRegsSize = Size;
308
99.5k
    } else {
309
99.5k
      Dwarf2LRegs = Map;
310
99.5k
      Dwarf2LRegsSize = Size;
311
99.5k
    }
312
199k
  }
313
314
  /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
315
  /// number mapping. By default the SEH register number is just the same
316
  /// as the LLVM register number.
317
  /// FIXME: TableGen these numbers. Currently this requires target specific
318
  /// initialization code.
319
10.1M
  void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
320
10.1M
    L2SEHRegs[LLVMReg] = SEHReg;
321
10.1M
  }
322
323
17.1M
  void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg) {
324
17.1M
    L2CVRegs[LLVMReg] = CVReg;
325
17.1M
  }
326
327
  /// This method should return the register where the return
328
  /// address can be found.
329
56.8k
  unsigned getRARegister() const {
330
56.8k
    return RAReg;
331
56.8k
  }
332
333
  /// Return the register which is the program counter.
334
681
  unsigned getProgramCounter() const {
335
681
    return PCReg;
336
681
  }
337
338
1.32G
  const MCRegisterDesc &operator[](unsigned RegNo) const {
339
1.32G
    assert(RegNo < NumRegs &&
340
1.32G
           "Attempting to access record for invalid register number!");
341
1.32G
    return Desc[RegNo];
342
1.32G
  }
343
344
  /// Provide a get method, equivalent to [], but more useful with a
345
  /// pointer to this object.
346
1.32G
  const MCRegisterDesc &get(unsigned RegNo) const {
347
1.32G
    return operator[](RegNo);
348
1.32G
  }
349
350
  /// Returns the physical register number of sub-register "Index"
351
  /// for physical register RegNo. Return zero if the sub-register does not
352
  /// exist.
353
  unsigned getSubReg(unsigned Reg, unsigned Idx) const;
354
355
  /// Return a super-register of the specified register
356
  /// Reg so its sub-register of index SubIdx is Reg.
357
  unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
358
                               const MCRegisterClass *RC) const;
359
360
  /// For a given register pair, return the sub-register index
361
  /// if the second register is a sub-register of the first. Return zero
362
  /// otherwise.
363
  unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
364
365
  /// Get the size of the bit range covered by a sub-register index.
366
  /// If the index isn't continuous, return the sum of the sizes of its parts.
367
  /// If the index is used to access subregisters of different sizes, return -1.
368
  unsigned getSubRegIdxSize(unsigned Idx) const;
369
370
  /// Get the offset of the bit range covered by a sub-register index.
371
  /// If an Offset doesn't make sense (the index isn't continuous, or is used to
372
  /// access sub-registers at different offsets), return -1.
373
  unsigned getSubRegIdxOffset(unsigned Idx) const;
374
375
  /// Return the human-readable symbolic target-specific name for the
376
  /// specified physical register.
377
102M
  const char *getName(unsigned RegNo) const {
378
102M
    return RegStrings + get(RegNo).Name;
379
102M
  }
380
381
  /// Return the number of registers this target has (useful for
382
  /// sizing arrays holding per register information)
383
67.3M
  unsigned getNumRegs() const {
384
67.3M
    return NumRegs;
385
67.3M
  }
386
387
  /// Return the number of sub-register indices
388
  /// understood by the target. Index 0 is reserved for the no-op sub-register,
389
  /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
390
304
  unsigned getNumSubRegIndices() const {
391
304
    return NumSubRegIndices;
392
304
  }
393
394
  /// Return the number of (native) register units in the
395
  /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
396
  /// can be accessed through MCRegUnitIterator defined below.
397
9.16M
  unsigned getNumRegUnits() const {
398
9.16M
    return NumRegUnits;
399
9.16M
  }
400
401
  /// Map a target register to an equivalent dwarf register
402
  /// number.  Returns -1 if there is no equivalent value.  The second
403
  /// parameter allows targets to use different numberings for EH info and
404
  /// debugging info.
405
  int getDwarfRegNum(unsigned RegNum, bool isEH) const;
406
407
  /// Map a dwarf register back to a target register.
408
  int getLLVMRegNum(unsigned RegNum, bool isEH) const;
409
410
  /// Map a DWARF EH register back to a target register (same as
411
  /// getLLVMRegNum(RegNum, true)) but return -1 if there is no mapping,
412
  /// rather than asserting that there must be one.
413
  int getLLVMRegNumFromEH(unsigned RegNum) const;
414
415
  /// Map a target EH register number to an equivalent DWARF register
416
  /// number.
417
  int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const;
418
419
  /// Map a target register to an equivalent SEH register
420
  /// number.  Returns LLVM register number if there is no equivalent value.
421
  int getSEHRegNum(unsigned RegNum) const;
422
423
  /// Map a target register to an equivalent CodeView register
424
  /// number.
425
  int getCodeViewRegNum(unsigned RegNum) const;
426
427
0
  regclass_iterator regclass_begin() const { return Classes; }
428
0
  regclass_iterator regclass_end() const { return Classes+NumClasses; }
429
0
  iterator_range<regclass_iterator> regclasses() const {
430
0
    return make_range(regclass_begin(), regclass_end());
431
0
  }
432
433
0
  unsigned getNumRegClasses() const {
434
0
    return (unsigned)(regclass_end()-regclass_begin());
435
0
  }
436
437
  /// Returns the register class associated with the enumeration
438
  /// value.  See class MCOperandInfo.
439
4.20M
  const MCRegisterClass& getRegClass(unsigned i) const {
440
4.20M
    assert(i < getNumRegClasses() && "Register Class ID out of range");
441
4.20M
    return Classes[i];
442
4.20M
  }
443
444
114k
  const char *getRegClassName(const MCRegisterClass *Class) const {
445
114k
    return RegClassStrings + Class->NameIdx;
446
114k
  }
447
448
   /// Returns the encoding for RegNo
449
63.1M
  uint16_t getEncodingValue(unsigned RegNo) const {
450
63.1M
    assert(RegNo < NumRegs &&
451
63.1M
           "Attempting to get encoding for invalid register number!");
452
63.1M
    return RegEncodingTable[RegNo];
453
63.1M
  }
454
455
  /// Returns true if RegB is a sub-register of RegA.
456
30.5M
  bool isSubRegister(unsigned RegA, unsigned RegB) const {
457
30.5M
    return isSuperRegister(RegB, RegA);
458
30.5M
  }
459
460
  /// Returns true if RegB is a super-register of RegA.
461
  bool isSuperRegister(unsigned RegA, unsigned RegB) const;
462
463
  /// Returns true if RegB is a sub-register of RegA or if RegB == RegA.
464
2.29k
  bool isSubRegisterEq(unsigned RegA, unsigned RegB) const {
465
2.29k
    return isSuperRegisterEq(RegB, RegA);
466
2.29k
  }
467
468
  /// Returns true if RegB is a super-register of RegA or if
469
  /// RegB == RegA.
470
65.8k
  bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const {
471
65.8k
    return RegA == RegB || 
isSuperRegister(RegA, RegB)2.87k
;
472
65.8k
  }
473
474
  /// Returns true if RegB is a super-register or sub-register of RegA
475
  /// or if RegB == RegA.
476
758
  bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const {
477
758
    return isSubRegisterEq(RegA, RegB) || 
isSuperRegister(RegA, RegB)544
;
478
758
  }
479
};
480
481
//===----------------------------------------------------------------------===//
482
//                          Register List Iterators
483
//===----------------------------------------------------------------------===//
484
485
// MCRegisterInfo provides lists of super-registers, sub-registers, and
486
// aliasing registers. Use these iterator classes to traverse the lists.
487
488
/// MCSubRegIterator enumerates all sub-registers of Reg.
489
/// If IncludeSelf is set, Reg itself is included in the list.
490
class MCSubRegIterator : public MCRegisterInfo::DiffListIterator {
491
public:
492
  MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
493
238M
                     bool IncludeSelf = false) {
494
238M
    init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
495
238M
    // Initially, the iterator points to Reg itself.
496
238M
    if (!IncludeSelf)
497
109M
      ++*this;
498
238M
  }
499
};
500
501
/// Iterator that enumerates the sub-registers of a Reg and the associated
502
/// sub-register indices.
503
class MCSubRegIndexIterator {
504
  MCSubRegIterator SRIter;
505
  const uint16_t *SRIndex;
506
507
public:
508
  /// Constructs an iterator that traverses subregisters and their
509
  /// associated subregister indices.
510
  MCSubRegIndexIterator(unsigned Reg, const MCRegisterInfo *MCRI)
511
4.33M
    : SRIter(Reg, MCRI) {
512
4.33M
    SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices;
513
4.33M
  }
514
515
  /// Returns current sub-register.
516
8.97k
  unsigned getSubReg() const {
517
8.97k
    return *SRIter;
518
8.97k
  }
519
520
  /// Returns sub-register index of the current sub-register.
521
13.0k
  unsigned getSubRegIndex() const {
522
13.0k
    return *SRIndex;
523
13.0k
  }
524
525
  /// Returns true if this iterator is not yet at the end.
526
113k
  bool isValid() const { return SRIter.isValid(); }
527
528
  /// Moves to the next position.
529
13.0k
  void operator++() {
530
13.0k
    ++SRIter;
531
13.0k
    ++SRIndex;
532
13.0k
  }
533
};
534
535
/// MCSuperRegIterator enumerates all super-registers of Reg.
536
/// If IncludeSelf is set, Reg itself is included in the list.
537
0
class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator {
538
public:
539
237M
  MCSuperRegIterator() = default;
540
541
  MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
542
376M
                     bool IncludeSelf = false) {
543
376M
    init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
544
376M
    // Initially, the iterator points to Reg itself.
545
376M
    if (!IncludeSelf)
546
78.6M
      ++*this;
547
376M
  }
548
};
549
550
// Definition for isSuperRegister. Put it down here since it needs the
551
// iterator defined above in addition to the MCRegisterInfo class itself.
552
66.8M
inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{
553
251M
  for (MCSuperRegIterator I(RegA, this); I.isValid(); 
++I184M
)
554
198M
    if (*I == RegB)
555
13.8M
      return true;
556
66.8M
  
return false53.0M
;
557
66.8M
}
558
559
//===----------------------------------------------------------------------===//
560
//                               Register Units
561
//===----------------------------------------------------------------------===//
562
563
// Register units are used to compute register aliasing. Every register has at
564
// least one register unit, but it can have more. Two registers overlap if and
565
// only if they have a common register unit.
566
//
567
// A target with a complicated sub-register structure will typically have many
568
// fewer register units than actual registers. MCRI::getNumRegUnits() returns
569
// the number of register units in the target.
570
571
// MCRegUnitIterator enumerates a list of register units for Reg. The list is
572
// in ascending numerical order.
573
0
class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
574
public:
575
  /// MCRegUnitIterator - Create an iterator that traverses the register units
576
  /// in Reg.
577
237M
  MCRegUnitIterator() = default;
578
579
593M
  MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
580
593M
    assert(Reg && "Null register has no regunits");
581
593M
    // Decode the RegUnits MCRegisterDesc field.
582
593M
    unsigned RU = MCRI->get(Reg).RegUnits;
583
593M
    unsigned Scale = RU & 15;
584
593M
    unsigned Offset = RU >> 4;
585
593M
586
593M
    // Initialize the iterator to Reg * Scale, and the List pointer to
587
593M
    // DiffLists + Offset.
588
593M
    init(Reg * Scale, MCRI->DiffLists + Offset);
589
593M
590
593M
    // That may not be a valid unit, we need to advance by one to get the real
591
593M
    // unit number. The first differential can be 0 which would normally
592
593M
    // terminate the list, but since we know every register has at least one
593
593M
    // unit, we can allow a 0 differential here.
594
593M
    advance();
595
593M
  }
596
};
597
598
/// MCRegUnitMaskIterator enumerates a list of register units and their
599
/// associated lane masks for Reg. The register units are in ascending
600
/// numerical order.
601
class MCRegUnitMaskIterator {
602
  MCRegUnitIterator RUIter;
603
  const LaneBitmask *MaskListIter;
604
605
public:
606
  MCRegUnitMaskIterator() = default;
607
608
  /// Constructs an iterator that traverses the register units and their
609
  /// associated LaneMasks in Reg.
610
  MCRegUnitMaskIterator(unsigned Reg, const MCRegisterInfo *MCRI)
611
7.59M
    : RUIter(Reg, MCRI) {
612
7.59M
      uint16_t Idx = MCRI->get(Reg).RegUnitLaneMasks;
613
7.59M
      MaskListIter = &MCRI->RegUnitMaskSequences[Idx];
614
7.59M
  }
615
616
  /// Returns a (RegUnit, LaneMask) pair.
617
16.3M
  std::pair<unsigned,LaneBitmask> operator*() const {
618
16.3M
    return std::make_pair(*RUIter, *MaskListIter);
619
16.3M
  }
620
621
  /// Returns true if this iterator is not yet at the end.
622
16.0M
  bool isValid() const { return RUIter.isValid(); }
623
624
  /// Moves to the next position.
625
8.15M
  void operator++() {
626
8.15M
    ++MaskListIter;
627
8.15M
    ++RUIter;
628
8.15M
  }
629
};
630
631
// Each register unit has one or two root registers. The complete set of
632
// registers containing a register unit is the union of the roots and their
633
// super-registers. All registers aliasing Unit can be visited like this:
634
//
635
//   for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
636
//     for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
637
//       visit(*SI);
638
//    }
639
640
/// MCRegUnitRootIterator enumerates the root registers of a register unit.
641
0
class MCRegUnitRootIterator {
642
  uint16_t Reg0 = 0;
643
  uint16_t Reg1 = 0;
644
645
public:
646
237M
  MCRegUnitRootIterator() = default;
647
648
367M
  MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
649
367M
    assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
650
367M
    Reg0 = MCRI->RegUnitRoots[RegUnit][0];
651
367M
    Reg1 = MCRI->RegUnitRoots[RegUnit][1];
652
367M
  }
653
654
  /// Dereference to get the current root register.
655
367M
  unsigned operator*() const {
656
367M
    return Reg0;
657
367M
  }
658
659
  /// Check if the iterator is at the end of the list.
660
646M
  bool isValid() const {
661
646M
    return Reg0;
662
646M
  }
663
664
  /// Preincrement to move to the next root register.
665
326M
  void operator++() {
666
326M
    assert(isValid() && "Cannot move off the end of the list.");
667
326M
    Reg0 = Reg1;
668
326M
    Reg1 = 0;
669
326M
  }
670
};
671
672
/// MCRegAliasIterator enumerates all registers aliasing Reg.  If IncludeSelf is
673
/// set, Reg itself is included in the list.  This iterator does not guarantee
674
/// any ordering or that entries are unique.
675
class MCRegAliasIterator {
676
private:
677
  unsigned Reg;
678
  const MCRegisterInfo *MCRI;
679
  bool IncludeSelf;
680
681
  MCRegUnitIterator RI;
682
  MCRegUnitRootIterator RRI;
683
  MCSuperRegIterator SI;
684
685
public:
686
  MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI,
687
                     bool IncludeSelf)
688
237M
    : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
689
237M
    // Initialize the iterators.
690
239M
    for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); 
++RI2.10M
) {
691
239M
      for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); 
++RRI2.11M
) {
692
253M
        for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); 
++SI16.4M
) {
693
251M
          if (!(!IncludeSelf && 
Reg == *SI46.8M
))
694
234M
            return;
695
251M
        }
696
237M
      }
697
237M
    }
698
237M
  }
699
700
1.67G
  bool isValid() const { return RI.isValid(); }
701
702
2.07G
  unsigned operator*() const {
703
2.07G
    assert(SI.isValid() && "Cannot dereference an invalid iterator.");
704
2.07G
    return *SI;
705
2.07G
  }
706
707
1.43G
  void advance() {
708
1.43G
    // Assuming SI is valid.
709
1.43G
    ++SI;
710
1.43G
    if (SI.isValid()) 
return1.19G
;
711
241M
712
241M
    ++RRI;
713
241M
    if (RRI.isValid()) {
714
56.8k
      SI = MCSuperRegIterator(*RRI, MCRI, true);
715
56.8k
      return;
716
56.8k
    }
717
241M
718
241M
    ++RI;
719
241M
    if (RI.isValid()) {
720
46.8M
      RRI = MCRegUnitRootIterator(*RI, MCRI);
721
46.8M
      SI = MCSuperRegIterator(*RRI, MCRI, true);
722
46.8M
    }
723
241M
  }
724
725
1.43G
  void operator++() {
726
1.43G
    assert(isValid() && "Cannot move off the end of the list.");
727
1.43G
    do advance();
728
1.43G
    while (!IncludeSelf && 
isValid()6.68M
&&
*SI == Reg5.71M
);
729
1.43G
  }
730
};
731
732
} // end namespace llvm
733
734
#endif // LLVM_MC_MCREGISTERINFO_H