Coverage Report

Created: 2018-11-12 17:33

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/MC/MCRegisterInfo.h
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//===- MC/MCRegisterInfo.h - Target Register Description --------*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes an abstract interface used to get information about a
11
// target machines register file.  This information is used for a variety of
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// purposed, especially register allocation.
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//
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//===----------------------------------------------------------------------===//
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16
#ifndef LLVM_MC_MCREGISTERINFO_H
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#define LLVM_MC_MCREGISTERINFO_H
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19
#include "llvm/ADT/DenseMap.h"
20
#include "llvm/ADT/iterator_range.h"
21
#include "llvm/MC/LaneBitmask.h"
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#include <cassert>
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#include <cstdint>
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#include <utility>
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namespace llvm {
27
28
/// An unsigned integer type large enough to represent all physical registers,
29
/// but not necessarily virtual registers.
30
using MCPhysReg = uint16_t;
31
32
/// MCRegisterClass - Base class of TargetRegisterClass.
33
class MCRegisterClass {
34
public:
35
  using iterator = const MCPhysReg*;
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  using const_iterator = const MCPhysReg*;
37
38
  const iterator RegsBegin;
39
  const uint8_t *const RegSet;
40
  const uint32_t NameIdx;
41
  const uint16_t RegsSize;
42
  const uint16_t RegSetSize;
43
  const uint16_t ID;
44
  const int8_t CopyCost;
45
  const bool Allocatable;
46
47
  /// getID() - Return the register class ID number.
48
  ///
49
538M
  unsigned getID() const { return ID; }
50
51
  /// begin/end - Return all of the registers in this class.
52
  ///
53
18.0M
  iterator       begin() const { return RegsBegin; }
54
16.9M
  iterator         end() const { return RegsBegin + RegsSize; }
55
56
  /// getNumRegs - Return the number of registers in this class.
57
  ///
58
568M
  unsigned getNumRegs() const { return RegsSize; }
59
60
  /// getRegister - Return the specified register in the class.
61
  ///
62
18.3M
  unsigned getRegister(unsigned i) const {
63
18.3M
    assert(i < getNumRegs() && "Register number out of range!");
64
18.3M
    return RegsBegin[i];
65
18.3M
  }
66
67
  /// contains - Return true if the specified register is included in this
68
  /// register class.  This does not include virtual registers.
69
1.08G
  bool contains(unsigned Reg) const {
70
1.08G
    unsigned InByte = Reg % 8;
71
1.08G
    unsigned Byte = Reg / 8;
72
1.08G
    if (Byte >= RegSetSize)
73
431M
      return false;
74
653M
    return (RegSet[Byte] & (1 << InByte)) != 0;
75
653M
  }
76
77
  /// contains - Return true if both registers are in this class.
78
667k
  bool contains(unsigned Reg1, unsigned Reg2) const {
79
667k
    return contains(Reg1) && 
contains(Reg2)334k
;
80
667k
  }
81
82
  /// getCopyCost - Return the cost of copying a value between two registers in
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  /// this class. A negative number means the register class is very expensive
84
  /// to copy e.g. status flag register classes.
85
1.32M
  int getCopyCost() const { return CopyCost; }
86
87
  /// isAllocatable - Return true if this register class may be used to create
88
  /// virtual registers.
89
14.6M
  bool isAllocatable() const { return Allocatable; }
90
};
91
92
/// MCRegisterDesc - This record contains information about a particular
93
/// register.  The SubRegs field is a zero terminated array of registers that
94
/// are sub-registers of the specific register, e.g. AL, AH are sub-registers
95
/// of AX. The SuperRegs field is a zero terminated array of registers that are
96
/// super-registers of the specific register, e.g. RAX, EAX, are
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/// super-registers of AX.
98
///
99
struct MCRegisterDesc {
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  uint32_t Name;      // Printable name for the reg (for debugging)
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  uint32_t SubRegs;   // Sub-register set, described above
102
  uint32_t SuperRegs; // Super-register set, described above
103
104
  // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
105
  // sub-register in SubRegs.
106
  uint32_t SubRegIndices;
107
108
  // RegUnits - Points to the list of register units. The low 4 bits holds the
109
  // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
110
  uint32_t RegUnits;
111
112
  /// Index into list with lane mask sequences. The sequence contains a lanemask
113
  /// for every register unit.
114
  uint16_t RegUnitLaneMasks;
115
};
116
117
/// MCRegisterInfo base class - We assume that the target defines a static
118
/// array of MCRegisterDesc objects that represent all of the machine
119
/// registers that the target has.  As such, we simply have to track a pointer
120
/// to this array so that we can turn register number into a register
121
/// descriptor.
122
///
123
/// Note this class is designed to be a base class of TargetRegisterInfo, which
124
/// is the interface used by codegen. However, specific targets *should never*
125
/// specialize this class. MCRegisterInfo should only contain getters to access
126
/// TableGen generated physical register data. It must not be extended with
127
/// virtual methods.
128
///
129
class MCRegisterInfo {
130
public:
131
  using regclass_iterator = const MCRegisterClass *;
132
133
  /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
134
  /// performed with a binary search.
135
  struct DwarfLLVMRegPair {
136
    unsigned FromReg;
137
    unsigned ToReg;
138
139
6.93M
    bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
140
  };
141
142
  /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
143
  /// index, -1 in any being invalid.
144
  struct SubRegCoveredBits {
145
    uint16_t Offset;
146
    uint16_t Size;
147
  };
148
149
private:
150
  const MCRegisterDesc *Desc;                 // Pointer to the descriptor array
151
  unsigned NumRegs;                           // Number of entries in the array
152
  unsigned RAReg;                             // Return address register
153
  unsigned PCReg;                             // Program counter register
154
  const MCRegisterClass *Classes;             // Pointer to the regclass array
155
  unsigned NumClasses;                        // Number of entries in the array
156
  unsigned NumRegUnits;                       // Number of regunits.
157
  const MCPhysReg (*RegUnitRoots)[2];         // Pointer to regunit root table.
158
  const MCPhysReg *DiffLists;                 // Pointer to the difflists array
159
  const LaneBitmask *RegUnitMaskSequences;    // Pointer to lane mask sequences
160
                                              // for register units.
161
  const char *RegStrings;                     // Pointer to the string table.
162
  const char *RegClassStrings;                // Pointer to the class strings.
163
  const uint16_t *SubRegIndices;              // Pointer to the subreg lookup
164
                                              // array.
165
  const SubRegCoveredBits *SubRegIdxRanges;   // Pointer to the subreg covered
166
                                              // bit ranges array.
167
  unsigned NumSubRegIndices;                  // Number of subreg indices.
168
  const uint16_t *RegEncodingTable;           // Pointer to array of register
169
                                              // encodings.
170
171
  unsigned L2DwarfRegsSize;
172
  unsigned EHL2DwarfRegsSize;
173
  unsigned Dwarf2LRegsSize;
174
  unsigned EHDwarf2LRegsSize;
175
  const DwarfLLVMRegPair *L2DwarfRegs;        // LLVM to Dwarf regs mapping
176
  const DwarfLLVMRegPair *EHL2DwarfRegs;      // LLVM to Dwarf regs mapping EH
177
  const DwarfLLVMRegPair *Dwarf2LRegs;        // Dwarf to LLVM regs mapping
178
  const DwarfLLVMRegPair *EHDwarf2LRegs;      // Dwarf to LLVM regs mapping EH
179
  DenseMap<unsigned, int> L2SEHRegs;          // LLVM to SEH regs mapping
180
  DenseMap<unsigned, int> L2CVRegs;           // LLVM to CV regs mapping
181
182
public:
183
  /// DiffListIterator - Base iterator class that can traverse the
184
  /// differentially encoded register and regunit lists in DiffLists.
185
  /// Don't use this class directly, use one of the specialized sub-classes
186
  /// defined below.
187
0
  class DiffListIterator {
188
    uint16_t Val = 0;
189
    const MCPhysReg *List = nullptr;
190
191
  protected:
192
    /// Create an invalid iterator. Call init() to point to something useful.
193
1.53G
    DiffListIterator() = default;
194
195
    /// init - Point the iterator to InitVal, decoding subsequent values from
196
    /// DiffList. The iterator will initially point to InitVal, sub-classes are
197
    /// responsible for skipping the seed value if it is not part of the list.
198
1.21G
    void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
199
1.21G
      Val = InitVal;
200
1.21G
      List = DiffList;
201
1.21G
    }
202
203
    /// advance - Move to the next list position, return the applied
204
    /// differential. This function does not detect the end of the list, that
205
    /// is the caller's responsibility (by checking for a 0 return value).
206
3.21G
    unsigned advance() {
207
3.21G
      assert(isValid() && "Cannot move off the end of the list.");
208
3.21G
      MCPhysReg D = *List++;
209
3.21G
      Val += D;
210
3.21G
      return D;
211
3.21G
    }
212
213
  public:
214
    /// isValid - returns true if this iterator is not yet at the end.
215
4.72G
    bool isValid() const { return List; }
216
217
    /// Dereference the iterator to get the value at the current position.
218
2.99G
    unsigned operator*() const { return Val; }
219
220
    /// Pre-increment to move to the next position.
221
2.58G
    void operator++() {
222
2.58G
      // The end of the list is encoded as a 0 differential.
223
2.58G
      if (!advance())
224
909M
        List = nullptr;
225
2.58G
    }
226
  };
227
228
  // These iterators are allowed to sub-class DiffListIterator and access
229
  // internal list pointers.
230
  friend class MCSubRegIterator;
231
  friend class MCSubRegIndexIterator;
232
  friend class MCSuperRegIterator;
233
  friend class MCRegUnitIterator;
234
  friend class MCRegUnitMaskIterator;
235
  friend class MCRegUnitRootIterator;
236
237
  /// Initialize MCRegisterInfo, called by TableGen
238
  /// auto-generated routines. *DO NOT USE*.
239
  void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
240
                          unsigned PC,
241
                          const MCRegisterClass *C, unsigned NC,
242
                          const MCPhysReg (*RURoots)[2],
243
                          unsigned NRU,
244
                          const MCPhysReg *DL,
245
                          const LaneBitmask *RUMS,
246
                          const char *Strings,
247
                          const char *ClassStrings,
248
                          const uint16_t *SubIndices,
249
                          unsigned NumIndices,
250
                          const SubRegCoveredBits *SubIdxRanges,
251
107k
                          const uint16_t *RET) {
252
107k
    Desc = D;
253
107k
    NumRegs = NR;
254
107k
    RAReg = RA;
255
107k
    PCReg = PC;
256
107k
    Classes = C;
257
107k
    DiffLists = DL;
258
107k
    RegUnitMaskSequences = RUMS;
259
107k
    RegStrings = Strings;
260
107k
    RegClassStrings = ClassStrings;
261
107k
    NumClasses = NC;
262
107k
    RegUnitRoots = RURoots;
263
107k
    NumRegUnits = NRU;
264
107k
    SubRegIndices = SubIndices;
265
107k
    NumSubRegIndices = NumIndices;
266
107k
    SubRegIdxRanges = SubIdxRanges;
267
107k
    RegEncodingTable = RET;
268
107k
269
107k
    // Initialize DWARF register mapping variables
270
107k
    EHL2DwarfRegs = nullptr;
271
107k
    EHL2DwarfRegsSize = 0;
272
107k
    L2DwarfRegs = nullptr;
273
107k
    L2DwarfRegsSize = 0;
274
107k
    EHDwarf2LRegs = nullptr;
275
107k
    EHDwarf2LRegsSize = 0;
276
107k
    Dwarf2LRegs = nullptr;
277
107k
    Dwarf2LRegsSize = 0;
278
107k
  }
279
280
  /// Used to initialize LLVM register to Dwarf
281
  /// register number mapping. Called by TableGen auto-generated routines.
282
  /// *DO NOT USE*.
283
  void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
284
209k
                              bool isEH) {
285
209k
    if (isEH) {
286
104k
      EHL2DwarfRegs = Map;
287
104k
      EHL2DwarfRegsSize = Size;
288
104k
    } else {
289
104k
      L2DwarfRegs = Map;
290
104k
      L2DwarfRegsSize = Size;
291
104k
    }
292
209k
  }
293
294
  /// Used to initialize Dwarf register to LLVM
295
  /// register number mapping. Called by TableGen auto-generated routines.
296
  /// *DO NOT USE*.
297
  void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
298
209k
                              bool isEH) {
299
209k
    if (isEH) {
300
104k
      EHDwarf2LRegs = Map;
301
104k
      EHDwarf2LRegsSize = Size;
302
104k
    } else {
303
104k
      Dwarf2LRegs = Map;
304
104k
      Dwarf2LRegsSize = Size;
305
104k
    }
306
209k
  }
307
308
  /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
309
  /// number mapping. By default the SEH register number is just the same
310
  /// as the LLVM register number.
311
  /// FIXME: TableGen these numbers. Currently this requires target specific
312
  /// initialization code.
313
10.6M
  void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
314
10.6M
    L2SEHRegs[LLVMReg] = SEHReg;
315
10.6M
  }
316
317
20.8M
  void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg) {
318
20.8M
    L2CVRegs[LLVMReg] = CVReg;
319
20.8M
  }
320
321
  /// This method should return the register where the return
322
  /// address can be found.
323
57.7k
  unsigned getRARegister() const {
324
57.7k
    return RAReg;
325
57.7k
  }
326
327
  /// Return the register which is the program counter.
328
2.16k
  unsigned getProgramCounter() const {
329
2.16k
    return PCReg;
330
2.16k
  }
331
332
1.34G
  const MCRegisterDesc &operator[](unsigned RegNo) const {
333
1.34G
    assert(RegNo < NumRegs &&
334
1.34G
           "Attempting to access record for invalid register number!");
335
1.34G
    return Desc[RegNo];
336
1.34G
  }
337
338
  /// Provide a get method, equivalent to [], but more useful with a
339
  /// pointer to this object.
340
1.34G
  const MCRegisterDesc &get(unsigned RegNo) const {
341
1.34G
    return operator[](RegNo);
342
1.34G
  }
343
344
  /// Returns the physical register number of sub-register "Index"
345
  /// for physical register RegNo. Return zero if the sub-register does not
346
  /// exist.
347
  unsigned getSubReg(unsigned Reg, unsigned Idx) const;
348
349
  /// Return a super-register of the specified register
350
  /// Reg so its sub-register of index SubIdx is Reg.
351
  unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
352
                               const MCRegisterClass *RC) const;
353
354
  /// For a given register pair, return the sub-register index
355
  /// if the second register is a sub-register of the first. Return zero
356
  /// otherwise.
357
  unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
358
359
  /// Get the size of the bit range covered by a sub-register index.
360
  /// If the index isn't continuous, return the sum of the sizes of its parts.
361
  /// If the index is used to access subregisters of different sizes, return -1.
362
  unsigned getSubRegIdxSize(unsigned Idx) const;
363
364
  /// Get the offset of the bit range covered by a sub-register index.
365
  /// If an Offset doesn't make sense (the index isn't continuous, or is used to
366
  /// access sub-registers at different offsets), return -1.
367
  unsigned getSubRegIdxOffset(unsigned Idx) const;
368
369
  /// Return the human-readable symbolic target-specific name for the
370
  /// specified physical register.
371
115M
  const char *getName(unsigned RegNo) const {
372
115M
    return RegStrings + get(RegNo).Name;
373
115M
  }
374
375
  /// Return the number of registers this target has (useful for
376
  /// sizing arrays holding per register information)
377
87.2M
  unsigned getNumRegs() const {
378
87.2M
    return NumRegs;
379
87.2M
  }
380
381
  /// Return the number of sub-register indices
382
  /// understood by the target. Index 0 is reserved for the no-op sub-register,
383
  /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
384
353
  unsigned getNumSubRegIndices() const {
385
353
    return NumSubRegIndices;
386
353
  }
387
388
  /// Return the number of (native) register units in the
389
  /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
390
  /// can be accessed through MCRegUnitIterator defined below.
391
9.37M
  unsigned getNumRegUnits() const {
392
9.37M
    return NumRegUnits;
393
9.37M
  }
394
395
  /// Map a target register to an equivalent dwarf register
396
  /// number.  Returns -1 if there is no equivalent value.  The second
397
  /// parameter allows targets to use different numberings for EH info and
398
  /// debugging info.
399
  int getDwarfRegNum(unsigned RegNum, bool isEH) const;
400
401
  /// Map a dwarf register back to a target register.
402
  int getLLVMRegNum(unsigned RegNum, bool isEH) const;
403
404
  /// Map a DWARF EH register back to a target register (same as
405
  /// getLLVMRegNum(RegNum, true)) but return -1 if there is no mapping,
406
  /// rather than asserting that there must be one.
407
  int getLLVMRegNumFromEH(unsigned RegNum) const;
408
409
  /// Map a target EH register number to an equivalent DWARF register
410
  /// number.
411
  int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const;
412
413
  /// Map a target register to an equivalent SEH register
414
  /// number.  Returns LLVM register number if there is no equivalent value.
415
  int getSEHRegNum(unsigned RegNum) const;
416
417
  /// Map a target register to an equivalent CodeView register
418
  /// number.
419
  int getCodeViewRegNum(unsigned RegNum) const;
420
421
0
  regclass_iterator regclass_begin() const { return Classes; }
422
0
  regclass_iterator regclass_end() const { return Classes+NumClasses; }
423
0
  iterator_range<regclass_iterator> regclasses() const {
424
0
    return make_range(regclass_begin(), regclass_end());
425
0
  }
426
427
0
  unsigned getNumRegClasses() const {
428
0
    return (unsigned)(regclass_end()-regclass_begin());
429
0
  }
430
431
  /// Returns the register class associated with the enumeration
432
  /// value.  See class MCOperandInfo.
433
4.06M
  const MCRegisterClass& getRegClass(unsigned i) const {
434
4.06M
    assert(i < getNumRegClasses() && "Register Class ID out of range");
435
4.06M
    return Classes[i];
436
4.06M
  }
437
438
153k
  const char *getRegClassName(const MCRegisterClass *Class) const {
439
153k
    return RegClassStrings + Class->NameIdx;
440
153k
  }
441
442
   /// Returns the encoding for RegNo
443
65.2M
  uint16_t getEncodingValue(unsigned RegNo) const {
444
65.2M
    assert(RegNo < NumRegs &&
445
65.2M
           "Attempting to get encoding for invalid register number!");
446
65.2M
    return RegEncodingTable[RegNo];
447
65.2M
  }
448
449
  /// Returns true if RegB is a sub-register of RegA.
450
30.4M
  bool isSubRegister(unsigned RegA, unsigned RegB) const {
451
30.4M
    return isSuperRegister(RegB, RegA);
452
30.4M
  }
453
454
  /// Returns true if RegB is a super-register of RegA.
455
  bool isSuperRegister(unsigned RegA, unsigned RegB) const;
456
457
  /// Returns true if RegB is a sub-register of RegA or if RegB == RegA.
458
1.65M
  bool isSubRegisterEq(unsigned RegA, unsigned RegB) const {
459
1.65M
    return isSuperRegisterEq(RegB, RegA);
460
1.65M
  }
461
462
  /// Returns true if RegB is a super-register of RegA or if
463
  /// RegB == RegA.
464
1.72M
  bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const {
465
1.72M
    return RegA == RegB || 
isSuperRegister(RegA, RegB)98.0k
;
466
1.72M
  }
467
468
  /// Returns true if RegB is a super-register or sub-register of RegA
469
  /// or if RegB == RegA.
470
758
  bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const {
471
758
    return isSubRegisterEq(RegA, RegB) || 
isSuperRegister(RegA, RegB)544
;
472
758
  }
473
};
474
475
//===----------------------------------------------------------------------===//
476
//                          Register List Iterators
477
//===----------------------------------------------------------------------===//
478
479
// MCRegisterInfo provides lists of super-registers, sub-registers, and
480
// aliasing registers. Use these iterator classes to traverse the lists.
481
482
/// MCSubRegIterator enumerates all sub-registers of Reg.
483
/// If IncludeSelf is set, Reg itself is included in the list.
484
class MCSubRegIterator : public MCRegisterInfo::DiffListIterator {
485
public:
486
  MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
487
245M
                     bool IncludeSelf = false) {
488
245M
    init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
489
245M
    // Initially, the iterator points to Reg itself.
490
245M
    if (!IncludeSelf)
491
117M
      ++*this;
492
245M
  }
493
};
494
495
/// Iterator that enumerates the sub-registers of a Reg and the associated
496
/// sub-register indices.
497
class MCSubRegIndexIterator {
498
  MCSubRegIterator SRIter;
499
  const uint16_t *SRIndex;
500
501
public:
502
  /// Constructs an iterator that traverses subregisters and their
503
  /// associated subregister indices.
504
  MCSubRegIndexIterator(unsigned Reg, const MCRegisterInfo *MCRI)
505
4.39M
    : SRIter(Reg, MCRI) {
506
4.39M
    SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices;
507
4.39M
  }
508
509
  /// Returns current sub-register.
510
10.5k
  unsigned getSubReg() const {
511
10.5k
    return *SRIter;
512
10.5k
  }
513
514
  /// Returns sub-register index of the current sub-register.
515
15.2k
  unsigned getSubRegIndex() const {
516
15.2k
    return *SRIndex;
517
15.2k
  }
518
519
  /// Returns true if this iterator is not yet at the end.
520
114k
  bool isValid() const { return SRIter.isValid(); }
521
522
  /// Moves to the next position.
523
15.2k
  void operator++() {
524
15.2k
    ++SRIter;
525
15.2k
    ++SRIndex;
526
15.2k
  }
527
};
528
529
/// MCSuperRegIterator enumerates all super-registers of Reg.
530
/// If IncludeSelf is set, Reg itself is included in the list.
531
0
class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator {
532
public:
533
158M
  MCSuperRegIterator() = default;
534
535
  MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
536
349M
                     bool IncludeSelf = false) {
537
349M
    init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
538
349M
    // Initially, the iterator points to Reg itself.
539
349M
    if (!IncludeSelf)
540
79.0M
      ++*this;
541
349M
  }
542
};
543
544
// Definition for isSuperRegister. Put it down here since it needs the
545
// iterator defined above in addition to the MCRegisterInfo class itself.
546
67.0M
inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{
547
244M
  for (MCSuperRegIterator I(RegA, this); I.isValid(); 
++I177M
)
548
191M
    if (*I == RegB)
549
14.0M
      return true;
550
67.0M
  
return false52.9M
;
551
67.0M
}
552
553
//===----------------------------------------------------------------------===//
554
//                               Register Units
555
//===----------------------------------------------------------------------===//
556
557
// Register units are used to compute register aliasing. Every register has at
558
// least one register unit, but it can have more. Two registers overlap if and
559
// only if they have a common register unit.
560
//
561
// A target with a complicated sub-register structure will typically have many
562
// fewer register units than actual registers. MCRI::getNumRegUnits() returns
563
// the number of register units in the target.
564
565
// MCRegUnitIterator enumerates a list of register units for Reg. The list is
566
// in ascending numerical order.
567
0
class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
568
public:
569
  /// MCRegUnitIterator - Create an iterator that traverses the register units
570
  /// in Reg.
571
158M
  MCRegUnitIterator() = default;
572
573
624M
  MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
574
624M
    assert(Reg && "Null register has no regunits");
575
624M
    // Decode the RegUnits MCRegisterDesc field.
576
624M
    unsigned RU = MCRI->get(Reg).RegUnits;
577
624M
    unsigned Scale = RU & 15;
578
624M
    unsigned Offset = RU >> 4;
579
624M
580
624M
    // Initialize the iterator to Reg * Scale, and the List pointer to
581
624M
    // DiffLists + Offset.
582
624M
    init(Reg * Scale, MCRI->DiffLists + Offset);
583
624M
584
624M
    // That may not be a valid unit, we need to advance by one to get the real
585
624M
    // unit number. The first differential can be 0 which would normally
586
624M
    // terminate the list, but since we know every register has at least one
587
624M
    // unit, we can allow a 0 differential here.
588
624M
    advance();
589
624M
  }
590
};
591
592
/// MCRegUnitMaskIterator enumerates a list of register units and their
593
/// associated lane masks for Reg. The register units are in ascending
594
/// numerical order.
595
class MCRegUnitMaskIterator {
596
  MCRegUnitIterator RUIter;
597
  const LaneBitmask *MaskListIter;
598
599
public:
600
  MCRegUnitMaskIterator() = default;
601
602
  /// Constructs an iterator that traverses the register units and their
603
  /// associated LaneMasks in Reg.
604
  MCRegUnitMaskIterator(unsigned Reg, const MCRegisterInfo *MCRI)
605
6.90M
    : RUIter(Reg, MCRI) {
606
6.90M
      uint16_t Idx = MCRI->get(Reg).RegUnitLaneMasks;
607
6.90M
      MaskListIter = &MCRI->RegUnitMaskSequences[Idx];
608
6.90M
  }
609
610
  /// Returns a (RegUnit, LaneMask) pair.
611
12.7M
  std::pair<unsigned,LaneBitmask> operator*() const {
612
12.7M
    return std::make_pair(*RUIter, *MaskListIter);
613
12.7M
  }
614
615
  /// Returns true if this iterator is not yet at the end.
616
14.0M
  bool isValid() const { return RUIter.isValid(); }
617
618
  /// Moves to the next position.
619
6.90M
  void operator++() {
620
6.90M
    ++MaskListIter;
621
6.90M
    ++RUIter;
622
6.90M
  }
623
};
624
625
// Each register unit has one or two root registers. The complete set of
626
// registers containing a register unit is the union of the roots and their
627
// super-registers. All registers aliasing Unit can be visited like this:
628
//
629
//   for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
630
//     for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
631
//       visit(*SI);
632
//    }
633
634
/// MCRegUnitRootIterator enumerates the root registers of a register unit.
635
0
class MCRegUnitRootIterator {
636
  uint16_t Reg0 = 0;
637
  uint16_t Reg1 = 0;
638
639
public:
640
158M
  MCRegUnitRootIterator() = default;
641
642
275M
  MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
643
275M
    assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
644
275M
    Reg0 = MCRI->RegUnitRoots[RegUnit][0];
645
275M
    Reg1 = MCRI->RegUnitRoots[RegUnit][1];
646
275M
  }
647
648
  /// Dereference to get the current root register.
649
275M
  unsigned operator*() const {
650
275M
    return Reg0;
651
275M
  }
652
653
  /// Check if the iterator is at the end of the list.
654
477M
  bool isValid() const {
655
477M
    return Reg0;
656
477M
  }
657
658
  /// Preincrement to move to the next root register.
659
233M
  void operator++() {
660
233M
    assert(isValid() && "Cannot move off the end of the list.");
661
233M
    Reg0 = Reg1;
662
233M
    Reg1 = 0;
663
233M
  }
664
};
665
666
/// MCRegAliasIterator enumerates all registers aliasing Reg.  If IncludeSelf is
667
/// set, Reg itself is included in the list.  This iterator does not guarantee
668
/// any ordering or that entries are unique.
669
class MCRegAliasIterator {
670
private:
671
  unsigned Reg;
672
  const MCRegisterInfo *MCRI;
673
  bool IncludeSelf;
674
675
  MCRegUnitIterator RI;
676
  MCRegUnitRootIterator RRI;
677
  MCSuperRegIterator SI;
678
679
public:
680
  MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI,
681
                     bool IncludeSelf)
682
158M
    : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
683
158M
    // Initialize the iterators.
684
160M
    for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); 
++RI2.17M
) {
685
160M
      for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); 
++RRI2.18M
) {
686
175M
        for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); 
++SI16.7M
) {
687
173M
          if (!(!IncludeSelf && 
Reg == *SI47.6M
))
688
156M
            return;
689
173M
        }
690
158M
      }
691
158M
    }
692
158M
  }
693
694
1.09G
  bool isValid() const { return RI.isValid(); }
695
696
1.11G
  unsigned operator*() const {
697
1.11G
    assert(SI.isValid() && "Cannot dereference an invalid iterator.");
698
1.11G
    return *SI;
699
1.11G
  }
700
701
933M
  void advance() {
702
933M
    // Assuming SI is valid.
703
933M
    ++SI;
704
933M
    if (SI.isValid()) 
return788M
;
705
145M
706
145M
    ++RRI;
707
145M
    if (RRI.isValid()) {
708
44.5k
      SI = MCSuperRegIterator(*RRI, MCRI, true);
709
44.5k
      return;
710
44.5k
    }
711
145M
712
145M
    ++RI;
713
145M
    if (RI.isValid()) {
714
30.8M
      RRI = MCRegUnitRootIterator(*RI, MCRI);
715
30.8M
      SI = MCSuperRegIterator(*RRI, MCRI, true);
716
30.8M
    }
717
145M
  }
718
719
933M
  void operator++() {
720
933M
    assert(isValid() && "Cannot move off the end of the list.");
721
933M
    do advance();
722
933M
    while (!IncludeSelf && 
isValid()7.27M
&&
*SI == Reg6.24M
);
723
933M
  }
724
};
725
726
} // end namespace llvm
727
728
#endif // LLVM_MC_MCREGISTERINFO_H