Coverage Report

Created: 2018-11-16 02:38

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/MC/MCSchedule.h
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//===-- llvm/MC/MCSchedule.h - Scheduling -----------------------*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the classes used to describe a subtarget's machine model
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// for scheduling and other instruction cost heuristics.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_MC_MCSCHEDULE_H
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#define LLVM_MC_MCSCHEDULE_H
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#include "llvm/ADT/Optional.h"
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#include "llvm/Config/llvm-config.h"
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#include "llvm/Support/DataTypes.h"
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#include <cassert>
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namespace llvm {
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struct InstrItinerary;
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class MCSubtargetInfo;
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class MCInstrInfo;
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class MCInst;
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class InstrItineraryData;
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/// Define a kind of processor resource that will be modeled by the scheduler.
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struct MCProcResourceDesc {
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  const char *Name;
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  unsigned NumUnits; // Number of resource of this kind
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  unsigned SuperIdx; // Index of the resources kind that contains this kind.
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  // Number of resources that may be buffered.
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  //
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  // Buffered resources (BufferSize != 0) may be consumed at some indeterminate
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  // cycle after dispatch. This should be used for out-of-order cpus when
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  // instructions that use this resource can be buffered in a reservaton
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  // station.
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  //
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  // Unbuffered resources (BufferSize == 0) always consume their resource some
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  // fixed number of cycles after dispatch. If a resource is unbuffered, then
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  // the scheduler will avoid scheduling instructions with conflicting resources
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  // in the same cycle. This is for in-order cpus, or the in-order portion of
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  // an out-of-order cpus.
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  int BufferSize;
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  // If the resource has sub-units, a pointer to the first element of an array
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  // of `NumUnits` elements containing the ProcResourceIdx of the sub units.
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  // nullptr if the resource does not have sub-units.
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  const unsigned *SubUnitsIdxBegin;
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  bool operator==(const MCProcResourceDesc &Other) const {
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    return NumUnits == Other.NumUnits && SuperIdx == Other.SuperIdx
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      && BufferSize == Other.BufferSize;
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  }
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};
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/// Identify one of the processor resource kinds consumed by a particular
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/// scheduling class for the specified number of cycles.
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struct MCWriteProcResEntry {
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  uint16_t ProcResourceIdx;
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  uint16_t Cycles;
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  bool operator==(const MCWriteProcResEntry &Other) const {
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    return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles;
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  }
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};
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/// Specify the latency in cpu cycles for a particular scheduling class and def
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/// index. -1 indicates an invalid latency. Heuristics would typically consider
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/// an instruction with invalid latency to have infinite latency.  Also identify
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/// the WriteResources of this def. When the operand expands to a sequence of
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/// writes, this ID is the last write in the sequence.
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struct MCWriteLatencyEntry {
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  int16_t Cycles;
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  uint16_t WriteResourceID;
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  bool operator==(const MCWriteLatencyEntry &Other) const {
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    return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
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  }
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};
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/// Specify the number of cycles allowed after instruction issue before a
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/// particular use operand reads its registers. This effectively reduces the
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/// write's latency. Here we allow negative cycles for corner cases where
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/// latency increases. This rule only applies when the entry's WriteResource
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/// matches the write's WriteResource.
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///
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/// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by
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/// WriteResourceIdx.
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struct MCReadAdvanceEntry {
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  unsigned UseIdx;
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  unsigned WriteResourceID;
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  int Cycles;
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  bool operator==(const MCReadAdvanceEntry &Other) const {
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    return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
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      && Cycles == Other.Cycles;
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  }
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};
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/// Summarize the scheduling resources required for an instruction of a
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/// particular scheduling class.
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///
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/// Defined as an aggregate struct for creating tables with initializer lists.
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struct MCSchedClassDesc {
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  static const unsigned short InvalidNumMicroOps = (1U << 14) - 1;
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  static const unsigned short VariantNumMicroOps = InvalidNumMicroOps - 1;
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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  const char* Name;
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#endif
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  uint16_t NumMicroOps : 14;
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  bool     BeginGroup : 1;
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  bool     EndGroup : 1;
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  uint16_t WriteProcResIdx; // First index into WriteProcResTable.
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  uint16_t NumWriteProcResEntries;
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  uint16_t WriteLatencyIdx; // First index into WriteLatencyTable.
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  uint16_t NumWriteLatencyEntries;
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  uint16_t ReadAdvanceIdx; // First index into ReadAdvanceTable.
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  uint16_t NumReadAdvanceEntries;
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318M
  bool isValid() const {
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318M
    return NumMicroOps != InvalidNumMicroOps;
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318M
  }
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207M
  bool isVariant() const {
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207M
    return NumMicroOps == VariantNumMicroOps;
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207M
  }
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};
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/// Specify the cost of a register definition in terms of number of physical
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/// register allocated at register renaming stage. For example, AMD Jaguar.
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/// natively supports 128-bit data types, and operations on 256-bit registers
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/// (i.e. YMM registers) are internally split into two COPs (complex operations)
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/// and each COP updates a physical register. Basically, on Jaguar, a YMM
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/// register write effectively consumes two physical registers. That means,
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/// the cost of a YMM write in the BtVer2 model is 2.
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struct MCRegisterCostEntry {
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  unsigned RegisterClassID;
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  unsigned Cost;
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  bool AllowMoveElimination;
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};
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/// A register file descriptor.
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///
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/// This struct allows to describe processor register files. In particular, it
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/// helps describing the size of the register file, as well as the cost of
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/// allocating a register file at register renaming stage.
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/// FIXME: this struct can be extended to provide information about the number
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/// of read/write ports to the register file.  A value of zero for field
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/// 'NumPhysRegs' means: this register file has an unbounded number of physical
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/// registers.
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struct MCRegisterFileDesc {
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  const char *Name;
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  uint16_t NumPhysRegs;
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  uint16_t NumRegisterCostEntries;
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  // Index of the first cost entry in MCExtraProcessorInfo::RegisterCostTable.
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  uint16_t RegisterCostEntryIdx;
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  // A value of zero means: there is no limit in the number of moves that can be
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  // eliminated every cycle.
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  uint16_t MaxMovesEliminatedPerCycle;
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  // Ture if this register file only knows how to optimize register moves from
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  // known zero registers.
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  bool AllowZeroMoveEliminationOnly;
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};
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/// Provide extra details about the machine processor.
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///
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/// This is a collection of "optional" processor information that is not
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/// normally used by the LLVM machine schedulers, but that can be consumed by
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/// external tools like llvm-mca to improve the quality of the peformance
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/// analysis.
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struct MCExtraProcessorInfo {
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  // Actual size of the reorder buffer in hardware.
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  unsigned ReorderBufferSize;
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  // Number of instructions retired per cycle.
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  unsigned MaxRetirePerCycle;
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  const MCRegisterFileDesc *RegisterFiles;
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  unsigned NumRegisterFiles;
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  const MCRegisterCostEntry *RegisterCostTable;
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  unsigned NumRegisterCostEntries;
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};
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/// Machine model for scheduling, bundling, and heuristics.
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///
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/// The machine model directly provides basic information about the
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/// microarchitecture to the scheduler in the form of properties. It also
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/// optionally refers to scheduler resource tables and itinerary
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/// tables. Scheduler resource tables model the latency and cost for each
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/// instruction type. Itinerary tables are an independent mechanism that
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/// provides a detailed reservation table describing each cycle of instruction
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/// execution. Subtargets may define any or all of the above categories of data
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/// depending on the type of CPU and selected scheduler.
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///
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/// The machine independent properties defined here are used by the scheduler as
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/// an abstract machine model. A real micro-architecture has a number of
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/// buffers, queues, and stages. Declaring that a given machine-independent
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/// abstract property corresponds to a specific physical property across all
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/// subtargets can't be done. Nonetheless, the abstract model is
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/// useful. Futhermore, subtargets typically extend this model with processor
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/// specific resources to model any hardware features that can be exploited by
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/// sceduling heuristics and aren't sufficiently represented in the abstract.
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///
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/// The abstract pipeline is built around the notion of an "issue point". This
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/// is merely a reference point for counting machine cycles. The physical
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/// machine will have pipeline stages that delay execution. The scheduler does
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/// not model those delays because they are irrelevant as long as they are
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/// consistent. Inaccuracies arise when instructions have different execution
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/// delays relative to each other, in addition to their intrinsic latency. Those
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/// special cases can be handled by TableGen constructs such as, ReadAdvance,
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/// which reduces latency when reading data, and ResourceCycles, which consumes
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/// a processor resource when writing data for a number of abstract
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/// cycles.
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///
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/// TODO: One tool currently missing is the ability to add a delay to
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/// ResourceCycles. That would be easy to add and would likely cover all cases
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/// currently handled by the legacy itinerary tables.
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///
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/// A note on out-of-order execution and, more generally, instruction
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/// buffers. Part of the CPU pipeline is always in-order. The issue point, which
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/// is the point of reference for counting cycles, only makes sense as an
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/// in-order part of the pipeline. Other parts of the pipeline are sometimes
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/// falling behind and sometimes catching up. It's only interesting to model
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/// those other, decoupled parts of the pipeline if they may be predictably
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/// resource constrained in a way that the scheduler can exploit.
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///
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/// The LLVM machine model distinguishes between in-order constraints and
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/// out-of-order constraints so that the target's scheduling strategy can apply
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/// appropriate heuristics. For a well-balanced CPU pipeline, out-of-order
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/// resources would not typically be treated as a hard scheduling
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/// constraint. For example, in the GenericScheduler, a delay caused by limited
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/// out-of-order resources is not directly reflected in the number of cycles
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/// that the scheduler sees between issuing an instruction and its dependent
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/// instructions. In other words, out-of-order resources don't directly increase
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/// the latency between pairs of instructions. However, they can still be used
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/// to detect potential bottlenecks across a sequence of instructions and bias
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/// the scheduling heuristics appropriately.
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struct MCSchedModel {
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  // IssueWidth is the maximum number of instructions that may be scheduled in
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  // the same per-cycle group. This is meant to be a hard in-order constraint
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  // (a.k.a. "hazard"). In the GenericScheduler strategy, no more than
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  // IssueWidth micro-ops can ever be scheduled in a particular cycle.
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  //
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  // In practice, IssueWidth is useful to model any bottleneck between the
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  // decoder (after micro-op expansion) and the out-of-order reservation
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  // stations or the decoder bandwidth itself. If the total number of
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  // reservation stations is also a bottleneck, or if any other pipeline stage
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  // has a bandwidth limitation, then that can be naturally modeled by adding an
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  // out-of-order processor resource.
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  unsigned IssueWidth;
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  static const unsigned DefaultIssueWidth = 1;
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  // MicroOpBufferSize is the number of micro-ops that the processor may buffer
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  // for out-of-order execution.
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  //
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  // "0" means operations that are not ready in this cycle are not considered
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  // for scheduling (they go in the pending queue). Latency is paramount. This
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  // may be more efficient if many instructions are pending in a schedule.
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  //
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  // "1" means all instructions are considered for scheduling regardless of
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  // whether they are ready in this cycle. Latency still causes issue stalls,
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  // but we balance those stalls against other heuristics.
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  //
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  // "> 1" means the processor is out-of-order. This is a machine independent
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  // estimate of highly machine specific characteristics such as the register
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  // renaming pool and reorder buffer.
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  unsigned MicroOpBufferSize;
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  static const unsigned DefaultMicroOpBufferSize = 0;
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  // LoopMicroOpBufferSize is the number of micro-ops that the processor may
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  // buffer for optimized loop execution. More generally, this represents the
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  // optimal number of micro-ops in a loop body. A loop may be partially
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  // unrolled to bring the count of micro-ops in the loop body closer to this
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  // number.
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  unsigned LoopMicroOpBufferSize;
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  static const unsigned DefaultLoopMicroOpBufferSize = 0;
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  // LoadLatency is the expected latency of load instructions.
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  unsigned LoadLatency;
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  static const unsigned DefaultLoadLatency = 4;
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  // HighLatency is the expected latency of "very high latency" operations.
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  // See TargetInstrInfo::isHighLatencyDef().
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  // By default, this is set to an arbitrarily high number of cycles
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  // likely to have some impact on scheduling heuristics.
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  unsigned HighLatency;
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  static const unsigned DefaultHighLatency = 10;
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  // MispredictPenalty is the typical number of extra cycles the processor
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  // takes to recover from a branch misprediction.
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  unsigned MispredictPenalty;
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  static const unsigned DefaultMispredictPenalty = 10;
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  bool PostRAScheduler; // default value is false
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  bool CompleteModel;
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  unsigned ProcID;
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  const MCProcResourceDesc *ProcResourceTable;
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  const MCSchedClassDesc *SchedClassTable;
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  unsigned NumProcResourceKinds;
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  unsigned NumSchedClasses;
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  // Instruction itinerary tables used by InstrItineraryData.
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  friend class InstrItineraryData;
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  const InstrItinerary *InstrItineraries;
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  const MCExtraProcessorInfo *ExtraProcessorInfo;
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  bool hasExtraProcessorInfo() const { return ExtraProcessorInfo; }
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36.6M
  unsigned getProcessorID() const { return ProcID; }
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  /// Does this machine model include instruction-level scheduling.
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301M
  bool hasInstrSchedModel() const { return SchedClassTable; }
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  const MCExtraProcessorInfo &getExtraProcessorInfo() const {
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    assert(hasExtraProcessorInfo() &&
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           "No extra information available for this model");
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    return *ExtraProcessorInfo;
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  }
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  /// Return true if this machine model data for all instructions with a
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  /// scheduling class (itinerary class or SchedRW list).
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  bool isComplete() const { return CompleteModel; }
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  /// Return true if machine supports out of order execution.
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1.11M
  bool isOutOfOrder() const { return MicroOpBufferSize > 1; }
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35.3M
  unsigned getNumProcResourceKinds() const {
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35.3M
    return NumProcResourceKinds;
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35.3M
  }
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85.4M
  const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const {
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85.4M
    assert(hasInstrSchedModel() && "No scheduling machine model");
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85.4M
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85.4M
    assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx");
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85.4M
    return &ProcResourceTable[ProcResourceIdx];
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85.4M
  }
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209M
  const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const {
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209M
    assert(hasInstrSchedModel() && "No scheduling machine model");
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209M
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209M
    assert(SchedClassIdx < NumSchedClasses && "bad scheduling class idx");
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209M
    return &SchedClassTable[SchedClassIdx];
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209M
  }
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  /// Returns the latency value for the scheduling class.
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  static int computeInstrLatency(const MCSubtargetInfo &STI,
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                                 const MCSchedClassDesc &SCDesc);
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  int computeInstrLatency(const MCSubtargetInfo &STI, unsigned SClass) const;
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  int computeInstrLatency(const MCSubtargetInfo &STI, const MCInstrInfo &MCII,
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                          const MCInst &Inst) const;
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  // Returns the reciprocal throughput information from a MCSchedClassDesc.
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  static double
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  getReciprocalThroughput(const MCSubtargetInfo &STI,
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                          const MCSchedClassDesc &SCDesc);
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  static double
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  getReciprocalThroughput(unsigned SchedClass, const InstrItineraryData &IID);
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  double
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  getReciprocalThroughput(const MCSubtargetInfo &STI, const MCInstrInfo &MCII,
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                          const MCInst &Inst) const;
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  /// Returns the default initialized model.
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1.55M
  static const MCSchedModel &GetDefaultSchedModel() { return Default; }
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  static const MCSchedModel Default;
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};
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} // namespace llvm
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#endif