Coverage Report

Created: 2019-02-20 00:17

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/MC/MCSubtargetInfo.h
Line
Count
Source (jump to first uncovered line)
1
//===- llvm/MC/MCSubtargetInfo.h - Subtarget Information --------*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file describes the subtarget options of a Target machine.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#ifndef LLVM_MC_MCSUBTARGETINFO_H
14
#define LLVM_MC_MCSUBTARGETINFO_H
15
16
#include "llvm/ADT/ArrayRef.h"
17
#include "llvm/ADT/StringRef.h"
18
#include "llvm/ADT/Triple.h"
19
#include "llvm/MC/MCInstrItineraries.h"
20
#include "llvm/MC/MCSchedule.h"
21
#include "llvm/MC/SubtargetFeature.h"
22
#include <algorithm>
23
#include <cassert>
24
#include <cstdint>
25
#include <string>
26
27
namespace llvm {
28
29
class MCInst;
30
31
//===----------------------------------------------------------------------===//
32
///
33
/// Generic base class for all target subtargets.
34
///
35
class MCSubtargetInfo {
36
  Triple TargetTriple;
37
  std::string CPU; // CPU being targeted.
38
  ArrayRef<SubtargetFeatureKV> ProcFeatures;  // Processor feature list
39
  ArrayRef<SubtargetFeatureKV> ProcDesc;  // Processor descriptions
40
41
  // Scheduler machine model
42
  const SubtargetInfoKV *ProcSchedModels;
43
  const MCWriteProcResEntry *WriteProcResTable;
44
  const MCWriteLatencyEntry *WriteLatencyTable;
45
  const MCReadAdvanceEntry *ReadAdvanceTable;
46
  const MCSchedModel *CPUSchedModel;
47
48
  const InstrStage *Stages;            // Instruction itinerary stages
49
  const unsigned *OperandCycles;       // Itinerary operand cycles
50
  const unsigned *ForwardingPaths;
51
  FeatureBitset FeatureBits;           // Feature bits for current CPU + FS
52
53
public:
54
3.29k
  MCSubtargetInfo(const MCSubtargetInfo &) = default;
55
  MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
56
                  ArrayRef<SubtargetFeatureKV> PF,
57
                  ArrayRef<SubtargetFeatureKV> PD,
58
                  const SubtargetInfoKV *ProcSched,
59
                  const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
60
                  const MCReadAdvanceEntry *RA, const InstrStage *IS,
61
                  const unsigned *OC, const unsigned *FP);
62
  MCSubtargetInfo() = delete;
63
  MCSubtargetInfo &operator=(const MCSubtargetInfo &) = delete;
64
  MCSubtargetInfo &operator=(MCSubtargetInfo &&) = delete;
65
94.3k
  virtual ~MCSubtargetInfo() = default;
66
67
2.37M
  const Triple &getTargetTriple() const { return TargetTriple; }
68
2.37M
  StringRef getCPU() const { return CPU; }
69
70
38.6M
  const FeatureBitset& getFeatureBits() const { return FeatureBits; }
71
2.40k
  void setFeatureBits(const FeatureBitset &FeatureBits_) {
72
2.40k
    FeatureBits = FeatureBits_;
73
2.40k
  }
74
75
90.1k
  bool hasFeature(unsigned Feature) const {
76
90.1k
    return FeatureBits[Feature];
77
90.1k
  }
78
79
protected:
80
  /// Initialize the scheduling model and feature bits.
81
  ///
82
  /// FIXME: Find a way to stick this in the constructor, since it should only
83
  /// be called during initialization.
84
  void InitMCProcessorInfo(StringRef CPU, StringRef FS);
85
86
public:
87
  /// Set the features to the default for the given CPU with an appended feature
88
  /// string.
89
  void setDefaultFeatures(StringRef CPU, StringRef FS);
90
91
  /// Toggle a feature and return the re-computed feature bits.
92
  /// This version does not change the implied bits.
93
  FeatureBitset ToggleFeature(uint64_t FB);
94
95
  /// Toggle a feature and return the re-computed feature bits.
96
  /// This version does not change the implied bits.
97
  FeatureBitset ToggleFeature(const FeatureBitset& FB);
98
99
  /// Toggle a set of features and return the re-computed feature bits.
100
  /// This version will also change all implied bits.
101
  FeatureBitset ToggleFeature(StringRef FS);
102
103
  /// Apply a feature flag and return the re-computed feature bits, including
104
  /// all feature bits implied by the flag.
105
  FeatureBitset ApplyFeatureFlag(StringRef FS);
106
107
  /// Check whether the subtarget features are enabled/disabled as per
108
  /// the provided string, ignoring all other features.
109
  bool checkFeatures(StringRef FS) const;
110
111
  /// Get the machine model of a CPU.
112
  const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;
113
114
  /// Get the machine model for this subtarget's CPU.
115
8.79M
  const MCSchedModel &getSchedModel() const { return *CPUSchedModel; }
116
117
  /// Return an iterator at the first process resource consumed by the given
118
  /// scheduling class.
119
  const MCWriteProcResEntry *getWriteProcResBegin(
120
114M
    const MCSchedClassDesc *SC) const {
121
114M
    return &WriteProcResTable[SC->WriteProcResIdx];
122
114M
  }
123
  const MCWriteProcResEntry *getWriteProcResEnd(
124
57.2M
    const MCSchedClassDesc *SC) const {
125
57.2M
    return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
126
57.2M
  }
127
128
  const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
129
28.0M
                                                  unsigned DefIdx) const {
130
28.0M
    assert(DefIdx < SC->NumWriteLatencyEntries &&
131
28.0M
           "MachineModel does not specify a WriteResource for DefIdx");
132
28.0M
133
28.0M
    return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
134
28.0M
  }
135
136
  int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
137
5.25M
                           unsigned WriteResID) const {
138
5.25M
    // TODO: The number of read advance entries in a class can be significant
139
5.25M
    // (~50). Consider compressing the WriteID into a dense ID of those that are
140
5.25M
    // used by ReadAdvance and representing them as a bitset.
141
5.25M
    for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
142
7.74M
           *E = I + SC->NumReadAdvanceEntries; I != E; 
++I2.48M
) {
143
7.41M
      if (I->UseIdx < UseIdx)
144
2.48M
        continue;
145
4.93M
      if (I->UseIdx > UseIdx)
146
17.0k
        break;
147
4.92M
      // Find the first WriteResIdx match, which has the highest cycle count.
148
4.92M
      if (!I->WriteResourceID || 
I->WriteResourceID == WriteResID4.94k
) {
149
4.91M
        return I->Cycles;
150
4.91M
      }
151
4.92M
    }
152
5.25M
    
return 0340k
;
153
5.25M
  }
154
155
  /// Return the set of ReadAdvance entries declared by the scheduling class
156
  /// descriptor in input.
157
  ArrayRef<MCReadAdvanceEntry>
158
  getReadAdvanceEntries(const MCSchedClassDesc &SC) const {
159
    if (!SC.NumReadAdvanceEntries)
160
      return ArrayRef<MCReadAdvanceEntry>();
161
    return ArrayRef<MCReadAdvanceEntry>(&ReadAdvanceTable[SC.ReadAdvanceIdx],
162
                                        SC.NumReadAdvanceEntries);
163
  }
164
165
  /// Get scheduling itinerary of a CPU.
166
  InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
167
168
  /// Initialize an InstrItineraryData instance.
169
  void initInstrItins(InstrItineraryData &InstrItins) const;
170
171
  /// Resolve a variant scheduling class for the given MCInst and CPU.
172
  virtual unsigned
173
  resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,
174
0
                           unsigned CPUID) const {
175
0
    return 0;
176
0
  }
177
178
  /// Check whether the CPU string is valid.
179
629
  bool isCPUStringValid(StringRef CPU) const {
180
629
    auto Found = std::lower_bound(ProcDesc.begin(), ProcDesc.end(), CPU);
181
629
    return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;
182
629
  }
183
};
184
185
} // end namespace llvm
186
187
#endif // LLVM_MC_MCSUBTARGETINFO_H