Coverage Report

Created: 2018-11-12 17:33

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/MC/MCSubtargetInfo.h
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//===- llvm/MC/MCSubtargetInfo.h - Subtarget Information --------*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the subtarget options of a Target machine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_MC_MCSUBTARGETINFO_H
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#define LLVM_MC_MCSUBTARGETINFO_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/MC/MCSchedule.h"
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#include "llvm/MC/SubtargetFeature.h"
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#include <algorithm>
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#include <cassert>
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#include <cstdint>
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#include <string>
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namespace llvm {
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class MCInst;
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//===----------------------------------------------------------------------===//
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///
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/// Generic base class for all target subtargets.
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///
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class MCSubtargetInfo {
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  Triple TargetTriple;
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  std::string CPU; // CPU being targeted.
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  ArrayRef<SubtargetFeatureKV> ProcFeatures;  // Processor feature list
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  ArrayRef<SubtargetFeatureKV> ProcDesc;  // Processor descriptions
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  // Scheduler machine model
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  const SubtargetInfoKV *ProcSchedModels;
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  const MCWriteProcResEntry *WriteProcResTable;
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  const MCWriteLatencyEntry *WriteLatencyTable;
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  const MCReadAdvanceEntry *ReadAdvanceTable;
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  const MCSchedModel *CPUSchedModel;
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  const InstrStage *Stages;            // Instruction itinerary stages
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  const unsigned *OperandCycles;       // Itinerary operand cycles
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  const unsigned *ForwardingPaths;
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  FeatureBitset FeatureBits;           // Feature bits for current CPU + FS
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public:
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  MCSubtargetInfo(const MCSubtargetInfo &) = default;
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  MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
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                  ArrayRef<SubtargetFeatureKV> PF,
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                  ArrayRef<SubtargetFeatureKV> PD,
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                  const SubtargetInfoKV *ProcSched,
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                  const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
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                  const MCReadAdvanceEntry *RA, const InstrStage *IS,
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                  const unsigned *OC, const unsigned *FP);
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  MCSubtargetInfo() = delete;
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  MCSubtargetInfo &operator=(const MCSubtargetInfo &) = delete;
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  MCSubtargetInfo &operator=(MCSubtargetInfo &&) = delete;
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  virtual ~MCSubtargetInfo() = default;
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  const Triple &getTargetTriple() const { return TargetTriple; }
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  StringRef getCPU() const { return CPU; }
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  const FeatureBitset& getFeatureBits() const { return FeatureBits; }
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  void setFeatureBits(const FeatureBitset &FeatureBits_) {
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    FeatureBits = FeatureBits_;
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  }
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  bool hasFeature(unsigned Feature) const {
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    return FeatureBits[Feature];
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  }
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protected:
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  /// Initialize the scheduling model and feature bits.
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  ///
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  /// FIXME: Find a way to stick this in the constructor, since it should only
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  /// be called during initialization.
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  void InitMCProcessorInfo(StringRef CPU, StringRef FS);
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public:
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  /// Set the features to the default for the given CPU with an appended feature
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  /// string.
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  void setDefaultFeatures(StringRef CPU, StringRef FS);
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  /// Toggle a feature and return the re-computed feature bits.
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  /// This version does not change the implied bits.
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  FeatureBitset ToggleFeature(uint64_t FB);
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  /// Toggle a feature and return the re-computed feature bits.
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  /// This version does not change the implied bits.
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  FeatureBitset ToggleFeature(const FeatureBitset& FB);
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  /// Toggle a set of features and return the re-computed feature bits.
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  /// This version will also change all implied bits.
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  FeatureBitset ToggleFeature(StringRef FS);
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  /// Apply a feature flag and return the re-computed feature bits, including
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  /// all feature bits implied by the flag.
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  FeatureBitset ApplyFeatureFlag(StringRef FS);
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  /// Check whether the subtarget features are enabled/disabled as per
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  /// the provided string, ignoring all other features.
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  bool checkFeatures(StringRef FS) const;
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  /// Get the machine model of a CPU.
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  const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;
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  /// Get the machine model for this subtarget's CPU.
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  const MCSchedModel &getSchedModel() const { return *CPUSchedModel; }
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  /// Return an iterator at the first process resource consumed by the given
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  /// scheduling class.
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  const MCWriteProcResEntry *getWriteProcResBegin(
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    const MCSchedClassDesc *SC) const {
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    return &WriteProcResTable[SC->WriteProcResIdx];
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  }
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  const MCWriteProcResEntry *getWriteProcResEnd(
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    const MCSchedClassDesc *SC) const {
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    return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
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  }
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  const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
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                                                  unsigned DefIdx) const {
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    assert(DefIdx < SC->NumWriteLatencyEntries &&
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           "MachineModel does not specify a WriteResource for DefIdx");
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    return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
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  }
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  int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
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                           unsigned WriteResID) const {
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    // TODO: The number of read advance entries in a class can be significant
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    // (~50). Consider compressing the WriteID into a dense ID of those that are
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    // used by ReadAdvance and representing them as a bitset.
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    for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
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           *E = I + SC->NumReadAdvanceEntries; I != E; 
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) {
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      if (I->UseIdx < UseIdx)
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        continue;
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      if (I->UseIdx > UseIdx)
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        break;
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      // Find the first WriteResIdx match, which has the highest cycle count.
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      if (!I->WriteResourceID || 
I->WriteResourceID == WriteResID5.01k
) {
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        return I->Cycles;
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      }
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    }
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return 0312k
;
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  }
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  /// Get scheduling itinerary of a CPU.
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  InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
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  /// Initialize an InstrItineraryData instance.
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  void initInstrItins(InstrItineraryData &InstrItins) const;
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  /// Resolve a variant scheduling class for the given MCInst and CPU.
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  virtual unsigned
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  resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,
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                           unsigned CPUID) const {
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    return 0;
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  }
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  /// Check whether the CPU string is valid.
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  bool isCPUStringValid(StringRef CPU) const {
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    auto Found = std::lower_bound(ProcDesc.begin(), ProcDesc.end(), CPU);
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    return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;
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  }
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  /// Returns string representation of scheduler comment
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  virtual std::string getSchedInfoStr(MCInst const &MCI) const {
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    return {};
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  }
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};
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} // end namespace llvm
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#endif // LLVM_MC_MCSUBTARGETINFO_H