Coverage Report

Created: 2018-11-16 02:38

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/Support/TargetRegistry.h
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//===- Support/TargetRegistry.h - Target Registration -----------*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file exposes the TargetRegistry interface, which tools can use to access
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// the appropriate target specific classes (TargetMachine, AsmPrinter, etc.)
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// which have been registered.
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//
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// Target specific class implementations should register themselves using the
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// appropriate TargetRegistry interfaces.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_SUPPORT_TARGETREGISTRY_H
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#define LLVM_SUPPORT_TARGETREGISTRY_H
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#include "llvm-c/DisassemblerTypes.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/ADT/iterator_range.h"
27
#include "llvm/Support/CodeGen.h"
28
#include "llvm/Support/ErrorHandling.h"
29
#include "llvm/Support/FormattedStream.h"
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#include <algorithm>
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#include <cassert>
32
#include <cstddef>
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#include <iterator>
34
#include <memory>
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#include <string>
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37
namespace llvm {
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39
class AsmPrinter;
40
class MCAsmBackend;
41
class MCAsmInfo;
42
class MCAsmParser;
43
class MCCodeEmitter;
44
class MCContext;
45
class MCDisassembler;
46
class MCInstPrinter;
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class MCInstrAnalysis;
48
class MCInstrInfo;
49
class MCObjectWriter;
50
class MCRegisterInfo;
51
class MCRelocationInfo;
52
class MCStreamer;
53
class MCSubtargetInfo;
54
class MCSymbolizer;
55
class MCTargetAsmParser;
56
class MCTargetOptions;
57
class MCTargetStreamer;
58
class raw_ostream;
59
class raw_pwrite_stream;
60
class TargetMachine;
61
class TargetOptions;
62
63
MCStreamer *createNullStreamer(MCContext &Ctx);
64
// Takes ownership of \p TAB and \p CE.
65
66
/// Create a machine code streamer which will print out assembly for the native
67
/// target, suitable for compiling with a native assembler.
68
///
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/// \param InstPrint - If given, the instruction printer to use. If not given
70
/// the MCInst representation will be printed.  This method takes ownership of
71
/// InstPrint.
72
///
73
/// \param CE - If given, a code emitter to use to show the instruction
74
/// encoding inline with the assembly. This method takes ownership of \p CE.
75
///
76
/// \param TAB - If given, a target asm backend to use to show the fixup
77
/// information in conjunction with encoding information. This method takes
78
/// ownership of \p TAB.
79
///
80
/// \param ShowInst - Whether to show the MCInst representation inline with
81
/// the assembly.
82
MCStreamer *
83
createAsmStreamer(MCContext &Ctx, std::unique_ptr<formatted_raw_ostream> OS,
84
                  bool isVerboseAsm, bool useDwarfDirectory,
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                  MCInstPrinter *InstPrint, std::unique_ptr<MCCodeEmitter> &&CE,
86
                  std::unique_ptr<MCAsmBackend> &&TAB, bool ShowInst);
87
88
MCStreamer *createELFStreamer(MCContext &Ctx,
89
                              std::unique_ptr<MCAsmBackend> &&TAB,
90
                              std::unique_ptr<MCObjectWriter> &&OW,
91
                              std::unique_ptr<MCCodeEmitter> &&CE,
92
                              bool RelaxAll);
93
MCStreamer *createMachOStreamer(MCContext &Ctx,
94
                                std::unique_ptr<MCAsmBackend> &&TAB,
95
                                std::unique_ptr<MCObjectWriter> &&OW,
96
                                std::unique_ptr<MCCodeEmitter> &&CE,
97
                                bool RelaxAll, bool DWARFMustBeAtTheEnd,
98
                                bool LabelSections = false);
99
MCStreamer *createWasmStreamer(MCContext &Ctx,
100
                               std::unique_ptr<MCAsmBackend> &&TAB,
101
                               std::unique_ptr<MCObjectWriter> &&OW,
102
                               std::unique_ptr<MCCodeEmitter> &&CE,
103
                               bool RelaxAll);
104
105
MCRelocationInfo *createMCRelocationInfo(const Triple &TT, MCContext &Ctx);
106
107
MCSymbolizer *createMCSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
108
                                 LLVMSymbolLookupCallback SymbolLookUp,
109
                                 void *DisInfo, MCContext *Ctx,
110
                                 std::unique_ptr<MCRelocationInfo> &&RelInfo);
111
112
/// Target - Wrapper for Target specific information.
113
///
114
/// For registration purposes, this is a POD type so that targets can be
115
/// registered without the use of static constructors.
116
///
117
/// Targets should implement a single global instance of this class (which
118
/// will be zero initialized), and pass that instance to the TargetRegistry as
119
/// part of their initialization.
120
class Target {
121
public:
122
  friend struct TargetRegistry;
123
124
  using ArchMatchFnTy = bool (*)(Triple::ArchType Arch);
125
126
  using MCAsmInfoCtorFnTy = MCAsmInfo *(*)(const MCRegisterInfo &MRI,
127
                                           const Triple &TT);
128
  using MCInstrInfoCtorFnTy = MCInstrInfo *(*)();
129
  using MCInstrAnalysisCtorFnTy = MCInstrAnalysis *(*)(const MCInstrInfo *Info);
130
  using MCRegInfoCtorFnTy = MCRegisterInfo *(*)(const Triple &TT);
131
  using MCSubtargetInfoCtorFnTy = MCSubtargetInfo *(*)(const Triple &TT,
132
                                                       StringRef CPU,
133
                                                       StringRef Features);
134
  using TargetMachineCtorTy = TargetMachine
135
      *(*)(const Target &T, const Triple &TT, StringRef CPU, StringRef Features,
136
           const TargetOptions &Options, Optional<Reloc::Model> RM,
137
           Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT);
138
  // If it weren't for layering issues (this header is in llvm/Support, but
139
  // depends on MC?) this should take the Streamer by value rather than rvalue
140
  // reference.
141
  using AsmPrinterCtorTy = AsmPrinter *(*)(
142
      TargetMachine &TM, std::unique_ptr<MCStreamer> &&Streamer);
143
  using MCAsmBackendCtorTy = MCAsmBackend *(*)(const Target &T,
144
                                               const MCSubtargetInfo &STI,
145
                                               const MCRegisterInfo &MRI,
146
                                               const MCTargetOptions &Options);
147
  using MCAsmParserCtorTy = MCTargetAsmParser *(*)(
148
      const MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII,
149
      const MCTargetOptions &Options);
150
  using MCDisassemblerCtorTy = MCDisassembler *(*)(const Target &T,
151
                                                   const MCSubtargetInfo &STI,
152
                                                   MCContext &Ctx);
153
  using MCInstPrinterCtorTy = MCInstPrinter *(*)(const Triple &T,
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                                                 unsigned SyntaxVariant,
155
                                                 const MCAsmInfo &MAI,
156
                                                 const MCInstrInfo &MII,
157
                                                 const MCRegisterInfo &MRI);
158
  using MCCodeEmitterCtorTy = MCCodeEmitter *(*)(const MCInstrInfo &II,
159
                                                 const MCRegisterInfo &MRI,
160
                                                 MCContext &Ctx);
161
  using ELFStreamerCtorTy =
162
      MCStreamer *(*)(const Triple &T, MCContext &Ctx,
163
                      std::unique_ptr<MCAsmBackend> &&TAB,
164
                      std::unique_ptr<MCObjectWriter> &&OW,
165
                      std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll);
166
  using MachOStreamerCtorTy =
167
      MCStreamer *(*)(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
168
                      std::unique_ptr<MCObjectWriter> &&OW,
169
                      std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
170
                      bool DWARFMustBeAtTheEnd);
171
  using COFFStreamerCtorTy =
172
      MCStreamer *(*)(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
173
                      std::unique_ptr<MCObjectWriter> &&OW,
174
                      std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
175
                      bool IncrementalLinkerCompatible);
176
  using WasmStreamerCtorTy =
177
      MCStreamer *(*)(const Triple &T, MCContext &Ctx,
178
                      std::unique_ptr<MCAsmBackend> &&TAB,
179
                      std::unique_ptr<MCObjectWriter> &&OW,
180
                      std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll);
181
  using NullTargetStreamerCtorTy = MCTargetStreamer *(*)(MCStreamer &S);
182
  using AsmTargetStreamerCtorTy = MCTargetStreamer *(*)(
183
      MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint,
184
      bool IsVerboseAsm);
185
  using ObjectTargetStreamerCtorTy = MCTargetStreamer *(*)(
186
      MCStreamer &S, const MCSubtargetInfo &STI);
187
  using MCRelocationInfoCtorTy = MCRelocationInfo *(*)(const Triple &TT,
188
                                                       MCContext &Ctx);
189
  using MCSymbolizerCtorTy = MCSymbolizer *(*)(
190
      const Triple &TT, LLVMOpInfoCallback GetOpInfo,
191
      LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx,
192
      std::unique_ptr<MCRelocationInfo> &&RelInfo);
193
194
private:
195
  /// Next - The next registered target in the linked list, maintained by the
196
  /// TargetRegistry.
197
  Target *Next;
198
199
  /// The target function for checking if an architecture is supported.
200
  ArchMatchFnTy ArchMatchFn;
201
202
  /// Name - The target name.
203
  const char *Name;
204
205
  /// ShortDesc - A short description of the target.
206
  const char *ShortDesc;
207
208
  /// BackendName - The name of the backend implementation. This must match the
209
  /// name of the 'def X : Target ...' in TableGen.
210
  const char *BackendName;
211
212
  /// HasJIT - Whether this target supports the JIT.
213
  bool HasJIT;
214
215
  /// MCAsmInfoCtorFn - Constructor function for this target's MCAsmInfo, if
216
  /// registered.
217
  MCAsmInfoCtorFnTy MCAsmInfoCtorFn;
218
219
  /// MCInstrInfoCtorFn - Constructor function for this target's MCInstrInfo,
220
  /// if registered.
221
  MCInstrInfoCtorFnTy MCInstrInfoCtorFn;
222
223
  /// MCInstrAnalysisCtorFn - Constructor function for this target's
224
  /// MCInstrAnalysis, if registered.
225
  MCInstrAnalysisCtorFnTy MCInstrAnalysisCtorFn;
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227
  /// MCRegInfoCtorFn - Constructor function for this target's MCRegisterInfo,
228
  /// if registered.
229
  MCRegInfoCtorFnTy MCRegInfoCtorFn;
230
231
  /// MCSubtargetInfoCtorFn - Constructor function for this target's
232
  /// MCSubtargetInfo, if registered.
233
  MCSubtargetInfoCtorFnTy MCSubtargetInfoCtorFn;
234
235
  /// TargetMachineCtorFn - Construction function for this target's
236
  /// TargetMachine, if registered.
237
  TargetMachineCtorTy TargetMachineCtorFn;
238
239
  /// MCAsmBackendCtorFn - Construction function for this target's
240
  /// MCAsmBackend, if registered.
241
  MCAsmBackendCtorTy MCAsmBackendCtorFn;
242
243
  /// MCAsmParserCtorFn - Construction function for this target's
244
  /// MCTargetAsmParser, if registered.
245
  MCAsmParserCtorTy MCAsmParserCtorFn;
246
247
  /// AsmPrinterCtorFn - Construction function for this target's AsmPrinter,
248
  /// if registered.
249
  AsmPrinterCtorTy AsmPrinterCtorFn;
250
251
  /// MCDisassemblerCtorFn - Construction function for this target's
252
  /// MCDisassembler, if registered.
253
  MCDisassemblerCtorTy MCDisassemblerCtorFn;
254
255
  /// MCInstPrinterCtorFn - Construction function for this target's
256
  /// MCInstPrinter, if registered.
257
  MCInstPrinterCtorTy MCInstPrinterCtorFn;
258
259
  /// MCCodeEmitterCtorFn - Construction function for this target's
260
  /// CodeEmitter, if registered.
261
  MCCodeEmitterCtorTy MCCodeEmitterCtorFn;
262
263
  // Construction functions for the various object formats, if registered.
264
  COFFStreamerCtorTy COFFStreamerCtorFn = nullptr;
265
  MachOStreamerCtorTy MachOStreamerCtorFn = nullptr;
266
  ELFStreamerCtorTy ELFStreamerCtorFn = nullptr;
267
  WasmStreamerCtorTy WasmStreamerCtorFn = nullptr;
268
269
  /// Construction function for this target's null TargetStreamer, if
270
  /// registered (default = nullptr).
271
  NullTargetStreamerCtorTy NullTargetStreamerCtorFn = nullptr;
272
273
  /// Construction function for this target's asm TargetStreamer, if
274
  /// registered (default = nullptr).
275
  AsmTargetStreamerCtorTy AsmTargetStreamerCtorFn = nullptr;
276
277
  /// Construction function for this target's obj TargetStreamer, if
278
  /// registered (default = nullptr).
279
  ObjectTargetStreamerCtorTy ObjectTargetStreamerCtorFn = nullptr;
280
281
  /// MCRelocationInfoCtorFn - Construction function for this target's
282
  /// MCRelocationInfo, if registered (default = llvm::createMCRelocationInfo)
283
  MCRelocationInfoCtorTy MCRelocationInfoCtorFn = nullptr;
284
285
  /// MCSymbolizerCtorFn - Construction function for this target's
286
  /// MCSymbolizer, if registered (default = llvm::createMCSymbolizer)
287
  MCSymbolizerCtorTy MCSymbolizerCtorFn = nullptr;
288
289
public:
290
3.53M
  Target() = default;
291
292
  /// @name Target Information
293
  /// @{
294
295
  // getNext - Return the next registered target.
296
1.89M
  const Target *getNext() const { return Next; }
297
298
  /// getName - Get the target name.
299
152k
  const char *getName() const { return Name; }
300
301
  /// getShortDescription - Get a short description of the target.
302
0
  const char *getShortDescription() const { return ShortDesc; }
303
304
  /// getBackendName - Get the backend name.
305
194k
  const char *getBackendName() const { return BackendName; }
306
307
  /// @}
308
  /// @name Feature Predicates
309
  /// @{
310
311
  /// hasJIT - Check if this targets supports the just-in-time compilation.
312
  bool hasJIT() const { return HasJIT; }
313
314
  /// hasTargetMachine - Check if this target supports code generation.
315
0
  bool hasTargetMachine() const { return TargetMachineCtorFn != nullptr; }
316
317
  /// hasMCAsmBackend - Check if this target supports .o generation.
318
0
  bool hasMCAsmBackend() const { return MCAsmBackendCtorFn != nullptr; }
319
320
  /// hasMCAsmParser - Check if this target supports assembly parsing.
321
39
  bool hasMCAsmParser() const { return MCAsmParserCtorFn != nullptr; }
322
323
  /// @}
324
  /// @name Feature Constructors
325
  /// @{
326
327
  /// createMCAsmInfo - Create a MCAsmInfo implementation for the specified
328
  /// target triple.
329
  ///
330
  /// \param TheTriple This argument is used to determine the target machine
331
  /// feature set; it should always be provided. Generally this should be
332
  /// either the target triple from the module, or the target triple of the
333
  /// host if that does not exist.
334
  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI,
335
59.6k
                             StringRef TheTriple) const {
336
59.6k
    if (!MCAsmInfoCtorFn)
337
0
      return nullptr;
338
59.6k
    return MCAsmInfoCtorFn(MRI, Triple(TheTriple));
339
59.6k
  }
340
341
  /// createMCInstrInfo - Create a MCInstrInfo implementation.
342
  ///
343
70.6k
  MCInstrInfo *createMCInstrInfo() const {
344
70.6k
    if (!MCInstrInfoCtorFn)
345
0
      return nullptr;
346
70.6k
    return MCInstrInfoCtorFn();
347
70.6k
  }
348
349
  /// createMCInstrAnalysis - Create a MCInstrAnalysis implementation.
350
  ///
351
2.16k
  MCInstrAnalysis *createMCInstrAnalysis(const MCInstrInfo *Info) const {
352
2.16k
    if (!MCInstrAnalysisCtorFn)
353
102
      return nullptr;
354
2.06k
    return MCInstrAnalysisCtorFn(Info);
355
2.06k
  }
356
357
  /// createMCRegInfo - Create a MCRegisterInfo implementation.
358
  ///
359
60.3k
  MCRegisterInfo *createMCRegInfo(StringRef TT) const {
360
60.3k
    if (!MCRegInfoCtorFn)
361
0
      return nullptr;
362
60.3k
    return MCRegInfoCtorFn(Triple(TT));
363
60.3k
  }
364
365
  /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
366
  ///
367
  /// \param TheTriple This argument is used to determine the target machine
368
  /// feature set; it should always be provided. Generally this should be
369
  /// either the target triple from the module, or the target triple of the
370
  /// host if that does not exist.
371
  /// \param CPU This specifies the name of the target CPU.
372
  /// \param Features This specifies the string representation of the
373
  /// additional target features.
374
  MCSubtargetInfo *createMCSubtargetInfo(StringRef TheTriple, StringRef CPU,
375
60.2k
                                         StringRef Features) const {
376
60.2k
    if (!MCSubtargetInfoCtorFn)
377
0
      return nullptr;
378
60.2k
    return MCSubtargetInfoCtorFn(Triple(TheTriple), CPU, Features);
379
60.2k
  }
380
381
  /// createTargetMachine - Create a target specific machine implementation
382
  /// for the specified \p Triple.
383
  ///
384
  /// \param TT This argument is used to determine the target machine
385
  /// feature set; it should always be provided. Generally this should be
386
  /// either the target triple from the module, or the target triple of the
387
  /// host if that does not exist.
388
  TargetMachine *createTargetMachine(StringRef TT, StringRef CPU,
389
                                     StringRef Features,
390
                                     const TargetOptions &Options,
391
                                     Optional<Reloc::Model> RM,
392
                                     Optional<CodeModel::Model> CM = None,
393
                                     CodeGenOpt::Level OL = CodeGenOpt::Default,
394
47.5k
                                     bool JIT = false) const {
395
47.5k
    if (!TargetMachineCtorFn)
396
0
      return nullptr;
397
47.5k
    return TargetMachineCtorFn(*this, Triple(TT), CPU, Features, Options, RM,
398
47.5k
                               CM, OL, JIT);
399
47.5k
  }
400
401
  /// createMCAsmBackend - Create a target specific assembly parser.
402
  MCAsmBackend *createMCAsmBackend(const MCSubtargetInfo &STI,
403
                                   const MCRegisterInfo &MRI,
404
42.6k
                                   const MCTargetOptions &Options) const {
405
42.6k
    if (!MCAsmBackendCtorFn)
406
316
      return nullptr;
407
42.2k
    return MCAsmBackendCtorFn(*this, STI, MRI, Options);
408
42.2k
  }
409
410
  /// createMCAsmParser - Create a target specific assembly parser.
411
  ///
412
  /// \param Parser The target independent parser implementation to use for
413
  /// parsing and lexing.
414
  MCTargetAsmParser *createMCAsmParser(const MCSubtargetInfo &STI,
415
                                       MCAsmParser &Parser,
416
                                       const MCInstrInfo &MII,
417
18.9k
                                       const MCTargetOptions &Options) const {
418
18.9k
    if (!MCAsmParserCtorFn)
419
0
      return nullptr;
420
18.9k
    return MCAsmParserCtorFn(STI, Parser, MII, Options);
421
18.9k
  }
422
423
  /// createAsmPrinter - Create a target specific assembly printer pass.  This
424
  /// takes ownership of the MCStreamer object.
425
  AsmPrinter *createAsmPrinter(TargetMachine &TM,
426
33.7k
                               std::unique_ptr<MCStreamer> &&Streamer) const {
427
33.7k
    if (!AsmPrinterCtorFn)
428
0
      return nullptr;
429
33.7k
    return AsmPrinterCtorFn(TM, std::move(Streamer));
430
33.7k
  }
431
432
  MCDisassembler *createMCDisassembler(const MCSubtargetInfo &STI,
433
                                       MCContext &Ctx) const {
434
    if (!MCDisassemblerCtorFn)
435
      return nullptr;
436
    return MCDisassemblerCtorFn(*this, STI, Ctx);
437
  }
438
439
  MCInstPrinter *createMCInstPrinter(const Triple &T, unsigned SyntaxVariant,
440
                                     const MCAsmInfo &MAI,
441
                                     const MCInstrInfo &MII,
442
25.6k
                                     const MCRegisterInfo &MRI) const {
443
25.6k
    if (!MCInstPrinterCtorFn)
444
0
      return nullptr;
445
25.6k
    return MCInstPrinterCtorFn(T, SyntaxVariant, MAI, MII, MRI);
446
25.6k
  }
447
448
  /// createMCCodeEmitter - Create a target specific code emitter.
449
  MCCodeEmitter *createMCCodeEmitter(const MCInstrInfo &II,
450
                                     const MCRegisterInfo &MRI,
451
157k
                                     MCContext &Ctx) const {
452
157k
    if (!MCCodeEmitterCtorFn)
453
0
      return nullptr;
454
157k
    return MCCodeEmitterCtorFn(II, MRI, Ctx);
455
157k
  }
456
457
  /// Create a target specific MCStreamer.
458
  ///
459
  /// \param T The target triple.
460
  /// \param Ctx The target context.
461
  /// \param TAB The target assembler backend object. Takes ownership.
462
  /// \param OW The stream object.
463
  /// \param Emitter The target independent assembler object.Takes ownership.
464
  /// \param RelaxAll Relax all fixups?
465
  MCStreamer *createMCObjectStreamer(const Triple &T, MCContext &Ctx,
466
                                     std::unique_ptr<MCAsmBackend> &&TAB,
467
                                     std::unique_ptr<MCObjectWriter> &&OW,
468
                                     std::unique_ptr<MCCodeEmitter> &&Emitter,
469
                                     const MCSubtargetInfo &STI, bool RelaxAll,
470
                                     bool IncrementalLinkerCompatible,
471
19.4k
                                     bool DWARFMustBeAtTheEnd) const {
472
19.4k
    MCStreamer *S;
473
19.4k
    switch (T.getObjectFormat()) {
474
19.4k
    default:
475
0
      llvm_unreachable("Unknown object format");
476
19.4k
    case Triple::COFF:
477
468
      assert(T.isOSWindows() && "only Windows COFF is supported");
478
468
      S = COFFStreamerCtorFn(Ctx, std::move(TAB), std::move(OW),
479
468
                             std::move(Emitter), RelaxAll,
480
468
                             IncrementalLinkerCompatible);
481
468
      break;
482
19.4k
    case Triple::MachO:
483
14.1k
      if (MachOStreamerCtorFn)
484
10.1k
        S = MachOStreamerCtorFn(Ctx, std::move(TAB), std::move(OW),
485
10.1k
                                std::move(Emitter), RelaxAll,
486
10.1k
                                DWARFMustBeAtTheEnd);
487
3.97k
      else
488
3.97k
        S = createMachOStreamer(Ctx, std::move(TAB), std::move(OW),
489
3.97k
                                std::move(Emitter), RelaxAll,
490
3.97k
                                DWARFMustBeAtTheEnd);
491
14.1k
      break;
492
19.4k
    case Triple::ELF:
493
4.65k
      if (ELFStreamerCtorFn)
494
2.06k
        S = ELFStreamerCtorFn(T, Ctx, std::move(TAB), std::move(OW),
495
2.06k
                              std::move(Emitter), RelaxAll);
496
2.58k
      else
497
2.58k
        S = createELFStreamer(Ctx, std::move(TAB), std::move(OW),
498
2.58k
                              std::move(Emitter), RelaxAll);
499
4.65k
      break;
500
19.4k
    case Triple::Wasm:
501
155
      if (WasmStreamerCtorFn)
502
0
        S = WasmStreamerCtorFn(T, Ctx, std::move(TAB), std::move(OW),
503
0
                               std::move(Emitter), RelaxAll);
504
155
      else
505
155
        S = createWasmStreamer(Ctx, std::move(TAB), std::move(OW),
506
155
                               std::move(Emitter), RelaxAll);
507
155
      break;
508
19.4k
    }
509
19.4k
    if (ObjectTargetStreamerCtorFn)
510
19.3k
      ObjectTargetStreamerCtorFn(*S, STI);
511
19.4k
    return S;
512
19.4k
  }
513
514
  MCStreamer *createAsmStreamer(MCContext &Ctx,
515
                                std::unique_ptr<formatted_raw_ostream> OS,
516
                                bool IsVerboseAsm, bool UseDwarfDirectory,
517
                                MCInstPrinter *InstPrint,
518
                                std::unique_ptr<MCCodeEmitter> &&CE,
519
                                std::unique_ptr<MCAsmBackend> &&TAB,
520
23.1k
                                bool ShowInst) const {
521
23.1k
    formatted_raw_ostream &OSRef = *OS;
522
23.1k
    MCStreamer *S = llvm::createAsmStreamer(
523
23.1k
        Ctx, std::move(OS), IsVerboseAsm, UseDwarfDirectory, InstPrint,
524
23.1k
        std::move(CE), std::move(TAB), ShowInst);
525
23.1k
    createAsmTargetStreamer(*S, OSRef, InstPrint, IsVerboseAsm);
526
23.1k
    return S;
527
23.1k
  }
528
529
  MCTargetStreamer *createAsmTargetStreamer(MCStreamer &S,
530
                                            formatted_raw_ostream &OS,
531
                                            MCInstPrinter *InstPrint,
532
23.1k
                                            bool IsVerboseAsm) const {
533
23.1k
    if (AsmTargetStreamerCtorFn)
534
21.8k
      return AsmTargetStreamerCtorFn(S, OS, InstPrint, IsVerboseAsm);
535
1.33k
    return nullptr;
536
1.33k
  }
537
538
17
  MCStreamer *createNullStreamer(MCContext &Ctx) const {
539
17
    MCStreamer *S = llvm::createNullStreamer(Ctx);
540
17
    createNullTargetStreamer(*S);
541
17
    return S;
542
17
  }
543
544
90
  MCTargetStreamer *createNullTargetStreamer(MCStreamer &S) const {
545
90
    if (NullTargetStreamerCtorFn)
546
5
      return NullTargetStreamerCtorFn(S);
547
85
    return nullptr;
548
85
  }
549
550
  /// createMCRelocationInfo - Create a target specific MCRelocationInfo.
551
  ///
552
  /// \param TT The target triple.
553
  /// \param Ctx The target context.
554
  MCRelocationInfo *createMCRelocationInfo(StringRef TT, MCContext &Ctx) const {
555
    MCRelocationInfoCtorTy Fn = MCRelocationInfoCtorFn
556
                                    ? MCRelocationInfoCtorFn
557
                                    : llvm::createMCRelocationInfo;
558
    return Fn(Triple(TT), Ctx);
559
  }
560
561
  /// createMCSymbolizer - Create a target specific MCSymbolizer.
562
  ///
563
  /// \param TT The target triple.
564
  /// \param GetOpInfo The function to get the symbolic information for
565
  /// operands.
566
  /// \param SymbolLookUp The function to lookup a symbol name.
567
  /// \param DisInfo The pointer to the block of symbolic information for above
568
  /// call
569
  /// back.
570
  /// \param Ctx The target context.
571
  /// \param RelInfo The relocation information for this target. Takes
572
  /// ownership.
573
  MCSymbolizer *
574
  createMCSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo,
575
                     LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo,
576
                     MCContext *Ctx,
577
                     std::unique_ptr<MCRelocationInfo> &&RelInfo) const {
578
    MCSymbolizerCtorTy Fn =
579
        MCSymbolizerCtorFn ? MCSymbolizerCtorFn : llvm::createMCSymbolizer;
580
    return Fn(Triple(TT), GetOpInfo, SymbolLookUp, DisInfo, Ctx,
581
              std::move(RelInfo));
582
  }
583
584
  /// @}
585
};
586
587
/// TargetRegistry - Generic interface to target specific features.
588
struct TargetRegistry {
589
  // FIXME: Make this a namespace, probably just move all the Register*
590
  // functions into Target (currently they all just set members on the Target
591
  // anyway, and Target friends this class so those functions can...
592
  // function).
593
  TargetRegistry() = delete;
594
595
  class iterator
596
      : public std::iterator<std::forward_iterator_tag, Target, ptrdiff_t> {
597
    friend struct TargetRegistry;
598
599
    const Target *Current = nullptr;
600
601
336k
    explicit iterator(Target *T) : Current(T) {}
602
603
  public:
604
336k
    iterator() = default;
605
606
2.12M
    bool operator==(const iterator &x) const { return Current == x.Current; }
607
2.01M
    bool operator!=(const iterator &x) const { return !operator==(x); }
608
609
    // Iterator traversal: forward iteration only
610
1.89M
    iterator &operator++() { // Preincrement
611
1.89M
      assert(Current && "Cannot increment end iterator!");
612
1.89M
      Current = Current->getNext();
613
1.89M
      return *this;
614
1.89M
    }
615
0
    iterator operator++(int) { // Postincrement
616
0
      iterator tmp = *this;
617
0
      ++*this;
618
0
      return tmp;
619
0
    }
620
621
1.96M
    const Target &operator*() const {
622
1.96M
      assert(Current && "Cannot dereference end iterator!");
623
1.96M
      return *Current;
624
1.96M
    }
625
626
0
    const Target *operator->() const { return &operator*(); }
627
  };
628
629
  /// printRegisteredTargetsForVersion - Print the registered targets
630
  /// appropriately for inclusion in a tool's version output.
631
  static void printRegisteredTargetsForVersion(raw_ostream &OS);
632
633
  /// @name Registry Access
634
  /// @{
635
636
  static iterator_range<iterator> targets();
637
638
  /// lookupTarget - Lookup a target based on a target triple.
639
  ///
640
  /// \param Triple - The triple to use for finding a target.
641
  /// \param Error - On failure, an error string describing why no target was
642
  /// found.
643
  static const Target *lookupTarget(const std::string &Triple,
644
                                    std::string &Error);
645
646
  /// lookupTarget - Lookup a target based on an architecture name
647
  /// and a target triple.  If the architecture name is non-empty,
648
  /// then the lookup is done by architecture.  Otherwise, the target
649
  /// triple is used.
650
  ///
651
  /// \param ArchName - The architecture to use for finding a target.
652
  /// \param TheTriple - The triple to use for finding a target.  The
653
  /// triple is updated with canonical architecture name if a lookup
654
  /// by architecture is done.
655
  /// \param Error - On failure, an error string describing why no target was
656
  /// found.
657
  static const Target *lookupTarget(const std::string &ArchName,
658
                                    Triple &TheTriple, std::string &Error);
659
660
  /// @}
661
  /// @name Target Registration
662
  /// @{
663
664
  /// RegisterTarget - Register the given target. Attempts to register a
665
  /// target which has already been registered will be ignored.
666
  ///
667
  /// Clients are responsible for ensuring that registration doesn't occur
668
  /// while another thread is attempting to access the registry. Typically
669
  /// this is done by initializing all targets at program startup.
670
  ///
671
  /// @param T - The target being registered.
672
  /// @param Name - The target name. This should be a static string.
673
  /// @param ShortDesc - A short target description. This should be a static
674
  /// string.
675
  /// @param BackendName - The name of the backend. This should be a static
676
  /// string that is the same for all targets that share a backend
677
  /// implementation and must match the name used in the 'def X : Target ...' in
678
  /// TableGen.
679
  /// @param ArchMatchFn - The arch match checking function for this target.
680
  /// @param HasJIT - Whether the target supports JIT code
681
  /// generation.
682
  static void RegisterTarget(Target &T, const char *Name, const char *ShortDesc,
683
                             const char *BackendName,
684
                             Target::ArchMatchFnTy ArchMatchFn,
685
                             bool HasJIT = false);
686
687
  /// RegisterMCAsmInfo - Register a MCAsmInfo implementation for the
688
  /// given target.
689
  ///
690
  /// Clients are responsible for ensuring that registration doesn't occur
691
  /// while another thread is attempting to access the registry. Typically
692
  /// this is done by initializing all targets at program startup.
693
  ///
694
  /// @param T - The target being registered.
695
  /// @param Fn - A function to construct a MCAsmInfo for the target.
696
2.82M
  static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn) {
697
2.82M
    T.MCAsmInfoCtorFn = Fn;
698
2.82M
  }
699
700
  /// RegisterMCInstrInfo - Register a MCInstrInfo implementation for the
701
  /// given target.
702
  ///
703
  /// Clients are responsible for ensuring that registration doesn't occur
704
  /// while another thread is attempting to access the registry. Typically
705
  /// this is done by initializing all targets at program startup.
706
  ///
707
  /// @param T - The target being registered.
708
  /// @param Fn - A function to construct a MCInstrInfo for the target.
709
2.82M
  static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn) {
710
2.82M
    T.MCInstrInfoCtorFn = Fn;
711
2.82M
  }
712
713
  /// RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for
714
  /// the given target.
715
  static void RegisterMCInstrAnalysis(Target &T,
716
1.53M
                                      Target::MCInstrAnalysisCtorFnTy Fn) {
717
1.53M
    T.MCInstrAnalysisCtorFn = Fn;
718
1.53M
  }
719
720
  /// RegisterMCRegInfo - Register a MCRegisterInfo implementation for the
721
  /// given target.
722
  ///
723
  /// Clients are responsible for ensuring that registration doesn't occur
724
  /// while another thread is attempting to access the registry. Typically
725
  /// this is done by initializing all targets at program startup.
726
  ///
727
  /// @param T - The target being registered.
728
  /// @param Fn - A function to construct a MCRegisterInfo for the target.
729
2.82M
  static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn) {
730
2.82M
    T.MCRegInfoCtorFn = Fn;
731
2.82M
  }
732
733
  /// RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for
734
  /// the given target.
735
  ///
736
  /// Clients are responsible for ensuring that registration doesn't occur
737
  /// while another thread is attempting to access the registry. Typically
738
  /// this is done by initializing all targets at program startup.
739
  ///
740
  /// @param T - The target being registered.
741
  /// @param Fn - A function to construct a MCSubtargetInfo for the target.
742
  static void RegisterMCSubtargetInfo(Target &T,
743
2.82M
                                      Target::MCSubtargetInfoCtorFnTy Fn) {
744
2.82M
    T.MCSubtargetInfoCtorFn = Fn;
745
2.82M
  }
746
747
  /// RegisterTargetMachine - Register a TargetMachine implementation for the
748
  /// given target.
749
  ///
750
  /// Clients are responsible for ensuring that registration doesn't occur
751
  /// while another thread is attempting to access the registry. Typically
752
  /// this is done by initializing all targets at program startup.
753
  ///
754
  /// @param T - The target being registered.
755
  /// @param Fn - A function to construct a TargetMachine for the target.
756
4.29M
  static void RegisterTargetMachine(Target &T, Target::TargetMachineCtorTy Fn) {
757
4.29M
    T.TargetMachineCtorFn = Fn;
758
4.29M
  }
759
760
  /// RegisterMCAsmBackend - Register a MCAsmBackend implementation for the
761
  /// given target.
762
  ///
763
  /// Clients are responsible for ensuring that registration doesn't occur
764
  /// while another thread is attempting to access the registry. Typically
765
  /// this is done by initializing all targets at program startup.
766
  ///
767
  /// @param T - The target being registered.
768
  /// @param Fn - A function to construct an AsmBackend for the target.
769
2.56M
  static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn) {
770
2.56M
    T.MCAsmBackendCtorFn = Fn;
771
2.56M
  }
772
773
  /// RegisterMCAsmParser - Register a MCTargetAsmParser implementation for
774
  /// the given target.
775
  ///
776
  /// Clients are responsible for ensuring that registration doesn't occur
777
  /// while another thread is attempting to access the registry. Typically
778
  /// this is done by initializing all targets at program startup.
779
  ///
780
  /// @param T - The target being registered.
781
  /// @param Fn - A function to construct an MCTargetAsmParser for the target.
782
2.45M
  static void RegisterMCAsmParser(Target &T, Target::MCAsmParserCtorTy Fn) {
783
2.45M
    T.MCAsmParserCtorFn = Fn;
784
2.45M
  }
785
786
  /// RegisterAsmPrinter - Register an AsmPrinter implementation for the given
787
  /// target.
788
  ///
789
  /// Clients are responsible for ensuring that registration doesn't occur
790
  /// while another thread is attempting to access the registry. Typically
791
  /// this is done by initializing all targets at program startup.
792
  ///
793
  /// @param T - The target being registered.
794
  /// @param Fn - A function to construct an AsmPrinter for the target.
795
2.37M
  static void RegisterAsmPrinter(Target &T, Target::AsmPrinterCtorTy Fn) {
796
2.37M
    T.AsmPrinterCtorFn = Fn;
797
2.37M
  }
798
799
  /// RegisterMCDisassembler - Register a MCDisassembler implementation for
800
  /// the given target.
801
  ///
802
  /// Clients are responsible for ensuring that registration doesn't occur
803
  /// while another thread is attempting to access the registry. Typically
804
  /// this is done by initializing all targets at program startup.
805
  ///
806
  /// @param T - The target being registered.
807
  /// @param Fn - A function to construct an MCDisassembler for the target.
808
  static void RegisterMCDisassembler(Target &T,
809
                                     Target::MCDisassemblerCtorTy Fn) {
810
    T.MCDisassemblerCtorFn = Fn;
811
  }
812
813
  /// RegisterMCInstPrinter - Register a MCInstPrinter implementation for the
814
  /// given target.
815
  ///
816
  /// Clients are responsible for ensuring that registration doesn't occur
817
  /// while another thread is attempting to access the registry. Typically
818
  /// this is done by initializing all targets at program startup.
819
  ///
820
  /// @param T - The target being registered.
821
  /// @param Fn - A function to construct an MCInstPrinter for the target.
822
2.82M
  static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn) {
823
2.82M
    T.MCInstPrinterCtorFn = Fn;
824
2.82M
  }
825
826
  /// RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the
827
  /// given target.
828
  ///
829
  /// Clients are responsible for ensuring that registration doesn't occur
830
  /// while another thread is attempting to access the registry. Typically
831
  /// this is done by initializing all targets at program startup.
832
  ///
833
  /// @param T - The target being registered.
834
  /// @param Fn - A function to construct an MCCodeEmitter for the target.
835
2.56M
  static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn) {
836
2.56M
    T.MCCodeEmitterCtorFn = Fn;
837
2.56M
  }
838
839
769k
  static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn) {
840
769k
    T.COFFStreamerCtorFn = Fn;
841
769k
  }
842
843
598k
  static void RegisterMachOStreamer(Target &T, Target::MachOStreamerCtorTy Fn) {
844
598k
    T.MachOStreamerCtorFn = Fn;
845
598k
  }
846
847
1.53M
  static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn) {
848
1.53M
    T.ELFStreamerCtorFn = Fn;
849
1.53M
  }
850
851
  static void RegisterWasmStreamer(Target &T, Target::WasmStreamerCtorTy Fn) {
852
    T.WasmStreamerCtorFn = Fn;
853
  }
854
855
  static void RegisterNullTargetStreamer(Target &T,
856
683k
                                         Target::NullTargetStreamerCtorTy Fn) {
857
683k
    T.NullTargetStreamerCtorFn = Fn;
858
683k
  }
859
860
  static void RegisterAsmTargetStreamer(Target &T,
861
2.22M
                                        Target::AsmTargetStreamerCtorTy Fn) {
862
2.22M
    T.AsmTargetStreamerCtorFn = Fn;
863
2.22M
  }
864
865
  static void
866
  RegisterObjectTargetStreamer(Target &T,
867
2.13M
                               Target::ObjectTargetStreamerCtorTy Fn) {
868
2.13M
    T.ObjectTargetStreamerCtorFn = Fn;
869
2.13M
  }
870
871
  /// RegisterMCRelocationInfo - Register an MCRelocationInfo
872
  /// implementation for the given target.
873
  ///
874
  /// Clients are responsible for ensuring that registration doesn't occur
875
  /// while another thread is attempting to access the registry. Typically
876
  /// this is done by initializing all targets at program startup.
877
  ///
878
  /// @param T - The target being registered.
879
  /// @param Fn - A function to construct an MCRelocationInfo for the target.
880
  static void RegisterMCRelocationInfo(Target &T,
881
598k
                                       Target::MCRelocationInfoCtorTy Fn) {
882
598k
    T.MCRelocationInfoCtorFn = Fn;
883
598k
  }
884
885
  /// RegisterMCSymbolizer - Register an MCSymbolizer
886
  /// implementation for the given target.
887
  ///
888
  /// Clients are responsible for ensuring that registration doesn't occur
889
  /// while another thread is attempting to access the registry. Typically
890
  /// this is done by initializing all targets at program startup.
891
  ///
892
  /// @param T - The target being registered.
893
  /// @param Fn - A function to construct an MCSymbolizer for the target.
894
  static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn) {
895
    T.MCSymbolizerCtorFn = Fn;
896
  }
897
898
  /// @}
899
};
900
901
//===--------------------------------------------------------------------===//
902
903
/// RegisterTarget - Helper template for registering a target, for use in the
904
/// target's initialization function. Usage:
905
///
906
///
907
/// Target &getTheFooTarget() { // The global target instance.
908
///   static Target TheFooTarget;
909
///   return TheFooTarget;
910
/// }
911
/// extern "C" void LLVMInitializeFooTargetInfo() {
912
///   RegisterTarget<Triple::foo> X(getTheFooTarget(), "foo", "Foo
913
///   description", "Foo" /* Backend Name */);
914
/// }
915
template <Triple::ArchType TargetArchType = Triple::UnknownArch,
916
          bool HasJIT = false>
917
struct RegisterTarget {
918
  RegisterTarget(Target &T, const char *Name, const char *Desc,
919
4.47M
                 const char *BackendName) {
920
4.47M
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
4.47M
                                   HasJIT);
922
4.47M
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)3, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)4, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)19, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)20, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)1, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)2, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)29, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)30, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)7, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)8, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)9, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)46, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)10, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)11, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)12, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)13, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)14, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)34, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)35, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)16, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)17, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)18, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)23, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)24, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)25, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)26, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)47, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)48, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)31, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)32, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)33, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
919
144k
                 const char *BackendName) {
920
144k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
921
144k
                                   HasJIT);
922
144k
  }
923
924
1.67M
  static bool getArchMatch(Triple::ArchType Arch) {
925
1.67M
    return Arch == TargetArchType;
926
1.67M
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)3, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)4, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)19, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)20, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)1, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)2, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)29, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)30, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)7, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)8, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)9, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)46, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)10, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)11, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)12, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)13, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)14, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)34, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)35, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)16, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)17, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)18, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)23, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)24, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)25, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)26, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)47, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)48, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)31, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
54.1k
  static bool getArchMatch(Triple::ArchType Arch) {
925
54.1k
    return Arch == TargetArchType;
926
54.1k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)32, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
54.1k
  static bool getArchMatch(Triple::ArchType Arch) {
925
54.1k
    return Arch == TargetArchType;
926
54.1k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)33, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
924
53.8k
  static bool getArchMatch(Triple::ArchType Arch) {
925
53.8k
    return Arch == TargetArchType;
926
53.8k
  }
927
};
928
929
/// RegisterMCAsmInfo - Helper template for registering a target assembly info
930
/// implementation.  This invokes the static "Create" method on the class to
931
/// actually do the construction.  Usage:
932
///
933
/// extern "C" void LLVMInitializeFooTarget() {
934
///   extern Target TheFooTarget;
935
///   RegisterMCAsmInfo<FooMCAsmInfo> X(TheFooTarget);
936
/// }
937
template <class MCAsmInfoImpl> struct RegisterMCAsmInfo {
938
769k
  RegisterMCAsmInfo(Target &T) {
939
769k
    TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
940
769k
  }
llvm::RegisterMCAsmInfo<llvm::AMDGPUMCAsmInfo>::RegisterMCAsmInfo(llvm::Target&)
Line
Count
Source
938
170k
  RegisterMCAsmInfo(Target &T) {
939
170k
    TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
940
170k
  }
llvm::RegisterMCAsmInfo<llvm::BPFMCAsmInfo>::RegisterMCAsmInfo(llvm::Target&)
Line
Count
Source
938
256k
  RegisterMCAsmInfo(Target &T) {
939
256k
    TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
940
256k
  }
llvm::RegisterMCAsmInfo<llvm::LanaiMCAsmInfo>::RegisterMCAsmInfo(llvm::Target&)
Line
Count
Source
938
85.4k
  RegisterMCAsmInfo(Target &T) {
939
85.4k
    TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
940
85.4k
  }
llvm::RegisterMCAsmInfo<llvm::MSP430MCAsmInfo>::RegisterMCAsmInfo(llvm::Target&)
Line
Count
Source
938
85.4k
  RegisterMCAsmInfo(Target &T) {
939
85.4k
    TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
940
85.4k
  }
llvm::RegisterMCAsmInfo<llvm::NVPTXMCAsmInfo>::RegisterMCAsmInfo(llvm::Target&)
Line
Count
Source
938
170k
  RegisterMCAsmInfo(Target &T) {
939
170k
    TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
940
170k
  }
941
942
private:
943
  static MCAsmInfo *Allocator(const MCRegisterInfo & /*MRI*/,
944
3.93k
                              const Triple &TT) {
945
3.93k
    return new MCAsmInfoImpl(TT);
946
3.93k
  }
llvm::RegisterMCAsmInfo<llvm::AMDGPUMCAsmInfo>::Allocator(llvm::MCRegisterInfo const&, llvm::Triple const&)
Line
Count
Source
944
3.32k
                              const Triple &TT) {
945
3.32k
    return new MCAsmInfoImpl(TT);
946
3.32k
  }
llvm::RegisterMCAsmInfo<llvm::BPFMCAsmInfo>::Allocator(llvm::MCRegisterInfo const&, llvm::Triple const&)
Line
Count
Source
944
84
                              const Triple &TT) {
945
84
    return new MCAsmInfoImpl(TT);
946
84
  }
llvm::RegisterMCAsmInfo<llvm::LanaiMCAsmInfo>::Allocator(llvm::MCRegisterInfo const&, llvm::Triple const&)
Line
Count
Source
944
32
                              const Triple &TT) {
945
32
    return new MCAsmInfoImpl(TT);
946
32
  }
llvm::RegisterMCAsmInfo<llvm::MSP430MCAsmInfo>::Allocator(llvm::MCRegisterInfo const&, llvm::Triple const&)
Line
Count
Source
944
74
                              const Triple &TT) {
945
74
    return new MCAsmInfoImpl(TT);
946
74
  }
llvm::RegisterMCAsmInfo<llvm::NVPTXMCAsmInfo>::Allocator(llvm::MCRegisterInfo const&, llvm::Triple const&)
Line
Count
Source
944
415
                              const Triple &TT) {
945
415
    return new MCAsmInfoImpl(TT);
946
415
  }
947
};
948
949
/// RegisterMCAsmInfoFn - Helper template for registering a target assembly info
950
/// implementation.  This invokes the specified function to do the
951
/// construction.  Usage:
952
///
953
/// extern "C" void LLVMInitializeFooTarget() {
954
///   extern Target TheFooTarget;
955
///   RegisterMCAsmInfoFn X(TheFooTarget, TheFunction);
956
/// }
957
struct RegisterMCAsmInfoFn {
958
1.96M
  RegisterMCAsmInfoFn(Target &T, Target::MCAsmInfoCtorFnTy Fn) {
959
1.96M
    TargetRegistry::RegisterMCAsmInfo(T, Fn);
960
1.96M
  }
961
};
962
963
/// RegisterMCInstrInfo - Helper template for registering a target instruction
964
/// info implementation.  This invokes the static "Create" method on the class
965
/// to actually do the construction.  Usage:
966
///
967
/// extern "C" void LLVMInitializeFooTarget() {
968
///   extern Target TheFooTarget;
969
///   RegisterMCInstrInfo<FooMCInstrInfo> X(TheFooTarget);
970
/// }
971
template <class MCInstrInfoImpl> struct RegisterMCInstrInfo {
972
  RegisterMCInstrInfo(Target &T) {
973
    TargetRegistry::RegisterMCInstrInfo(T, &Allocator);
974
  }
975
976
private:
977
  static MCInstrInfo *Allocator() { return new MCInstrInfoImpl(); }
978
};
979
980
/// RegisterMCInstrInfoFn - Helper template for registering a target
981
/// instruction info implementation.  This invokes the specified function to
982
/// do the construction.  Usage:
983
///
984
/// extern "C" void LLVMInitializeFooTarget() {
985
///   extern Target TheFooTarget;
986
///   RegisterMCInstrInfoFn X(TheFooTarget, TheFunction);
987
/// }
988
struct RegisterMCInstrInfoFn {
989
  RegisterMCInstrInfoFn(Target &T, Target::MCInstrInfoCtorFnTy Fn) {
990
    TargetRegistry::RegisterMCInstrInfo(T, Fn);
991
  }
992
};
993
994
/// RegisterMCInstrAnalysis - Helper template for registering a target
995
/// instruction analyzer implementation.  This invokes the static "Create"
996
/// method on the class to actually do the construction.  Usage:
997
///
998
/// extern "C" void LLVMInitializeFooTarget() {
999
///   extern Target TheFooTarget;
1000
///   RegisterMCInstrAnalysis<FooMCInstrAnalysis> X(TheFooTarget);
1001
/// }
1002
template <class MCInstrAnalysisImpl> struct RegisterMCInstrAnalysis {
1003
  RegisterMCInstrAnalysis(Target &T) {
1004
    TargetRegistry::RegisterMCInstrAnalysis(T, &Allocator);
1005
  }
1006
1007
private:
1008
  static MCInstrAnalysis *Allocator(const MCInstrInfo *Info) {
1009
    return new MCInstrAnalysisImpl(Info);
1010
  }
1011
};
1012
1013
/// RegisterMCInstrAnalysisFn - Helper template for registering a target
1014
/// instruction analyzer implementation.  This invokes the specified function
1015
/// to do the construction.  Usage:
1016
///
1017
/// extern "C" void LLVMInitializeFooTarget() {
1018
///   extern Target TheFooTarget;
1019
///   RegisterMCInstrAnalysisFn X(TheFooTarget, TheFunction);
1020
/// }
1021
struct RegisterMCInstrAnalysisFn {
1022
  RegisterMCInstrAnalysisFn(Target &T, Target::MCInstrAnalysisCtorFnTy Fn) {
1023
    TargetRegistry::RegisterMCInstrAnalysis(T, Fn);
1024
  }
1025
};
1026
1027
/// RegisterMCRegInfo - Helper template for registering a target register info
1028
/// implementation.  This invokes the static "Create" method on the class to
1029
/// actually do the construction.  Usage:
1030
///
1031
/// extern "C" void LLVMInitializeFooTarget() {
1032
///   extern Target TheFooTarget;
1033
///   RegisterMCRegInfo<FooMCRegInfo> X(TheFooTarget);
1034
/// }
1035
template <class MCRegisterInfoImpl> struct RegisterMCRegInfo {
1036
  RegisterMCRegInfo(Target &T) {
1037
    TargetRegistry::RegisterMCRegInfo(T, &Allocator);
1038
  }
1039
1040
private:
1041
  static MCRegisterInfo *Allocator(const Triple & /*TT*/) {
1042
    return new MCRegisterInfoImpl();
1043
  }
1044
};
1045
1046
/// RegisterMCRegInfoFn - Helper template for registering a target register
1047
/// info implementation.  This invokes the specified function to do the
1048
/// construction.  Usage:
1049
///
1050
/// extern "C" void LLVMInitializeFooTarget() {
1051
///   extern Target TheFooTarget;
1052
///   RegisterMCRegInfoFn X(TheFooTarget, TheFunction);
1053
/// }
1054
struct RegisterMCRegInfoFn {
1055
  RegisterMCRegInfoFn(Target &T, Target::MCRegInfoCtorFnTy Fn) {
1056
    TargetRegistry::RegisterMCRegInfo(T, Fn);
1057
  }
1058
};
1059
1060
/// RegisterMCSubtargetInfo - Helper template for registering a target
1061
/// subtarget info implementation.  This invokes the static "Create" method
1062
/// on the class to actually do the construction.  Usage:
1063
///
1064
/// extern "C" void LLVMInitializeFooTarget() {
1065
///   extern Target TheFooTarget;
1066
///   RegisterMCSubtargetInfo<FooMCSubtargetInfo> X(TheFooTarget);
1067
/// }
1068
template <class MCSubtargetInfoImpl> struct RegisterMCSubtargetInfo {
1069
  RegisterMCSubtargetInfo(Target &T) {
1070
    TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator);
1071
  }
1072
1073
private:
1074
  static MCSubtargetInfo *Allocator(const Triple & /*TT*/, StringRef /*CPU*/,
1075
                                    StringRef /*FS*/) {
1076
    return new MCSubtargetInfoImpl();
1077
  }
1078
};
1079
1080
/// RegisterMCSubtargetInfoFn - Helper template for registering a target
1081
/// subtarget info implementation.  This invokes the specified function to
1082
/// do the construction.  Usage:
1083
///
1084
/// extern "C" void LLVMInitializeFooTarget() {
1085
///   extern Target TheFooTarget;
1086
///   RegisterMCSubtargetInfoFn X(TheFooTarget, TheFunction);
1087
/// }
1088
struct RegisterMCSubtargetInfoFn {
1089
  RegisterMCSubtargetInfoFn(Target &T, Target::MCSubtargetInfoCtorFnTy Fn) {
1090
    TargetRegistry::RegisterMCSubtargetInfo(T, Fn);
1091
  }
1092
};
1093
1094
/// RegisterTargetMachine - Helper template for registering a target machine
1095
/// implementation, for use in the target machine initialization
1096
/// function. Usage:
1097
///
1098
/// extern "C" void LLVMInitializeFooTarget() {
1099
///   extern Target TheFooTarget;
1100
///   RegisterTargetMachine<FooTargetMachine> X(TheFooTarget);
1101
/// }
1102
template <class TargetMachineImpl> struct RegisterTargetMachine {
1103
4.29M
  RegisterTargetMachine(Target &T) {
1104
4.29M
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
4.29M
  }
llvm::RegisterTargetMachine<llvm::AArch64leTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
260k
  RegisterTargetMachine(Target &T) {
1104
260k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
260k
  }
llvm::RegisterTargetMachine<llvm::AArch64beTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
130k
  RegisterTargetMachine(Target &T) {
1104
130k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
130k
  }
llvm::RegisterTargetMachine<llvm::R600TargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
130k
  RegisterTargetMachine(Target &T) {
1104
130k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
130k
  }
llvm::RegisterTargetMachine<llvm::GCNTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
130k
  RegisterTargetMachine(Target &T) {
1104
130k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
130k
  }
llvm::RegisterTargetMachine<llvm::ARMLETargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
260k
  RegisterTargetMachine(Target &T) {
1104
260k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
260k
  }
llvm::RegisterTargetMachine<llvm::ARMBETargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
260k
  RegisterTargetMachine(Target &T) {
1104
260k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
260k
  }
llvm::RegisterTargetMachine<llvm::BPFTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
390k
  RegisterTargetMachine(Target &T) {
1104
390k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
390k
  }
llvm::RegisterTargetMachine<llvm::HexagonTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
130k
  RegisterTargetMachine(Target &T) {
1104
130k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
130k
  }
llvm::RegisterTargetMachine<llvm::LanaiTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
130k
  RegisterTargetMachine(Target &T) {
1104
130k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
130k
  }
llvm::RegisterTargetMachine<llvm::MipsebTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
260k
  RegisterTargetMachine(Target &T) {
1104
260k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
260k
  }
llvm::RegisterTargetMachine<llvm::MipselTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
260k
  RegisterTargetMachine(Target &T) {
1104
260k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
260k
  }
llvm::RegisterTargetMachine<llvm::MSP430TargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
130k
  RegisterTargetMachine(Target &T) {
1104
130k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
130k
  }
llvm::RegisterTargetMachine<llvm::NVPTXTargetMachine32>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
130k
  RegisterTargetMachine(Target &T) {
1104
130k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
130k
  }
llvm::RegisterTargetMachine<llvm::NVPTXTargetMachine64>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
130k
  RegisterTargetMachine(Target &T) {
1104
130k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
130k
  }
llvm::RegisterTargetMachine<llvm::PPCTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
390k
  RegisterTargetMachine(Target &T) {
1104
390k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
390k
  }
llvm::RegisterTargetMachine<llvm::SparcV8TargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
130k
  RegisterTargetMachine(Target &T) {
1104
130k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
130k
  }
llvm::RegisterTargetMachine<llvm::SparcV9TargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
130k
  RegisterTargetMachine(Target &T) {
1104
130k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
130k
  }
llvm::RegisterTargetMachine<llvm::SparcelTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
130k
  RegisterTargetMachine(Target &T) {
1104
130k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
130k
  }
llvm::RegisterTargetMachine<llvm::SystemZTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
130k
  RegisterTargetMachine(Target &T) {
1104
130k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
130k
  }
llvm::RegisterTargetMachine<llvm::WebAssemblyTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
260k
  RegisterTargetMachine(Target &T) {
1104
260k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
260k
  }
llvm::RegisterTargetMachine<llvm::X86TargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
260k
  RegisterTargetMachine(Target &T) {
1104
260k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
260k
  }
llvm::RegisterTargetMachine<llvm::XCoreTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1103
130k
  RegisterTargetMachine(Target &T) {
1104
130k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1105
130k
  }
1106
1107
private:
1108
  static TargetMachine *
1109
  Allocator(const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
1110
            const TargetOptions &Options, Optional<Reloc::Model> RM,
1111
47.5k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
47.5k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
47.5k
  }
llvm::RegisterTargetMachine<llvm::AArch64leTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
9.12k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
9.12k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
9.12k
  }
llvm::RegisterTargetMachine<llvm::AArch64beTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
36
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
36
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
36
  }
llvm::RegisterTargetMachine<llvm::R600TargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
295
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
295
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
295
  }
llvm::RegisterTargetMachine<llvm::GCNTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
2.56k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
2.56k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
2.56k
  }
llvm::RegisterTargetMachine<llvm::ARMLETargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
5.54k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
5.54k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
5.54k
  }
llvm::RegisterTargetMachine<llvm::ARMBETargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
47
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
47
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
47
  }
llvm::RegisterTargetMachine<llvm::BPFTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
67
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
67
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
67
  }
llvm::RegisterTargetMachine<llvm::HexagonTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
1.00k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
1.00k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
1.00k
  }
llvm::RegisterTargetMachine<llvm::LanaiTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
26
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
26
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
26
  }
llvm::RegisterTargetMachine<llvm::MipsebTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
1.11k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
1.11k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
1.11k
  }
llvm::RegisterTargetMachine<llvm::MipselTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
1.04k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
1.04k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
1.04k
  }
llvm::RegisterTargetMachine<llvm::MSP430TargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
64
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
64
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
64
  }
llvm::RegisterTargetMachine<llvm::NVPTXTargetMachine32>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
232
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
232
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
232
  }
llvm::RegisterTargetMachine<llvm::NVPTXTargetMachine64>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
183
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
183
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
183
  }
llvm::RegisterTargetMachine<llvm::PPCTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
3.31k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
3.31k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
3.31k
  }
llvm::RegisterTargetMachine<llvm::SparcV8TargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
150
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
150
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
150
  }
llvm::RegisterTargetMachine<llvm::SparcV9TargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
70
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
70
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
70
  }
llvm::RegisterTargetMachine<llvm::SparcelTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
5
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
5
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
5
  }
llvm::RegisterTargetMachine<llvm::SystemZTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
970
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
970
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
970
  }
llvm::RegisterTargetMachine<llvm::WebAssemblyTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
370
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
370
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
370
  }
llvm::RegisterTargetMachine<llvm::X86TargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
21.2k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
21.2k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
21.2k
  }
llvm::RegisterTargetMachine<llvm::XCoreTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1111
82
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1112
82
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1113
82
  }
1114
};
1115
1116
/// RegisterMCAsmBackend - Helper template for registering a target specific
1117
/// assembler backend. Usage:
1118
///
1119
/// extern "C" void LLVMInitializeFooMCAsmBackend() {
1120
///   extern Target TheFooTarget;
1121
///   RegisterMCAsmBackend<FooAsmLexer> X(TheFooTarget);
1122
/// }
1123
template <class MCAsmBackendImpl> struct RegisterMCAsmBackend {
1124
  RegisterMCAsmBackend(Target &T) {
1125
    TargetRegistry::RegisterMCAsmBackend(T, &Allocator);
1126
  }
1127
1128
private:
1129
  static MCAsmBackend *Allocator(const Target &T, const MCSubtargetInfo &STI,
1130
                                 const MCRegisterInfo &MRI,
1131
                                 const MCTargetOptions &Options) {
1132
    return new MCAsmBackendImpl(T, STI, MRI);
1133
  }
1134
};
1135
1136
/// RegisterMCAsmParser - Helper template for registering a target specific
1137
/// assembly parser, for use in the target machine initialization
1138
/// function. Usage:
1139
///
1140
/// extern "C" void LLVMInitializeFooMCAsmParser() {
1141
///   extern Target TheFooTarget;
1142
///   RegisterMCAsmParser<FooAsmParser> X(TheFooTarget);
1143
/// }
1144
template <class MCAsmParserImpl> struct RegisterMCAsmParser {
1145
2.45M
  RegisterMCAsmParser(Target &T) {
1146
2.45M
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1147
2.45M
  }
AArch64AsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::AArch64AsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1145
245k
  RegisterMCAsmParser(Target &T) {
1146
245k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1147
245k
  }
AMDGPUAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::AMDGPUAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1145
163k
  RegisterMCAsmParser(Target &T) {
1146
163k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1147
163k
  }
ARMAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::ARMAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1145
327k
  RegisterMCAsmParser(Target &T) {
1146
327k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1147
327k
  }
BPFAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::BPFAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1145
245k
  RegisterMCAsmParser(Target &T) {
1146
245k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1147
245k
  }
HexagonAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::HexagonAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1145
81.8k
  RegisterMCAsmParser(Target &T) {
1146
81.8k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1147
81.8k
  }
LanaiAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::LanaiAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1145
81.8k
  RegisterMCAsmParser(Target &T) {
1146
81.8k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1147
81.8k
  }
MipsAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::MipsAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1145
327k
  RegisterMCAsmParser(Target &T) {
1146
327k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1147
327k
  }
MSP430AsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::MSP430AsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1145
81.8k
  RegisterMCAsmParser(Target &T) {
1146
81.8k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1147
81.8k
  }
PPCAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::PPCAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1145
245k
  RegisterMCAsmParser(Target &T) {
1146
245k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1147
245k
  }
SparcAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::SparcAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1145
245k
  RegisterMCAsmParser(Target &T) {
1146
245k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1147
245k
  }
SystemZAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::SystemZAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1145
81.8k
  RegisterMCAsmParser(Target &T) {
1146
81.8k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1147
81.8k
  }
WebAssemblyAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::WebAssemblyAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1145
163k
  RegisterMCAsmParser(Target &T) {
1146
163k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1147
163k
  }
X86AsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::X86AsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1145
164k
  RegisterMCAsmParser(Target &T) {
1146
164k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1147
164k
  }
1148
1149
private:
1150
  static MCTargetAsmParser *Allocator(const MCSubtargetInfo &STI,
1151
                                      MCAsmParser &P, const MCInstrInfo &MII,
1152
18.9k
                                      const MCTargetOptions &Options) {
1153
18.9k
    return new MCAsmParserImpl(STI, P, MII, Options);
1154
18.9k
  }
AArch64AsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::AArch64AsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1152
2.33k
                                      const MCTargetOptions &Options) {
1153
2.33k
    return new MCAsmParserImpl(STI, P, MII, Options);
1154
2.33k
  }
AMDGPUAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::AMDGPUAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1152
378
                                      const MCTargetOptions &Options) {
1153
378
    return new MCAsmParserImpl(STI, P, MII, Options);
1154
378
  }
ARMAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::ARMAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1152
2.19k
                                      const MCTargetOptions &Options) {
1153
2.19k
    return new MCAsmParserImpl(STI, P, MII, Options);
1154
2.19k
  }
BPFAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::BPFAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1152
3
                                      const MCTargetOptions &Options) {
1153
3
    return new MCAsmParserImpl(STI, P, MII, Options);
1154
3
  }
HexagonAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::HexagonAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1152
115
                                      const MCTargetOptions &Options) {
1153
115
    return new MCAsmParserImpl(STI, P, MII, Options);
1154
115
  }
LanaiAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::LanaiAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1152
4
                                      const MCTargetOptions &Options) {
1153
4
    return new MCAsmParserImpl(STI, P, MII, Options);
1154
4
  }
MipsAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::MipsAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1152
1.30k
                                      const MCTargetOptions &Options) {
1153
1.30k
    return new MCAsmParserImpl(STI, P, MII, Options);
1154
1.30k
  }
MSP430AsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::MSP430AsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1152
7
                                      const MCTargetOptions &Options) {
1153
7
    return new MCAsmParserImpl(STI, P, MII, Options);
1154
7
  }
PPCAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::PPCAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1152
423
                                      const MCTargetOptions &Options) {
1153
423
    return new MCAsmParserImpl(STI, P, MII, Options);
1154
423
  }
SparcAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::SparcAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1152
103
                                      const MCTargetOptions &Options) {
1153
103
    return new MCAsmParserImpl(STI, P, MII, Options);
1154
103
  }
SystemZAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::SystemZAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1152
40
                                      const MCTargetOptions &Options) {
1153
40
    return new MCAsmParserImpl(STI, P, MII, Options);
1154
40
  }
WebAssemblyAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::WebAssemblyAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1152
4
                                      const MCTargetOptions &Options) {
1153
4
    return new MCAsmParserImpl(STI, P, MII, Options);
1154
4
  }
X86AsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::X86AsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1152
12.0k
                                      const MCTargetOptions &Options) {
1153
12.0k
    return new MCAsmParserImpl(STI, P, MII, Options);
1154
12.0k
  }
1155
};
1156
1157
/// RegisterAsmPrinter - Helper template for registering a target specific
1158
/// assembly printer, for use in the target machine initialization
1159
/// function. Usage:
1160
///
1161
/// extern "C" void LLVMInitializeFooAsmPrinter() {
1162
///   extern Target TheFooTarget;
1163
///   RegisterAsmPrinter<FooAsmPrinter> X(TheFooTarget);
1164
/// }
1165
template <class AsmPrinterImpl> struct RegisterAsmPrinter {
1166
2.01M
  RegisterAsmPrinter(Target &T) {
1167
2.01M
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1168
2.01M
  }
AArch64AsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::AArch64AsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1166
215k
  RegisterAsmPrinter(Target &T) {
1167
215k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1168
215k
  }
llvm::RegisterAsmPrinter<llvm::ARMAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1166
287k
  RegisterAsmPrinter(Target &T) {
1167
287k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1168
287k
  }
BPFAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::BPFAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1166
215k
  RegisterAsmPrinter(Target &T) {
1167
215k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1168
215k
  }
llvm::RegisterAsmPrinter<llvm::HexagonAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1166
71.9k
  RegisterAsmPrinter(Target &T) {
1167
71.9k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1168
71.9k
  }
LanaiAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::LanaiAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1166
71.9k
  RegisterAsmPrinter(Target &T) {
1167
71.9k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1168
71.9k
  }
llvm::RegisterAsmPrinter<llvm::MipsAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1166
287k
  RegisterAsmPrinter(Target &T) {
1167
287k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1168
287k
  }
MSP430AsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::MSP430AsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1166
71.9k
  RegisterAsmPrinter(Target &T) {
1167
71.9k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1168
71.9k
  }
llvm::RegisterAsmPrinter<llvm::NVPTXAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1166
143k
  RegisterAsmPrinter(Target &T) {
1167
143k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1168
143k
  }
SparcAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::SparcAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1166
215k
  RegisterAsmPrinter(Target &T) {
1167
215k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1168
215k
  }
llvm::RegisterAsmPrinter<llvm::SystemZAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1166
71.9k
  RegisterAsmPrinter(Target &T) {
1167
71.9k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1168
71.9k
  }
llvm::RegisterAsmPrinter<llvm::WebAssemblyAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1166
143k
  RegisterAsmPrinter(Target &T) {
1167
143k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1168
143k
  }
llvm::RegisterAsmPrinter<llvm::X86AsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1166
144k
  RegisterAsmPrinter(Target &T) {
1167
144k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1168
144k
  }
XCoreAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::XCoreAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1166
71.9k
  RegisterAsmPrinter(Target &T) {
1167
71.9k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1168
71.9k
  }
1169
1170
private:
1171
  static AsmPrinter *Allocator(TargetMachine &TM,
1172
29.9k
                               std::unique_ptr<MCStreamer> &&Streamer) {
1173
29.9k
    return new AsmPrinterImpl(TM, std::move(Streamer));
1174
29.9k
  }
AArch64AsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::AArch64AsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1172
8.47k
                               std::unique_ptr<MCStreamer> &&Streamer) {
1173
8.47k
    return new AsmPrinterImpl(TM, std::move(Streamer));
1174
8.47k
  }
llvm::RegisterAsmPrinter<llvm::ARMAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1172
4.94k
                               std::unique_ptr<MCStreamer> &&Streamer) {
1173
4.94k
    return new AsmPrinterImpl(TM, std::move(Streamer));
1174
4.94k
  }
BPFAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::BPFAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1172
65
                               std::unique_ptr<MCStreamer> &&Streamer) {
1173
65
    return new AsmPrinterImpl(TM, std::move(Streamer));
1174
65
  }
llvm::RegisterAsmPrinter<llvm::HexagonAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1172
908
                               std::unique_ptr<MCStreamer> &&Streamer) {
1173
908
    return new AsmPrinterImpl(TM, std::move(Streamer));
1174
908
  }
LanaiAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::LanaiAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1172
21
                               std::unique_ptr<MCStreamer> &&Streamer) {
1173
21
    return new AsmPrinterImpl(TM, std::move(Streamer));
1174
21
  }
llvm::RegisterAsmPrinter<llvm::MipsAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1172
1.89k
                               std::unique_ptr<MCStreamer> &&Streamer) {
1173
1.89k
    return new AsmPrinterImpl(TM, std::move(Streamer));
1174
1.89k
  }
MSP430AsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::MSP430AsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1172
62
                               std::unique_ptr<MCStreamer> &&Streamer) {
1173
62
    return new AsmPrinterImpl(TM, std::move(Streamer));
1174
62
  }
llvm::RegisterAsmPrinter<llvm::NVPTXAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1172
246
                               std::unique_ptr<MCStreamer> &&Streamer) {
1173
246
    return new AsmPrinterImpl(TM, std::move(Streamer));
1174
246
  }
SparcAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::SparcAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1172
195
                               std::unique_ptr<MCStreamer> &&Streamer) {
1173
195
    return new AsmPrinterImpl(TM, std::move(Streamer));
1174
195
  }
llvm::RegisterAsmPrinter<llvm::SystemZAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1172
896
                               std::unique_ptr<MCStreamer> &&Streamer) {
1173
896
    return new AsmPrinterImpl(TM, std::move(Streamer));
1174
896
  }
llvm::RegisterAsmPrinter<llvm::WebAssemblyAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1172
320
                               std::unique_ptr<MCStreamer> &&Streamer) {
1173
320
    return new AsmPrinterImpl(TM, std::move(Streamer));
1174
320
  }
llvm::RegisterAsmPrinter<llvm::X86AsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1172
11.8k
                               std::unique_ptr<MCStreamer> &&Streamer) {
1173
11.8k
    return new AsmPrinterImpl(TM, std::move(Streamer));
1174
11.8k
  }
XCoreAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::XCoreAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1172
69
                               std::unique_ptr<MCStreamer> &&Streamer) {
1173
69
    return new AsmPrinterImpl(TM, std::move(Streamer));
1174
69
  }
1175
};
1176
1177
/// RegisterMCCodeEmitter - Helper template for registering a target specific
1178
/// machine code emitter, for use in the target initialization
1179
/// function. Usage:
1180
///
1181
/// extern "C" void LLVMInitializeFooMCCodeEmitter() {
1182
///   extern Target TheFooTarget;
1183
///   RegisterMCCodeEmitter<FooCodeEmitter> X(TheFooTarget);
1184
/// }
1185
template <class MCCodeEmitterImpl> struct RegisterMCCodeEmitter {
1186
  RegisterMCCodeEmitter(Target &T) {
1187
    TargetRegistry::RegisterMCCodeEmitter(T, &Allocator);
1188
  }
1189
1190
private:
1191
  static MCCodeEmitter *Allocator(const MCInstrInfo & /*II*/,
1192
                                  const MCRegisterInfo & /*MRI*/,
1193
                                  MCContext & /*Ctx*/) {
1194
    return new MCCodeEmitterImpl();
1195
  }
1196
};
1197
1198
} // end namespace llvm
1199
1200
#endif // LLVM_SUPPORT_TARGETREGISTRY_H