Coverage Report

Created: 2019-02-20 07:29

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/Support/TargetRegistry.h
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//===- Support/TargetRegistry.h - Target Registration -----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file exposes the TargetRegistry interface, which tools can use to access
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// the appropriate target specific classes (TargetMachine, AsmPrinter, etc.)
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// which have been registered.
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//
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// Target specific class implementations should register themselves using the
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// appropriate TargetRegistry interfaces.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_SUPPORT_TARGETREGISTRY_H
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#define LLVM_SUPPORT_TARGETREGISTRY_H
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#include "llvm-c/DisassemblerTypes.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/ADT/iterator_range.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormattedStream.h"
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#include <algorithm>
30
#include <cassert>
31
#include <cstddef>
32
#include <iterator>
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#include <memory>
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#include <string>
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36
namespace llvm {
37
38
class AsmPrinter;
39
class MCAsmBackend;
40
class MCAsmInfo;
41
class MCAsmParser;
42
class MCCodeEmitter;
43
class MCContext;
44
class MCDisassembler;
45
class MCInstPrinter;
46
class MCInstrAnalysis;
47
class MCInstrInfo;
48
class MCObjectWriter;
49
class MCRegisterInfo;
50
class MCRelocationInfo;
51
class MCStreamer;
52
class MCSubtargetInfo;
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class MCSymbolizer;
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class MCTargetAsmParser;
55
class MCTargetOptions;
56
class MCTargetStreamer;
57
class raw_ostream;
58
class raw_pwrite_stream;
59
class TargetMachine;
60
class TargetOptions;
61
62
MCStreamer *createNullStreamer(MCContext &Ctx);
63
// Takes ownership of \p TAB and \p CE.
64
65
/// Create a machine code streamer which will print out assembly for the native
66
/// target, suitable for compiling with a native assembler.
67
///
68
/// \param InstPrint - If given, the instruction printer to use. If not given
69
/// the MCInst representation will be printed.  This method takes ownership of
70
/// InstPrint.
71
///
72
/// \param CE - If given, a code emitter to use to show the instruction
73
/// encoding inline with the assembly. This method takes ownership of \p CE.
74
///
75
/// \param TAB - If given, a target asm backend to use to show the fixup
76
/// information in conjunction with encoding information. This method takes
77
/// ownership of \p TAB.
78
///
79
/// \param ShowInst - Whether to show the MCInst representation inline with
80
/// the assembly.
81
MCStreamer *
82
createAsmStreamer(MCContext &Ctx, std::unique_ptr<formatted_raw_ostream> OS,
83
                  bool isVerboseAsm, bool useDwarfDirectory,
84
                  MCInstPrinter *InstPrint, std::unique_ptr<MCCodeEmitter> &&CE,
85
                  std::unique_ptr<MCAsmBackend> &&TAB, bool ShowInst);
86
87
MCStreamer *createELFStreamer(MCContext &Ctx,
88
                              std::unique_ptr<MCAsmBackend> &&TAB,
89
                              std::unique_ptr<MCObjectWriter> &&OW,
90
                              std::unique_ptr<MCCodeEmitter> &&CE,
91
                              bool RelaxAll);
92
MCStreamer *createMachOStreamer(MCContext &Ctx,
93
                                std::unique_ptr<MCAsmBackend> &&TAB,
94
                                std::unique_ptr<MCObjectWriter> &&OW,
95
                                std::unique_ptr<MCCodeEmitter> &&CE,
96
                                bool RelaxAll, bool DWARFMustBeAtTheEnd,
97
                                bool LabelSections = false);
98
MCStreamer *createWasmStreamer(MCContext &Ctx,
99
                               std::unique_ptr<MCAsmBackend> &&TAB,
100
                               std::unique_ptr<MCObjectWriter> &&OW,
101
                               std::unique_ptr<MCCodeEmitter> &&CE,
102
                               bool RelaxAll);
103
104
MCRelocationInfo *createMCRelocationInfo(const Triple &TT, MCContext &Ctx);
105
106
MCSymbolizer *createMCSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
107
                                 LLVMSymbolLookupCallback SymbolLookUp,
108
                                 void *DisInfo, MCContext *Ctx,
109
                                 std::unique_ptr<MCRelocationInfo> &&RelInfo);
110
111
/// Target - Wrapper for Target specific information.
112
///
113
/// For registration purposes, this is a POD type so that targets can be
114
/// registered without the use of static constructors.
115
///
116
/// Targets should implement a single global instance of this class (which
117
/// will be zero initialized), and pass that instance to the TargetRegistry as
118
/// part of their initialization.
119
class Target {
120
public:
121
  friend struct TargetRegistry;
122
123
  using ArchMatchFnTy = bool (*)(Triple::ArchType Arch);
124
125
  using MCAsmInfoCtorFnTy = MCAsmInfo *(*)(const MCRegisterInfo &MRI,
126
                                           const Triple &TT);
127
  using MCInstrInfoCtorFnTy = MCInstrInfo *(*)();
128
  using MCInstrAnalysisCtorFnTy = MCInstrAnalysis *(*)(const MCInstrInfo *Info);
129
  using MCRegInfoCtorFnTy = MCRegisterInfo *(*)(const Triple &TT);
130
  using MCSubtargetInfoCtorFnTy = MCSubtargetInfo *(*)(const Triple &TT,
131
                                                       StringRef CPU,
132
                                                       StringRef Features);
133
  using TargetMachineCtorTy = TargetMachine
134
      *(*)(const Target &T, const Triple &TT, StringRef CPU, StringRef Features,
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           const TargetOptions &Options, Optional<Reloc::Model> RM,
136
           Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT);
137
  // If it weren't for layering issues (this header is in llvm/Support, but
138
  // depends on MC?) this should take the Streamer by value rather than rvalue
139
  // reference.
140
  using AsmPrinterCtorTy = AsmPrinter *(*)(
141
      TargetMachine &TM, std::unique_ptr<MCStreamer> &&Streamer);
142
  using MCAsmBackendCtorTy = MCAsmBackend *(*)(const Target &T,
143
                                               const MCSubtargetInfo &STI,
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                                               const MCRegisterInfo &MRI,
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                                               const MCTargetOptions &Options);
146
  using MCAsmParserCtorTy = MCTargetAsmParser *(*)(
147
      const MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII,
148
      const MCTargetOptions &Options);
149
  using MCDisassemblerCtorTy = MCDisassembler *(*)(const Target &T,
150
                                                   const MCSubtargetInfo &STI,
151
                                                   MCContext &Ctx);
152
  using MCInstPrinterCtorTy = MCInstPrinter *(*)(const Triple &T,
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                                                 unsigned SyntaxVariant,
154
                                                 const MCAsmInfo &MAI,
155
                                                 const MCInstrInfo &MII,
156
                                                 const MCRegisterInfo &MRI);
157
  using MCCodeEmitterCtorTy = MCCodeEmitter *(*)(const MCInstrInfo &II,
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                                                 const MCRegisterInfo &MRI,
159
                                                 MCContext &Ctx);
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  using ELFStreamerCtorTy =
161
      MCStreamer *(*)(const Triple &T, MCContext &Ctx,
162
                      std::unique_ptr<MCAsmBackend> &&TAB,
163
                      std::unique_ptr<MCObjectWriter> &&OW,
164
                      std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll);
165
  using MachOStreamerCtorTy =
166
      MCStreamer *(*)(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
167
                      std::unique_ptr<MCObjectWriter> &&OW,
168
                      std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
169
                      bool DWARFMustBeAtTheEnd);
170
  using COFFStreamerCtorTy =
171
      MCStreamer *(*)(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
172
                      std::unique_ptr<MCObjectWriter> &&OW,
173
                      std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
174
                      bool IncrementalLinkerCompatible);
175
  using WasmStreamerCtorTy =
176
      MCStreamer *(*)(const Triple &T, MCContext &Ctx,
177
                      std::unique_ptr<MCAsmBackend> &&TAB,
178
                      std::unique_ptr<MCObjectWriter> &&OW,
179
                      std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll);
180
  using NullTargetStreamerCtorTy = MCTargetStreamer *(*)(MCStreamer &S);
181
  using AsmTargetStreamerCtorTy = MCTargetStreamer *(*)(
182
      MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint,
183
      bool IsVerboseAsm);
184
  using ObjectTargetStreamerCtorTy = MCTargetStreamer *(*)(
185
      MCStreamer &S, const MCSubtargetInfo &STI);
186
  using MCRelocationInfoCtorTy = MCRelocationInfo *(*)(const Triple &TT,
187
                                                       MCContext &Ctx);
188
  using MCSymbolizerCtorTy = MCSymbolizer *(*)(
189
      const Triple &TT, LLVMOpInfoCallback GetOpInfo,
190
      LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx,
191
      std::unique_ptr<MCRelocationInfo> &&RelInfo);
192
193
private:
194
  /// Next - The next registered target in the linked list, maintained by the
195
  /// TargetRegistry.
196
  Target *Next;
197
198
  /// The target function for checking if an architecture is supported.
199
  ArchMatchFnTy ArchMatchFn;
200
201
  /// Name - The target name.
202
  const char *Name;
203
204
  /// ShortDesc - A short description of the target.
205
  const char *ShortDesc;
206
207
  /// BackendName - The name of the backend implementation. This must match the
208
  /// name of the 'def X : Target ...' in TableGen.
209
  const char *BackendName;
210
211
  /// HasJIT - Whether this target supports the JIT.
212
  bool HasJIT;
213
214
  /// MCAsmInfoCtorFn - Constructor function for this target's MCAsmInfo, if
215
  /// registered.
216
  MCAsmInfoCtorFnTy MCAsmInfoCtorFn;
217
218
  /// MCInstrInfoCtorFn - Constructor function for this target's MCInstrInfo,
219
  /// if registered.
220
  MCInstrInfoCtorFnTy MCInstrInfoCtorFn;
221
222
  /// MCInstrAnalysisCtorFn - Constructor function for this target's
223
  /// MCInstrAnalysis, if registered.
224
  MCInstrAnalysisCtorFnTy MCInstrAnalysisCtorFn;
225
226
  /// MCRegInfoCtorFn - Constructor function for this target's MCRegisterInfo,
227
  /// if registered.
228
  MCRegInfoCtorFnTy MCRegInfoCtorFn;
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230
  /// MCSubtargetInfoCtorFn - Constructor function for this target's
231
  /// MCSubtargetInfo, if registered.
232
  MCSubtargetInfoCtorFnTy MCSubtargetInfoCtorFn;
233
234
  /// TargetMachineCtorFn - Construction function for this target's
235
  /// TargetMachine, if registered.
236
  TargetMachineCtorTy TargetMachineCtorFn;
237
238
  /// MCAsmBackendCtorFn - Construction function for this target's
239
  /// MCAsmBackend, if registered.
240
  MCAsmBackendCtorTy MCAsmBackendCtorFn;
241
242
  /// MCAsmParserCtorFn - Construction function for this target's
243
  /// MCTargetAsmParser, if registered.
244
  MCAsmParserCtorTy MCAsmParserCtorFn;
245
246
  /// AsmPrinterCtorFn - Construction function for this target's AsmPrinter,
247
  /// if registered.
248
  AsmPrinterCtorTy AsmPrinterCtorFn;
249
250
  /// MCDisassemblerCtorFn - Construction function for this target's
251
  /// MCDisassembler, if registered.
252
  MCDisassemblerCtorTy MCDisassemblerCtorFn;
253
254
  /// MCInstPrinterCtorFn - Construction function for this target's
255
  /// MCInstPrinter, if registered.
256
  MCInstPrinterCtorTy MCInstPrinterCtorFn;
257
258
  /// MCCodeEmitterCtorFn - Construction function for this target's
259
  /// CodeEmitter, if registered.
260
  MCCodeEmitterCtorTy MCCodeEmitterCtorFn;
261
262
  // Construction functions for the various object formats, if registered.
263
  COFFStreamerCtorTy COFFStreamerCtorFn = nullptr;
264
  MachOStreamerCtorTy MachOStreamerCtorFn = nullptr;
265
  ELFStreamerCtorTy ELFStreamerCtorFn = nullptr;
266
  WasmStreamerCtorTy WasmStreamerCtorFn = nullptr;
267
268
  /// Construction function for this target's null TargetStreamer, if
269
  /// registered (default = nullptr).
270
  NullTargetStreamerCtorTy NullTargetStreamerCtorFn = nullptr;
271
272
  /// Construction function for this target's asm TargetStreamer, if
273
  /// registered (default = nullptr).
274
  AsmTargetStreamerCtorTy AsmTargetStreamerCtorFn = nullptr;
275
276
  /// Construction function for this target's obj TargetStreamer, if
277
  /// registered (default = nullptr).
278
  ObjectTargetStreamerCtorTy ObjectTargetStreamerCtorFn = nullptr;
279
280
  /// MCRelocationInfoCtorFn - Construction function for this target's
281
  /// MCRelocationInfo, if registered (default = llvm::createMCRelocationInfo)
282
  MCRelocationInfoCtorTy MCRelocationInfoCtorFn = nullptr;
283
284
  /// MCSymbolizerCtorFn - Construction function for this target's
285
  /// MCSymbolizer, if registered (default = llvm::createMCSymbolizer)
286
  MCSymbolizerCtorTy MCSymbolizerCtorFn = nullptr;
287
288
public:
289
3.62M
  Target() = default;
290
291
  /// @name Target Information
292
  /// @{
293
294
  // getNext - Return the next registered target.
295
1.96M
  const Target *getNext() const { return Next; }
296
297
  /// getName - Get the target name.
298
159k
  const char *getName() const { return Name; }
299
300
  /// getShortDescription - Get a short description of the target.
301
0
  const char *getShortDescription() const { return ShortDesc; }
302
303
  /// getBackendName - Get the backend name.
304
217k
  const char *getBackendName() const { return BackendName; }
305
306
  /// @}
307
  /// @name Feature Predicates
308
  /// @{
309
310
  /// hasJIT - Check if this targets supports the just-in-time compilation.
311
  bool hasJIT() const { return HasJIT; }
312
313
  /// hasTargetMachine - Check if this target supports code generation.
314
0
  bool hasTargetMachine() const { return TargetMachineCtorFn != nullptr; }
315
316
  /// hasMCAsmBackend - Check if this target supports .o generation.
317
0
  bool hasMCAsmBackend() const { return MCAsmBackendCtorFn != nullptr; }
318
319
  /// hasMCAsmParser - Check if this target supports assembly parsing.
320
39
  bool hasMCAsmParser() const { return MCAsmParserCtorFn != nullptr; }
321
322
  /// @}
323
  /// @name Feature Constructors
324
  /// @{
325
326
  /// createMCAsmInfo - Create a MCAsmInfo implementation for the specified
327
  /// target triple.
328
  ///
329
  /// \param TheTriple This argument is used to determine the target machine
330
  /// feature set; it should always be provided. Generally this should be
331
  /// either the target triple from the module, or the target triple of the
332
  /// host if that does not exist.
333
  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI,
334
61.5k
                             StringRef TheTriple) const {
335
61.5k
    if (!MCAsmInfoCtorFn)
336
0
      return nullptr;
337
61.5k
    return MCAsmInfoCtorFn(MRI, Triple(TheTriple));
338
61.5k
  }
339
340
  /// createMCInstrInfo - Create a MCInstrInfo implementation.
341
  ///
342
69.2k
  MCInstrInfo *createMCInstrInfo() const {
343
69.2k
    if (!MCInstrInfoCtorFn)
344
0
      return nullptr;
345
69.2k
    return MCInstrInfoCtorFn();
346
69.2k
  }
347
348
  /// createMCInstrAnalysis - Create a MCInstrAnalysis implementation.
349
  ///
350
2.28k
  MCInstrAnalysis *createMCInstrAnalysis(const MCInstrInfo *Info) const {
351
2.28k
    if (!MCInstrAnalysisCtorFn)
352
112
      return nullptr;
353
2.17k
    return MCInstrAnalysisCtorFn(Info);
354
2.17k
  }
355
356
  /// createMCRegInfo - Create a MCRegisterInfo implementation.
357
  ///
358
62.3k
  MCRegisterInfo *createMCRegInfo(StringRef TT) const {
359
62.3k
    if (!MCRegInfoCtorFn)
360
0
      return nullptr;
361
62.3k
    return MCRegInfoCtorFn(Triple(TT));
362
62.3k
  }
363
364
  /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
365
  ///
366
  /// \param TheTriple This argument is used to determine the target machine
367
  /// feature set; it should always be provided. Generally this should be
368
  /// either the target triple from the module, or the target triple of the
369
  /// host if that does not exist.
370
  /// \param CPU This specifies the name of the target CPU.
371
  /// \param Features This specifies the string representation of the
372
  /// additional target features.
373
  MCSubtargetInfo *createMCSubtargetInfo(StringRef TheTriple, StringRef CPU,
374
62.0k
                                         StringRef Features) const {
375
62.0k
    if (!MCSubtargetInfoCtorFn)
376
0
      return nullptr;
377
62.0k
    return MCSubtargetInfoCtorFn(Triple(TheTriple), CPU, Features);
378
62.0k
  }
379
380
  /// createTargetMachine - Create a target specific machine implementation
381
  /// for the specified \p Triple.
382
  ///
383
  /// \param TT This argument is used to determine the target machine
384
  /// feature set; it should always be provided. Generally this should be
385
  /// either the target triple from the module, or the target triple of the
386
  /// host if that does not exist.
387
  TargetMachine *createTargetMachine(StringRef TT, StringRef CPU,
388
                                     StringRef Features,
389
                                     const TargetOptions &Options,
390
                                     Optional<Reloc::Model> RM,
391
                                     Optional<CodeModel::Model> CM = None,
392
                                     CodeGenOpt::Level OL = CodeGenOpt::Default,
393
49.1k
                                     bool JIT = false) const {
394
49.1k
    if (!TargetMachineCtorFn)
395
0
      return nullptr;
396
49.1k
    return TargetMachineCtorFn(*this, Triple(TT), CPU, Features, Options, RM,
397
49.1k
                               CM, OL, JIT);
398
49.1k
  }
399
400
  /// createMCAsmBackend - Create a target specific assembly parser.
401
  MCAsmBackend *createMCAsmBackend(const MCSubtargetInfo &STI,
402
                                   const MCRegisterInfo &MRI,
403
43.1k
                                   const MCTargetOptions &Options) const {
404
43.1k
    if (!MCAsmBackendCtorFn)
405
327
      return nullptr;
406
42.8k
    return MCAsmBackendCtorFn(*this, STI, MRI, Options);
407
42.8k
  }
408
409
  /// createMCAsmParser - Create a target specific assembly parser.
410
  ///
411
  /// \param Parser The target independent parser implementation to use for
412
  /// parsing and lexing.
413
  MCTargetAsmParser *createMCAsmParser(const MCSubtargetInfo &STI,
414
                                       MCAsmParser &Parser,
415
                                       const MCInstrInfo &MII,
416
15.8k
                                       const MCTargetOptions &Options) const {
417
15.8k
    if (!MCAsmParserCtorFn)
418
0
      return nullptr;
419
15.8k
    return MCAsmParserCtorFn(STI, Parser, MII, Options);
420
15.8k
  }
421
422
  /// createAsmPrinter - Create a target specific assembly printer pass.  This
423
  /// takes ownership of the MCStreamer object.
424
  AsmPrinter *createAsmPrinter(TargetMachine &TM,
425
34.1k
                               std::unique_ptr<MCStreamer> &&Streamer) const {
426
34.1k
    if (!AsmPrinterCtorFn)
427
0
      return nullptr;
428
34.1k
    return AsmPrinterCtorFn(TM, std::move(Streamer));
429
34.1k
  }
430
431
  MCDisassembler *createMCDisassembler(const MCSubtargetInfo &STI,
432
                                       MCContext &Ctx) const {
433
    if (!MCDisassemblerCtorFn)
434
      return nullptr;
435
    return MCDisassemblerCtorFn(*this, STI, Ctx);
436
  }
437
438
  MCInstPrinter *createMCInstPrinter(const Triple &T, unsigned SyntaxVariant,
439
                                     const MCAsmInfo &MAI,
440
                                     const MCInstrInfo &MII,
441
26.3k
                                     const MCRegisterInfo &MRI) const {
442
26.3k
    if (!MCInstPrinterCtorFn)
443
0
      return nullptr;
444
26.3k
    return MCInstPrinterCtorFn(T, SyntaxVariant, MAI, MII, MRI);
445
26.3k
  }
446
447
  /// createMCCodeEmitter - Create a target specific code emitter.
448
  MCCodeEmitter *createMCCodeEmitter(const MCInstrInfo &II,
449
                                     const MCRegisterInfo &MRI,
450
150k
                                     MCContext &Ctx) const {
451
150k
    if (!MCCodeEmitterCtorFn)
452
0
      return nullptr;
453
150k
    return MCCodeEmitterCtorFn(II, MRI, Ctx);
454
150k
  }
455
456
  /// Create a target specific MCStreamer.
457
  ///
458
  /// \param T The target triple.
459
  /// \param Ctx The target context.
460
  /// \param TAB The target assembler backend object. Takes ownership.
461
  /// \param OW The stream object.
462
  /// \param Emitter The target independent assembler object.Takes ownership.
463
  /// \param RelaxAll Relax all fixups?
464
  MCStreamer *createMCObjectStreamer(const Triple &T, MCContext &Ctx,
465
                                     std::unique_ptr<MCAsmBackend> &&TAB,
466
                                     std::unique_ptr<MCObjectWriter> &&OW,
467
                                     std::unique_ptr<MCCodeEmitter> &&Emitter,
468
                                     const MCSubtargetInfo &STI, bool RelaxAll,
469
                                     bool IncrementalLinkerCompatible,
470
19.3k
                                     bool DWARFMustBeAtTheEnd) const {
471
19.3k
    MCStreamer *S;
472
19.3k
    switch (T.getObjectFormat()) {
473
19.3k
    default:
474
0
      llvm_unreachable("Unknown object format");
475
19.3k
    case Triple::COFF:
476
506
      assert(T.isOSWindows() && "only Windows COFF is supported");
477
506
      S = COFFStreamerCtorFn(Ctx, std::move(TAB), std::move(OW),
478
506
                             std::move(Emitter), RelaxAll,
479
506
                             IncrementalLinkerCompatible);
480
506
      break;
481
19.3k
    case Triple::MachO:
482
13.7k
      if (MachOStreamerCtorFn)
483
10.2k
        S = MachOStreamerCtorFn(Ctx, std::move(TAB), std::move(OW),
484
10.2k
                                std::move(Emitter), RelaxAll,
485
10.2k
                                DWARFMustBeAtTheEnd);
486
3.55k
      else
487
3.55k
        S = createMachOStreamer(Ctx, std::move(TAB), std::move(OW),
488
3.55k
                                std::move(Emitter), RelaxAll,
489
3.55k
                                DWARFMustBeAtTheEnd);
490
13.7k
      break;
491
19.3k
    case Triple::ELF:
492
4.88k
      if (ELFStreamerCtorFn)
493
2.13k
        S = ELFStreamerCtorFn(T, Ctx, std::move(TAB), std::move(OW),
494
2.13k
                              std::move(Emitter), RelaxAll);
495
2.74k
      else
496
2.74k
        S = createELFStreamer(Ctx, std::move(TAB), std::move(OW),
497
2.74k
                              std::move(Emitter), RelaxAll);
498
4.88k
      break;
499
19.3k
    case Triple::Wasm:
500
178
      if (WasmStreamerCtorFn)
501
0
        S = WasmStreamerCtorFn(T, Ctx, std::move(TAB), std::move(OW),
502
0
                               std::move(Emitter), RelaxAll);
503
178
      else
504
178
        S = createWasmStreamer(Ctx, std::move(TAB), std::move(OW),
505
178
                               std::move(Emitter), RelaxAll);
506
178
      break;
507
19.3k
    }
508
19.3k
    if (ObjectTargetStreamerCtorFn)
509
19.3k
      ObjectTargetStreamerCtorFn(*S, STI);
510
19.3k
    return S;
511
19.3k
  }
512
513
  MCStreamer *createAsmStreamer(MCContext &Ctx,
514
                                std::unique_ptr<formatted_raw_ostream> OS,
515
                                bool IsVerboseAsm, bool UseDwarfDirectory,
516
                                MCInstPrinter *InstPrint,
517
                                std::unique_ptr<MCCodeEmitter> &&CE,
518
                                std::unique_ptr<MCAsmBackend> &&TAB,
519
23.8k
                                bool ShowInst) const {
520
23.8k
    formatted_raw_ostream &OSRef = *OS;
521
23.8k
    MCStreamer *S = llvm::createAsmStreamer(
522
23.8k
        Ctx, std::move(OS), IsVerboseAsm, UseDwarfDirectory, InstPrint,
523
23.8k
        std::move(CE), std::move(TAB), ShowInst);
524
23.8k
    createAsmTargetStreamer(*S, OSRef, InstPrint, IsVerboseAsm);
525
23.8k
    return S;
526
23.8k
  }
527
528
  MCTargetStreamer *createAsmTargetStreamer(MCStreamer &S,
529
                                            formatted_raw_ostream &OS,
530
                                            MCInstPrinter *InstPrint,
531
23.8k
                                            bool IsVerboseAsm) const {
532
23.8k
    if (AsmTargetStreamerCtorFn)
533
22.3k
      return AsmTargetStreamerCtorFn(S, OS, InstPrint, IsVerboseAsm);
534
1.42k
    return nullptr;
535
1.42k
  }
536
537
18
  MCStreamer *createNullStreamer(MCContext &Ctx) const {
538
18
    MCStreamer *S = llvm::createNullStreamer(Ctx);
539
18
    createNullTargetStreamer(*S);
540
18
    return S;
541
18
  }
542
543
92
  MCTargetStreamer *createNullTargetStreamer(MCStreamer &S) const {
544
92
    if (NullTargetStreamerCtorFn)
545
6
      return NullTargetStreamerCtorFn(S);
546
86
    return nullptr;
547
86
  }
548
549
  /// createMCRelocationInfo - Create a target specific MCRelocationInfo.
550
  ///
551
  /// \param TT The target triple.
552
  /// \param Ctx The target context.
553
  MCRelocationInfo *createMCRelocationInfo(StringRef TT, MCContext &Ctx) const {
554
    MCRelocationInfoCtorTy Fn = MCRelocationInfoCtorFn
555
                                    ? MCRelocationInfoCtorFn
556
                                    : llvm::createMCRelocationInfo;
557
    return Fn(Triple(TT), Ctx);
558
  }
559
560
  /// createMCSymbolizer - Create a target specific MCSymbolizer.
561
  ///
562
  /// \param TT The target triple.
563
  /// \param GetOpInfo The function to get the symbolic information for
564
  /// operands.
565
  /// \param SymbolLookUp The function to lookup a symbol name.
566
  /// \param DisInfo The pointer to the block of symbolic information for above
567
  /// call
568
  /// back.
569
  /// \param Ctx The target context.
570
  /// \param RelInfo The relocation information for this target. Takes
571
  /// ownership.
572
  MCSymbolizer *
573
  createMCSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo,
574
                     LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo,
575
                     MCContext *Ctx,
576
                     std::unique_ptr<MCRelocationInfo> &&RelInfo) const {
577
    MCSymbolizerCtorTy Fn =
578
        MCSymbolizerCtorFn ? MCSymbolizerCtorFn : llvm::createMCSymbolizer;
579
    return Fn(Triple(TT), GetOpInfo, SymbolLookUp, DisInfo, Ctx,
580
              std::move(RelInfo));
581
  }
582
583
  /// @}
584
};
585
586
/// TargetRegistry - Generic interface to target specific features.
587
struct TargetRegistry {
588
  // FIXME: Make this a namespace, probably just move all the Register*
589
  // functions into Target (currently they all just set members on the Target
590
  // anyway, and Target friends this class so those functions can...
591
  // function).
592
  TargetRegistry() = delete;
593
594
  class iterator
595
      : public std::iterator<std::forward_iterator_tag, Target, ptrdiff_t> {
596
    friend struct TargetRegistry;
597
598
    const Target *Current = nullptr;
599
600
347k
    explicit iterator(Target *T) : Current(T) {}
601
602
  public:
603
347k
    iterator() = default;
604
605
2.19M
    bool operator==(const iterator &x) const { return Current == x.Current; }
606
2.08M
    bool operator!=(const iterator &x) const { return !operator==(x); }
607
608
    // Iterator traversal: forward iteration only
609
1.96M
    iterator &operator++() { // Preincrement
610
1.96M
      assert(Current && "Cannot increment end iterator!");
611
1.96M
      Current = Current->getNext();
612
1.96M
      return *this;
613
1.96M
    }
614
0
    iterator operator++(int) { // Postincrement
615
0
      iterator tmp = *this;
616
0
      ++*this;
617
0
      return tmp;
618
0
    }
619
620
2.03M
    const Target &operator*() const {
621
2.03M
      assert(Current && "Cannot dereference end iterator!");
622
2.03M
      return *Current;
623
2.03M
    }
624
625
0
    const Target *operator->() const { return &operator*(); }
626
  };
627
628
  /// printRegisteredTargetsForVersion - Print the registered targets
629
  /// appropriately for inclusion in a tool's version output.
630
  static void printRegisteredTargetsForVersion(raw_ostream &OS);
631
632
  /// @name Registry Access
633
  /// @{
634
635
  static iterator_range<iterator> targets();
636
637
  /// lookupTarget - Lookup a target based on a target triple.
638
  ///
639
  /// \param Triple - The triple to use for finding a target.
640
  /// \param Error - On failure, an error string describing why no target was
641
  /// found.
642
  static const Target *lookupTarget(const std::string &Triple,
643
                                    std::string &Error);
644
645
  /// lookupTarget - Lookup a target based on an architecture name
646
  /// and a target triple.  If the architecture name is non-empty,
647
  /// then the lookup is done by architecture.  Otherwise, the target
648
  /// triple is used.
649
  ///
650
  /// \param ArchName - The architecture to use for finding a target.
651
  /// \param TheTriple - The triple to use for finding a target.  The
652
  /// triple is updated with canonical architecture name if a lookup
653
  /// by architecture is done.
654
  /// \param Error - On failure, an error string describing why no target was
655
  /// found.
656
  static const Target *lookupTarget(const std::string &ArchName,
657
                                    Triple &TheTriple, std::string &Error);
658
659
  /// @}
660
  /// @name Target Registration
661
  /// @{
662
663
  /// RegisterTarget - Register the given target. Attempts to register a
664
  /// target which has already been registered will be ignored.
665
  ///
666
  /// Clients are responsible for ensuring that registration doesn't occur
667
  /// while another thread is attempting to access the registry. Typically
668
  /// this is done by initializing all targets at program startup.
669
  ///
670
  /// @param T - The target being registered.
671
  /// @param Name - The target name. This should be a static string.
672
  /// @param ShortDesc - A short target description. This should be a static
673
  /// string.
674
  /// @param BackendName - The name of the backend. This should be a static
675
  /// string that is the same for all targets that share a backend
676
  /// implementation and must match the name used in the 'def X : Target ...' in
677
  /// TableGen.
678
  /// @param ArchMatchFn - The arch match checking function for this target.
679
  /// @param HasJIT - Whether the target supports JIT code
680
  /// generation.
681
  static void RegisterTarget(Target &T, const char *Name, const char *ShortDesc,
682
                             const char *BackendName,
683
                             Target::ArchMatchFnTy ArchMatchFn,
684
                             bool HasJIT = false);
685
686
  /// RegisterMCAsmInfo - Register a MCAsmInfo implementation for the
687
  /// given target.
688
  ///
689
  /// Clients are responsible for ensuring that registration doesn't occur
690
  /// while another thread is attempting to access the registry. Typically
691
  /// this is done by initializing all targets at program startup.
692
  ///
693
  /// @param T - The target being registered.
694
  /// @param Fn - A function to construct a MCAsmInfo for the target.
695
2.91M
  static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn) {
696
2.91M
    T.MCAsmInfoCtorFn = Fn;
697
2.91M
  }
698
699
  /// RegisterMCInstrInfo - Register a MCInstrInfo implementation for the
700
  /// given target.
701
  ///
702
  /// Clients are responsible for ensuring that registration doesn't occur
703
  /// while another thread is attempting to access the registry. Typically
704
  /// this is done by initializing all targets at program startup.
705
  ///
706
  /// @param T - The target being registered.
707
  /// @param Fn - A function to construct a MCInstrInfo for the target.
708
2.91M
  static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn) {
709
2.91M
    T.MCInstrInfoCtorFn = Fn;
710
2.91M
  }
711
712
  /// RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for
713
  /// the given target.
714
  static void RegisterMCInstrAnalysis(Target &T,
715
1.58M
                                      Target::MCInstrAnalysisCtorFnTy Fn) {
716
1.58M
    T.MCInstrAnalysisCtorFn = Fn;
717
1.58M
  }
718
719
  /// RegisterMCRegInfo - Register a MCRegisterInfo implementation for the
720
  /// given target.
721
  ///
722
  /// Clients are responsible for ensuring that registration doesn't occur
723
  /// while another thread is attempting to access the registry. Typically
724
  /// this is done by initializing all targets at program startup.
725
  ///
726
  /// @param T - The target being registered.
727
  /// @param Fn - A function to construct a MCRegisterInfo for the target.
728
2.91M
  static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn) {
729
2.91M
    T.MCRegInfoCtorFn = Fn;
730
2.91M
  }
731
732
  /// RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for
733
  /// the given target.
734
  ///
735
  /// Clients are responsible for ensuring that registration doesn't occur
736
  /// while another thread is attempting to access the registry. Typically
737
  /// this is done by initializing all targets at program startup.
738
  ///
739
  /// @param T - The target being registered.
740
  /// @param Fn - A function to construct a MCSubtargetInfo for the target.
741
  static void RegisterMCSubtargetInfo(Target &T,
742
2.91M
                                      Target::MCSubtargetInfoCtorFnTy Fn) {
743
2.91M
    T.MCSubtargetInfoCtorFn = Fn;
744
2.91M
  }
745
746
  /// RegisterTargetMachine - Register a TargetMachine implementation for the
747
  /// given target.
748
  ///
749
  /// Clients are responsible for ensuring that registration doesn't occur
750
  /// while another thread is attempting to access the registry. Typically
751
  /// this is done by initializing all targets at program startup.
752
  ///
753
  /// @param T - The target being registered.
754
  /// @param Fn - A function to construct a TargetMachine for the target.
755
4.37M
  static void RegisterTargetMachine(Target &T, Target::TargetMachineCtorTy Fn) {
756
4.37M
    T.TargetMachineCtorFn = Fn;
757
4.37M
  }
758
759
  /// RegisterMCAsmBackend - Register a MCAsmBackend implementation for the
760
  /// given target.
761
  ///
762
  /// Clients are responsible for ensuring that registration doesn't occur
763
  /// while another thread is attempting to access the registry. Typically
764
  /// this is done by initializing all targets at program startup.
765
  ///
766
  /// @param T - The target being registered.
767
  /// @param Fn - A function to construct an AsmBackend for the target.
768
2.64M
  static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn) {
769
2.64M
    T.MCAsmBackendCtorFn = Fn;
770
2.64M
  }
771
772
  /// RegisterMCAsmParser - Register a MCTargetAsmParser implementation for
773
  /// the given target.
774
  ///
775
  /// Clients are responsible for ensuring that registration doesn't occur
776
  /// while another thread is attempting to access the registry. Typically
777
  /// this is done by initializing all targets at program startup.
778
  ///
779
  /// @param T - The target being registered.
780
  /// @param Fn - A function to construct an MCTargetAsmParser for the target.
781
2.53M
  static void RegisterMCAsmParser(Target &T, Target::MCAsmParserCtorTy Fn) {
782
2.53M
    T.MCAsmParserCtorFn = Fn;
783
2.53M
  }
784
785
  /// RegisterAsmPrinter - Register an AsmPrinter implementation for the given
786
  /// target.
787
  ///
788
  /// Clients are responsible for ensuring that registration doesn't occur
789
  /// while another thread is attempting to access the registry. Typically
790
  /// this is done by initializing all targets at program startup.
791
  ///
792
  /// @param T - The target being registered.
793
  /// @param Fn - A function to construct an AsmPrinter for the target.
794
2.44M
  static void RegisterAsmPrinter(Target &T, Target::AsmPrinterCtorTy Fn) {
795
2.44M
    T.AsmPrinterCtorFn = Fn;
796
2.44M
  }
797
798
  /// RegisterMCDisassembler - Register a MCDisassembler implementation for
799
  /// the given target.
800
  ///
801
  /// Clients are responsible for ensuring that registration doesn't occur
802
  /// while another thread is attempting to access the registry. Typically
803
  /// this is done by initializing all targets at program startup.
804
  ///
805
  /// @param T - The target being registered.
806
  /// @param Fn - A function to construct an MCDisassembler for the target.
807
  static void RegisterMCDisassembler(Target &T,
808
                                     Target::MCDisassemblerCtorTy Fn) {
809
    T.MCDisassemblerCtorFn = Fn;
810
  }
811
812
  /// RegisterMCInstPrinter - Register a MCInstPrinter implementation for the
813
  /// given target.
814
  ///
815
  /// Clients are responsible for ensuring that registration doesn't occur
816
  /// while another thread is attempting to access the registry. Typically
817
  /// this is done by initializing all targets at program startup.
818
  ///
819
  /// @param T - The target being registered.
820
  /// @param Fn - A function to construct an MCInstPrinter for the target.
821
2.91M
  static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn) {
822
2.91M
    T.MCInstPrinterCtorFn = Fn;
823
2.91M
  }
824
825
  /// RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the
826
  /// given target.
827
  ///
828
  /// Clients are responsible for ensuring that registration doesn't occur
829
  /// while another thread is attempting to access the registry. Typically
830
  /// this is done by initializing all targets at program startup.
831
  ///
832
  /// @param T - The target being registered.
833
  /// @param Fn - A function to construct an MCCodeEmitter for the target.
834
2.64M
  static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn) {
835
2.64M
    T.MCCodeEmitterCtorFn = Fn;
836
2.64M
  }
837
838
794k
  static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn) {
839
794k
    T.COFFStreamerCtorFn = Fn;
840
794k
  }
841
842
617k
  static void RegisterMachOStreamer(Target &T, Target::MachOStreamerCtorTy Fn) {
843
617k
    T.MachOStreamerCtorFn = Fn;
844
617k
  }
845
846
1.58M
  static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn) {
847
1.58M
    T.ELFStreamerCtorFn = Fn;
848
1.58M
  }
849
850
  static void RegisterWasmStreamer(Target &T, Target::WasmStreamerCtorTy Fn) {
851
    T.WasmStreamerCtorFn = Fn;
852
  }
853
854
  static void RegisterNullTargetStreamer(Target &T,
855
881k
                                         Target::NullTargetStreamerCtorTy Fn) {
856
881k
    T.NullTargetStreamerCtorFn = Fn;
857
881k
  }
858
859
  static void RegisterAsmTargetStreamer(Target &T,
860
2.29M
                                        Target::AsmTargetStreamerCtorTy Fn) {
861
2.29M
    T.AsmTargetStreamerCtorFn = Fn;
862
2.29M
  }
863
864
  static void
865
  RegisterObjectTargetStreamer(Target &T,
866
2.20M
                               Target::ObjectTargetStreamerCtorTy Fn) {
867
2.20M
    T.ObjectTargetStreamerCtorFn = Fn;
868
2.20M
  }
869
870
  /// RegisterMCRelocationInfo - Register an MCRelocationInfo
871
  /// implementation for the given target.
872
  ///
873
  /// Clients are responsible for ensuring that registration doesn't occur
874
  /// while another thread is attempting to access the registry. Typically
875
  /// this is done by initializing all targets at program startup.
876
  ///
877
  /// @param T - The target being registered.
878
  /// @param Fn - A function to construct an MCRelocationInfo for the target.
879
  static void RegisterMCRelocationInfo(Target &T,
880
617k
                                       Target::MCRelocationInfoCtorTy Fn) {
881
617k
    T.MCRelocationInfoCtorFn = Fn;
882
617k
  }
883
884
  /// RegisterMCSymbolizer - Register an MCSymbolizer
885
  /// implementation for the given target.
886
  ///
887
  /// Clients are responsible for ensuring that registration doesn't occur
888
  /// while another thread is attempting to access the registry. Typically
889
  /// this is done by initializing all targets at program startup.
890
  ///
891
  /// @param T - The target being registered.
892
  /// @param Fn - A function to construct an MCSymbolizer for the target.
893
  static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn) {
894
    T.MCSymbolizerCtorFn = Fn;
895
  }
896
897
  /// @}
898
};
899
900
//===--------------------------------------------------------------------===//
901
902
/// RegisterTarget - Helper template for registering a target, for use in the
903
/// target's initialization function. Usage:
904
///
905
///
906
/// Target &getTheFooTarget() { // The global target instance.
907
///   static Target TheFooTarget;
908
///   return TheFooTarget;
909
/// }
910
/// extern "C" void LLVMInitializeFooTargetInfo() {
911
///   RegisterTarget<Triple::foo> X(getTheFooTarget(), "foo", "Foo
912
///   description", "Foo" /* Backend Name */);
913
/// }
914
template <Triple::ArchType TargetArchType = Triple::UnknownArch,
915
          bool HasJIT = false>
916
struct RegisterTarget {
917
  RegisterTarget(Target &T, const char *Name, const char *Desc,
918
4.56M
                 const char *BackendName) {
919
4.56M
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
4.56M
                                   HasJIT);
921
4.56M
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)3, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)4, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)18, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)19, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)1, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)2, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)28, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)29, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)7, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)8, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)9, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)45, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)10, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)11, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)12, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)13, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)14, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)33, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)34, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)15, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)16, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)17, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)22, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)23, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)24, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)25, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)46, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)47, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)30, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)31, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)32, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
918
147k
                 const char *BackendName) {
919
147k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
920
147k
                                   HasJIT);
921
147k
  }
922
923
1.72M
  static bool getArchMatch(Triple::ArchType Arch) {
924
1.72M
    return Arch == TargetArchType;
925
1.72M
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)3, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)4, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)18, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)19, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)1, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)2, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)28, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)29, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)7, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)8, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)9, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)45, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)10, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)11, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)12, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)13, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)14, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)33, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)34, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)15, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)16, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)17, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)22, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)23, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)24, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)25, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)46, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)47, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)30, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.9k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.9k
    return Arch == TargetArchType;
925
55.9k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)31, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.9k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.9k
    return Arch == TargetArchType;
925
55.9k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)32, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
923
55.6k
  static bool getArchMatch(Triple::ArchType Arch) {
924
55.6k
    return Arch == TargetArchType;
925
55.6k
  }
926
};
927
928
/// RegisterMCAsmInfo - Helper template for registering a target assembly info
929
/// implementation.  This invokes the static "Create" method on the class to
930
/// actually do the construction.  Usage:
931
///
932
/// extern "C" void LLVMInitializeFooTarget() {
933
///   extern Target TheFooTarget;
934
///   RegisterMCAsmInfo<FooMCAsmInfo> X(TheFooTarget);
935
/// }
936
template <class MCAsmInfoImpl> struct RegisterMCAsmInfo {
937
793k
  RegisterMCAsmInfo(Target &T) {
938
793k
    TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
939
793k
  }
llvm::RegisterMCAsmInfo<llvm::AMDGPUMCAsmInfo>::RegisterMCAsmInfo(llvm::Target&)
Line
Count
Source
937
176k
  RegisterMCAsmInfo(Target &T) {
938
176k
    TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
939
176k
  }
llvm::RegisterMCAsmInfo<llvm::BPFMCAsmInfo>::RegisterMCAsmInfo(llvm::Target&)
Line
Count
Source
937
264k
  RegisterMCAsmInfo(Target &T) {
938
264k
    TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
939
264k
  }
llvm::RegisterMCAsmInfo<llvm::LanaiMCAsmInfo>::RegisterMCAsmInfo(llvm::Target&)
Line
Count
Source
937
88.1k
  RegisterMCAsmInfo(Target &T) {
938
88.1k
    TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
939
88.1k
  }
llvm::RegisterMCAsmInfo<llvm::MSP430MCAsmInfo>::RegisterMCAsmInfo(llvm::Target&)
Line
Count
Source
937
88.1k
  RegisterMCAsmInfo(Target &T) {
938
88.1k
    TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
939
88.1k
  }
llvm::RegisterMCAsmInfo<llvm::NVPTXMCAsmInfo>::RegisterMCAsmInfo(llvm::Target&)
Line
Count
Source
937
176k
  RegisterMCAsmInfo(Target &T) {
938
176k
    TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
939
176k
  }
940
941
private:
942
  static MCAsmInfo *Allocator(const MCRegisterInfo & /*MRI*/,
943
4.44k
                              const Triple &TT) {
944
4.44k
    return new MCAsmInfoImpl(TT);
945
4.44k
  }
llvm::RegisterMCAsmInfo<llvm::AMDGPUMCAsmInfo>::Allocator(llvm::MCRegisterInfo const&, llvm::Triple const&)
Line
Count
Source
943
3.71k
                              const Triple &TT) {
944
3.71k
    return new MCAsmInfoImpl(TT);
945
3.71k
  }
llvm::RegisterMCAsmInfo<llvm::BPFMCAsmInfo>::Allocator(llvm::MCRegisterInfo const&, llvm::Triple const&)
Line
Count
Source
943
161
                              const Triple &TT) {
944
161
    return new MCAsmInfoImpl(TT);
945
161
  }
llvm::RegisterMCAsmInfo<llvm::LanaiMCAsmInfo>::Allocator(llvm::MCRegisterInfo const&, llvm::Triple const&)
Line
Count
Source
943
32
                              const Triple &TT) {
944
32
    return new MCAsmInfoImpl(TT);
945
32
  }
llvm::RegisterMCAsmInfo<llvm::MSP430MCAsmInfo>::Allocator(llvm::MCRegisterInfo const&, llvm::Triple const&)
Line
Count
Source
943
94
                              const Triple &TT) {
944
94
    return new MCAsmInfoImpl(TT);
945
94
  }
llvm::RegisterMCAsmInfo<llvm::NVPTXMCAsmInfo>::Allocator(llvm::MCRegisterInfo const&, llvm::Triple const&)
Line
Count
Source
943
443
                              const Triple &TT) {
944
443
    return new MCAsmInfoImpl(TT);
945
443
  }
946
};
947
948
/// RegisterMCAsmInfoFn - Helper template for registering a target assembly info
949
/// implementation.  This invokes the specified function to do the
950
/// construction.  Usage:
951
///
952
/// extern "C" void LLVMInitializeFooTarget() {
953
///   extern Target TheFooTarget;
954
///   RegisterMCAsmInfoFn X(TheFooTarget, TheFunction);
955
/// }
956
struct RegisterMCAsmInfoFn {
957
2.02M
  RegisterMCAsmInfoFn(Target &T, Target::MCAsmInfoCtorFnTy Fn) {
958
2.02M
    TargetRegistry::RegisterMCAsmInfo(T, Fn);
959
2.02M
  }
960
};
961
962
/// RegisterMCInstrInfo - Helper template for registering a target instruction
963
/// info implementation.  This invokes the static "Create" method on the class
964
/// to actually do the construction.  Usage:
965
///
966
/// extern "C" void LLVMInitializeFooTarget() {
967
///   extern Target TheFooTarget;
968
///   RegisterMCInstrInfo<FooMCInstrInfo> X(TheFooTarget);
969
/// }
970
template <class MCInstrInfoImpl> struct RegisterMCInstrInfo {
971
  RegisterMCInstrInfo(Target &T) {
972
    TargetRegistry::RegisterMCInstrInfo(T, &Allocator);
973
  }
974
975
private:
976
  static MCInstrInfo *Allocator() { return new MCInstrInfoImpl(); }
977
};
978
979
/// RegisterMCInstrInfoFn - Helper template for registering a target
980
/// instruction info implementation.  This invokes the specified function to
981
/// do the construction.  Usage:
982
///
983
/// extern "C" void LLVMInitializeFooTarget() {
984
///   extern Target TheFooTarget;
985
///   RegisterMCInstrInfoFn X(TheFooTarget, TheFunction);
986
/// }
987
struct RegisterMCInstrInfoFn {
988
  RegisterMCInstrInfoFn(Target &T, Target::MCInstrInfoCtorFnTy Fn) {
989
    TargetRegistry::RegisterMCInstrInfo(T, Fn);
990
  }
991
};
992
993
/// RegisterMCInstrAnalysis - Helper template for registering a target
994
/// instruction analyzer implementation.  This invokes the static "Create"
995
/// method on the class to actually do the construction.  Usage:
996
///
997
/// extern "C" void LLVMInitializeFooTarget() {
998
///   extern Target TheFooTarget;
999
///   RegisterMCInstrAnalysis<FooMCInstrAnalysis> X(TheFooTarget);
1000
/// }
1001
template <class MCInstrAnalysisImpl> struct RegisterMCInstrAnalysis {
1002
  RegisterMCInstrAnalysis(Target &T) {
1003
    TargetRegistry::RegisterMCInstrAnalysis(T, &Allocator);
1004
  }
1005
1006
private:
1007
  static MCInstrAnalysis *Allocator(const MCInstrInfo *Info) {
1008
    return new MCInstrAnalysisImpl(Info);
1009
  }
1010
};
1011
1012
/// RegisterMCInstrAnalysisFn - Helper template for registering a target
1013
/// instruction analyzer implementation.  This invokes the specified function
1014
/// to do the construction.  Usage:
1015
///
1016
/// extern "C" void LLVMInitializeFooTarget() {
1017
///   extern Target TheFooTarget;
1018
///   RegisterMCInstrAnalysisFn X(TheFooTarget, TheFunction);
1019
/// }
1020
struct RegisterMCInstrAnalysisFn {
1021
  RegisterMCInstrAnalysisFn(Target &T, Target::MCInstrAnalysisCtorFnTy Fn) {
1022
    TargetRegistry::RegisterMCInstrAnalysis(T, Fn);
1023
  }
1024
};
1025
1026
/// RegisterMCRegInfo - Helper template for registering a target register info
1027
/// implementation.  This invokes the static "Create" method on the class to
1028
/// actually do the construction.  Usage:
1029
///
1030
/// extern "C" void LLVMInitializeFooTarget() {
1031
///   extern Target TheFooTarget;
1032
///   RegisterMCRegInfo<FooMCRegInfo> X(TheFooTarget);
1033
/// }
1034
template <class MCRegisterInfoImpl> struct RegisterMCRegInfo {
1035
  RegisterMCRegInfo(Target &T) {
1036
    TargetRegistry::RegisterMCRegInfo(T, &Allocator);
1037
  }
1038
1039
private:
1040
  static MCRegisterInfo *Allocator(const Triple & /*TT*/) {
1041
    return new MCRegisterInfoImpl();
1042
  }
1043
};
1044
1045
/// RegisterMCRegInfoFn - Helper template for registering a target register
1046
/// info implementation.  This invokes the specified function to do the
1047
/// construction.  Usage:
1048
///
1049
/// extern "C" void LLVMInitializeFooTarget() {
1050
///   extern Target TheFooTarget;
1051
///   RegisterMCRegInfoFn X(TheFooTarget, TheFunction);
1052
/// }
1053
struct RegisterMCRegInfoFn {
1054
  RegisterMCRegInfoFn(Target &T, Target::MCRegInfoCtorFnTy Fn) {
1055
    TargetRegistry::RegisterMCRegInfo(T, Fn);
1056
  }
1057
};
1058
1059
/// RegisterMCSubtargetInfo - Helper template for registering a target
1060
/// subtarget info implementation.  This invokes the static "Create" method
1061
/// on the class to actually do the construction.  Usage:
1062
///
1063
/// extern "C" void LLVMInitializeFooTarget() {
1064
///   extern Target TheFooTarget;
1065
///   RegisterMCSubtargetInfo<FooMCSubtargetInfo> X(TheFooTarget);
1066
/// }
1067
template <class MCSubtargetInfoImpl> struct RegisterMCSubtargetInfo {
1068
  RegisterMCSubtargetInfo(Target &T) {
1069
    TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator);
1070
  }
1071
1072
private:
1073
  static MCSubtargetInfo *Allocator(const Triple & /*TT*/, StringRef /*CPU*/,
1074
                                    StringRef /*FS*/) {
1075
    return new MCSubtargetInfoImpl();
1076
  }
1077
};
1078
1079
/// RegisterMCSubtargetInfoFn - Helper template for registering a target
1080
/// subtarget info implementation.  This invokes the specified function to
1081
/// do the construction.  Usage:
1082
///
1083
/// extern "C" void LLVMInitializeFooTarget() {
1084
///   extern Target TheFooTarget;
1085
///   RegisterMCSubtargetInfoFn X(TheFooTarget, TheFunction);
1086
/// }
1087
struct RegisterMCSubtargetInfoFn {
1088
  RegisterMCSubtargetInfoFn(Target &T, Target::MCSubtargetInfoCtorFnTy Fn) {
1089
    TargetRegistry::RegisterMCSubtargetInfo(T, Fn);
1090
  }
1091
};
1092
1093
/// RegisterTargetMachine - Helper template for registering a target machine
1094
/// implementation, for use in the target machine initialization
1095
/// function. Usage:
1096
///
1097
/// extern "C" void LLVMInitializeFooTarget() {
1098
///   extern Target TheFooTarget;
1099
///   RegisterTargetMachine<FooTargetMachine> X(TheFooTarget);
1100
/// }
1101
template <class TargetMachineImpl> struct RegisterTargetMachine {
1102
4.37M
  RegisterTargetMachine(Target &T) {
1103
4.37M
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
4.37M
  }
llvm::RegisterTargetMachine<llvm::AArch64leTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
265k
  RegisterTargetMachine(Target &T) {
1103
265k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
265k
  }
llvm::RegisterTargetMachine<llvm::AArch64beTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
132k
  RegisterTargetMachine(Target &T) {
1103
132k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
132k
  }
llvm::RegisterTargetMachine<llvm::R600TargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
132k
  RegisterTargetMachine(Target &T) {
1103
132k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
132k
  }
llvm::RegisterTargetMachine<llvm::GCNTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
132k
  RegisterTargetMachine(Target &T) {
1103
132k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
132k
  }
llvm::RegisterTargetMachine<llvm::ARMLETargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
265k
  RegisterTargetMachine(Target &T) {
1103
265k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
265k
  }
llvm::RegisterTargetMachine<llvm::ARMBETargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
265k
  RegisterTargetMachine(Target &T) {
1103
265k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
265k
  }
llvm::RegisterTargetMachine<llvm::BPFTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
397k
  RegisterTargetMachine(Target &T) {
1103
397k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
397k
  }
llvm::RegisterTargetMachine<llvm::HexagonTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
132k
  RegisterTargetMachine(Target &T) {
1103
132k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
132k
  }
llvm::RegisterTargetMachine<llvm::LanaiTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
132k
  RegisterTargetMachine(Target &T) {
1103
132k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
132k
  }
llvm::RegisterTargetMachine<llvm::MipsebTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
265k
  RegisterTargetMachine(Target &T) {
1103
265k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
265k
  }
llvm::RegisterTargetMachine<llvm::MipselTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
265k
  RegisterTargetMachine(Target &T) {
1103
265k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
265k
  }
llvm::RegisterTargetMachine<llvm::MSP430TargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
132k
  RegisterTargetMachine(Target &T) {
1103
132k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
132k
  }
llvm::RegisterTargetMachine<llvm::NVPTXTargetMachine32>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
132k
  RegisterTargetMachine(Target &T) {
1103
132k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
132k
  }
llvm::RegisterTargetMachine<llvm::NVPTXTargetMachine64>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
132k
  RegisterTargetMachine(Target &T) {
1103
132k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
132k
  }
llvm::RegisterTargetMachine<llvm::PPCTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
397k
  RegisterTargetMachine(Target &T) {
1103
397k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
397k
  }
llvm::RegisterTargetMachine<llvm::SparcV8TargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
132k
  RegisterTargetMachine(Target &T) {
1103
132k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
132k
  }
llvm::RegisterTargetMachine<llvm::SparcV9TargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
132k
  RegisterTargetMachine(Target &T) {
1103
132k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
132k
  }
llvm::RegisterTargetMachine<llvm::SparcelTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
132k
  RegisterTargetMachine(Target &T) {
1103
132k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
132k
  }
llvm::RegisterTargetMachine<llvm::SystemZTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
132k
  RegisterTargetMachine(Target &T) {
1103
132k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
132k
  }
llvm::RegisterTargetMachine<llvm::WebAssemblyTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
265k
  RegisterTargetMachine(Target &T) {
1103
265k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
265k
  }
llvm::RegisterTargetMachine<llvm::X86TargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
265k
  RegisterTargetMachine(Target &T) {
1103
265k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
265k
  }
llvm::RegisterTargetMachine<llvm::XCoreTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1102
132k
  RegisterTargetMachine(Target &T) {
1103
132k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1104
132k
  }
1105
1106
private:
1107
  static TargetMachine *
1108
  Allocator(const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
1109
            const TargetOptions &Options, Optional<Reloc::Model> RM,
1110
49.1k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
49.1k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
49.1k
  }
llvm::RegisterTargetMachine<llvm::AArch64leTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
9.32k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
9.32k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
9.32k
  }
llvm::RegisterTargetMachine<llvm::AArch64beTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
36
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
36
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
36
  }
llvm::RegisterTargetMachine<llvm::R600TargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
291
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
291
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
291
  }
llvm::RegisterTargetMachine<llvm::GCNTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
2.93k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
2.93k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
2.93k
  }
llvm::RegisterTargetMachine<llvm::ARMLETargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
5.65k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
5.65k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
5.65k
  }
llvm::RegisterTargetMachine<llvm::ARMBETargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
48
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
48
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
48
  }
llvm::RegisterTargetMachine<llvm::BPFTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
144
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
144
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
144
  }
llvm::RegisterTargetMachine<llvm::HexagonTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
1.01k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
1.01k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
1.01k
  }
llvm::RegisterTargetMachine<llvm::LanaiTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
28
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
28
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
28
  }
llvm::RegisterTargetMachine<llvm::MipsebTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
1.15k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
1.15k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
1.15k
  }
llvm::RegisterTargetMachine<llvm::MipselTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
1.09k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
1.09k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
1.09k
  }
llvm::RegisterTargetMachine<llvm::MSP430TargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
76
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
76
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
76
  }
llvm::RegisterTargetMachine<llvm::NVPTXTargetMachine32>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
239
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
239
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
239
  }
llvm::RegisterTargetMachine<llvm::NVPTXTargetMachine64>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
204
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
204
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
204
  }
llvm::RegisterTargetMachine<llvm::PPCTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
3.41k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
3.41k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
3.41k
  }
llvm::RegisterTargetMachine<llvm::SparcV8TargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
150
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
150
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
150
  }
llvm::RegisterTargetMachine<llvm::SparcV9TargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
72
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
72
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
72
  }
llvm::RegisterTargetMachine<llvm::SparcelTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
5
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
5
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
5
  }
llvm::RegisterTargetMachine<llvm::SystemZTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
987
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
987
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
987
  }
llvm::RegisterTargetMachine<llvm::WebAssemblyTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
408
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
408
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
408
  }
llvm::RegisterTargetMachine<llvm::X86TargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
21.7k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
21.7k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
21.7k
  }
llvm::RegisterTargetMachine<llvm::XCoreTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1110
83
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1111
83
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1112
83
  }
1113
};
1114
1115
/// RegisterMCAsmBackend - Helper template for registering a target specific
1116
/// assembler backend. Usage:
1117
///
1118
/// extern "C" void LLVMInitializeFooMCAsmBackend() {
1119
///   extern Target TheFooTarget;
1120
///   RegisterMCAsmBackend<FooAsmLexer> X(TheFooTarget);
1121
/// }
1122
template <class MCAsmBackendImpl> struct RegisterMCAsmBackend {
1123
  RegisterMCAsmBackend(Target &T) {
1124
    TargetRegistry::RegisterMCAsmBackend(T, &Allocator);
1125
  }
1126
1127
private:
1128
  static MCAsmBackend *Allocator(const Target &T, const MCSubtargetInfo &STI,
1129
                                 const MCRegisterInfo &MRI,
1130
                                 const MCTargetOptions &Options) {
1131
    return new MCAsmBackendImpl(T, STI, MRI);
1132
  }
1133
};
1134
1135
/// RegisterMCAsmParser - Helper template for registering a target specific
1136
/// assembly parser, for use in the target machine initialization
1137
/// function. Usage:
1138
///
1139
/// extern "C" void LLVMInitializeFooMCAsmParser() {
1140
///   extern Target TheFooTarget;
1141
///   RegisterMCAsmParser<FooAsmParser> X(TheFooTarget);
1142
/// }
1143
template <class MCAsmParserImpl> struct RegisterMCAsmParser {
1144
2.53M
  RegisterMCAsmParser(Target &T) {
1145
2.53M
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1146
2.53M
  }
AArch64AsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::AArch64AsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1144
253k
  RegisterMCAsmParser(Target &T) {
1145
253k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1146
253k
  }
AMDGPUAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::AMDGPUAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1144
168k
  RegisterMCAsmParser(Target &T) {
1145
168k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1146
168k
  }
ARMAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::ARMAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1144
337k
  RegisterMCAsmParser(Target &T) {
1145
337k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1146
337k
  }
BPFAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::BPFAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1144
253k
  RegisterMCAsmParser(Target &T) {
1145
253k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1146
253k
  }
HexagonAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::HexagonAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1144
84.4k
  RegisterMCAsmParser(Target &T) {
1145
84.4k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1146
84.4k
  }
LanaiAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::LanaiAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1144
84.4k
  RegisterMCAsmParser(Target &T) {
1145
84.4k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1146
84.4k
  }
MipsAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::MipsAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1144
337k
  RegisterMCAsmParser(Target &T) {
1145
337k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1146
337k
  }
MSP430AsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::MSP430AsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1144
84.4k
  RegisterMCAsmParser(Target &T) {
1145
84.4k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1146
84.4k
  }
PPCAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::PPCAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1144
253k
  RegisterMCAsmParser(Target &T) {
1145
253k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1146
253k
  }
SparcAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::SparcAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1144
253k
  RegisterMCAsmParser(Target &T) {
1145
253k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1146
253k
  }
SystemZAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::SystemZAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1144
84.4k
  RegisterMCAsmParser(Target &T) {
1145
84.4k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1146
84.4k
  }
WebAssemblyAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::WebAssemblyAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1144
168k
  RegisterMCAsmParser(Target &T) {
1145
168k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1146
168k
  }
X86AsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::X86AsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1144
169k
  RegisterMCAsmParser(Target &T) {
1145
169k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1146
169k
  }
1147
1148
private:
1149
  static MCTargetAsmParser *Allocator(const MCSubtargetInfo &STI,
1150
                                      MCAsmParser &P, const MCInstrInfo &MII,
1151
15.8k
                                      const MCTargetOptions &Options) {
1152
15.8k
    return new MCAsmParserImpl(STI, P, MII, Options);
1153
15.8k
  }
AArch64AsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::AArch64AsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1151
2.37k
                                      const MCTargetOptions &Options) {
1152
2.37k
    return new MCAsmParserImpl(STI, P, MII, Options);
1153
2.37k
  }
AMDGPUAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::AMDGPUAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1151
392
                                      const MCTargetOptions &Options) {
1152
392
    return new MCAsmParserImpl(STI, P, MII, Options);
1153
392
  }
ARMAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::ARMAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1151
2.21k
                                      const MCTargetOptions &Options) {
1152
2.21k
    return new MCAsmParserImpl(STI, P, MII, Options);
1153
2.21k
  }
BPFAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::BPFAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1151
3
                                      const MCTargetOptions &Options) {
1152
3
    return new MCAsmParserImpl(STI, P, MII, Options);
1153
3
  }
HexagonAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::HexagonAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1151
118
                                      const MCTargetOptions &Options) {
1152
118
    return new MCAsmParserImpl(STI, P, MII, Options);
1153
118
  }
LanaiAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::LanaiAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1151
4
                                      const MCTargetOptions &Options) {
1152
4
    return new MCAsmParserImpl(STI, P, MII, Options);
1153
4
  }
MipsAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::MipsAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1151
1.43k
                                      const MCTargetOptions &Options) {
1152
1.43k
    return new MCAsmParserImpl(STI, P, MII, Options);
1153
1.43k
  }
MSP430AsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::MSP430AsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1151
20
                                      const MCTargetOptions &Options) {
1152
20
    return new MCAsmParserImpl(STI, P, MII, Options);
1153
20
  }
PPCAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::PPCAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1151
451
                                      const MCTargetOptions &Options) {
1152
451
    return new MCAsmParserImpl(STI, P, MII, Options);
1153
451
  }
SparcAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::SparcAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1151
105
                                      const MCTargetOptions &Options) {
1152
105
    return new MCAsmParserImpl(STI, P, MII, Options);
1153
105
  }
SystemZAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::SystemZAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1151
41
                                      const MCTargetOptions &Options) {
1152
41
    return new MCAsmParserImpl(STI, P, MII, Options);
1153
41
  }
WebAssemblyAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::WebAssemblyAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1151
12
                                      const MCTargetOptions &Options) {
1152
12
    return new MCAsmParserImpl(STI, P, MII, Options);
1153
12
  }
X86AsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::X86AsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1151
8.66k
                                      const MCTargetOptions &Options) {
1152
8.66k
    return new MCAsmParserImpl(STI, P, MII, Options);
1153
8.66k
  }
1154
};
1155
1156
/// RegisterAsmPrinter - Helper template for registering a target specific
1157
/// assembly printer, for use in the target machine initialization
1158
/// function. Usage:
1159
///
1160
/// extern "C" void LLVMInitializeFooAsmPrinter() {
1161
///   extern Target TheFooTarget;
1162
///   RegisterAsmPrinter<FooAsmPrinter> X(TheFooTarget);
1163
/// }
1164
template <class AsmPrinterImpl> struct RegisterAsmPrinter {
1165
2.07M
  RegisterAsmPrinter(Target &T) {
1166
2.07M
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1167
2.07M
  }
AArch64AsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::AArch64AsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1165
222k
  RegisterAsmPrinter(Target &T) {
1166
222k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1167
222k
  }
llvm::RegisterAsmPrinter<llvm::ARMAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1165
296k
  RegisterAsmPrinter(Target &T) {
1166
296k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1167
296k
  }
BPFAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::BPFAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1165
222k
  RegisterAsmPrinter(Target &T) {
1166
222k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1167
222k
  }
llvm::RegisterAsmPrinter<llvm::HexagonAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1165
74.1k
  RegisterAsmPrinter(Target &T) {
1166
74.1k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1167
74.1k
  }
LanaiAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::LanaiAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1165
74.1k
  RegisterAsmPrinter(Target &T) {
1166
74.1k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1167
74.1k
  }
llvm::RegisterAsmPrinter<llvm::MipsAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1165
296k
  RegisterAsmPrinter(Target &T) {
1166
296k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1167
296k
  }
MSP430AsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::MSP430AsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1165
74.1k
  RegisterAsmPrinter(Target &T) {
1166
74.1k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1167
74.1k
  }
llvm::RegisterAsmPrinter<llvm::NVPTXAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1165
148k
  RegisterAsmPrinter(Target &T) {
1166
148k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1167
148k
  }
SparcAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::SparcAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1165
222k
  RegisterAsmPrinter(Target &T) {
1166
222k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1167
222k
  }
llvm::RegisterAsmPrinter<llvm::SystemZAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1165
74.1k
  RegisterAsmPrinter(Target &T) {
1166
74.1k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1167
74.1k
  }
llvm::RegisterAsmPrinter<llvm::WebAssemblyAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1165
148k
  RegisterAsmPrinter(Target &T) {
1166
148k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1167
148k
  }
llvm::RegisterAsmPrinter<llvm::X86AsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1165
148k
  RegisterAsmPrinter(Target &T) {
1166
148k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1167
148k
  }
XCoreAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::XCoreAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1165
74.1k
  RegisterAsmPrinter(Target &T) {
1166
74.1k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1167
74.1k
  }
1168
1169
private:
1170
  static AsmPrinter *Allocator(TargetMachine &TM,
1171
30.0k
                               std::unique_ptr<MCStreamer> &&Streamer) {
1172
30.0k
    return new AsmPrinterImpl(TM, std::move(Streamer));
1173
30.0k
  }
AArch64AsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::AArch64AsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1171
8.59k
                               std::unique_ptr<MCStreamer> &&Streamer) {
1172
8.59k
    return new AsmPrinterImpl(TM, std::move(Streamer));
1173
8.59k
  }
llvm::RegisterAsmPrinter<llvm::ARMAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1171
4.99k
                               std::unique_ptr<MCStreamer> &&Streamer) {
1172
4.99k
    return new AsmPrinterImpl(TM, std::move(Streamer));
1173
4.99k
  }
BPFAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::BPFAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1171
142
                               std::unique_ptr<MCStreamer> &&Streamer) {
1172
142
    return new AsmPrinterImpl(TM, std::move(Streamer));
1173
142
  }
llvm::RegisterAsmPrinter<llvm::HexagonAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1171
913
                               std::unique_ptr<MCStreamer> &&Streamer) {
1172
913
    return new AsmPrinterImpl(TM, std::move(Streamer));
1173
913
  }
LanaiAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::LanaiAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1171
21
                               std::unique_ptr<MCStreamer> &&Streamer) {
1172
21
    return new AsmPrinterImpl(TM, std::move(Streamer));
1173
21
  }
llvm::RegisterAsmPrinter<llvm::MipsAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1171
1.95k
                               std::unique_ptr<MCStreamer> &&Streamer) {
1172
1.95k
    return new AsmPrinterImpl(TM, std::move(Streamer));
1173
1.95k
  }
MSP430AsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::MSP430AsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1171
71
                               std::unique_ptr<MCStreamer> &&Streamer) {
1172
71
    return new AsmPrinterImpl(TM, std::move(Streamer));
1173
71
  }
llvm::RegisterAsmPrinter<llvm::NVPTXAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1171
257
                               std::unique_ptr<MCStreamer> &&Streamer) {
1172
257
    return new AsmPrinterImpl(TM, std::move(Streamer));
1173
257
  }
SparcAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::SparcAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1171
195
                               std::unique_ptr<MCStreamer> &&Streamer) {
1172
195
    return new AsmPrinterImpl(TM, std::move(Streamer));
1173
195
  }
llvm::RegisterAsmPrinter<llvm::SystemZAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1171
906
                               std::unique_ptr<MCStreamer> &&Streamer) {
1172
906
    return new AsmPrinterImpl(TM, std::move(Streamer));
1173
906
  }
llvm::RegisterAsmPrinter<llvm::WebAssemblyAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1171
356
                               std::unique_ptr<MCStreamer> &&Streamer) {
1172
356
    return new AsmPrinterImpl(TM, std::move(Streamer));
1173
356
  }
llvm::RegisterAsmPrinter<llvm::X86AsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1171
11.6k
                               std::unique_ptr<MCStreamer> &&Streamer) {
1172
11.6k
    return new AsmPrinterImpl(TM, std::move(Streamer));
1173
11.6k
  }
XCoreAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::XCoreAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1171
69
                               std::unique_ptr<MCStreamer> &&Streamer) {
1172
69
    return new AsmPrinterImpl(TM, std::move(Streamer));
1173
69
  }
1174
};
1175
1176
/// RegisterMCCodeEmitter - Helper template for registering a target specific
1177
/// machine code emitter, for use in the target initialization
1178
/// function. Usage:
1179
///
1180
/// extern "C" void LLVMInitializeFooMCCodeEmitter() {
1181
///   extern Target TheFooTarget;
1182
///   RegisterMCCodeEmitter<FooCodeEmitter> X(TheFooTarget);
1183
/// }
1184
template <class MCCodeEmitterImpl> struct RegisterMCCodeEmitter {
1185
  RegisterMCCodeEmitter(Target &T) {
1186
    TargetRegistry::RegisterMCCodeEmitter(T, &Allocator);
1187
  }
1188
1189
private:
1190
  static MCCodeEmitter *Allocator(const MCInstrInfo & /*II*/,
1191
                                  const MCRegisterInfo & /*MRI*/,
1192
                                  MCContext & /*Ctx*/) {
1193
    return new MCCodeEmitterImpl();
1194
  }
1195
};
1196
1197
} // end namespace llvm
1198
1199
#endif // LLVM_SUPPORT_TARGETREGISTRY_H