Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/Support/TargetRegistry.h
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//===- Support/TargetRegistry.h - Target Registration -----------*- C++ -*-===//
2
//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
9
// This file exposes the TargetRegistry interface, which tools can use to access
10
// the appropriate target specific classes (TargetMachine, AsmPrinter, etc.)
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// which have been registered.
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//
13
// Target specific class implementations should register themselves using the
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// appropriate TargetRegistry interfaces.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_SUPPORT_TARGETREGISTRY_H
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#define LLVM_SUPPORT_TARGETREGISTRY_H
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#include "llvm-c/DisassemblerTypes.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/Triple.h"
25
#include "llvm/ADT/iterator_range.h"
26
#include "llvm/Support/CodeGen.h"
27
#include "llvm/Support/ErrorHandling.h"
28
#include "llvm/Support/FormattedStream.h"
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#include <algorithm>
30
#include <cassert>
31
#include <cstddef>
32
#include <iterator>
33
#include <memory>
34
#include <string>
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36
namespace llvm {
37
38
class AsmPrinter;
39
class MCAsmBackend;
40
class MCAsmInfo;
41
class MCAsmParser;
42
class MCCodeEmitter;
43
class MCContext;
44
class MCDisassembler;
45
class MCInstPrinter;
46
class MCInstrAnalysis;
47
class MCInstrInfo;
48
class MCObjectWriter;
49
class MCRegisterInfo;
50
class MCRelocationInfo;
51
class MCStreamer;
52
class MCSubtargetInfo;
53
class MCSymbolizer;
54
class MCTargetAsmParser;
55
class MCTargetOptions;
56
class MCTargetStreamer;
57
class raw_ostream;
58
class raw_pwrite_stream;
59
class TargetMachine;
60
class TargetOptions;
61
62
MCStreamer *createNullStreamer(MCContext &Ctx);
63
// Takes ownership of \p TAB and \p CE.
64
65
/// Create a machine code streamer which will print out assembly for the native
66
/// target, suitable for compiling with a native assembler.
67
///
68
/// \param InstPrint - If given, the instruction printer to use. If not given
69
/// the MCInst representation will be printed.  This method takes ownership of
70
/// InstPrint.
71
///
72
/// \param CE - If given, a code emitter to use to show the instruction
73
/// encoding inline with the assembly. This method takes ownership of \p CE.
74
///
75
/// \param TAB - If given, a target asm backend to use to show the fixup
76
/// information in conjunction with encoding information. This method takes
77
/// ownership of \p TAB.
78
///
79
/// \param ShowInst - Whether to show the MCInst representation inline with
80
/// the assembly.
81
MCStreamer *
82
createAsmStreamer(MCContext &Ctx, std::unique_ptr<formatted_raw_ostream> OS,
83
                  bool isVerboseAsm, bool useDwarfDirectory,
84
                  MCInstPrinter *InstPrint, std::unique_ptr<MCCodeEmitter> &&CE,
85
                  std::unique_ptr<MCAsmBackend> &&TAB, bool ShowInst);
86
87
MCStreamer *createELFStreamer(MCContext &Ctx,
88
                              std::unique_ptr<MCAsmBackend> &&TAB,
89
                              std::unique_ptr<MCObjectWriter> &&OW,
90
                              std::unique_ptr<MCCodeEmitter> &&CE,
91
                              bool RelaxAll);
92
MCStreamer *createMachOStreamer(MCContext &Ctx,
93
                                std::unique_ptr<MCAsmBackend> &&TAB,
94
                                std::unique_ptr<MCObjectWriter> &&OW,
95
                                std::unique_ptr<MCCodeEmitter> &&CE,
96
                                bool RelaxAll, bool DWARFMustBeAtTheEnd,
97
                                bool LabelSections = false);
98
MCStreamer *createWasmStreamer(MCContext &Ctx,
99
                               std::unique_ptr<MCAsmBackend> &&TAB,
100
                               std::unique_ptr<MCObjectWriter> &&OW,
101
                               std::unique_ptr<MCCodeEmitter> &&CE,
102
                               bool RelaxAll);
103
MCStreamer *createXCOFFStreamer(MCContext &Ctx,
104
                                std::unique_ptr<MCAsmBackend> &&TAB,
105
                                std::unique_ptr<MCObjectWriter> &&OW,
106
                                std::unique_ptr<MCCodeEmitter> &&CE,
107
                                bool RelaxAll);
108
109
MCRelocationInfo *createMCRelocationInfo(const Triple &TT, MCContext &Ctx);
110
111
MCSymbolizer *createMCSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
112
                                 LLVMSymbolLookupCallback SymbolLookUp,
113
                                 void *DisInfo, MCContext *Ctx,
114
                                 std::unique_ptr<MCRelocationInfo> &&RelInfo);
115
116
/// Target - Wrapper for Target specific information.
117
///
118
/// For registration purposes, this is a POD type so that targets can be
119
/// registered without the use of static constructors.
120
///
121
/// Targets should implement a single global instance of this class (which
122
/// will be zero initialized), and pass that instance to the TargetRegistry as
123
/// part of their initialization.
124
class Target {
125
public:
126
  friend struct TargetRegistry;
127
128
  using ArchMatchFnTy = bool (*)(Triple::ArchType Arch);
129
130
  using MCAsmInfoCtorFnTy = MCAsmInfo *(*)(const MCRegisterInfo &MRI,
131
                                           const Triple &TT);
132
  using MCInstrInfoCtorFnTy = MCInstrInfo *(*)();
133
  using MCInstrAnalysisCtorFnTy = MCInstrAnalysis *(*)(const MCInstrInfo *Info);
134
  using MCRegInfoCtorFnTy = MCRegisterInfo *(*)(const Triple &TT);
135
  using MCSubtargetInfoCtorFnTy = MCSubtargetInfo *(*)(const Triple &TT,
136
                                                       StringRef CPU,
137
                                                       StringRef Features);
138
  using TargetMachineCtorTy = TargetMachine
139
      *(*)(const Target &T, const Triple &TT, StringRef CPU, StringRef Features,
140
           const TargetOptions &Options, Optional<Reloc::Model> RM,
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           Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT);
142
  // If it weren't for layering issues (this header is in llvm/Support, but
143
  // depends on MC?) this should take the Streamer by value rather than rvalue
144
  // reference.
145
  using AsmPrinterCtorTy = AsmPrinter *(*)(
146
      TargetMachine &TM, std::unique_ptr<MCStreamer> &&Streamer);
147
  using MCAsmBackendCtorTy = MCAsmBackend *(*)(const Target &T,
148
                                               const MCSubtargetInfo &STI,
149
                                               const MCRegisterInfo &MRI,
150
                                               const MCTargetOptions &Options);
151
  using MCAsmParserCtorTy = MCTargetAsmParser *(*)(
152
      const MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII,
153
      const MCTargetOptions &Options);
154
  using MCDisassemblerCtorTy = MCDisassembler *(*)(const Target &T,
155
                                                   const MCSubtargetInfo &STI,
156
                                                   MCContext &Ctx);
157
  using MCInstPrinterCtorTy = MCInstPrinter *(*)(const Triple &T,
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                                                 unsigned SyntaxVariant,
159
                                                 const MCAsmInfo &MAI,
160
                                                 const MCInstrInfo &MII,
161
                                                 const MCRegisterInfo &MRI);
162
  using MCCodeEmitterCtorTy = MCCodeEmitter *(*)(const MCInstrInfo &II,
163
                                                 const MCRegisterInfo &MRI,
164
                                                 MCContext &Ctx);
165
  using ELFStreamerCtorTy =
166
      MCStreamer *(*)(const Triple &T, MCContext &Ctx,
167
                      std::unique_ptr<MCAsmBackend> &&TAB,
168
                      std::unique_ptr<MCObjectWriter> &&OW,
169
                      std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll);
170
  using MachOStreamerCtorTy =
171
      MCStreamer *(*)(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
172
                      std::unique_ptr<MCObjectWriter> &&OW,
173
                      std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
174
                      bool DWARFMustBeAtTheEnd);
175
  using COFFStreamerCtorTy =
176
      MCStreamer *(*)(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
177
                      std::unique_ptr<MCObjectWriter> &&OW,
178
                      std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
179
                      bool IncrementalLinkerCompatible);
180
  using WasmStreamerCtorTy =
181
      MCStreamer *(*)(const Triple &T, MCContext &Ctx,
182
                      std::unique_ptr<MCAsmBackend> &&TAB,
183
                      std::unique_ptr<MCObjectWriter> &&OW,
184
                      std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll);
185
  using NullTargetStreamerCtorTy = MCTargetStreamer *(*)(MCStreamer &S);
186
  using AsmTargetStreamerCtorTy = MCTargetStreamer *(*)(
187
      MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint,
188
      bool IsVerboseAsm);
189
  using ObjectTargetStreamerCtorTy = MCTargetStreamer *(*)(
190
      MCStreamer &S, const MCSubtargetInfo &STI);
191
  using MCRelocationInfoCtorTy = MCRelocationInfo *(*)(const Triple &TT,
192
                                                       MCContext &Ctx);
193
  using MCSymbolizerCtorTy = MCSymbolizer *(*)(
194
      const Triple &TT, LLVMOpInfoCallback GetOpInfo,
195
      LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx,
196
      std::unique_ptr<MCRelocationInfo> &&RelInfo);
197
198
private:
199
  /// Next - The next registered target in the linked list, maintained by the
200
  /// TargetRegistry.
201
  Target *Next;
202
203
  /// The target function for checking if an architecture is supported.
204
  ArchMatchFnTy ArchMatchFn;
205
206
  /// Name - The target name.
207
  const char *Name;
208
209
  /// ShortDesc - A short description of the target.
210
  const char *ShortDesc;
211
212
  /// BackendName - The name of the backend implementation. This must match the
213
  /// name of the 'def X : Target ...' in TableGen.
214
  const char *BackendName;
215
216
  /// HasJIT - Whether this target supports the JIT.
217
  bool HasJIT;
218
219
  /// MCAsmInfoCtorFn - Constructor function for this target's MCAsmInfo, if
220
  /// registered.
221
  MCAsmInfoCtorFnTy MCAsmInfoCtorFn;
222
223
  /// MCInstrInfoCtorFn - Constructor function for this target's MCInstrInfo,
224
  /// if registered.
225
  MCInstrInfoCtorFnTy MCInstrInfoCtorFn;
226
227
  /// MCInstrAnalysisCtorFn - Constructor function for this target's
228
  /// MCInstrAnalysis, if registered.
229
  MCInstrAnalysisCtorFnTy MCInstrAnalysisCtorFn;
230
231
  /// MCRegInfoCtorFn - Constructor function for this target's MCRegisterInfo,
232
  /// if registered.
233
  MCRegInfoCtorFnTy MCRegInfoCtorFn;
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235
  /// MCSubtargetInfoCtorFn - Constructor function for this target's
236
  /// MCSubtargetInfo, if registered.
237
  MCSubtargetInfoCtorFnTy MCSubtargetInfoCtorFn;
238
239
  /// TargetMachineCtorFn - Construction function for this target's
240
  /// TargetMachine, if registered.
241
  TargetMachineCtorTy TargetMachineCtorFn;
242
243
  /// MCAsmBackendCtorFn - Construction function for this target's
244
  /// MCAsmBackend, if registered.
245
  MCAsmBackendCtorTy MCAsmBackendCtorFn;
246
247
  /// MCAsmParserCtorFn - Construction function for this target's
248
  /// MCTargetAsmParser, if registered.
249
  MCAsmParserCtorTy MCAsmParserCtorFn;
250
251
  /// AsmPrinterCtorFn - Construction function for this target's AsmPrinter,
252
  /// if registered.
253
  AsmPrinterCtorTy AsmPrinterCtorFn;
254
255
  /// MCDisassemblerCtorFn - Construction function for this target's
256
  /// MCDisassembler, if registered.
257
  MCDisassemblerCtorTy MCDisassemblerCtorFn;
258
259
  /// MCInstPrinterCtorFn - Construction function for this target's
260
  /// MCInstPrinter, if registered.
261
  MCInstPrinterCtorTy MCInstPrinterCtorFn;
262
263
  /// MCCodeEmitterCtorFn - Construction function for this target's
264
  /// CodeEmitter, if registered.
265
  MCCodeEmitterCtorTy MCCodeEmitterCtorFn;
266
267
  // Construction functions for the various object formats, if registered.
268
  COFFStreamerCtorTy COFFStreamerCtorFn = nullptr;
269
  MachOStreamerCtorTy MachOStreamerCtorFn = nullptr;
270
  ELFStreamerCtorTy ELFStreamerCtorFn = nullptr;
271
  WasmStreamerCtorTy WasmStreamerCtorFn = nullptr;
272
273
  /// Construction function for this target's null TargetStreamer, if
274
  /// registered (default = nullptr).
275
  NullTargetStreamerCtorTy NullTargetStreamerCtorFn = nullptr;
276
277
  /// Construction function for this target's asm TargetStreamer, if
278
  /// registered (default = nullptr).
279
  AsmTargetStreamerCtorTy AsmTargetStreamerCtorFn = nullptr;
280
281
  /// Construction function for this target's obj TargetStreamer, if
282
  /// registered (default = nullptr).
283
  ObjectTargetStreamerCtorTy ObjectTargetStreamerCtorFn = nullptr;
284
285
  /// MCRelocationInfoCtorFn - Construction function for this target's
286
  /// MCRelocationInfo, if registered (default = llvm::createMCRelocationInfo)
287
  MCRelocationInfoCtorTy MCRelocationInfoCtorFn = nullptr;
288
289
  /// MCSymbolizerCtorFn - Construction function for this target's
290
  /// MCSymbolizer, if registered (default = llvm::createMCSymbolizer)
291
  MCSymbolizerCtorTy MCSymbolizerCtorFn = nullptr;
292
293
public:
294
4.38M
  Target() = default;
295
296
  /// @name Target Information
297
  /// @{
298
299
  // getNext - Return the next registered target.
300
2.42M
  const Target *getNext() const { return Next; }
301
302
  /// getName - Get the target name.
303
190k
  const char *getName() const { return Name; }
304
305
  /// getShortDescription - Get a short description of the target.
306
0
  const char *getShortDescription() const { return ShortDesc; }
307
308
  /// getBackendName - Get the backend name.
309
223k
  const char *getBackendName() const { return BackendName; }
310
311
  /// @}
312
  /// @name Feature Predicates
313
  /// @{
314
315
  /// hasJIT - Check if this targets supports the just-in-time compilation.
316
  bool hasJIT() const { return HasJIT; }
317
318
  /// hasTargetMachine - Check if this target supports code generation.
319
0
  bool hasTargetMachine() const { return TargetMachineCtorFn != nullptr; }
320
321
  /// hasMCAsmBackend - Check if this target supports .o generation.
322
0
  bool hasMCAsmBackend() const { return MCAsmBackendCtorFn != nullptr; }
323
324
  /// hasMCAsmParser - Check if this target supports assembly parsing.
325
39
  bool hasMCAsmParser() const { return MCAsmParserCtorFn != nullptr; }
326
327
  /// @}
328
  /// @name Feature Constructors
329
  /// @{
330
331
  /// createMCAsmInfo - Create a MCAsmInfo implementation for the specified
332
  /// target triple.
333
  ///
334
  /// \param TheTriple This argument is used to determine the target machine
335
  /// feature set; it should always be provided. Generally this should be
336
  /// either the target triple from the module, or the target triple of the
337
  /// host if that does not exist.
338
  MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI,
339
68.0k
                             StringRef TheTriple) const {
340
68.0k
    if (!MCAsmInfoCtorFn)
341
0
      return nullptr;
342
68.0k
    return MCAsmInfoCtorFn(MRI, Triple(TheTriple));
343
68.0k
  }
344
345
  /// createMCInstrInfo - Create a MCInstrInfo implementation.
346
  ///
347
76.2k
  MCInstrInfo *createMCInstrInfo() const {
348
76.2k
    if (!MCInstrInfoCtorFn)
349
0
      return nullptr;
350
76.2k
    return MCInstrInfoCtorFn();
351
76.2k
  }
352
353
  /// createMCInstrAnalysis - Create a MCInstrAnalysis implementation.
354
  ///
355
3.10k
  MCInstrAnalysis *createMCInstrAnalysis(const MCInstrInfo *Info) const {
356
3.10k
    if (!MCInstrAnalysisCtorFn)
357
279
      return nullptr;
358
2.83k
    return MCInstrAnalysisCtorFn(Info);
359
2.83k
  }
360
361
  /// createMCRegInfo - Create a MCRegisterInfo implementation.
362
  ///
363
68.7k
  MCRegisterInfo *createMCRegInfo(StringRef TT) const {
364
68.7k
    if (!MCRegInfoCtorFn)
365
0
      return nullptr;
366
68.7k
    return MCRegInfoCtorFn(Triple(TT));
367
68.7k
  }
368
369
  /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
370
  ///
371
  /// \param TheTriple This argument is used to determine the target machine
372
  /// feature set; it should always be provided. Generally this should be
373
  /// either the target triple from the module, or the target triple of the
374
  /// host if that does not exist.
375
  /// \param CPU This specifies the name of the target CPU.
376
  /// \param Features This specifies the string representation of the
377
  /// additional target features.
378
  MCSubtargetInfo *createMCSubtargetInfo(StringRef TheTriple, StringRef CPU,
379
68.7k
                                         StringRef Features) const {
380
68.7k
    if (!MCSubtargetInfoCtorFn)
381
0
      return nullptr;
382
68.7k
    return MCSubtargetInfoCtorFn(Triple(TheTriple), CPU, Features);
383
68.7k
  }
384
385
  /// createTargetMachine - Create a target specific machine implementation
386
  /// for the specified \p Triple.
387
  ///
388
  /// \param TT This argument is used to determine the target machine
389
  /// feature set; it should always be provided. Generally this should be
390
  /// either the target triple from the module, or the target triple of the
391
  /// host if that does not exist.
392
  TargetMachine *createTargetMachine(StringRef TT, StringRef CPU,
393
                                     StringRef Features,
394
                                     const TargetOptions &Options,
395
                                     Optional<Reloc::Model> RM,
396
                                     Optional<CodeModel::Model> CM = None,
397
                                     CodeGenOpt::Level OL = CodeGenOpt::Default,
398
52.5k
                                     bool JIT = false) const {
399
52.5k
    if (!TargetMachineCtorFn)
400
1
      return nullptr;
401
52.5k
    return TargetMachineCtorFn(*this, Triple(TT), CPU, Features, Options, RM,
402
52.5k
                               CM, OL, JIT);
403
52.5k
  }
404
405
  /// createMCAsmBackend - Create a target specific assembly parser.
406
  MCAsmBackend *createMCAsmBackend(const MCSubtargetInfo &STI,
407
                                   const MCRegisterInfo &MRI,
408
47.3k
                                   const MCTargetOptions &Options) const {
409
47.3k
    if (!MCAsmBackendCtorFn)
410
329
      return nullptr;
411
47.0k
    return MCAsmBackendCtorFn(*this, STI, MRI, Options);
412
47.0k
  }
413
414
  /// createMCAsmParser - Create a target specific assembly parser.
415
  ///
416
  /// \param Parser The target independent parser implementation to use for
417
  /// parsing and lexing.
418
  MCTargetAsmParser *createMCAsmParser(const MCSubtargetInfo &STI,
419
                                       MCAsmParser &Parser,
420
                                       const MCInstrInfo &MII,
421
18.4k
                                       const MCTargetOptions &Options) const {
422
18.4k
    if (!MCAsmParserCtorFn)
423
0
      return nullptr;
424
18.4k
    return MCAsmParserCtorFn(STI, Parser, MII, Options);
425
18.4k
  }
426
427
  /// createAsmPrinter - Create a target specific assembly printer pass.  This
428
  /// takes ownership of the MCStreamer object.
429
  AsmPrinter *createAsmPrinter(TargetMachine &TM,
430
36.2k
                               std::unique_ptr<MCStreamer> &&Streamer) const {
431
36.2k
    if (!AsmPrinterCtorFn)
432
0
      return nullptr;
433
36.2k
    return AsmPrinterCtorFn(TM, std::move(Streamer));
434
36.2k
  }
435
436
  MCDisassembler *createMCDisassembler(const MCSubtargetInfo &STI,
437
                                       MCContext &Ctx) const {
438
    if (!MCDisassemblerCtorFn)
439
      return nullptr;
440
    return MCDisassemblerCtorFn(*this, STI, Ctx);
441
  }
442
443
  MCInstPrinter *createMCInstPrinter(const Triple &T, unsigned SyntaxVariant,
444
                                     const MCAsmInfo &MAI,
445
                                     const MCInstrInfo &MII,
446
30.1k
                                     const MCRegisterInfo &MRI) const {
447
30.1k
    if (!MCInstPrinterCtorFn)
448
0
      return nullptr;
449
30.1k
    return MCInstPrinterCtorFn(T, SyntaxVariant, MAI, MII, MRI);
450
30.1k
  }
451
452
  /// createMCCodeEmitter - Create a target specific code emitter.
453
  MCCodeEmitter *createMCCodeEmitter(const MCInstrInfo &II,
454
                                     const MCRegisterInfo &MRI,
455
162k
                                     MCContext &Ctx) const {
456
162k
    if (!MCCodeEmitterCtorFn)
457
0
      return nullptr;
458
162k
    return MCCodeEmitterCtorFn(II, MRI, Ctx);
459
162k
  }
460
461
  /// Create a target specific MCStreamer.
462
  ///
463
  /// \param T The target triple.
464
  /// \param Ctx The target context.
465
  /// \param TAB The target assembler backend object. Takes ownership.
466
  /// \param OW The stream object.
467
  /// \param Emitter The target independent assembler object.Takes ownership.
468
  /// \param RelaxAll Relax all fixups?
469
  MCStreamer *createMCObjectStreamer(const Triple &T, MCContext &Ctx,
470
                                     std::unique_ptr<MCAsmBackend> &&TAB,
471
                                     std::unique_ptr<MCObjectWriter> &&OW,
472
                                     std::unique_ptr<MCCodeEmitter> &&Emitter,
473
                                     const MCSubtargetInfo &STI, bool RelaxAll,
474
                                     bool IncrementalLinkerCompatible,
475
20.6k
                                     bool DWARFMustBeAtTheEnd) const {
476
20.6k
    MCStreamer *S;
477
20.6k
    switch (T.getObjectFormat()) {
478
20.6k
    case Triple::UnknownObjectFormat:
479
0
      llvm_unreachable("Unknown object format");
480
20.6k
    case Triple::COFF:
481
592
      assert(T.isOSWindows() && "only Windows COFF is supported");
482
592
      S = COFFStreamerCtorFn(Ctx, std::move(TAB), std::move(OW),
483
592
                             std::move(Emitter), RelaxAll,
484
592
                             IncrementalLinkerCompatible);
485
592
      break;
486
20.6k
    case Triple::MachO:
487
13.9k
      if (MachOStreamerCtorFn)
488
10.2k
        S = MachOStreamerCtorFn(Ctx, std::move(TAB), std::move(OW),
489
10.2k
                                std::move(Emitter), RelaxAll,
490
10.2k
                                DWARFMustBeAtTheEnd);
491
3.69k
      else
492
3.69k
        S = createMachOStreamer(Ctx, std::move(TAB), std::move(OW),
493
3.69k
                                std::move(Emitter), RelaxAll,
494
3.69k
                                DWARFMustBeAtTheEnd);
495
13.9k
      break;
496
20.6k
    case Triple::ELF:
497
5.87k
      if (ELFStreamerCtorFn)
498
2.64k
        S = ELFStreamerCtorFn(T, Ctx, std::move(TAB), std::move(OW),
499
2.64k
                              std::move(Emitter), RelaxAll);
500
3.23k
      else
501
3.23k
        S = createELFStreamer(Ctx, std::move(TAB), std::move(OW),
502
3.23k
                              std::move(Emitter), RelaxAll);
503
5.87k
      break;
504
20.6k
    case Triple::Wasm:
505
209
      if (WasmStreamerCtorFn)
506
0
        S = WasmStreamerCtorFn(T, Ctx, std::move(TAB), std::move(OW),
507
0
                               std::move(Emitter), RelaxAll);
508
209
      else
509
209
        S = createWasmStreamer(Ctx, std::move(TAB), std::move(OW),
510
209
                               std::move(Emitter), RelaxAll);
511
209
      break;
512
20.6k
    case Triple::XCOFF:
513
2
      S = createXCOFFStreamer(Ctx, std::move(TAB), std::move(OW),
514
2
                              std::move(Emitter), RelaxAll);
515
2
      break;
516
20.6k
    }
517
20.6k
    if (ObjectTargetStreamerCtorFn)
518
20.5k
      ObjectTargetStreamerCtorFn(*S, STI);
519
20.6k
    return S;
520
20.6k
  }
521
522
  MCStreamer *createAsmStreamer(MCContext &Ctx,
523
                                std::unique_ptr<formatted_raw_ostream> OS,
524
                                bool IsVerboseAsm, bool UseDwarfDirectory,
525
                                MCInstPrinter *InstPrint,
526
                                std::unique_ptr<MCCodeEmitter> &&CE,
527
                                std::unique_ptr<MCAsmBackend> &&TAB,
528
26.7k
                                bool ShowInst) const {
529
26.7k
    formatted_raw_ostream &OSRef = *OS;
530
26.7k
    MCStreamer *S = llvm::createAsmStreamer(
531
26.7k
        Ctx, std::move(OS), IsVerboseAsm, UseDwarfDirectory, InstPrint,
532
26.7k
        std::move(CE), std::move(TAB), ShowInst);
533
26.7k
    createAsmTargetStreamer(*S, OSRef, InstPrint, IsVerboseAsm);
534
26.7k
    return S;
535
26.7k
  }
536
537
  MCTargetStreamer *createAsmTargetStreamer(MCStreamer &S,
538
                                            formatted_raw_ostream &OS,
539
                                            MCInstPrinter *InstPrint,
540
26.7k
                                            bool IsVerboseAsm) const {
541
26.7k
    if (AsmTargetStreamerCtorFn)
542
25.1k
      return AsmTargetStreamerCtorFn(S, OS, InstPrint, IsVerboseAsm);
543
1.59k
    return nullptr;
544
1.59k
  }
545
546
18
  MCStreamer *createNullStreamer(MCContext &Ctx) const {
547
18
    MCStreamer *S = llvm::createNullStreamer(Ctx);
548
18
    createNullTargetStreamer(*S);
549
18
    return S;
550
18
  }
551
552
94
  MCTargetStreamer *createNullTargetStreamer(MCStreamer &S) const {
553
94
    if (NullTargetStreamerCtorFn)
554
6
      return NullTargetStreamerCtorFn(S);
555
88
    return nullptr;
556
88
  }
557
558
  /// createMCRelocationInfo - Create a target specific MCRelocationInfo.
559
  ///
560
  /// \param TT The target triple.
561
  /// \param Ctx The target context.
562
  MCRelocationInfo *createMCRelocationInfo(StringRef TT, MCContext &Ctx) const {
563
    MCRelocationInfoCtorTy Fn = MCRelocationInfoCtorFn
564
                                    ? MCRelocationInfoCtorFn
565
                                    : llvm::createMCRelocationInfo;
566
    return Fn(Triple(TT), Ctx);
567
  }
568
569
  /// createMCSymbolizer - Create a target specific MCSymbolizer.
570
  ///
571
  /// \param TT The target triple.
572
  /// \param GetOpInfo The function to get the symbolic information for
573
  /// operands.
574
  /// \param SymbolLookUp The function to lookup a symbol name.
575
  /// \param DisInfo The pointer to the block of symbolic information for above
576
  /// call
577
  /// back.
578
  /// \param Ctx The target context.
579
  /// \param RelInfo The relocation information for this target. Takes
580
  /// ownership.
581
  MCSymbolizer *
582
  createMCSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo,
583
                     LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo,
584
                     MCContext *Ctx,
585
                     std::unique_ptr<MCRelocationInfo> &&RelInfo) const {
586
    MCSymbolizerCtorTy Fn =
587
        MCSymbolizerCtorFn ? MCSymbolizerCtorFn : llvm::createMCSymbolizer;
588
    return Fn(Triple(TT), GetOpInfo, SymbolLookUp, DisInfo, Ctx,
589
              std::move(RelInfo));
590
  }
591
592
  /// @}
593
};
594
595
/// TargetRegistry - Generic interface to target specific features.
596
struct TargetRegistry {
597
  // FIXME: Make this a namespace, probably just move all the Register*
598
  // functions into Target (currently they all just set members on the Target
599
  // anyway, and Target friends this class so those functions can...
600
  // function).
601
  TargetRegistry() = delete;
602
603
  class iterator
604
      : public std::iterator<std::forward_iterator_tag, Target, ptrdiff_t> {
605
    friend struct TargetRegistry;
606
607
    const Target *Current = nullptr;
608
609
383k
    explicit iterator(Target *T) : Current(T) {}
610
611
  public:
612
383k
    iterator() = default;
613
614
2.68M
    bool operator==(const iterator &x) const { return Current == x.Current; }
615
2.55M
    bool operator!=(const iterator &x) const { return !operator==(x); }
616
617
    // Iterator traversal: forward iteration only
618
2.42M
    iterator &operator++() { // Preincrement
619
2.42M
      assert(Current && "Cannot increment end iterator!");
620
2.42M
      Current = Current->getNext();
621
2.42M
      return *this;
622
2.42M
    }
623
0
    iterator operator++(int) { // Postincrement
624
0
      iterator tmp = *this;
625
0
      ++*this;
626
0
      return tmp;
627
0
    }
628
629
2.50M
    const Target &operator*() const {
630
2.50M
      assert(Current && "Cannot dereference end iterator!");
631
2.50M
      return *Current;
632
2.50M
    }
633
634
0
    const Target *operator->() const { return &operator*(); }
635
  };
636
637
  /// printRegisteredTargetsForVersion - Print the registered targets
638
  /// appropriately for inclusion in a tool's version output.
639
  static void printRegisteredTargetsForVersion(raw_ostream &OS);
640
641
  /// @name Registry Access
642
  /// @{
643
644
  static iterator_range<iterator> targets();
645
646
  /// lookupTarget - Lookup a target based on a target triple.
647
  ///
648
  /// \param Triple - The triple to use for finding a target.
649
  /// \param Error - On failure, an error string describing why no target was
650
  /// found.
651
  static const Target *lookupTarget(const std::string &Triple,
652
                                    std::string &Error);
653
654
  /// lookupTarget - Lookup a target based on an architecture name
655
  /// and a target triple.  If the architecture name is non-empty,
656
  /// then the lookup is done by architecture.  Otherwise, the target
657
  /// triple is used.
658
  ///
659
  /// \param ArchName - The architecture to use for finding a target.
660
  /// \param TheTriple - The triple to use for finding a target.  The
661
  /// triple is updated with canonical architecture name if a lookup
662
  /// by architecture is done.
663
  /// \param Error - On failure, an error string describing why no target was
664
  /// found.
665
  static const Target *lookupTarget(const std::string &ArchName,
666
                                    Triple &TheTriple, std::string &Error);
667
668
  /// @}
669
  /// @name Target Registration
670
  /// @{
671
672
  /// RegisterTarget - Register the given target. Attempts to register a
673
  /// target which has already been registered will be ignored.
674
  ///
675
  /// Clients are responsible for ensuring that registration doesn't occur
676
  /// while another thread is attempting to access the registry. Typically
677
  /// this is done by initializing all targets at program startup.
678
  ///
679
  /// @param T - The target being registered.
680
  /// @param Name - The target name. This should be a static string.
681
  /// @param ShortDesc - A short target description. This should be a static
682
  /// string.
683
  /// @param BackendName - The name of the backend. This should be a static
684
  /// string that is the same for all targets that share a backend
685
  /// implementation and must match the name used in the 'def X : Target ...' in
686
  /// TableGen.
687
  /// @param ArchMatchFn - The arch match checking function for this target.
688
  /// @param HasJIT - Whether the target supports JIT code
689
  /// generation.
690
  static void RegisterTarget(Target &T, const char *Name, const char *ShortDesc,
691
                             const char *BackendName,
692
                             Target::ArchMatchFnTy ArchMatchFn,
693
                             bool HasJIT = false);
694
695
  /// RegisterMCAsmInfo - Register a MCAsmInfo implementation for the
696
  /// given target.
697
  ///
698
  /// Clients are responsible for ensuring that registration doesn't occur
699
  /// while another thread is attempting to access the registry. Typically
700
  /// this is done by initializing all targets at program startup.
701
  ///
702
  /// @param T - The target being registered.
703
  /// @param Fn - A function to construct a MCAsmInfo for the target.
704
3.56M
  static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn) {
705
3.56M
    T.MCAsmInfoCtorFn = Fn;
706
3.56M
  }
707
708
  /// RegisterMCInstrInfo - Register a MCInstrInfo implementation for the
709
  /// given target.
710
  ///
711
  /// Clients are responsible for ensuring that registration doesn't occur
712
  /// while another thread is attempting to access the registry. Typically
713
  /// this is done by initializing all targets at program startup.
714
  ///
715
  /// @param T - The target being registered.
716
  /// @param Fn - A function to construct a MCInstrInfo for the target.
717
3.56M
  static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn) {
718
3.56M
    T.MCInstrInfoCtorFn = Fn;
719
3.56M
  }
720
721
  /// RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for
722
  /// the given target.
723
  static void RegisterMCInstrAnalysis(Target &T,
724
2.12M
                                      Target::MCInstrAnalysisCtorFnTy Fn) {
725
2.12M
    T.MCInstrAnalysisCtorFn = Fn;
726
2.12M
  }
727
728
  /// RegisterMCRegInfo - Register a MCRegisterInfo implementation for the
729
  /// given target.
730
  ///
731
  /// Clients are responsible for ensuring that registration doesn't occur
732
  /// while another thread is attempting to access the registry. Typically
733
  /// this is done by initializing all targets at program startup.
734
  ///
735
  /// @param T - The target being registered.
736
  /// @param Fn - A function to construct a MCRegisterInfo for the target.
737
3.56M
  static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn) {
738
3.56M
    T.MCRegInfoCtorFn = Fn;
739
3.56M
  }
740
741
  /// RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for
742
  /// the given target.
743
  ///
744
  /// Clients are responsible for ensuring that registration doesn't occur
745
  /// while another thread is attempting to access the registry. Typically
746
  /// this is done by initializing all targets at program startup.
747
  ///
748
  /// @param T - The target being registered.
749
  /// @param Fn - A function to construct a MCSubtargetInfo for the target.
750
  static void RegisterMCSubtargetInfo(Target &T,
751
3.56M
                                      Target::MCSubtargetInfoCtorFnTy Fn) {
752
3.56M
    T.MCSubtargetInfoCtorFn = Fn;
753
3.56M
  }
754
755
  /// RegisterTargetMachine - Register a TargetMachine implementation for the
756
  /// given target.
757
  ///
758
  /// Clients are responsible for ensuring that registration doesn't occur
759
  /// while another thread is attempting to access the registry. Typically
760
  /// this is done by initializing all targets at program startup.
761
  ///
762
  /// @param T - The target being registered.
763
  /// @param Fn - A function to construct a TargetMachine for the target.
764
4.86M
  static void RegisterTargetMachine(Target &T, Target::TargetMachineCtorTy Fn) {
765
4.86M
    T.TargetMachineCtorFn = Fn;
766
4.86M
  }
767
768
  /// RegisterMCAsmBackend - Register a MCAsmBackend implementation for the
769
  /// given target.
770
  ///
771
  /// Clients are responsible for ensuring that registration doesn't occur
772
  /// while another thread is attempting to access the registry. Typically
773
  /// this is done by initializing all targets at program startup.
774
  ///
775
  /// @param T - The target being registered.
776
  /// @param Fn - A function to construct an AsmBackend for the target.
777
3.27M
  static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn) {
778
3.27M
    T.MCAsmBackendCtorFn = Fn;
779
3.27M
  }
780
781
  /// RegisterMCAsmParser - Register a MCTargetAsmParser implementation for
782
  /// the given target.
783
  ///
784
  /// Clients are responsible for ensuring that registration doesn't occur
785
  /// while another thread is attempting to access the registry. Typically
786
  /// this is done by initializing all targets at program startup.
787
  ///
788
  /// @param T - The target being registered.
789
  /// @param Fn - A function to construct an MCTargetAsmParser for the target.
790
3.12M
  static void RegisterMCAsmParser(Target &T, Target::MCAsmParserCtorTy Fn) {
791
3.12M
    T.MCAsmParserCtorFn = Fn;
792
3.12M
  }
793
794
  /// RegisterAsmPrinter - Register an AsmPrinter implementation for the given
795
  /// target.
796
  ///
797
  /// Clients are responsible for ensuring that registration doesn't occur
798
  /// while another thread is attempting to access the registry. Typically
799
  /// this is done by initializing all targets at program startup.
800
  ///
801
  /// @param T - The target being registered.
802
  /// @param Fn - A function to construct an AsmPrinter for the target.
803
2.76M
  static void RegisterAsmPrinter(Target &T, Target::AsmPrinterCtorTy Fn) {
804
2.76M
    T.AsmPrinterCtorFn = Fn;
805
2.76M
  }
806
807
  /// RegisterMCDisassembler - Register a MCDisassembler implementation for
808
  /// the given target.
809
  ///
810
  /// Clients are responsible for ensuring that registration doesn't occur
811
  /// while another thread is attempting to access the registry. Typically
812
  /// this is done by initializing all targets at program startup.
813
  ///
814
  /// @param T - The target being registered.
815
  /// @param Fn - A function to construct an MCDisassembler for the target.
816
  static void RegisterMCDisassembler(Target &T,
817
                                     Target::MCDisassemblerCtorTy Fn) {
818
    T.MCDisassemblerCtorFn = Fn;
819
  }
820
821
  /// RegisterMCInstPrinter - Register a MCInstPrinter implementation for the
822
  /// given target.
823
  ///
824
  /// Clients are responsible for ensuring that registration doesn't occur
825
  /// while another thread is attempting to access the registry. Typically
826
  /// this is done by initializing all targets at program startup.
827
  ///
828
  /// @param T - The target being registered.
829
  /// @param Fn - A function to construct an MCInstPrinter for the target.
830
3.56M
  static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn) {
831
3.56M
    T.MCInstPrinterCtorFn = Fn;
832
3.56M
  }
833
834
  /// RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the
835
  /// given target.
836
  ///
837
  /// Clients are responsible for ensuring that registration doesn't occur
838
  /// while another thread is attempting to access the registry. Typically
839
  /// this is done by initializing all targets at program startup.
840
  ///
841
  /// @param T - The target being registered.
842
  /// @param Fn - A function to construct an MCCodeEmitter for the target.
843
3.27M
  static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn) {
844
3.27M
    T.MCCodeEmitterCtorFn = Fn;
845
3.27M
  }
846
847
1.06M
  static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn) {
848
1.06M
    T.COFFStreamerCtorFn = Fn;
849
1.06M
  }
850
851
867k
  static void RegisterMachOStreamer(Target &T, Target::MachOStreamerCtorTy Fn) {
852
867k
    T.MachOStreamerCtorFn = Fn;
853
867k
  }
854
855
1.92M
  static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn) {
856
1.92M
    T.ELFStreamerCtorFn = Fn;
857
1.92M
  }
858
859
0
  static void RegisterWasmStreamer(Target &T, Target::WasmStreamerCtorTy Fn) {
860
0
    T.WasmStreamerCtorFn = Fn;
861
0
  }
862
863
  static void RegisterNullTargetStreamer(Target &T,
864
964k
                                         Target::NullTargetStreamerCtorTy Fn) {
865
964k
    T.NullTargetStreamerCtorFn = Fn;
866
964k
  }
867
868
  static void RegisterAsmTargetStreamer(Target &T,
869
2.89M
                                        Target::AsmTargetStreamerCtorTy Fn) {
870
2.89M
    T.AsmTargetStreamerCtorFn = Fn;
871
2.89M
  }
872
873
  static void
874
  RegisterObjectTargetStreamer(Target &T,
875
2.79M
                               Target::ObjectTargetStreamerCtorTy Fn) {
876
2.79M
    T.ObjectTargetStreamerCtorFn = Fn;
877
2.79M
  }
878
879
  /// RegisterMCRelocationInfo - Register an MCRelocationInfo
880
  /// implementation for the given target.
881
  ///
882
  /// Clients are responsible for ensuring that registration doesn't occur
883
  /// while another thread is attempting to access the registry. Typically
884
  /// this is done by initializing all targets at program startup.
885
  ///
886
  /// @param T - The target being registered.
887
  /// @param Fn - A function to construct an MCRelocationInfo for the target.
888
  static void RegisterMCRelocationInfo(Target &T,
889
675k
                                       Target::MCRelocationInfoCtorTy Fn) {
890
675k
    T.MCRelocationInfoCtorFn = Fn;
891
675k
  }
892
893
  /// RegisterMCSymbolizer - Register an MCSymbolizer
894
  /// implementation for the given target.
895
  ///
896
  /// Clients are responsible for ensuring that registration doesn't occur
897
  /// while another thread is attempting to access the registry. Typically
898
  /// this is done by initializing all targets at program startup.
899
  ///
900
  /// @param T - The target being registered.
901
  /// @param Fn - A function to construct an MCSymbolizer for the target.
902
  static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn) {
903
    T.MCSymbolizerCtorFn = Fn;
904
  }
905
906
  /// @}
907
};
908
909
//===--------------------------------------------------------------------===//
910
911
/// RegisterTarget - Helper template for registering a target, for use in the
912
/// target's initialization function. Usage:
913
///
914
///
915
/// Target &getTheFooTarget() { // The global target instance.
916
///   static Target TheFooTarget;
917
///   return TheFooTarget;
918
/// }
919
/// extern "C" void LLVMInitializeFooTargetInfo() {
920
///   RegisterTarget<Triple::foo> X(getTheFooTarget(), "foo", "Foo
921
///   description", "Foo" /* Backend Name */);
922
/// }
923
template <Triple::ArchType TargetArchType = Triple::UnknownArch,
924
          bool HasJIT = false>
925
struct RegisterTarget {
926
  RegisterTarget(Target &T, const char *Name, const char *Desc,
927
5.35M
                 const char *BackendName) {
928
5.35M
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
5.35M
                                   HasJIT);
930
5.35M
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)3, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)4, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)5, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)19, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)20, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)1, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)2, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)29, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)30, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)8, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)9, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)10, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)46, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)11, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)12, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)13, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)14, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)15, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)34, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)35, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)16, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)17, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)18, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)21, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)22, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)23, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)24, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)25, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)26, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)47, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)48, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)31, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)32, true>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)33, false>::RegisterTarget(llvm::Target&, char const*, char const*, char const*)
Line
Count
Source
927
157k
                 const char *BackendName) {
928
157k
    TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
929
157k
                                   HasJIT);
930
157k
  }
931
932
2.08M
  static bool getArchMatch(Triple::ArchType Arch) {
933
2.08M
    return Arch == TargetArchType;
934
2.08M
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)3, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)4, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)5, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)19, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)20, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)1, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)2, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)29, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)30, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)8, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)9, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)10, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)46, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)11, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)12, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)13, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)14, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)15, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)34, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)35, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)16, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)17, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)18, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)21, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)22, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)23, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)24, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)25, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)26, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)47, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)48, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)31, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.7k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.7k
    return Arch == TargetArchType;
934
61.7k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)32, true>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.7k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.7k
    return Arch == TargetArchType;
934
61.7k
  }
llvm::RegisterTarget<(llvm::Triple::ArchType)33, false>::getArchMatch(llvm::Triple::ArchType)
Line
Count
Source
932
61.3k
  static bool getArchMatch(Triple::ArchType Arch) {
933
61.3k
    return Arch == TargetArchType;
934
61.3k
  }
935
};
936
937
/// RegisterMCAsmInfo - Helper template for registering a target assembly info
938
/// implementation.  This invokes the static "Create" method on the class to
939
/// actually do the construction.  Usage:
940
///
941
/// extern "C" void LLVMInitializeFooTarget() {
942
///   extern Target TheFooTarget;
943
///   RegisterMCAsmInfo<FooMCAsmInfo> X(TheFooTarget);
944
/// }
945
template <class MCAsmInfoImpl> struct RegisterMCAsmInfo {
946
867k
  RegisterMCAsmInfo(Target &T) {
947
867k
    TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
948
867k
  }
llvm::RegisterMCAsmInfo<llvm::AMDGPUMCAsmInfo>::RegisterMCAsmInfo(llvm::Target&)
Line
Count
Source
946
192k
  RegisterMCAsmInfo(Target &T) {
947
192k
    TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
948
192k
  }
llvm::RegisterMCAsmInfo<llvm::BPFMCAsmInfo>::RegisterMCAsmInfo(llvm::Target&)
Line
Count
Source
946
289k
  RegisterMCAsmInfo(Target &T) {
947
289k
    TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
948
289k
  }
llvm::RegisterMCAsmInfo<llvm::LanaiMCAsmInfo>::RegisterMCAsmInfo(llvm::Target&)
Line
Count
Source
946
96.4k
  RegisterMCAsmInfo(Target &T) {
947
96.4k
    TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
948
96.4k
  }
llvm::RegisterMCAsmInfo<llvm::MSP430MCAsmInfo>::RegisterMCAsmInfo(llvm::Target&)
Line
Count
Source
946
96.4k
  RegisterMCAsmInfo(Target &T) {
947
96.4k
    TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
948
96.4k
  }
llvm::RegisterMCAsmInfo<llvm::NVPTXMCAsmInfo>::RegisterMCAsmInfo(llvm::Target&)
Line
Count
Source
946
192k
  RegisterMCAsmInfo(Target &T) {
947
192k
    TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
948
192k
  }
949
950
private:
951
  static MCAsmInfo *Allocator(const MCRegisterInfo & /*MRI*/,
952
5.41k
                              const Triple &TT) {
953
5.41k
    return new MCAsmInfoImpl(TT);
954
5.41k
  }
llvm::RegisterMCAsmInfo<llvm::AMDGPUMCAsmInfo>::Allocator(llvm::MCRegisterInfo const&, llvm::Triple const&)
Line
Count
Source
952
4.60k
                              const Triple &TT) {
953
4.60k
    return new MCAsmInfoImpl(TT);
954
4.60k
  }
llvm::RegisterMCAsmInfo<llvm::BPFMCAsmInfo>::Allocator(llvm::MCRegisterInfo const&, llvm::Triple const&)
Line
Count
Source
952
231
                              const Triple &TT) {
953
231
    return new MCAsmInfoImpl(TT);
954
231
  }
llvm::RegisterMCAsmInfo<llvm::LanaiMCAsmInfo>::Allocator(llvm::MCRegisterInfo const&, llvm::Triple const&)
Line
Count
Source
952
33
                              const Triple &TT) {
953
33
    return new MCAsmInfoImpl(TT);
954
33
  }
llvm::RegisterMCAsmInfo<llvm::MSP430MCAsmInfo>::Allocator(llvm::MCRegisterInfo const&, llvm::Triple const&)
Line
Count
Source
952
95
                              const Triple &TT) {
953
95
    return new MCAsmInfoImpl(TT);
954
95
  }
llvm::RegisterMCAsmInfo<llvm::NVPTXMCAsmInfo>::Allocator(llvm::MCRegisterInfo const&, llvm::Triple const&)
Line
Count
Source
952
455
                              const Triple &TT) {
953
455
    return new MCAsmInfoImpl(TT);
954
455
  }
955
};
956
957
/// RegisterMCAsmInfoFn - Helper template for registering a target assembly info
958
/// implementation.  This invokes the specified function to do the
959
/// construction.  Usage:
960
///
961
/// extern "C" void LLVMInitializeFooTarget() {
962
///   extern Target TheFooTarget;
963
///   RegisterMCAsmInfoFn X(TheFooTarget, TheFunction);
964
/// }
965
struct RegisterMCAsmInfoFn {
966
2.41M
  RegisterMCAsmInfoFn(Target &T, Target::MCAsmInfoCtorFnTy Fn) {
967
2.41M
    TargetRegistry::RegisterMCAsmInfo(T, Fn);
968
2.41M
  }
969
};
970
971
/// RegisterMCInstrInfo - Helper template for registering a target instruction
972
/// info implementation.  This invokes the static "Create" method on the class
973
/// to actually do the construction.  Usage:
974
///
975
/// extern "C" void LLVMInitializeFooTarget() {
976
///   extern Target TheFooTarget;
977
///   RegisterMCInstrInfo<FooMCInstrInfo> X(TheFooTarget);
978
/// }
979
template <class MCInstrInfoImpl> struct RegisterMCInstrInfo {
980
  RegisterMCInstrInfo(Target &T) {
981
    TargetRegistry::RegisterMCInstrInfo(T, &Allocator);
982
  }
983
984
private:
985
  static MCInstrInfo *Allocator() { return new MCInstrInfoImpl(); }
986
};
987
988
/// RegisterMCInstrInfoFn - Helper template for registering a target
989
/// instruction info implementation.  This invokes the specified function to
990
/// do the construction.  Usage:
991
///
992
/// extern "C" void LLVMInitializeFooTarget() {
993
///   extern Target TheFooTarget;
994
///   RegisterMCInstrInfoFn X(TheFooTarget, TheFunction);
995
/// }
996
struct RegisterMCInstrInfoFn {
997
0
  RegisterMCInstrInfoFn(Target &T, Target::MCInstrInfoCtorFnTy Fn) {
998
0
    TargetRegistry::RegisterMCInstrInfo(T, Fn);
999
0
  }
1000
};
1001
1002
/// RegisterMCInstrAnalysis - Helper template for registering a target
1003
/// instruction analyzer implementation.  This invokes the static "Create"
1004
/// method on the class to actually do the construction.  Usage:
1005
///
1006
/// extern "C" void LLVMInitializeFooTarget() {
1007
///   extern Target TheFooTarget;
1008
///   RegisterMCInstrAnalysis<FooMCInstrAnalysis> X(TheFooTarget);
1009
/// }
1010
template <class MCInstrAnalysisImpl> struct RegisterMCInstrAnalysis {
1011
  RegisterMCInstrAnalysis(Target &T) {
1012
    TargetRegistry::RegisterMCInstrAnalysis(T, &Allocator);
1013
  }
1014
1015
private:
1016
  static MCInstrAnalysis *Allocator(const MCInstrInfo *Info) {
1017
    return new MCInstrAnalysisImpl(Info);
1018
  }
1019
};
1020
1021
/// RegisterMCInstrAnalysisFn - Helper template for registering a target
1022
/// instruction analyzer implementation.  This invokes the specified function
1023
/// to do the construction.  Usage:
1024
///
1025
/// extern "C" void LLVMInitializeFooTarget() {
1026
///   extern Target TheFooTarget;
1027
///   RegisterMCInstrAnalysisFn X(TheFooTarget, TheFunction);
1028
/// }
1029
struct RegisterMCInstrAnalysisFn {
1030
0
  RegisterMCInstrAnalysisFn(Target &T, Target::MCInstrAnalysisCtorFnTy Fn) {
1031
0
    TargetRegistry::RegisterMCInstrAnalysis(T, Fn);
1032
0
  }
1033
};
1034
1035
/// RegisterMCRegInfo - Helper template for registering a target register info
1036
/// implementation.  This invokes the static "Create" method on the class to
1037
/// actually do the construction.  Usage:
1038
///
1039
/// extern "C" void LLVMInitializeFooTarget() {
1040
///   extern Target TheFooTarget;
1041
///   RegisterMCRegInfo<FooMCRegInfo> X(TheFooTarget);
1042
/// }
1043
template <class MCRegisterInfoImpl> struct RegisterMCRegInfo {
1044
  RegisterMCRegInfo(Target &T) {
1045
    TargetRegistry::RegisterMCRegInfo(T, &Allocator);
1046
  }
1047
1048
private:
1049
  static MCRegisterInfo *Allocator(const Triple & /*TT*/) {
1050
    return new MCRegisterInfoImpl();
1051
  }
1052
};
1053
1054
/// RegisterMCRegInfoFn - Helper template for registering a target register
1055
/// info implementation.  This invokes the specified function to do the
1056
/// construction.  Usage:
1057
///
1058
/// extern "C" void LLVMInitializeFooTarget() {
1059
///   extern Target TheFooTarget;
1060
///   RegisterMCRegInfoFn X(TheFooTarget, TheFunction);
1061
/// }
1062
struct RegisterMCRegInfoFn {
1063
0
  RegisterMCRegInfoFn(Target &T, Target::MCRegInfoCtorFnTy Fn) {
1064
0
    TargetRegistry::RegisterMCRegInfo(T, Fn);
1065
0
  }
1066
};
1067
1068
/// RegisterMCSubtargetInfo - Helper template for registering a target
1069
/// subtarget info implementation.  This invokes the static "Create" method
1070
/// on the class to actually do the construction.  Usage:
1071
///
1072
/// extern "C" void LLVMInitializeFooTarget() {
1073
///   extern Target TheFooTarget;
1074
///   RegisterMCSubtargetInfo<FooMCSubtargetInfo> X(TheFooTarget);
1075
/// }
1076
template <class MCSubtargetInfoImpl> struct RegisterMCSubtargetInfo {
1077
  RegisterMCSubtargetInfo(Target &T) {
1078
    TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator);
1079
  }
1080
1081
private:
1082
  static MCSubtargetInfo *Allocator(const Triple & /*TT*/, StringRef /*CPU*/,
1083
                                    StringRef /*FS*/) {
1084
    return new MCSubtargetInfoImpl();
1085
  }
1086
};
1087
1088
/// RegisterMCSubtargetInfoFn - Helper template for registering a target
1089
/// subtarget info implementation.  This invokes the specified function to
1090
/// do the construction.  Usage:
1091
///
1092
/// extern "C" void LLVMInitializeFooTarget() {
1093
///   extern Target TheFooTarget;
1094
///   RegisterMCSubtargetInfoFn X(TheFooTarget, TheFunction);
1095
/// }
1096
struct RegisterMCSubtargetInfoFn {
1097
0
  RegisterMCSubtargetInfoFn(Target &T, Target::MCSubtargetInfoCtorFnTy Fn) {
1098
0
    TargetRegistry::RegisterMCSubtargetInfo(T, Fn);
1099
0
  }
1100
};
1101
1102
/// RegisterTargetMachine - Helper template for registering a target machine
1103
/// implementation, for use in the target machine initialization
1104
/// function. Usage:
1105
///
1106
/// extern "C" void LLVMInitializeFooTarget() {
1107
///   extern Target TheFooTarget;
1108
///   RegisterTargetMachine<FooTargetMachine> X(TheFooTarget);
1109
/// }
1110
template <class TargetMachineImpl> struct RegisterTargetMachine {
1111
4.86M
  RegisterTargetMachine(Target &T) {
1112
4.86M
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
4.86M
  }
llvm::RegisterTargetMachine<llvm::AArch64leTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
278k
  RegisterTargetMachine(Target &T) {
1112
278k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
278k
  }
llvm::RegisterTargetMachine<llvm::AArch64beTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
139k
  RegisterTargetMachine(Target &T) {
1112
139k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
139k
  }
llvm::RegisterTargetMachine<llvm::R600TargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
139k
  RegisterTargetMachine(Target &T) {
1112
139k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
139k
  }
llvm::RegisterTargetMachine<llvm::GCNTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
139k
  RegisterTargetMachine(Target &T) {
1112
139k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
139k
  }
llvm::RegisterTargetMachine<llvm::ARMLETargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
278k
  RegisterTargetMachine(Target &T) {
1112
278k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
278k
  }
llvm::RegisterTargetMachine<llvm::ARMBETargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
278k
  RegisterTargetMachine(Target &T) {
1112
278k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
278k
  }
llvm::RegisterTargetMachine<llvm::BPFTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
417k
  RegisterTargetMachine(Target &T) {
1112
417k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
417k
  }
llvm::RegisterTargetMachine<llvm::HexagonTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
139k
  RegisterTargetMachine(Target &T) {
1112
139k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
139k
  }
llvm::RegisterTargetMachine<llvm::LanaiTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
139k
  RegisterTargetMachine(Target &T) {
1112
139k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
139k
  }
llvm::RegisterTargetMachine<llvm::MipsebTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
278k
  RegisterTargetMachine(Target &T) {
1112
278k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
278k
  }
llvm::RegisterTargetMachine<llvm::MipselTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
278k
  RegisterTargetMachine(Target &T) {
1112
278k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
278k
  }
llvm::RegisterTargetMachine<llvm::MSP430TargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
139k
  RegisterTargetMachine(Target &T) {
1112
139k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
139k
  }
llvm::RegisterTargetMachine<llvm::NVPTXTargetMachine32>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
139k
  RegisterTargetMachine(Target &T) {
1112
139k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
139k
  }
llvm::RegisterTargetMachine<llvm::NVPTXTargetMachine64>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
139k
  RegisterTargetMachine(Target &T) {
1112
139k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
139k
  }
llvm::RegisterTargetMachine<llvm::PPCTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
417k
  RegisterTargetMachine(Target &T) {
1112
417k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
417k
  }
llvm::RegisterTargetMachine<llvm::RISCVTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
278k
  RegisterTargetMachine(Target &T) {
1112
278k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
278k
  }
llvm::RegisterTargetMachine<llvm::SparcV8TargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
139k
  RegisterTargetMachine(Target &T) {
1112
139k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
139k
  }
llvm::RegisterTargetMachine<llvm::SparcV9TargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
139k
  RegisterTargetMachine(Target &T) {
1112
139k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
139k
  }
llvm::RegisterTargetMachine<llvm::SparcelTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
139k
  RegisterTargetMachine(Target &T) {
1112
139k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
139k
  }
llvm::RegisterTargetMachine<llvm::SystemZTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
139k
  RegisterTargetMachine(Target &T) {
1112
139k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
139k
  }
llvm::RegisterTargetMachine<llvm::WebAssemblyTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
278k
  RegisterTargetMachine(Target &T) {
1112
278k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
278k
  }
llvm::RegisterTargetMachine<llvm::X86TargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
278k
  RegisterTargetMachine(Target &T) {
1112
278k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
278k
  }
llvm::RegisterTargetMachine<llvm::XCoreTargetMachine>::RegisterTargetMachine(llvm::Target&)
Line
Count
Source
1111
139k
  RegisterTargetMachine(Target &T) {
1112
139k
    TargetRegistry::RegisterTargetMachine(T, &Allocator);
1113
139k
  }
1114
1115
private:
1116
  static TargetMachine *
1117
  Allocator(const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
1118
            const TargetOptions &Options, Optional<Reloc::Model> RM,
1119
52.5k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
52.5k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
52.5k
  }
llvm::RegisterTargetMachine<llvm::AArch64leTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
9.60k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
9.60k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
9.60k
  }
llvm::RegisterTargetMachine<llvm::AArch64beTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
36
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
36
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
36
  }
llvm::RegisterTargetMachine<llvm::R600TargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
295
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
295
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
295
  }
llvm::RegisterTargetMachine<llvm::GCNTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
3.63k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
3.63k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
3.63k
  }
llvm::RegisterTargetMachine<llvm::ARMLETargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
5.94k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
5.94k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
5.94k
  }
llvm::RegisterTargetMachine<llvm::ARMBETargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
57
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
57
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
57
  }
llvm::RegisterTargetMachine<llvm::BPFTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
212
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
212
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
212
  }
llvm::RegisterTargetMachine<llvm::HexagonTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
1.02k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
1.02k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
1.02k
  }
llvm::RegisterTargetMachine<llvm::LanaiTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
29
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
29
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
29
  }
llvm::RegisterTargetMachine<llvm::MipsebTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
1.17k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
1.17k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
1.17k
  }
llvm::RegisterTargetMachine<llvm::MipselTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
1.20k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
1.20k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
1.20k
  }
llvm::RegisterTargetMachine<llvm::MSP430TargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
77
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
77
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
77
  }
llvm::RegisterTargetMachine<llvm::NVPTXTargetMachine32>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
240
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
240
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
240
  }
llvm::RegisterTargetMachine<llvm::NVPTXTargetMachine64>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
215
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
215
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
215
  }
llvm::RegisterTargetMachine<llvm::PPCTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
3.59k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
3.59k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
3.59k
  }
llvm::RegisterTargetMachine<llvm::RISCVTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
374
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
374
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
374
  }
llvm::RegisterTargetMachine<llvm::SparcV8TargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
151
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
151
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
151
  }
llvm::RegisterTargetMachine<llvm::SparcV9TargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
74
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
74
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
74
  }
llvm::RegisterTargetMachine<llvm::SparcelTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
5
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
5
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
5
  }
llvm::RegisterTargetMachine<llvm::SystemZTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
1.10k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
1.10k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
1.10k
  }
llvm::RegisterTargetMachine<llvm::WebAssemblyTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
484
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
484
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
484
  }
llvm::RegisterTargetMachine<llvm::X86TargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
22.9k
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
22.9k
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
22.9k
  }
llvm::RegisterTargetMachine<llvm::XCoreTargetMachine>::Allocator(llvm::Target const&, llvm::Triple const&, llvm::StringRef, llvm::StringRef, llvm::TargetOptions const&, llvm::Optional<llvm::Reloc::Model>, llvm::Optional<llvm::CodeModel::Model>, llvm::CodeGenOpt::Level, bool)
Line
Count
Source
1119
84
            Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) {
1120
84
    return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT);
1121
84
  }
1122
};
1123
1124
/// RegisterMCAsmBackend - Helper template for registering a target specific
1125
/// assembler backend. Usage:
1126
///
1127
/// extern "C" void LLVMInitializeFooMCAsmBackend() {
1128
///   extern Target TheFooTarget;
1129
///   RegisterMCAsmBackend<FooAsmLexer> X(TheFooTarget);
1130
/// }
1131
template <class MCAsmBackendImpl> struct RegisterMCAsmBackend {
1132
  RegisterMCAsmBackend(Target &T) {
1133
    TargetRegistry::RegisterMCAsmBackend(T, &Allocator);
1134
  }
1135
1136
private:
1137
  static MCAsmBackend *Allocator(const Target &T, const MCSubtargetInfo &STI,
1138
                                 const MCRegisterInfo &MRI,
1139
                                 const MCTargetOptions &Options) {
1140
    return new MCAsmBackendImpl(T, STI, MRI);
1141
  }
1142
};
1143
1144
/// RegisterMCAsmParser - Helper template for registering a target specific
1145
/// assembly parser, for use in the target machine initialization
1146
/// function. Usage:
1147
///
1148
/// extern "C" void LLVMInitializeFooMCAsmParser() {
1149
///   extern Target TheFooTarget;
1150
///   RegisterMCAsmParser<FooAsmParser> X(TheFooTarget);
1151
/// }
1152
template <class MCAsmParserImpl> struct RegisterMCAsmParser {
1153
3.12M
  RegisterMCAsmParser(Target &T) {
1154
3.12M
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1155
3.12M
  }
AArch64AsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::AArch64AsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1153
458k
  RegisterMCAsmParser(Target &T) {
1154
458k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1155
458k
  }
AMDGPUAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::AMDGPUAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1153
183k
  RegisterMCAsmParser(Target &T) {
1154
183k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1155
183k
  }
ARMAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::ARMAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1153
367k
  RegisterMCAsmParser(Target &T) {
1154
367k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1155
367k
  }
BPFAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::BPFAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1153
275k
  RegisterMCAsmParser(Target &T) {
1154
275k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1155
275k
  }
HexagonAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::HexagonAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1153
91.7k
  RegisterMCAsmParser(Target &T) {
1154
91.7k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1155
91.7k
  }
LanaiAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::LanaiAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1153
91.7k
  RegisterMCAsmParser(Target &T) {
1154
91.7k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1155
91.7k
  }
MipsAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::MipsAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1153
367k
  RegisterMCAsmParser(Target &T) {
1154
367k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1155
367k
  }
MSP430AsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::MSP430AsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1153
91.7k
  RegisterMCAsmParser(Target &T) {
1154
91.7k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1155
91.7k
  }
PPCAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::PPCAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1153
275k
  RegisterMCAsmParser(Target &T) {
1154
275k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1155
275k
  }
RISCVAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::RISCVAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1153
183k
  RegisterMCAsmParser(Target &T) {
1154
183k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1155
183k
  }
SparcAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::SparcAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1153
275k
  RegisterMCAsmParser(Target &T) {
1154
275k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1155
275k
  }
SystemZAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::SystemZAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1153
91.7k
  RegisterMCAsmParser(Target &T) {
1154
91.7k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1155
91.7k
  }
WebAssemblyAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::WebAssemblyAsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1153
183k
  RegisterMCAsmParser(Target &T) {
1154
183k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1155
183k
  }
X86AsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::X86AsmParser>::RegisterMCAsmParser(llvm::Target&)
Line
Count
Source
1153
184k
  RegisterMCAsmParser(Target &T) {
1154
184k
    TargetRegistry::RegisterMCAsmParser(T, &Allocator);
1155
184k
  }
1156
1157
private:
1158
  static MCTargetAsmParser *Allocator(const MCSubtargetInfo &STI,
1159
                                      MCAsmParser &P, const MCInstrInfo &MII,
1160
18.4k
                                      const MCTargetOptions &Options) {
1161
18.4k
    return new MCAsmParserImpl(STI, P, MII, Options);
1162
18.4k
  }
AArch64AsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::AArch64AsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1160
3.49k
                                      const MCTargetOptions &Options) {
1161
3.49k
    return new MCAsmParserImpl(STI, P, MII, Options);
1162
3.49k
  }
AMDGPUAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::AMDGPUAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1160
521
                                      const MCTargetOptions &Options) {
1161
521
    return new MCAsmParserImpl(STI, P, MII, Options);
1162
521
  }
ARMAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::ARMAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1160
2.40k
                                      const MCTargetOptions &Options) {
1161
2.40k
    return new MCAsmParserImpl(STI, P, MII, Options);
1162
2.40k
  }
BPFAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::BPFAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1160
3
                                      const MCTargetOptions &Options) {
1161
3
    return new MCAsmParserImpl(STI, P, MII, Options);
1162
3
  }
HexagonAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::HexagonAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1160
120
                                      const MCTargetOptions &Options) {
1161
120
    return new MCAsmParserImpl(STI, P, MII, Options);
1162
120
  }
LanaiAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::LanaiAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1160
7
                                      const MCTargetOptions &Options) {
1161
7
    return new MCAsmParserImpl(STI, P, MII, Options);
1162
7
  }
MipsAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::MipsAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1160
1.46k
                                      const MCTargetOptions &Options) {
1161
1.46k
    return new MCAsmParserImpl(STI, P, MII, Options);
1162
1.46k
  }
MSP430AsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::MSP430AsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1160
23
                                      const MCTargetOptions &Options) {
1161
23
    return new MCAsmParserImpl(STI, P, MII, Options);
1162
23
  }
PPCAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::PPCAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1160
506
                                      const MCTargetOptions &Options) {
1161
506
    return new MCAsmParserImpl(STI, P, MII, Options);
1162
506
  }
RISCVAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::RISCVAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1160
417
                                      const MCTargetOptions &Options) {
1161
417
    return new MCAsmParserImpl(STI, P, MII, Options);
1162
417
  }
SparcAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::SparcAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1160
109
                                      const MCTargetOptions &Options) {
1161
109
    return new MCAsmParserImpl(STI, P, MII, Options);
1162
109
  }
SystemZAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::SystemZAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1160
47
                                      const MCTargetOptions &Options) {
1161
47
    return new MCAsmParserImpl(STI, P, MII, Options);
1162
47
  }
WebAssemblyAsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::WebAssemblyAsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1160
17
                                      const MCTargetOptions &Options) {
1161
17
    return new MCAsmParserImpl(STI, P, MII, Options);
1162
17
  }
X86AsmParser.cpp:llvm::RegisterMCAsmParser<(anonymous namespace)::X86AsmParser>::Allocator(llvm::MCSubtargetInfo const&, llvm::MCAsmParser&, llvm::MCInstrInfo const&, llvm::MCTargetOptions const&)
Line
Count
Source
1160
9.30k
                                      const MCTargetOptions &Options) {
1161
9.30k
    return new MCAsmParserImpl(STI, P, MII, Options);
1162
9.30k
  }
1163
};
1164
1165
/// RegisterAsmPrinter - Helper template for registering a target specific
1166
/// assembly printer, for use in the target machine initialization
1167
/// function. Usage:
1168
///
1169
/// extern "C" void LLVMInitializeFooAsmPrinter() {
1170
///   extern Target TheFooTarget;
1171
///   RegisterAsmPrinter<FooAsmPrinter> X(TheFooTarget);
1172
/// }
1173
template <class AsmPrinterImpl> struct RegisterAsmPrinter {
1174
2.36M
  RegisterAsmPrinter(Target &T) {
1175
2.36M
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1176
2.36M
  }
AArch64AsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::AArch64AsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1174
236k
  RegisterAsmPrinter(Target &T) {
1175
236k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1176
236k
  }
llvm::RegisterAsmPrinter<llvm::ARMAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1174
315k
  RegisterAsmPrinter(Target &T) {
1175
315k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1176
315k
  }
BPFAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::BPFAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1174
236k
  RegisterAsmPrinter(Target &T) {
1175
236k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1176
236k
  }
llvm::RegisterAsmPrinter<llvm::HexagonAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1174
78.9k
  RegisterAsmPrinter(Target &T) {
1175
78.9k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1176
78.9k
  }
LanaiAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::LanaiAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1174
78.9k
  RegisterAsmPrinter(Target &T) {
1175
78.9k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1176
78.9k
  }
llvm::RegisterAsmPrinter<llvm::MipsAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1174
315k
  RegisterAsmPrinter(Target &T) {
1175
315k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1176
315k
  }
MSP430AsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::MSP430AsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1174
78.9k
  RegisterAsmPrinter(Target &T) {
1175
78.9k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1176
78.9k
  }
llvm::RegisterAsmPrinter<llvm::NVPTXAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1174
157k
  RegisterAsmPrinter(Target &T) {
1175
157k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1176
157k
  }
RISCVAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::RISCVAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1174
157k
  RegisterAsmPrinter(Target &T) {
1175
157k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1176
157k
  }
SparcAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::SparcAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1174
236k
  RegisterAsmPrinter(Target &T) {
1175
236k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1176
236k
  }
llvm::RegisterAsmPrinter<llvm::SystemZAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1174
78.9k
  RegisterAsmPrinter(Target &T) {
1175
78.9k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1176
78.9k
  }
llvm::RegisterAsmPrinter<llvm::WebAssemblyAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1174
157k
  RegisterAsmPrinter(Target &T) {
1175
157k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1176
157k
  }
llvm::RegisterAsmPrinter<llvm::X86AsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1174
158k
  RegisterAsmPrinter(Target &T) {
1175
158k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1176
158k
  }
XCoreAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::XCoreAsmPrinter>::RegisterAsmPrinter(llvm::Target&)
Line
Count
Source
1174
78.9k
  RegisterAsmPrinter(Target &T) {
1175
78.9k
    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
1176
78.9k
  }
1177
1178
private:
1179
  static AsmPrinter *Allocator(TargetMachine &TM,
1180
31.7k
                               std::unique_ptr<MCStreamer> &&Streamer) {
1181
31.7k
    return new AsmPrinterImpl(TM, std::move(Streamer));
1182
31.7k
  }
AArch64AsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::AArch64AsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1180
8.72k
                               std::unique_ptr<MCStreamer> &&Streamer) {
1181
8.72k
    return new AsmPrinterImpl(TM, std::move(Streamer));
1182
8.72k
  }
llvm::RegisterAsmPrinter<llvm::ARMAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1180
5.17k
                               std::unique_ptr<MCStreamer> &&Streamer) {
1181
5.17k
    return new AsmPrinterImpl(TM, std::move(Streamer));
1182
5.17k
  }
BPFAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::BPFAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1180
206
                               std::unique_ptr<MCStreamer> &&Streamer) {
1181
206
    return new AsmPrinterImpl(TM, std::move(Streamer));
1182
206
  }
llvm::RegisterAsmPrinter<llvm::HexagonAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1180
918
                               std::unique_ptr<MCStreamer> &&Streamer) {
1181
918
    return new AsmPrinterImpl(TM, std::move(Streamer));
1182
918
  }
LanaiAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::LanaiAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1180
22
                               std::unique_ptr<MCStreamer> &&Streamer) {
1181
22
    return new AsmPrinterImpl(TM, std::move(Streamer));
1182
22
  }
llvm::RegisterAsmPrinter<llvm::MipsAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1180
2.01k
                               std::unique_ptr<MCStreamer> &&Streamer) {
1181
2.01k
    return new AsmPrinterImpl(TM, std::move(Streamer));
1182
2.01k
  }
MSP430AsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::MSP430AsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1180
72
                               std::unique_ptr<MCStreamer> &&Streamer) {
1181
72
    return new AsmPrinterImpl(TM, std::move(Streamer));
1182
72
  }
llvm::RegisterAsmPrinter<llvm::NVPTXAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1180
258
                               std::unique_ptr<MCStreamer> &&Streamer) {
1181
258
    return new AsmPrinterImpl(TM, std::move(Streamer));
1182
258
  }
RISCVAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::RISCVAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1180
329
                               std::unique_ptr<MCStreamer> &&Streamer) {
1181
329
    return new AsmPrinterImpl(TM, std::move(Streamer));
1182
329
  }
SparcAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::SparcAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1180
198
                               std::unique_ptr<MCStreamer> &&Streamer) {
1181
198
    return new AsmPrinterImpl(TM, std::move(Streamer));
1182
198
  }
llvm::RegisterAsmPrinter<llvm::SystemZAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1180
1.00k
                               std::unique_ptr<MCStreamer> &&Streamer) {
1181
1.00k
    return new AsmPrinterImpl(TM, std::move(Streamer));
1182
1.00k
  }
llvm::RegisterAsmPrinter<llvm::WebAssemblyAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1180
425
                               std::unique_ptr<MCStreamer> &&Streamer) {
1181
425
    return new AsmPrinterImpl(TM, std::move(Streamer));
1182
425
  }
llvm::RegisterAsmPrinter<llvm::X86AsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1180
12.3k
                               std::unique_ptr<MCStreamer> &&Streamer) {
1181
12.3k
    return new AsmPrinterImpl(TM, std::move(Streamer));
1182
12.3k
  }
XCoreAsmPrinter.cpp:llvm::RegisterAsmPrinter<(anonymous namespace)::XCoreAsmPrinter>::Allocator(llvm::TargetMachine&, std::__1::unique_ptr<llvm::MCStreamer, std::__1::default_delete<llvm::MCStreamer> >&&)
Line
Count
Source
1180
70
                               std::unique_ptr<MCStreamer> &&Streamer) {
1181
70
    return new AsmPrinterImpl(TM, std::move(Streamer));
1182
70
  }
1183
};
1184
1185
/// RegisterMCCodeEmitter - Helper template for registering a target specific
1186
/// machine code emitter, for use in the target initialization
1187
/// function. Usage:
1188
///
1189
/// extern "C" void LLVMInitializeFooMCCodeEmitter() {
1190
///   extern Target TheFooTarget;
1191
///   RegisterMCCodeEmitter<FooCodeEmitter> X(TheFooTarget);
1192
/// }
1193
template <class MCCodeEmitterImpl> struct RegisterMCCodeEmitter {
1194
  RegisterMCCodeEmitter(Target &T) {
1195
    TargetRegistry::RegisterMCCodeEmitter(T, &Allocator);
1196
  }
1197
1198
private:
1199
  static MCCodeEmitter *Allocator(const MCInstrInfo & /*II*/,
1200
                                  const MCRegisterInfo & /*MRI*/,
1201
                                  MCContext & /*Ctx*/) {
1202
    return new MCCodeEmitterImpl();
1203
  }
1204
};
1205
1206
} // end namespace llvm
1207
1208
#endif // LLVM_SUPPORT_TARGETREGISTRY_H