Coverage Report

Created: 2017-11-02 10:23

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/include/llvm/Target/TargetInstrInfo.h
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//===- llvm/Target/TargetInstrInfo.h - Instruction Info ---------*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the target machine instruction set to the code generator.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETINSTRINFO_H
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#define LLVM_TARGET_TARGETINSTRINFO_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/DenseMapInfo.h"
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#include "llvm/ADT/None.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineCombinerPattern.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/Support/BranchProbability.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <cassert>
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#include <cstddef>
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#include <cstdint>
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#include <utility>
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#include <vector>
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namespace llvm {
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class DFAPacketizer;
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class InstrItineraryData;
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class LiveVariables;
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class MachineMemOperand;
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class MachineRegisterInfo;
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class MCAsmInfo;
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class MCInst;
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struct MCSchedModel;
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class Module;
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class ScheduleDAG;
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class ScheduleHazardRecognizer;
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class SDNode;
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class SelectionDAG;
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class RegScavenger;
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class TargetRegisterClass;
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class TargetRegisterInfo;
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class TargetSchedModel;
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class TargetSubtargetInfo;
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59
template <class T> class SmallVectorImpl;
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//---------------------------------------------------------------------------
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///
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/// TargetInstrInfo - Interface to description of machine instruction set
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///
65
class TargetInstrInfo : public MCInstrInfo {
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public:
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  TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
68
                  unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
69
      : CallFrameSetupOpcode(CFSetupOpcode),
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        CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
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40.0k
        ReturnOpcode(ReturnOpcode) {}
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  TargetInstrInfo(const TargetInstrInfo &) = delete;
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  TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
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  virtual ~TargetInstrInfo();
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76
18.2M
  static bool isGenericOpcode(unsigned Opc) {
77
18.2M
    return Opc <= TargetOpcode::GENERIC_OP_END;
78
18.2M
  }
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80
  /// Given a machine instruction descriptor, returns the register
81
  /// class constraint for OpNum, or NULL.
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  const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
83
                                         const TargetRegisterInfo *TRI,
84
                                         const MachineFunction &MF) const;
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86
  /// Return true if the instruction is trivially rematerializable, meaning it
87
  /// has no side effects and requires no operands that aren't always available.
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  /// This means the only allowed uses are constants and unallocatable physical
89
  /// registers so that the instructions result is independent of the place
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  /// in the function.
91
  bool isTriviallyReMaterializable(const MachineInstr &MI,
92
5.69M
                                   AliasAnalysis *AA = nullptr) const {
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5.69M
    return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
94
5.68M
           (MI.getDesc().isRematerializable() &&
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3.49M
            (isReallyTriviallyReMaterializable(MI, AA) ||
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3.30M
             isReallyTriviallyReMaterializableGeneric(MI, AA)));
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5.69M
  }
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protected:
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  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
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  /// set, this hook lets the target specify whether the instruction is actually
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  /// trivially rematerializable, taking into consideration its operands. This
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  /// predicate must return false if the instruction has any side effects other
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  /// than producing a value, or if it requres any address registers that are
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  /// not always available.
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  /// Requirements must be check as stated in isTriviallyReMaterializable() .
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  virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
108
3.08M
                                                 AliasAnalysis *AA) const {
109
3.08M
    return false;
110
3.08M
  }
111
112
  /// This method commutes the operands of the given machine instruction MI.
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  /// The operands to be commuted are specified by their indices OpIdx1 and
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  /// OpIdx2.
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  ///
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  /// If a target has any instructions that are commutable but require
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  /// converting to different instructions or making non-trivial changes
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  /// to commute them, this method can be overloaded to do that.
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  /// The default implementation simply swaps the commutable operands.
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  ///
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  /// If NewMI is false, MI is modified in place and returned; otherwise, a
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  /// new machine instruction is created and returned.
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  ///
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  /// Do not call this method for a non-commutable instruction.
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  /// Even though the instruction is commutable, the method may still
126
  /// fail to commute the operands, null pointer is returned in such cases.
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  virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
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                                               unsigned OpIdx1,
129
                                               unsigned OpIdx2) const;
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  /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
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  /// operand indices to (ResultIdx1, ResultIdx2).
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  /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
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  /// predefined to some indices or be undefined (designated by the special
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  /// value 'CommuteAnyOperandIndex').
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  /// The predefined result indices cannot be re-defined.
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  /// The function returns true iff after the result pair redefinition
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  /// the fixed result pair is equal to or equivalent to the source pair of
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  /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
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  /// the pairs (x,y) and (y,x) are equivalent.
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  static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
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                                   unsigned CommutableOpIdx1,
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                                   unsigned CommutableOpIdx2);
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private:
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  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
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  /// set and the target hook isReallyTriviallyReMaterializable returns false,
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  /// this function does target-independent tests to determine if the
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  /// instruction is really trivially rematerializable.
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  bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
151
                                                AliasAnalysis *AA) const;
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153
public:
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  /// These methods return the opcode of the frame setup/destroy instructions
155
  /// if they exist (-1 otherwise).  Some targets use pseudo instructions in
156
  /// order to abstract away the difference between operating with a frame
157
  /// pointer and operating without, through the use of these two instructions.
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  ///
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41.3M
  unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
160
52.7M
  unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
161
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  /// Returns true if the argument is a frame pseudo instruction.
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36.5M
  bool isFrameInstr(const MachineInstr &I) const {
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36.5M
    return I.getOpcode() == getCallFrameSetupOpcode() ||
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35.1M
           I.getOpcode() == getCallFrameDestroyOpcode();
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36.5M
  }
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  /// Returns true if the argument is a frame setup pseudo instruction.
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398k
  bool isFrameSetup(const MachineInstr &I) const {
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398k
    return I.getOpcode() == getCallFrameSetupOpcode();
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398k
  }
172
173
  /// Returns size of the frame associated with the given frame instruction.
174
  /// For frame setup instruction this is frame that is set up space set up
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  /// after the instruction. For frame destroy instruction this is the frame
176
  /// freed by the caller.
177
  /// Note, in some cases a call frame (or a part of it) may be prepared prior
178
  /// to the frame setup instruction. It occurs in the calls that involve
179
  /// inalloca arguments. This function reports only the size of the frame part
180
  /// that is set up between the frame setup and destroy pseudo instructions.
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3.35M
  int64_t getFrameSize(const MachineInstr &I) const {
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3.35M
    assert(isFrameInstr(I) && "Not a frame instruction");
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3.35M
    assert(I.getOperand(0).getImm() >= 0);
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3.35M
    return I.getOperand(0).getImm();
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3.35M
  }
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187
  /// Returns the total frame size, which is made up of the space set up inside
188
  /// the pair of frame start-stop instructions and the space that is set up
189
  /// prior to the pair.
190
192k
  int64_t getFrameTotalSize(const MachineInstr &I) const {
191
192k
    if (isFrameSetup(I)) {
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96.0k
      assert(I.getOperand(1).getImm() >= 0 &&
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96.0k
             "Frame size must not be negative");
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96.0k
      return getFrameSize(I) + I.getOperand(1).getImm();
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96.0k
    }
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96.0k
    return getFrameSize(I);
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192k
  }
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1.22k
  unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
200
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  unsigned getReturnOpcode() const { return ReturnOpcode; }
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  /// Returns the actual stack pointer adjustment made by an instruction
203
  /// as part of a call sequence. By default, only call frame setup/destroy
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  /// instructions adjust the stack, but targets may want to override this
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  /// to enable more fine-grained adjustment, or adjust by a different value.
206
  virtual int getSPAdjust(const MachineInstr &MI) const;
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208
  /// Return true if the instruction is a "coalescable" extension instruction.
209
  /// That is, it's like a copy where it's legal for the source to overlap the
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  /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
211
  /// expected the pre-extension value is available as a subreg of the result
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  /// register. This also returns the sub-register index in SubIdx.
213
  virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
214
1.66M
                                     unsigned &DstReg, unsigned &SubIdx) const {
215
1.66M
    return false;
216
1.66M
  }
217
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  /// If the specified machine instruction is a direct
219
  /// load from a stack slot, return the virtual or physical register number of
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  /// the destination along with the FrameIndex of the loaded stack slot.  If
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  /// not, return 0.  This predicate must return 0 if the instruction has
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  /// any side effects other than loading from the stack slot.
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  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
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1.66k
                                       int &FrameIndex) const {
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1.66k
    return 0;
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1.66k
  }
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  /// Check for post-frame ptr elimination stack locations as well.
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  /// This uses a heuristic so it isn't reliable for correctness.
230
  virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
231
706k
                                             int &FrameIndex) const {
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706k
    return 0;
233
706k
  }
234
235
  /// If the specified machine instruction has a load from a stack slot,
236
  /// return true along with the FrameIndex of the loaded stack slot and the
237
  /// machine mem operand containing the reference.
238
  /// If not, return false.  Unlike isLoadFromStackSlot, this returns true for
239
  /// any instructions that loads from the stack.  This is just a hint, as some
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  /// cases may be missed.
241
  virtual bool hasLoadFromStackSlot(const MachineInstr &MI,
242
                                    const MachineMemOperand *&MMO,
243
                                    int &FrameIndex) const;
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245
  /// If the specified machine instruction is a direct
246
  /// store to a stack slot, return the virtual or physical register number of
247
  /// the source reg along with the FrameIndex of the loaded stack slot.  If
248
  /// not, return 0.  This predicate must return 0 if the instruction has
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  /// any side effects other than storing to the stack slot.
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  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
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1.00k
                                      int &FrameIndex) const {
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1.00k
    return 0;
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1.00k
  }
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255
  /// Check for post-frame ptr elimination stack locations as well.
256
  /// This uses a heuristic, so it isn't reliable for correctness.
257
  virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
258
687k
                                            int &FrameIndex) const {
259
687k
    return 0;
260
687k
  }
261
262
  /// If the specified machine instruction has a store to a stack slot,
263
  /// return true along with the FrameIndex of the loaded stack slot and the
264
  /// machine mem operand containing the reference.
265
  /// If not, return false.  Unlike isStoreToStackSlot,
266
  /// this returns true for any instructions that stores to the
267
  /// stack.  This is just a hint, as some cases may be missed.
268
  virtual bool hasStoreToStackSlot(const MachineInstr &MI,
269
                                   const MachineMemOperand *&MMO,
270
                                   int &FrameIndex) const;
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272
  /// Return true if the specified machine instruction
273
  /// is a copy of one stack slot to another and has no other effect.
274
  /// Provide the identity of the two frame indices.
275
  virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
276
4.30M
                               int &SrcFrameIndex) const {
277
4.30M
    return false;
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4.30M
  }
279
280
  /// Compute the size in bytes and offset within a stack slot of a spilled
281
  /// register or subregister.
282
  ///
283
  /// \param [out] Size in bytes of the spilled value.
284
  /// \param [out] Offset in bytes within the stack slot.
285
  /// \returns true if both Size and Offset are successfully computed.
286
  ///
287
  /// Not all subregisters have computable spill slots. For example,
288
  /// subregisters registers may not be byte-sized, and a pair of discontiguous
289
  /// subregisters has no single offset.
290
  ///
291
  /// Targets with nontrivial bigendian implementations may need to override
292
  /// this, particularly to support spilled vector registers.
293
  virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
294
                                 unsigned &Size, unsigned &Offset,
295
                                 const MachineFunction &MF) const;
296
297
  /// Returns the size in bytes of the specified MachineInstr, or ~0U
298
  /// when this function is not implemented by a target.
299
0
  virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
300
0
    return ~0U;
301
0
  }
302
303
  /// Return true if the instruction is as cheap as a move instruction.
304
  ///
305
  /// Targets for different archs need to override this, and different
306
  /// micro-architectures can also be finely tuned inside.
307
603k
  virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
308
603k
    return MI.isAsCheapAsAMove();
309
603k
  }
310
311
  /// Return true if the instruction should be sunk by MachineSink.
312
  ///
313
  /// MachineSink determines on its own whether the instruction is safe to sink;
314
  /// this gives the target a hook to override the default behavior with regards
315
  /// to which instructions should be sunk.
316
30.3M
  virtual bool shouldSink(const MachineInstr &MI) const { return true; }
317
318
  /// Re-issue the specified 'original' instruction at the
319
  /// specific location targeting a new destination register.
320
  /// The register in Orig->getOperand(0).getReg() will be substituted by
321
  /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
322
  /// SubIdx.
323
  virtual void reMaterialize(MachineBasicBlock &MBB,
324
                             MachineBasicBlock::iterator MI, unsigned DestReg,
325
                             unsigned SubIdx, const MachineInstr &Orig,
326
                             const TargetRegisterInfo &TRI) const;
327
328
  /// \brief Clones instruction or the whole instruction bundle \p Orig and
329
  /// insert into \p MBB before \p InsertBefore. The target may update operands
330
  /// that are required to be unique.
331
  ///
332
  /// \p Orig must not return true for MachineInstr::isNotDuplicable().
333
  virtual MachineInstr &duplicate(MachineBasicBlock &MBB,
334
                                  MachineBasicBlock::iterator InsertBefore,
335
                                  const MachineInstr &Orig) const;
336
337
  /// This method must be implemented by targets that
338
  /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
339
  /// may be able to convert a two-address instruction into one or more true
340
  /// three-address instructions on demand.  This allows the X86 target (for
341
  /// example) to convert ADD and SHL instructions into LEA instructions if they
342
  /// would require register copies due to two-addressness.
343
  ///
344
  /// This method returns a null pointer if the transformation cannot be
345
  /// performed, otherwise it returns the last new instruction.
346
  ///
347
  virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
348
                                              MachineInstr &MI,
349
0
                                              LiveVariables *LV) const {
350
0
    return nullptr;
351
0
  }
352
353
  // This constant can be used as an input value of operand index passed to
354
  // the method findCommutedOpIndices() to tell the method that the
355
  // corresponding operand index is not pre-defined and that the method
356
  // can pick any commutable operand.
357
  static const unsigned CommuteAnyOperandIndex = ~0U;
358
359
  /// This method commutes the operands of the given machine instruction MI.
360
  ///
361
  /// The operands to be commuted are specified by their indices OpIdx1 and
362
  /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
363
  /// 'CommuteAnyOperandIndex', which means that the method is free to choose
364
  /// any arbitrarily chosen commutable operand. If both arguments are set to
365
  /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
366
  /// operands; then commutes them if such operands could be found.
367
  ///
368
  /// If NewMI is false, MI is modified in place and returned; otherwise, a
369
  /// new machine instruction is created and returned.
370
  ///
371
  /// Do not call this method for a non-commutable instruction or
372
  /// for non-commuable operands.
373
  /// Even though the instruction is commutable, the method may still
374
  /// fail to commute the operands, null pointer is returned in such cases.
375
  MachineInstr *
376
  commuteInstruction(MachineInstr &MI, bool NewMI = false,
377
                     unsigned OpIdx1 = CommuteAnyOperandIndex,
378
                     unsigned OpIdx2 = CommuteAnyOperandIndex) const;
379
380
  /// Returns true iff the routine could find two commutable operands in the
381
  /// given machine instruction.
382
  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
383
  /// If any of the INPUT values is set to the special value
384
  /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
385
  /// operand, then returns its index in the corresponding argument.
386
  /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
387
  /// looks for 2 commutable operands.
388
  /// If INPUT values refer to some operands of MI, then the method simply
389
  /// returns true if the corresponding operands are commutable and returns
390
  /// false otherwise.
391
  ///
392
  /// For example, calling this method this way:
393
  ///     unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
394
  ///     findCommutedOpIndices(MI, Op1, Op2);
395
  /// can be interpreted as a query asking to find an operand that would be
396
  /// commutable with the operand#1.
397
  virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
398
                                     unsigned &SrcOpIdx2) const;
399
400
  /// A pair composed of a register and a sub-register index.
401
  /// Used to give some type checking when modeling Reg:SubReg.
402
  struct RegSubRegPair {
403
    unsigned Reg;
404
    unsigned SubReg;
405
406
    RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
407
47.1M
        : Reg(Reg), SubReg(SubReg) {}
408
  };
409
410
  /// A pair composed of a pair of a register and a sub-register index,
411
  /// and another sub-register index.
412
  /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
413
  struct RegSubRegPairAndIdx : RegSubRegPair {
414
    unsigned SubIdx;
415
416
    RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
417
                        unsigned SubIdx = 0)
418
588k
        : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
419
  };
420
421
  /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
422
  /// and \p DefIdx.
423
  /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
424
  /// the list is modeled as <Reg:SubReg, SubIdx>.
425
  /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
426
  /// two elements:
427
  /// - vreg1:sub1, sub0
428
  /// - vreg2<:0>, sub1
429
  ///
430
  /// \returns true if it is possible to build such an input sequence
431
  /// with the pair \p MI, \p DefIdx. False otherwise.
432
  ///
433
  /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
434
  ///
435
  /// \note The generic implementation does not provide any support for
436
  /// MI.isRegSequenceLike(). In other words, one has to override
437
  /// getRegSequenceLikeInputs for target specific instructions.
438
  bool
439
  getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
440
                       SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
441
442
  /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
443
  /// and \p DefIdx.
444
  /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
445
  /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
446
  /// - vreg1:sub1, sub0
447
  ///
448
  /// \returns true if it is possible to build such an input sequence
449
  /// with the pair \p MI, \p DefIdx. False otherwise.
450
  ///
451
  /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
452
  ///
453
  /// \note The generic implementation does not provide any support for
454
  /// MI.isExtractSubregLike(). In other words, one has to override
455
  /// getExtractSubregLikeInputs for target specific instructions.
456
  bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
457
                              RegSubRegPairAndIdx &InputReg) const;
458
459
  /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
460
  /// and \p DefIdx.
461
  /// \p [out] BaseReg and \p [out] InsertedReg contain
462
  /// the equivalent inputs of INSERT_SUBREG.
463
  /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
464
  /// - BaseReg: vreg0:sub0
465
  /// - InsertedReg: vreg1:sub1, sub3
466
  ///
467
  /// \returns true if it is possible to build such an input sequence
468
  /// with the pair \p MI, \p DefIdx. False otherwise.
469
  ///
470
  /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
471
  ///
472
  /// \note The generic implementation does not provide any support for
473
  /// MI.isInsertSubregLike(). In other words, one has to override
474
  /// getInsertSubregLikeInputs for target specific instructions.
475
  bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
476
                             RegSubRegPair &BaseReg,
477
                             RegSubRegPairAndIdx &InsertedReg) const;
478
479
  /// Return true if two machine instructions would produce identical values.
480
  /// By default, this is only true when the two instructions
481
  /// are deemed identical except for defs. If this function is called when the
482
  /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
483
  /// aggressive checks.
484
  virtual bool produceSameValue(const MachineInstr &MI0,
485
                                const MachineInstr &MI1,
486
                                const MachineRegisterInfo *MRI = nullptr) const;
487
488
  /// \returns true if a branch from an instruction with opcode \p BranchOpc
489
  ///  bytes is capable of jumping to a position \p BrOffset bytes away.
490
  virtual bool isBranchOffsetInRange(unsigned BranchOpc,
491
0
                                     int64_t BrOffset) const {
492
0
    llvm_unreachable("target did not implement");
493
0
  }
494
495
  /// \returns The block that branch instruction \p MI jumps to.
496
0
  virtual MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const {
497
0
    llvm_unreachable("target did not implement");
498
0
  }
499
500
  /// Insert an unconditional indirect branch at the end of \p MBB to \p
501
  /// NewDestBB.  \p BrOffset indicates the offset of \p NewDestBB relative to
502
  /// the offset of the position to insert the new branch.
503
  ///
504
  /// \returns The number of bytes added to the block.
505
  virtual unsigned insertIndirectBranch(MachineBasicBlock &MBB,
506
                                        MachineBasicBlock &NewDestBB,
507
                                        const DebugLoc &DL,
508
                                        int64_t BrOffset = 0,
509
0
                                        RegScavenger *RS = nullptr) const {
510
0
    llvm_unreachable("target did not implement");
511
0
  }
512
513
  /// Analyze the branching code at the end of MBB, returning
514
  /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
515
  /// implemented for a target).  Upon success, this returns false and returns
516
  /// with the following information in various cases:
517
  ///
518
  /// 1. If this block ends with no branches (it just falls through to its succ)
519
  ///    just return false, leaving TBB/FBB null.
520
  /// 2. If this block ends with only an unconditional branch, it sets TBB to be
521
  ///    the destination block.
522
  /// 3. If this block ends with a conditional branch and it falls through to a
523
  ///    successor block, it sets TBB to be the branch destination block and a
524
  ///    list of operands that evaluate the condition. These operands can be
525
  ///    passed to other TargetInstrInfo methods to create new branches.
526
  /// 4. If this block ends with a conditional branch followed by an
527
  ///    unconditional branch, it returns the 'true' destination in TBB, the
528
  ///    'false' destination in FBB, and a list of operands that evaluate the
529
  ///    condition.  These operands can be passed to other TargetInstrInfo
530
  ///    methods to create new branches.
531
  ///
532
  /// Note that removeBranch and insertBranch must be implemented to support
533
  /// cases where this method returns success.
534
  ///
535
  /// If AllowModify is true, then this routine is allowed to modify the basic
536
  /// block (e.g. delete instructions after the unconditional branch).
537
  ///
538
  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
539
  /// before calling this function.
540
  virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
541
                             MachineBasicBlock *&FBB,
542
                             SmallVectorImpl<MachineOperand> &Cond,
543
0
                             bool AllowModify = false) const {
544
0
    return true;
545
0
  }
546
547
  /// Represents a predicate at the MachineFunction level.  The control flow a
548
  /// MachineBranchPredicate represents is:
549
  ///
550
  ///  Reg <def>= LHS `Predicate` RHS         == ConditionDef
551
  ///  if Reg then goto TrueDest else goto FalseDest
552
  ///
553
  struct MachineBranchPredicate {
554
    enum ComparePredicate {
555
      PRED_EQ,     // True if two values are equal
556
      PRED_NE,     // True if two values are not equal
557
      PRED_INVALID // Sentinel value
558
    };
559
560
    ComparePredicate Predicate = PRED_INVALID;
561
    MachineOperand LHS = MachineOperand::CreateImm(0);
562
    MachineOperand RHS = MachineOperand::CreateImm(0);
563
    MachineBasicBlock *TrueDest = nullptr;
564
    MachineBasicBlock *FalseDest = nullptr;
565
    MachineInstr *ConditionDef = nullptr;
566
567
    /// SingleUseCondition is true if ConditionDef is dead except for the
568
    /// branch(es) at the end of the basic block.
569
    ///
570
    bool SingleUseCondition = false;
571
572
60
    explicit MachineBranchPredicate() = default;
573
  };
574
575
  /// Analyze the branching code at the end of MBB and parse it into the
576
  /// MachineBranchPredicate structure if possible.  Returns false on success
577
  /// and true on failure.
578
  ///
579
  /// If AllowModify is true, then this routine is allowed to modify the basic
580
  /// block (e.g. delete instructions after the unconditional branch).
581
  ///
582
  virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB,
583
                                      MachineBranchPredicate &MBP,
584
0
                                      bool AllowModify = false) const {
585
0
    return true;
586
0
  }
587
588
  /// Remove the branching code at the end of the specific MBB.
589
  /// This is only invoked in cases where AnalyzeBranch returns success. It
590
  /// returns the number of instructions that were removed.
591
  /// If \p BytesRemoved is non-null, report the change in code size from the
592
  /// removed instructions.
593
  virtual unsigned removeBranch(MachineBasicBlock &MBB,
594
0
                                int *BytesRemoved = nullptr) const {
595
0
    llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
596
0
  }
597
598
  /// Insert branch code into the end of the specified MachineBasicBlock. The
599
  /// operands to this method are the same as those returned by AnalyzeBranch.
600
  /// This is only invoked in cases where AnalyzeBranch returns success. It
601
  /// returns the number of instructions inserted. If \p BytesAdded is non-null,
602
  /// report the change in code size from the added instructions.
603
  ///
604
  /// It is also invoked by tail merging to add unconditional branches in
605
  /// cases where AnalyzeBranch doesn't apply because there was no original
606
  /// branch to analyze.  At least this much must be implemented, else tail
607
  /// merging needs to be disabled.
608
  ///
609
  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
610
  /// before calling this function.
611
  virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
612
                                MachineBasicBlock *FBB,
613
                                ArrayRef<MachineOperand> Cond,
614
                                const DebugLoc &DL,
615
0
                                int *BytesAdded = nullptr) const {
616
0
    llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
617
0
  }
618
619
  unsigned insertUnconditionalBranch(MachineBasicBlock &MBB,
620
                                     MachineBasicBlock *DestBB,
621
                                     const DebugLoc &DL,
622
3
                                     int *BytesAdded = nullptr) const {
623
3
    return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL,
624
3
                        BytesAdded);
625
3
  }
626
627
  /// Analyze the loop code, return true if it cannot be understoo. Upon
628
  /// success, this function returns false and returns information about the
629
  /// induction variable and compare instruction used at the end.
630
  virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
631
0
                           MachineInstr *&CmpInst) const {
632
0
    return true;
633
0
  }
634
635
  /// Generate code to reduce the loop iteration by one and check if the loop is
636
  /// finished.  Return the value/register of the the new loop count.  We need
637
  /// this function when peeling off one or more iterations of a loop. This
638
  /// function assumes the nth iteration is peeled first.
639
  virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar,
640
                                   MachineInstr &Cmp,
641
                                   SmallVectorImpl<MachineOperand> &Cond,
642
                                   SmallVectorImpl<MachineInstr *> &PrevInsts,
643
0
                                   unsigned Iter, unsigned MaxIter) const {
644
0
    llvm_unreachable("Target didn't implement ReduceLoopCount");
645
0
  }
646
647
  /// Delete the instruction OldInst and everything after it, replacing it with
648
  /// an unconditional branch to NewDest. This is used by the tail merging pass.
649
  virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
650
                                       MachineBasicBlock *NewDest) const;
651
652
  /// Return true if it's legal to split the given basic
653
  /// block at the specified instruction (i.e. instruction would be the start
654
  /// of a new basic block).
655
  virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
656
57.8k
                                   MachineBasicBlock::iterator MBBI) const {
657
57.8k
    return true;
658
57.8k
  }
659
660
  /// Return true if it's profitable to predicate
661
  /// instructions with accumulated instruction latency of "NumCycles"
662
  /// of the specified basic block, where the probability of the instructions
663
  /// being executed is given by Probability, and Confidence is a measure
664
  /// of our confidence that it will be properly predicted.
665
  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
666
                                   unsigned ExtraPredCycles,
667
0
                                   BranchProbability Probability) const {
668
0
    return false;
669
0
  }
670
671
  /// Second variant of isProfitableToIfCvt. This one
672
  /// checks for the case where two basic blocks from true and false path
673
  /// of a if-then-else (diamond) are predicated on mutally exclusive
674
  /// predicates, where the probability of the true path being taken is given
675
  /// by Probability, and Confidence is a measure of our confidence that it
676
  /// will be properly predicted.
677
  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,
678
                                   unsigned ExtraTCycles,
679
                                   MachineBasicBlock &FMBB, unsigned NumFCycles,
680
                                   unsigned ExtraFCycles,
681
0
                                   BranchProbability Probability) const {
682
0
    return false;
683
0
  }
684
685
  /// Return true if it's profitable for if-converter to duplicate instructions
686
  /// of specified accumulated instruction latencies in the specified MBB to
687
  /// enable if-conversion.
688
  /// The probability of the instructions being executed is given by
689
  /// Probability, and Confidence is a measure of our confidence that it
690
  /// will be properly predicted.
691
  virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
692
                                         unsigned NumCycles,
693
0
                                         BranchProbability Probability) const {
694
0
    return false;
695
0
  }
696
697
  /// Return true if it's profitable to unpredicate
698
  /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
699
  /// exclusive predicates.
700
  /// e.g.
701
  ///   subeq  r0, r1, #1
702
  ///   addne  r0, r1, #1
703
  /// =>
704
  ///   sub    r0, r1, #1
705
  ///   addne  r0, r1, #1
706
  ///
707
  /// This may be profitable is conditional instructions are always executed.
708
  virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
709
17
                                         MachineBasicBlock &FMBB) const {
710
17
    return false;
711
17
  }
712
713
  /// Return true if it is possible to insert a select
714
  /// instruction that chooses between TrueReg and FalseReg based on the
715
  /// condition code in Cond.
716
  ///
717
  /// When successful, also return the latency in cycles from TrueReg,
718
  /// FalseReg, and Cond to the destination register. In most cases, a select
719
  /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
720
  ///
721
  /// Some x86 implementations have 2-cycle cmov instructions.
722
  ///
723
  /// @param MBB         Block where select instruction would be inserted.
724
  /// @param Cond        Condition returned by AnalyzeBranch.
725
  /// @param TrueReg     Virtual register to select when Cond is true.
726
  /// @param FalseReg    Virtual register to select when Cond is false.
727
  /// @param CondCycles  Latency from Cond+Branch to select output.
728
  /// @param TrueCycles  Latency from TrueReg to select output.
729
  /// @param FalseCycles Latency from FalseReg to select output.
730
  virtual bool canInsertSelect(const MachineBasicBlock &MBB,
731
                               ArrayRef<MachineOperand> Cond, unsigned TrueReg,
732
                               unsigned FalseReg, int &CondCycles,
733
0
                               int &TrueCycles, int &FalseCycles) const {
734
0
    return false;
735
0
  }
736
737
  /// Insert a select instruction into MBB before I that will copy TrueReg to
738
  /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
739
  ///
740
  /// This function can only be called after canInsertSelect() returned true.
741
  /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
742
  /// that the same flags or registers required by Cond are available at the
743
  /// insertion point.
744
  ///
745
  /// @param MBB      Block where select instruction should be inserted.
746
  /// @param I        Insertion point.
747
  /// @param DL       Source location for debugging.
748
  /// @param DstReg   Virtual register to be defined by select instruction.
749
  /// @param Cond     Condition as computed by AnalyzeBranch.
750
  /// @param TrueReg  Virtual register to copy when Cond is true.
751
  /// @param FalseReg Virtual register to copy when Cons is false.
752
  virtual void insertSelect(MachineBasicBlock &MBB,
753
                            MachineBasicBlock::iterator I, const DebugLoc &DL,
754
                            unsigned DstReg, ArrayRef<MachineOperand> Cond,
755
0
                            unsigned TrueReg, unsigned FalseReg) const {
756
0
    llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
757
0
  }
758
759
  /// Analyze the given select instruction, returning true if
760
  /// it cannot be understood. It is assumed that MI->isSelect() is true.
761
  ///
762
  /// When successful, return the controlling condition and the operands that
763
  /// determine the true and false result values.
764
  ///
765
  ///   Result = SELECT Cond, TrueOp, FalseOp
766
  ///
767
  /// Some targets can optimize select instructions, for example by predicating
768
  /// the instruction defining one of the operands. Such targets should set
769
  /// Optimizable.
770
  ///
771
  /// @param         MI Select instruction to analyze.
772
  /// @param Cond    Condition controlling the select.
773
  /// @param TrueOp  Operand number of the value selected when Cond is true.
774
  /// @param FalseOp Operand number of the value selected when Cond is false.
775
  /// @param Optimizable Returned as true if MI is optimizable.
776
  /// @returns False on success.
777
  virtual bool analyzeSelect(const MachineInstr &MI,
778
                             SmallVectorImpl<MachineOperand> &Cond,
779
                             unsigned &TrueOp, unsigned &FalseOp,
780
696
                             bool &Optimizable) const {
781
696
    assert(MI.getDesc().isSelect() && "MI must be a select instruction");
782
696
    return true;
783
696
  }
784
785
  /// Given a select instruction that was understood by
786
  /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
787
  /// merging it with one of its operands. Returns NULL on failure.
788
  ///
789
  /// When successful, returns the new select instruction. The client is
790
  /// responsible for deleting MI.
791
  ///
792
  /// If both sides of the select can be optimized, PreferFalse is used to pick
793
  /// a side.
794
  ///
795
  /// @param MI          Optimizable select instruction.
796
  /// @param NewMIs     Set that record all MIs in the basic block up to \p
797
  /// MI. Has to be updated with any newly created MI or deleted ones.
798
  /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
799
  /// @returns Optimized instruction or NULL.
800
  virtual MachineInstr *optimizeSelect(MachineInstr &MI,
801
                                       SmallPtrSetImpl<MachineInstr *> &NewMIs,
802
0
                                       bool PreferFalse = false) const {
803
0
    // This function must be implemented if Optimizable is ever set.
804
0
    llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
805
0
  }
806
807
  /// Emit instructions to copy a pair of physical registers.
808
  ///
809
  /// This function should support copies within any legal register class as
810
  /// well as any cross-class copies created during instruction selection.
811
  ///
812
  /// The source and destination registers may overlap, which may require a
813
  /// careful implementation when multiple copy instructions are required for
814
  /// large registers. See for example the ARM target.
815
  virtual void copyPhysReg(MachineBasicBlock &MBB,
816
                           MachineBasicBlock::iterator MI, const DebugLoc &DL,
817
                           unsigned DestReg, unsigned SrcReg,
818
0
                           bool KillSrc) const {
819
0
    llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
820
0
  }
821
822
  /// Store the specified register of the given register class to the specified
823
  /// stack frame index. The store instruction is to be added to the given
824
  /// machine basic block before the specified machine instruction. If isKill
825
  /// is true, the register operand is the last use and must be marked kill.
826
  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
827
                                   MachineBasicBlock::iterator MI,
828
                                   unsigned SrcReg, bool isKill, int FrameIndex,
829
                                   const TargetRegisterClass *RC,
830
0
                                   const TargetRegisterInfo *TRI) const {
831
0
    llvm_unreachable("Target didn't implement "
832
0
                     "TargetInstrInfo::storeRegToStackSlot!");
833
0
  }
834
835
  /// Load the specified register of the given register class from the specified
836
  /// stack frame index. The load instruction is to be added to the given
837
  /// machine basic block before the specified machine instruction.
838
  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
839
                                    MachineBasicBlock::iterator MI,
840
                                    unsigned DestReg, int FrameIndex,
841
                                    const TargetRegisterClass *RC,
842
0
                                    const TargetRegisterInfo *TRI) const {
843
0
    llvm_unreachable("Target didn't implement "
844
0
                     "TargetInstrInfo::loadRegFromStackSlot!");
845
0
  }
846
847
  /// This function is called for all pseudo instructions
848
  /// that remain after register allocation. Many pseudo instructions are
849
  /// created to help register allocation. This is the place to convert them
850
  /// into real instructions. The target can edit MI in place, or it can insert
851
  /// new instructions and erase MI. The function should return true if
852
  /// anything was changed.
853
239k
  virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
854
855
  /// Check whether the target can fold a load that feeds a subreg operand
856
  /// (or a subreg operand that feeds a store).
857
  /// For example, X86 may want to return true if it can fold
858
  /// movl (%esp), %eax
859
  /// subb, %al, ...
860
  /// Into:
861
  /// subb (%esp), ...
862
  ///
863
  /// Ideally, we'd like the target implementation of foldMemoryOperand() to
864
  /// reject subregs - but since this behavior used to be enforced in the
865
  /// target-independent code, moving this responsibility to the targets
866
  /// has the potential of causing nasty silent breakage in out-of-tree targets.
867
31.8k
  virtual bool isSubregFoldable() const { return false; }
868
869
  /// Attempt to fold a load or store of the specified stack
870
  /// slot into the specified machine instruction for the specified operand(s).
871
  /// If this is possible, a new instruction is returned with the specified
872
  /// operand folded, otherwise NULL is returned.
873
  /// The new instruction is inserted before MI, and the client is responsible
874
  /// for removing the old instruction.
875
  MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
876
                                  int FrameIndex,
877
                                  LiveIntervals *LIS = nullptr) const;
878
879
  /// Same as the previous version except it allows folding of any load and
880
  /// store from / to any address, not just from a specific stack slot.
881
  MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
882
                                  MachineInstr &LoadMI,
883
                                  LiveIntervals *LIS = nullptr) const;
884
885
  /// Return true when there is potentially a faster code sequence
886
  /// for an instruction chain ending in \p Root. All potential patterns are
887
  /// returned in the \p Pattern vector. Pattern should be sorted in priority
888
  /// order since the pattern evaluator stops checking as soon as it finds a
889
  /// faster sequence.
890
  /// \param Root - Instruction that could be combined with one of its operands
891
  /// \param Patterns - Vector of possible combination patterns
892
  virtual bool getMachineCombinerPatterns(
893
      MachineInstr &Root,
894
      SmallVectorImpl<MachineCombinerPattern> &Patterns) const;
895
896
  /// Return true when a code sequence can improve throughput. It
897
  /// should be called only for instructions in loops.
898
  /// \param Pattern - combiner pattern
899
  virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const;
900
901
  /// Return true if the input \P Inst is part of a chain of dependent ops
902
  /// that are suitable for reassociation, otherwise return false.
903
  /// If the instruction's operands must be commuted to have a previous
904
  /// instruction of the same type define the first source operand, \P Commuted
905
  /// will be set to true.
906
  bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
907
908
  /// Return true when \P Inst is both associative and commutative.
909
0
  virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
910
0
    return false;
911
0
  }
912
913
  /// Return true when \P Inst has reassociable operands in the same \P MBB.
914
  virtual bool hasReassociableOperands(const MachineInstr &Inst,
915
                                       const MachineBasicBlock *MBB) const;
916
917
  /// Return true when \P Inst has reassociable sibling.
918
  bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
919
920
  /// When getMachineCombinerPatterns() finds patterns, this function generates
921
  /// the instructions that could replace the original code sequence. The client
922
  /// has to decide whether the actual replacement is beneficial or not.
923
  /// \param Root - Instruction that could be combined with one of its operands
924
  /// \param Pattern - Combination pattern for Root
925
  /// \param InsInstrs - Vector of new instructions that implement P
926
  /// \param DelInstrs - Old instructions, including Root, that could be
927
  /// replaced by InsInstr
928
  /// \param InstrIdxForVirtReg - map of virtual register to instruction in
929
  /// InsInstr that defines it
930
  virtual void genAlternativeCodeSequence(
931
      MachineInstr &Root, MachineCombinerPattern Pattern,
932
      SmallVectorImpl<MachineInstr *> &InsInstrs,
933
      SmallVectorImpl<MachineInstr *> &DelInstrs,
934
      DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
935
936
  /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
937
  /// reduce critical path length.
938
  void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
939
                      MachineCombinerPattern Pattern,
940
                      SmallVectorImpl<MachineInstr *> &InsInstrs,
941
                      SmallVectorImpl<MachineInstr *> &DelInstrs,
942
                      DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
943
944
  /// This is an architecture-specific helper function of reassociateOps.
945
  /// Set special operand attributes for new instructions after reassociation.
946
  virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
947
                                     MachineInstr &NewMI1,
948
205
                                     MachineInstr &NewMI2) const {}
949
950
  /// Return true when a target supports MachineCombiner.
951
0
  virtual bool useMachineCombiner() const { return false; }
952
953
protected:
954
  /// Target-dependent implementation for foldMemoryOperand.
955
  /// Target-independent code in foldMemoryOperand will
956
  /// take care of adding a MachineMemOperand to the newly created instruction.
957
  /// The instruction and any auxiliary instructions necessary will be inserted
958
  /// at InsertPt.
959
  virtual MachineInstr *
960
  foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
961
                        ArrayRef<unsigned> Ops,
962
                        MachineBasicBlock::iterator InsertPt, int FrameIndex,
963
30.0k
                        LiveIntervals *LIS = nullptr) const {
964
30.0k
    return nullptr;
965
30.0k
  }
966
967
  /// Target-dependent implementation for foldMemoryOperand.
968
  /// Target-independent code in foldMemoryOperand will
969
  /// take care of adding a MachineMemOperand to the newly created instruction.
970
  /// The instruction and any auxiliary instructions necessary will be inserted
971
  /// at InsertPt.
972
  virtual MachineInstr *foldMemoryOperandImpl(
973
      MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
974
      MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
975
900
      LiveIntervals *LIS = nullptr) const {
976
900
    return nullptr;
977
900
  }
978
979
  /// \brief Target-dependent implementation of getRegSequenceInputs.
980
  ///
981
  /// \returns true if it is possible to build the equivalent
982
  /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
983
  ///
984
  /// \pre MI.isRegSequenceLike().
985
  ///
986
  /// \see TargetInstrInfo::getRegSequenceInputs.
987
  virtual bool getRegSequenceLikeInputs(
988
      const MachineInstr &MI, unsigned DefIdx,
989
0
      SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
990
0
    return false;
991
0
  }
992
993
  /// \brief Target-dependent implementation of getExtractSubregInputs.
994
  ///
995
  /// \returns true if it is possible to build the equivalent
996
  /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
997
  ///
998
  /// \pre MI.isExtractSubregLike().
999
  ///
1000
  /// \see TargetInstrInfo::getExtractSubregInputs.
1001
  virtual bool getExtractSubregLikeInputs(const MachineInstr &MI,
1002
                                          unsigned DefIdx,
1003
0
                                          RegSubRegPairAndIdx &InputReg) const {
1004
0
    return false;
1005
0
  }
1006
1007
  /// \brief Target-dependent implementation of getInsertSubregInputs.
1008
  ///
1009
  /// \returns true if it is possible to build the equivalent
1010
  /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1011
  ///
1012
  /// \pre MI.isInsertSubregLike().
1013
  ///
1014
  /// \see TargetInstrInfo::getInsertSubregInputs.
1015
  virtual bool
1016
  getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
1017
                            RegSubRegPair &BaseReg,
1018
0
                            RegSubRegPairAndIdx &InsertedReg) const {
1019
0
    return false;
1020
0
  }
1021
1022
public:
1023
  /// getAddressSpaceForPseudoSourceKind - Given the kind of memory
1024
  /// (e.g. stack) the target returns the corresponding address space.
1025
  virtual unsigned
1026
3.18M
  getAddressSpaceForPseudoSourceKind(PseudoSourceValue::PSVKind Kind) const {
1027
3.18M
    return 0;
1028
3.18M
  }
1029
1030
  /// unfoldMemoryOperand - Separate a single instruction which folded a load or
1031
  /// a store or a load and a store into two or more instruction. If this is
1032
  /// possible, returns true as well as the new instructions by reference.
1033
  virtual bool
1034
  unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
1035
                      bool UnfoldLoad, bool UnfoldStore,
1036
0
                      SmallVectorImpl<MachineInstr *> &NewMIs) const {
1037
0
    return false;
1038
0
  }
1039
1040
  virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
1041
0
                                   SmallVectorImpl<SDNode *> &NewNodes) const {
1042
0
    return false;
1043
0
  }
1044
1045
  /// Returns the opcode of the would be new
1046
  /// instruction after load / store are unfolded from an instruction of the
1047
  /// specified opcode. It returns zero if the specified unfolding is not
1048
  /// possible. If LoadRegIndex is non-null, it is filled in with the operand
1049
  /// index of the operand which will hold the register holding the loaded
1050
  /// value.
1051
  virtual unsigned
1052
  getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
1053
7.85k
                             unsigned *LoadRegIndex = nullptr) const {
1054
7.85k
    return 0;
1055
7.85k
  }
1056
1057
  /// This is used by the pre-regalloc scheduler to determine if two loads are
1058
  /// loading from the same base address. It should only return true if the base
1059
  /// pointers are the same and the only differences between the two addresses
1060
  /// are the offset. It also returns the offsets by reference.
1061
  virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1062
                                       int64_t &Offset1,
1063
4.82M
                                       int64_t &Offset2) const {
1064
4.82M
    return false;
1065
4.82M
  }
1066
1067
  /// This is a used by the pre-regalloc scheduler to determine (in conjunction
1068
  /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
1069
  /// On some targets if two loads are loading from
1070
  /// addresses in the same cache line, it's better if they are scheduled
1071
  /// together. This function takes two integers that represent the load offsets
1072
  /// from the common base address. It returns true if it decides it's desirable
1073
  /// to schedule the two loads together. "NumLoads" is the number of loads that
1074
  /// have already been scheduled after Load1.
1075
  virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1076
                                       int64_t Offset1, int64_t Offset2,
1077
0
                                       unsigned NumLoads) const {
1078
0
    return false;
1079
0
  }
1080
1081
  /// Get the base register and byte offset of an instruction that reads/writes
1082
  /// memory.
1083
  virtual bool getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
1084
                                     int64_t &Offset,
1085
0
                                     const TargetRegisterInfo *TRI) const {
1086
0
    return false;
1087
0
  }
1088
1089
  /// Return true if the instruction contains a base register and offset. If
1090
  /// true, the function also sets the operand position in the instruction
1091
  /// for the base register and offset.
1092
  virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
1093
                                        unsigned &BasePos,
1094
0
                                        unsigned &OffsetPos) const {
1095
0
    return false;
1096
0
  }
1097
1098
  /// If the instruction is an increment of a constant value, return the amount.
1099
0
  virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
1100
0
    return false;
1101
0
  }
1102
1103
  /// Returns true if the two given memory operations should be scheduled
1104
  /// adjacent. Note that you have to add:
1105
  ///   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1106
  /// or
1107
  ///   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1108
  /// to TargetPassConfig::createMachineScheduler() to have an effect.
1109
  virtual bool shouldClusterMemOps(MachineInstr &FirstLdSt, unsigned BaseReg1,
1110
                                   MachineInstr &SecondLdSt, unsigned BaseReg2,
1111
0
                                   unsigned NumLoads) const {
1112
0
    llvm_unreachable("target did not implement shouldClusterMemOps()");
1113
0
  }
1114
1115
  /// Reverses the branch condition of the specified condition list,
1116
  /// returning false on success and true if it cannot be reversed.
1117
  virtual bool
1118
94
  reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1119
94
    return true;
1120
94
  }
1121
1122
  /// Insert a noop into the instruction stream at the specified point.
1123
  virtual void insertNoop(MachineBasicBlock &MBB,
1124
                          MachineBasicBlock::iterator MI) const;
1125
1126
  /// Return the noop instruction to use for a noop.
1127
  virtual void getNoop(MCInst &NopInst) const;
1128
1129
  /// Return true for post-incremented instructions.
1130
0
  virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
1131
1132
  /// Returns true if the instruction is already predicated.
1133
1.83M
  virtual bool isPredicated(const MachineInstr &MI) const { return false; }
1134
1135
  /// Returns true if the instruction is a
1136
  /// terminator instruction that has not been predicated.
1137
  virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
1138
1139
  /// Returns true if MI is an unconditional tail call.
1140
25.4k
  virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
1141
25.4k
    return false;
1142
25.4k
  }
1143
1144
  /// Returns true if the tail call can be made conditional on BranchCond.
1145
  virtual bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
1146
0
                                          const MachineInstr &TailCall) const {
1147
0
    return false;
1148
0
  }
1149
1150
  /// Replace the conditional branch in MBB with a conditional tail call.
1151
  virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB,
1152
                                         SmallVectorImpl<MachineOperand> &Cond,
1153
0
                                         const MachineInstr &TailCall) const {
1154
0
    llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
1155
0
  }
1156
1157
  /// Convert the instruction into a predicated instruction.
1158
  /// It returns true if the operation was successful.
1159
  virtual bool PredicateInstruction(MachineInstr &MI,
1160
                                    ArrayRef<MachineOperand> Pred) const;
1161
1162
  /// Returns true if the first specified predicate
1163
  /// subsumes the second, e.g. GE subsumes GT.
1164
  virtual bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1165
0
                                 ArrayRef<MachineOperand> Pred2) const {
1166
0
    return false;
1167
0
  }
1168
1169
  /// If the specified instruction defines any predicate
1170
  /// or condition code register(s) used for predication, returns true as well
1171
  /// as the definition predicate(s) by reference.
1172
  virtual bool DefinesPredicate(MachineInstr &MI,
1173
9.85k
                                std::vector<MachineOperand> &Pred) const {
1174
9.85k
    return false;
1175
9.85k
  }
1176
1177
  /// Return true if the specified instruction can be predicated.
1178
  /// By default, this returns true for every instruction with a
1179
  /// PredicateOperand.
1180
818
  virtual bool isPredicable(const MachineInstr &MI) const {
1181
818
    return MI.getDesc().isPredicable();
1182
818
  }
1183
1184
  /// Return true if it's safe to move a machine
1185
  /// instruction that defines the specified register class.
1186
13.1M
  virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1187
13.1M
    return true;
1188
13.1M
  }
1189
1190
  /// Test if the given instruction should be considered a scheduling boundary.
1191
  /// This primarily includes labels and terminators.
1192
  virtual bool isSchedulingBoundary(const MachineInstr &MI,
1193
                                    const MachineBasicBlock *MBB,
1194
                                    const MachineFunction &MF) const;
1195
1196
  /// Measure the specified inline asm to determine an approximation of its
1197
  /// length.
1198
  virtual unsigned getInlineAsmLength(const char *Str,
1199
                                      const MCAsmInfo &MAI) const;
1200
1201
  /// Allocate and return a hazard recognizer to use for this target when
1202
  /// scheduling the machine instructions before register allocation.
1203
  virtual ScheduleHazardRecognizer *
1204
  CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
1205
                               const ScheduleDAG *DAG) const;
1206
1207
  /// Allocate and return a hazard recognizer to use for this target when
1208
  /// scheduling the machine instructions before register allocation.
1209
  virtual ScheduleHazardRecognizer *
1210
  CreateTargetMIHazardRecognizer(const InstrItineraryData *,
1211
                                 const ScheduleDAG *DAG) const;
1212
1213
  /// Allocate and return a hazard recognizer to use for this target when
1214
  /// scheduling the machine instructions after register allocation.
1215
  virtual ScheduleHazardRecognizer *
1216
  CreateTargetPostRAHazardRecognizer(const InstrItineraryData *,
1217
                                     const ScheduleDAG *DAG) const;
1218
1219
  /// Allocate and return a hazard recognizer to use for by non-scheduling
1220
  /// passes.
1221
  virtual ScheduleHazardRecognizer *
1222
0
  CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {
1223
0
    return nullptr;
1224
0
  }
1225
1226
  /// Provide a global flag for disabling the PreRA hazard recognizer that
1227
  /// targets may choose to honor.
1228
  bool usePreRAHazardRecognizer() const;
1229
1230
  /// For a comparison instruction, return the source registers
1231
  /// in SrcReg and SrcReg2 if having two register operands, and the value it
1232
  /// compares against in CmpValue. Return true if the comparison instruction
1233
  /// can be analyzed.
1234
  virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1235
4.26k
                              unsigned &SrcReg2, int &Mask, int &Value) const {
1236
4.26k
    return false;
1237
4.26k
  }
1238
1239
  /// See if the comparison instruction can be converted
1240
  /// into something more efficient. E.g., on ARM most instructions can set the
1241
  /// flags register, obviating the need for a separate CMP.
1242
  virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1243
                                    unsigned SrcReg2, int Mask, int Value,
1244
544
                                    const MachineRegisterInfo *MRI) const {
1245
544
    return false;
1246
544
  }
1247
206k
  virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
1248
1249
  /// Try to remove the load by folding it to a register operand at the use.
1250
  /// We fold the load instructions if and only if the
1251
  /// def and use are in the same BB. We only look at one load and see
1252
  /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
1253
  /// defined by the load we are trying to fold. DefMI returns the machine
1254
  /// instruction that defines FoldAsLoadDefReg, and the function returns
1255
  /// the machine instruction generated due to folding.
1256
  virtual MachineInstr *optimizeLoadInstr(MachineInstr &MI,
1257
                                          const MachineRegisterInfo *MRI,
1258
                                          unsigned &FoldAsLoadDefReg,
1259
25.2k
                                          MachineInstr *&DefMI) const {
1260
25.2k
    return nullptr;
1261
25.2k
  }
1262
1263
  /// 'Reg' is known to be defined by a move immediate instruction,
1264
  /// try to fold the immediate into the use instruction.
1265
  /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1266
  /// then the caller may assume that DefMI has been erased from its parent
1267
  /// block. The caller may assume that it will not be erased by this
1268
  /// function otherwise.
1269
  virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
1270
733k
                             unsigned Reg, MachineRegisterInfo *MRI) const {
1271
733k
    return false;
1272
733k
  }
1273
1274
  /// Return the number of u-operations the given machine
1275
  /// instruction will be decoded to on the target cpu. The itinerary's
1276
  /// IssueWidth is the number of microops that can be dispatched each
1277
  /// cycle. An instruction with zero microops takes no dispatch resources.
1278
  virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1279
                                  const MachineInstr &MI) const;
1280
1281
  /// Return true for pseudo instructions that don't consume any
1282
  /// machine resources in their current form. These are common cases that the
1283
  /// scheduler should consider free, rather than conservatively handling them
1284
  /// as instructions with no itinerary.
1285
1.07M
  bool isZeroCost(unsigned Opcode) const {
1286
1.07M
    return Opcode <= TargetOpcode::COPY;
1287
1.07M
  }
1288
1289
  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1290
                                SDNode *DefNode, unsigned DefIdx,
1291
                                SDNode *UseNode, unsigned UseIdx) const;
1292
1293
  /// Compute and return the use operand latency of a given pair of def and use.
1294
  /// In most cases, the static scheduling itinerary was enough to determine the
1295
  /// operand latency. But it may not be possible for instructions with variable
1296
  /// number of defs / uses.
1297
  ///
1298
  /// This is a raw interface to the itinerary that may be directly overridden
1299
  /// by a target. Use computeOperandLatency to get the best estimate of
1300
  /// latency.
1301
  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1302
                                const MachineInstr &DefMI, unsigned DefIdx,
1303
                                const MachineInstr &UseMI,
1304
                                unsigned UseIdx) const;
1305
1306
  /// Compute the instruction latency of a given instruction.
1307
  /// If the instruction has higher cost when predicated, it's returned via
1308
  /// PredCost.
1309
  virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1310
                                   const MachineInstr &MI,
1311
                                   unsigned *PredCost = nullptr) const;
1312
1313
  virtual unsigned getPredicationCost(const MachineInstr &MI) const;
1314
1315
  virtual int getInstrLatency(const InstrItineraryData *ItinData,
1316
                              SDNode *Node) const;
1317
1318
  /// Return the default expected latency for a def based on its opcode.
1319
  unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1320
                             const MachineInstr &DefMI) const;
1321
1322
  int computeDefOperandLatency(const InstrItineraryData *ItinData,
1323
                               const MachineInstr &DefMI) const;
1324
1325
  /// Return true if this opcode has high latency to its result.
1326
2.35M
  virtual bool isHighLatencyDef(int opc) const { return false; }
1327
1328
  /// Compute operand latency between a def of 'Reg'
1329
  /// and a use in the current loop. Return true if the target considered
1330
  /// it 'high'. This is used by optimization passes such as machine LICM to
1331
  /// determine whether it makes sense to hoist an instruction out even in a
1332
  /// high register pressure situation.
1333
  virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1334
                                     const MachineRegisterInfo *MRI,
1335
                                     const MachineInstr &DefMI, unsigned DefIdx,
1336
                                     const MachineInstr &UseMI,
1337
89.9k
                                     unsigned UseIdx) const {
1338
89.9k
    return false;
1339
89.9k
  }
1340
1341
  /// Compute operand latency of a def of 'Reg'. Return true
1342
  /// if the target considered it 'low'.
1343
  virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1344
                                const MachineInstr &DefMI,
1345
                                unsigned DefIdx) const;
1346
1347
  /// Perform target-specific instruction verification.
1348
  virtual bool verifyInstruction(const MachineInstr &MI,
1349
4.64M
                                 StringRef &ErrInfo) const {
1350
4.64M
    return true;
1351
4.64M
  }
1352
1353
  /// Return the current execution domain and bit mask of
1354
  /// possible domains for instruction.
1355
  ///
1356
  /// Some micro-architectures have multiple execution domains, and multiple
1357
  /// opcodes that perform the same operation in different domains.  For
1358
  /// example, the x86 architecture provides the por, orps, and orpd
1359
  /// instructions that all do the same thing.  There is a latency penalty if a
1360
  /// register is written in one domain and read in another.
1361
  ///
1362
  /// This function returns a pair (domain, mask) containing the execution
1363
  /// domain of MI, and a bit mask of possible domains.  The setExecutionDomain
1364
  /// function can be used to change the opcode to one of the domains in the
1365
  /// bit mask.  Instructions whose execution domain can't be changed should
1366
  /// return a 0 mask.
1367
  ///
1368
  /// The execution domain numbers don't have any special meaning except domain
1369
  /// 0 is used for instructions that are not associated with any interesting
1370
  /// execution domain.
1371
  ///
1372
  virtual std::pair<uint16_t, uint16_t>
1373
0
  getExecutionDomain(const MachineInstr &MI) const {
1374
0
    return std::make_pair(0, 0);
1375
0
  }
1376
1377
  /// Change the opcode of MI to execute in Domain.
1378
  ///
1379
  /// The bit (1 << Domain) must be set in the mask returned from
1380
  /// getExecutionDomain(MI).
1381
0
  virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
1382
1383
  /// Returns the preferred minimum clearance
1384
  /// before an instruction with an unwanted partial register update.
1385
  ///
1386
  /// Some instructions only write part of a register, and implicitly need to
1387
  /// read the other parts of the register.  This may cause unwanted stalls
1388
  /// preventing otherwise unrelated instructions from executing in parallel in
1389
  /// an out-of-order CPU.
1390
  ///
1391
  /// For example, the x86 instruction cvtsi2ss writes its result to bits
1392
  /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1393
  /// the instruction needs to wait for the old value of the register to become
1394
  /// available:
1395
  ///
1396
  ///   addps %xmm1, %xmm0
1397
  ///   movaps %xmm0, (%rax)
1398
  ///   cvtsi2ss %rbx, %xmm0
1399
  ///
1400
  /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1401
  /// instruction before it can issue, even though the high bits of %xmm0
1402
  /// probably aren't needed.
1403
  ///
1404
  /// This hook returns the preferred clearance before MI, measured in
1405
  /// instructions.  Other defs of MI's operand OpNum are avoided in the last N
1406
  /// instructions before MI.  It should only return a positive value for
1407
  /// unwanted dependencies.  If the old bits of the defined register have
1408
  /// useful values, or if MI is determined to otherwise read the dependency,
1409
  /// the hook should return 0.
1410
  ///
1411
  /// The unwanted dependency may be handled by:
1412
  ///
1413
  /// 1. Allocating the same register for an MI def and use.  That makes the
1414
  ///    unwanted dependency identical to a required dependency.
1415
  ///
1416
  /// 2. Allocating a register for the def that has no defs in the previous N
1417
  ///    instructions.
1418
  ///
1419
  /// 3. Calling breakPartialRegDependency() with the same arguments.  This
1420
  ///    allows the target to insert a dependency breaking instruction.
1421
  ///
1422
  virtual unsigned
1423
  getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
1424
0
                               const TargetRegisterInfo *TRI) const {
1425
0
    // The default implementation returns 0 for no partial register dependency.
1426
0
    return 0;
1427
0
  }
1428
1429
  /// \brief Return the minimum clearance before an instruction that reads an
1430
  /// unused register.
1431
  ///
1432
  /// For example, AVX instructions may copy part of a register operand into
1433
  /// the unused high bits of the destination register.
1434
  ///
1435
  /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
1436
  ///
1437
  /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1438
  /// false dependence on any previous write to %xmm0.
1439
  ///
1440
  /// This hook works similarly to getPartialRegUpdateClearance, except that it
1441
  /// does not take an operand index. Instead sets \p OpNum to the index of the
1442
  /// unused register.
1443
  virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
1444
676k
                                        const TargetRegisterInfo *TRI) const {
1445
676k
    // The default implementation returns 0 for no undef register dependency.
1446
676k
    return 0;
1447
676k
  }
1448
1449
  /// Insert a dependency-breaking instruction
1450
  /// before MI to eliminate an unwanted dependency on OpNum.
1451
  ///
1452
  /// If it wasn't possible to avoid a def in the last N instructions before MI
1453
  /// (see getPartialRegUpdateClearance), this hook will be called to break the
1454
  /// unwanted dependency.
1455
  ///
1456
  /// On x86, an xorps instruction can be used as a dependency breaker:
1457
  ///
1458
  ///   addps %xmm1, %xmm0
1459
  ///   movaps %xmm0, (%rax)
1460
  ///   xorps %xmm0, %xmm0
1461
  ///   cvtsi2ss %rbx, %xmm0
1462
  ///
1463
  /// An <imp-kill> operand should be added to MI if an instruction was
1464
  /// inserted.  This ties the instructions together in the post-ra scheduler.
1465
  ///
1466
  virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
1467
0
                                         const TargetRegisterInfo *TRI) const {}
1468
1469
  /// Create machine specific model for scheduling.
1470
  virtual DFAPacketizer *
1471
0
  CreateTargetScheduleState(const TargetSubtargetInfo &) const {
1472
0
    return nullptr;
1473
0
  }
1474
1475
  /// Sometimes, it is possible for the target
1476
  /// to tell, even without aliasing information, that two MIs access different
1477
  /// memory addresses. This function returns true if two MIs access different
1478
  /// memory addresses and false otherwise.
1479
  ///
1480
  /// Assumes any physical registers used to compute addresses have the same
1481
  /// value for both instructions. (This is the most useful assumption for
1482
  /// post-RA scheduling.)
1483
  ///
1484
  /// See also MachineInstr::mayAlias, which is implemented on top of this
1485
  /// function.
1486
  virtual bool
1487
  areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
1488
1.28M
                                  AliasAnalysis *AA = nullptr) const {
1489
1.28M
    assert((MIa.mayLoad() || MIa.mayStore()) &&
1490
1.28M
           "MIa must load from or modify a memory location");
1491
1.28M
    assert((MIb.mayLoad() || MIb.mayStore()) &&
1492
1.28M
           "MIb must load from or modify a memory location");
1493
1.28M
    return false;
1494
1.28M
  }
1495
1496
  /// \brief Return the value to use for the MachineCSE's LookAheadLimit,
1497
  /// which is a heuristic used for CSE'ing phys reg defs.
1498
393k
  virtual unsigned getMachineCSELookAheadLimit() const {
1499
393k
    // The default lookahead is small to prevent unprofitable quadratic
1500
393k
    // behavior.
1501
393k
    return 5;
1502
393k
  }
1503
1504
  /// Return an array that contains the ids of the target indices (used for the
1505
  /// TargetIndex machine operand) and their names.
1506
  ///
1507
  /// MIR Serialization is able to serialize only the target indices that are
1508
  /// defined by this method.
1509
  virtual ArrayRef<std::pair<int, const char *>>
1510
0
  getSerializableTargetIndices() const {
1511
0
    return None;
1512
0
  }
1513
1514
  /// Decompose the machine operand's target flags into two values - the direct
1515
  /// target flag value and any of bit flags that are applied.
1516
  virtual std::pair<unsigned, unsigned>
1517
12
  decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
1518
12
    return std::make_pair(0u, 0u);
1519
12
  }
1520
1521
  /// Return an array that contains the direct target flag values and their
1522
  /// names.
1523
  ///
1524
  /// MIR Serialization is able to serialize only the target flags that are
1525
  /// defined by this method.
1526
  virtual ArrayRef<std::pair<unsigned, const char *>>
1527
0
  getSerializableDirectMachineOperandTargetFlags() const {
1528
0
    return None;
1529
0
  }
1530
1531
  /// Return an array that contains the bitmask target flag values and their
1532
  /// names.
1533
  ///
1534
  /// MIR Serialization is able to serialize only the target flags that are
1535
  /// defined by this method.
1536
  virtual ArrayRef<std::pair<unsigned, const char *>>
1537
1
  getSerializableBitmaskMachineOperandTargetFlags() const {
1538
1
    return None;
1539
1
  }
1540
1541
  /// Return an array that contains the MMO target flag values and their
1542
  /// names.
1543
  ///
1544
  /// MIR Serialization is able to serialize only the MMO target flags that are
1545
  /// defined by this method.
1546
  virtual ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
1547
0
  getSerializableMachineMemOperandTargetFlags() const {
1548
0
    return None;
1549
0
  }
1550
1551
  /// Determines whether \p Inst is a tail call instruction. Override this
1552
  /// method on targets that do not properly set MCID::Return and MCID::Call on
1553
  /// tail call instructions."
1554
209
  virtual bool isTailCall(const MachineInstr &Inst) const {
1555
209
    return Inst.isReturn() && 
Inst.isCall()89
;
1556
209
  }
1557
1558
  /// True if the instruction is bound to the top of its basic block and no
1559
  /// other instructions shall be inserted before it. This can be implemented
1560
  /// to prevent register allocator to insert spills before such instructions.
1561
496k
  virtual bool isBasicBlockPrologue(const MachineInstr &MI) const {
1562
496k
    return false;
1563
496k
  }
1564
1565
  /// \brief Describes the number of instructions that it will take to call and
1566
  /// construct a frame for a given outlining candidate.
1567
  struct MachineOutlinerInfo {
1568
    /// Number of instructions to call an outlined function for this candidate.
1569
    unsigned CallOverhead;
1570
1571
    /// \brief Number of instructions to construct an outlined function frame
1572
    /// for this candidate.
1573
    unsigned FrameOverhead;
1574
1575
    /// \brief Represents the specific instructions that must be emitted to
1576
    /// construct a call to this candidate.
1577
    unsigned CallConstructionID;
1578
1579
    /// \brief Represents the specific instructions that must be emitted to
1580
    /// construct a frame for this candidate's outlined function.
1581
    unsigned FrameConstructionID;
1582
1583
101
    MachineOutlinerInfo() {}
1584
    MachineOutlinerInfo(unsigned CallOverhead, unsigned FrameOverhead,
1585
                        unsigned CallConstructionID,
1586
                        unsigned FrameConstructionID)
1587
        : CallOverhead(CallOverhead), FrameOverhead(FrameOverhead),
1588
          CallConstructionID(CallConstructionID),
1589
45
          FrameConstructionID(FrameConstructionID) {}
1590
  };
1591
1592
  /// \brief Returns a \p MachineOutlinerInfo struct containing target-specific
1593
  /// information for a set of outlining candidates.
1594
  virtual MachineOutlinerInfo getOutlininingCandidateInfo(
1595
      std::vector<
1596
          std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>>
1597
0
          &RepeatedSequenceLocs) const {
1598
0
    llvm_unreachable(
1599
0
        "Target didn't implement TargetInstrInfo::getOutliningOverhead!");
1600
0
  }
1601
1602
  /// Represents how an instruction should be mapped by the outliner.
1603
  /// \p Legal instructions are those which are safe to outline.
1604
  /// \p Illegal instructions are those which cannot be outlined.
1605
  /// \p Invisible instructions are instructions which can be outlined, but
1606
  /// shouldn't actually impact the outlining result.
1607
  enum MachineOutlinerInstrType { Legal, Illegal, Invisible };
1608
1609
  /// Returns how or if \p MI should be outlined.
1610
0
  virtual MachineOutlinerInstrType getOutliningType(MachineInstr &MI) const {
1611
0
    llvm_unreachable(
1612
0
        "Target didn't implement TargetInstrInfo::getOutliningType!");
1613
0
  }
1614
1615
  /// Insert a custom epilogue for outlined functions.
1616
  /// This may be empty, in which case no epilogue or return statement will be
1617
  /// emitted.
1618
  virtual void insertOutlinerEpilogue(MachineBasicBlock &MBB,
1619
                                      MachineFunction &MF,
1620
0
                                      const MachineOutlinerInfo &MInfo) const {
1621
0
    llvm_unreachable(
1622
0
        "Target didn't implement TargetInstrInfo::insertOutlinerEpilogue!");
1623
0
  }
1624
1625
  /// Insert a call to an outlined function into the program.
1626
  /// Returns an iterator to the spot where we inserted the call. This must be
1627
  /// implemented by the target.
1628
  virtual MachineBasicBlock::iterator
1629
  insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
1630
                     MachineBasicBlock::iterator &It, MachineFunction &MF,
1631
0
                     const MachineOutlinerInfo &MInfo) const {
1632
0
    llvm_unreachable(
1633
0
        "Target didn't implement TargetInstrInfo::insertOutlinedCall!");
1634
0
  }
1635
1636
  /// Insert a custom prologue for outlined functions.
1637
  /// This may be empty, in which case no prologue will be emitted.
1638
  virtual void insertOutlinerPrologue(MachineBasicBlock &MBB,
1639
                                      MachineFunction &MF,
1640
0
                                      const MachineOutlinerInfo &MInfo) const {
1641
0
    llvm_unreachable(
1642
0
        "Target didn't implement TargetInstrInfo::insertOutlinerPrologue!");
1643
0
  }
1644
1645
  /// Return true if the function can safely be outlined from.
1646
  /// A function \p MF is considered safe for outlining if an outlined function
1647
  /// produced from instructions in F will produce a program which produces the
1648
  /// same output for any set of given inputs.
1649
  virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
1650
0
                                           bool OutlineFromLinkOnceODRs) const {
1651
0
    llvm_unreachable("Target didn't implement "
1652
0
                     "TargetInstrInfo::isFunctionSafeToOutlineFrom!");
1653
0
  }
1654
1655
private:
1656
  unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
1657
  unsigned CatchRetOpcode;
1658
  unsigned ReturnOpcode;
1659
};
1660
1661
/// \brief Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
1662
template <> struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> {
1663
  using RegInfo = DenseMapInfo<unsigned>;
1664
1665
21.6M
  static inline TargetInstrInfo::RegSubRegPair getEmptyKey() {
1666
21.6M
    return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
1667
21.6M
                                          RegInfo::getEmptyKey());
1668
21.6M
  }
1669
1670
14.2M
  static inline TargetInstrInfo::RegSubRegPair getTombstoneKey() {
1671
14.2M
    return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
1672
14.2M
                                          RegInfo::getTombstoneKey());
1673
14.2M
  }
1674
1675
  /// \brief Reuse getHashValue implementation from
1676
  /// std::pair<unsigned, unsigned>.
1677
10.5M
  static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
1678
10.5M
    std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
1679
10.5M
    return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
1680
10.5M
  }
1681
1682
  static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
1683
43.3M
                      const TargetInstrInfo::RegSubRegPair &RHS) {
1684
43.3M
    return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
1685
25.4M
           RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
1686
43.3M
  }
1687
};
1688
1689
} // end namespace llvm
1690
1691
#endif // LLVM_TARGET_TARGETINSTRINFO_H