Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
Line
Count
Source (jump to first uncovered line)
1
//===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file contains support for writing dwarf debug info into asm files.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "DwarfExpression.h"
14
#include "DwarfCompileUnit.h"
15
#include "llvm/ADT/APInt.h"
16
#include "llvm/ADT/SmallBitVector.h"
17
#include "llvm/BinaryFormat/Dwarf.h"
18
#include "llvm/CodeGen/TargetRegisterInfo.h"
19
#include "llvm/IR/DebugInfoMetadata.h"
20
#include "llvm/Support/ErrorHandling.h"
21
#include <algorithm>
22
#include <cassert>
23
#include <cstdint>
24
25
using namespace llvm;
26
27
4.09k
void DwarfExpression::emitConstu(uint64_t Value) {
28
4.09k
  if (Value < 32)
29
73
    emitOp(dwarf::DW_OP_lit0 + Value);
30
4.01k
  else if (Value == std::numeric_limits<uint64_t>::max()) {
31
0
    // Only do this for 64-bit values as the DWARF expression stack uses
32
0
    // target-address-size values.
33
0
    emitOp(dwarf::DW_OP_lit0);
34
0
    emitOp(dwarf::DW_OP_not);
35
4.01k
  } else {
36
4.01k
    emitOp(dwarf::DW_OP_constu);
37
4.01k
    emitUnsigned(Value);
38
4.01k
  }
39
4.09k
}
40
41
1.54k
void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
42
1.54k
 assert(DwarfReg >= 0 && "invalid negative dwarf register number");
43
1.54k
 assert((isUnknownLocation() || isRegisterLocation()) &&
44
1.54k
        "location description already locked down");
45
1.54k
 LocationKind = Register;
46
1.54k
 if (DwarfReg < 32) {
47
1.50k
   emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
48
1.50k
  } else {
49
38
    emitOp(dwarf::DW_OP_regx, Comment);
50
38
    emitUnsigned(DwarfReg);
51
38
  }
52
1.54k
}
53
54
200
void DwarfExpression::addBReg(int DwarfReg, int Offset) {
55
200
  assert(DwarfReg >= 0 && "invalid negative dwarf register number");
56
200
  assert(!isRegisterLocation() && "location description already locked down");
57
200
  if (DwarfReg < 32) {
58
172
    emitOp(dwarf::DW_OP_breg0 + DwarfReg);
59
172
  } else {
60
28
    emitOp(dwarf::DW_OP_bregx);
61
28
    emitUnsigned(DwarfReg);
62
28
  }
63
200
  emitSigned(Offset);
64
200
}
65
66
489
void DwarfExpression::addFBReg(int Offset) {
67
489
  emitOp(dwarf::DW_OP_fbreg);
68
489
  emitSigned(Offset);
69
489
}
70
71
9.67k
void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
72
9.67k
  if (!SizeInBits)
73
1.53k
    return;
74
8.14k
75
8.14k
  const unsigned SizeOfByte = 8;
76
8.14k
  if (OffsetInBits > 0 || 
SizeInBits % SizeOfByte8.14k
) {
77
5
    emitOp(dwarf::DW_OP_bit_piece);
78
5
    emitUnsigned(SizeInBits);
79
5
    emitUnsigned(OffsetInBits);
80
8.14k
  } else {
81
8.14k
    emitOp(dwarf::DW_OP_piece);
82
8.14k
    unsigned ByteSize = SizeInBits / SizeOfByte;
83
8.14k
    emitUnsigned(ByteSize);
84
8.14k
  }
85
8.14k
  this->OffsetInBits += SizeInBits;
86
8.14k
}
87
88
0
void DwarfExpression::addShr(unsigned ShiftBy) {
89
0
  emitConstu(ShiftBy);
90
0
  emitOp(dwarf::DW_OP_shr);
91
0
}
92
93
5
void DwarfExpression::addAnd(unsigned Mask) {
94
5
  emitConstu(Mask);
95
5
  emitOp(dwarf::DW_OP_and);
96
5
}
97
98
bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
99
2.29k
                                    unsigned MachineReg, unsigned MaxSize) {
100
2.29k
  if (!TRI.isPhysicalRegister(MachineReg)) {
101
30
    if (isFrameRegister(TRI, MachineReg)) {
102
0
      DwarfRegs.push_back({-1, 0, nullptr});
103
0
      return true;
104
0
    }
105
30
    return false;
106
30
  }
107
2.26k
108
2.26k
  int Reg = TRI.getDwarfRegNum(MachineReg, false);
109
2.26k
110
2.26k
  // If this is a valid register number, emit it.
111
2.26k
  if (Reg >= 0) {
112
2.08k
    DwarfRegs.push_back({Reg, 0, nullptr});
113
2.08k
    return true;
114
2.08k
  }
115
181
116
181
  // Walk up the super-register chain until we find a valid number.
117
181
  // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
118
292
  
for (MCSuperRegIterator SR(MachineReg, &TRI); 181
SR.isValid();
++SR111
) {
119
255
    Reg = TRI.getDwarfRegNum(*SR, false);
120
255
    if (Reg >= 0) {
121
144
      unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
122
144
      unsigned Size = TRI.getSubRegIdxSize(Idx);
123
144
      unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
124
144
      DwarfRegs.push_back({Reg, 0, "super-register"});
125
144
      // Use a DW_OP_bit_piece to describe the sub-register.
126
144
      setSubRegisterPiece(Size, RegOffset);
127
144
      return true;
128
144
    }
129
255
  }
130
181
131
181
  // Otherwise, attempt to find a covering set of sub-register numbers.
132
181
  // For example, Q0 on ARM is a composition of D0+D1.
133
181
  unsigned CurPos = 0;
134
37
  // The size of the register in bits.
135
37
  const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
136
37
  unsigned RegSize = TRI.getRegSizeInBits(*RC);
137
37
  // Keep track of the bits in the register we already emitted, so we
138
37
  // can avoid emitting redundant aliasing subregs. Because this is
139
37
  // just doing a greedy scan of all subregisters, it is possible that
140
37
  // this doesn't find a combination of subregisters that fully cover
141
37
  // the register (even though one may exist).
142
37
  SmallBitVector Coverage(RegSize, false);
143
93
  for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); 
++SR56
) {
144
56
    unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
145
56
    unsigned Size = TRI.getSubRegIdxSize(Idx);
146
56
    unsigned Offset = TRI.getSubRegIdxOffset(Idx);
147
56
    Reg = TRI.getDwarfRegNum(*SR, false);
148
56
    if (Reg < 0)
149
24
      continue;
150
32
151
32
    // Intersection between the bits we already emitted and the bits
152
32
    // covered by this subregister.
153
32
    SmallBitVector CurSubReg(RegSize, false);
154
32
    CurSubReg.set(Offset, Offset + Size);
155
32
156
32
    // If this sub-register has a DWARF number and we haven't covered
157
32
    // its range, emit a DWARF piece for it.
158
32
    if (CurSubReg.test(Coverage)) {
159
28
      // Emit a piece for any gap in the coverage.
160
28
      if (Offset > CurPos)
161
0
        DwarfRegs.push_back({-1, Offset - CurPos, "no DWARF register encoding"});
162
28
      DwarfRegs.push_back(
163
28
          {Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"});
164
28
      if (Offset >= MaxSize)
165
0
        break;
166
28
167
28
      // Mark it as emitted.
168
28
      Coverage.set(Offset, Offset + Size);
169
28
      CurPos = Offset + Size;
170
28
    }
171
32
  }
172
37
  // Failed to find any DWARF encoding.
173
37
  if (CurPos == 0)
174
23
    return false;
175
14
  // Found a partial or complete DWARF encoding.
176
14
  if (CurPos < RegSize)
177
0
    DwarfRegs.push_back({-1, RegSize - CurPos, "no DWARF register encoding"});
178
14
  return true;
179
14
}
180
181
4.10k
void DwarfExpression::addStackValue() {
182
4.10k
  if (DwarfVersion >= 4)
183
4.08k
    emitOp(dwarf::DW_OP_stack_value);
184
4.10k
}
185
186
35
void DwarfExpression::addSignedConstant(int64_t Value) {
187
35
  assert(isImplicitLocation() || isUnknownLocation());
188
35
  LocationKind = Implicit;
189
35
  emitOp(dwarf::DW_OP_consts);
190
35
  emitSigned(Value);
191
35
}
192
193
4.04k
void DwarfExpression::addUnsignedConstant(uint64_t Value) {
194
4.04k
  assert(isImplicitLocation() || isUnknownLocation());
195
4.04k
  LocationKind = Implicit;
196
4.04k
  emitConstu(Value);
197
4.04k
}
198
199
6
void DwarfExpression::addUnsignedConstant(const APInt &Value) {
200
6
  assert(isImplicitLocation() || isUnknownLocation());
201
6
  LocationKind = Implicit;
202
6
203
6
  unsigned Size = Value.getBitWidth();
204
6
  const uint64_t *Data = Value.getRawData();
205
6
206
6
  // Chop it up into 64-bit pieces, because that's the maximum that
207
6
  // addUnsignedConstant takes.
208
6
  unsigned Offset = 0;
209
10
  while (Offset < Size) {
210
8
    addUnsignedConstant(*Data++);
211
8
    if (Offset == 0 && 
Size <= 646
)
212
4
      break;
213
4
    addStackValue();
214
4
    addOpPiece(std::min(Size - Offset, 64u), Offset);
215
4
    Offset += 64;
216
4
  }
217
6
}
218
219
bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
220
                                              DIExpressionCursor &ExprCursor,
221
                                              unsigned MachineReg,
222
2.29k
                                              unsigned FragmentOffsetInBits) {
223
2.29k
  auto Fragment = ExprCursor.getFragmentInfo();
224
2.29k
  if (!addMachineReg(TRI, MachineReg, Fragment ? 
Fragment->SizeInBits79
:
~1U2.21k
)) {
225
53
    LocationKind = Unknown;
226
53
    return false;
227
53
  }
228
2.23k
229
2.23k
  bool HasComplexExpression = false;
230
2.23k
  auto Op = ExprCursor.peek();
231
2.23k
  if (Op && 
Op->getOp() != dwarf::DW_OP_LLVM_fragment715
)
232
678
    HasComplexExpression = true;
233
2.23k
234
2.23k
  // If the register can only be described by a complex expression (i.e.,
235
2.23k
  // multiple subregisters) it doesn't safely compose with another complex
236
2.23k
  // expression. For example, it is not possible to apply a DW_OP_deref
237
2.23k
  // operation to multiple DW_OP_pieces.
238
2.23k
  if (HasComplexExpression && 
DwarfRegs.size() > 1678
) {
239
4
    DwarfRegs.clear();
240
4
    LocationKind = Unknown;
241
4
    return false;
242
4
  }
243
2.23k
244
2.23k
  // Handle simple register locations.
245
2.23k
  if (!isMemoryLocation() && 
!HasComplexExpression1.60k
) {
246
1.54k
    for (auto &Reg : DwarfRegs) {
247
1.54k
      if (Reg.DwarfRegNo >= 0)
248
1.54k
        addReg(Reg.DwarfRegNo, Reg.Comment);
249
1.54k
      addOpPiece(Reg.Size);
250
1.54k
    }
251
1.53k
252
1.53k
    if (isEntryValue() && 
DwarfVersion >= 41
)
253
1
      emitOp(dwarf::DW_OP_stack_value);
254
1.53k
255
1.53k
    DwarfRegs.clear();
256
1.53k
    return true;
257
1.53k
  }
258
697
259
697
  // Don't emit locations that cannot be expressed without DW_OP_stack_value.
260
697
  if (DwarfVersion < 4)
261
194
    
if (125
any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool 125
{
262
194
          return Op.getOp() == dwarf::DW_OP_stack_value;
263
194
        })) {
264
8
      DwarfRegs.clear();
265
8
      LocationKind = Unknown;
266
8
      return false;
267
8
    }
268
689
269
689
  assert(DwarfRegs.size() == 1);
270
689
  auto Reg = DwarfRegs[0];
271
689
  bool FBReg = isFrameRegister(TRI, MachineReg);
272
689
  int SignedOffset = 0;
273
689
  assert(Reg.Size == 0 && "subregister has same size as superregister");
274
689
275
689
  // Pattern-match combinations for which more efficient representations exist.
276
689
  // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset].
277
689
  if (Op && 
(Op->getOp() == dwarf::DW_OP_plus_uconst)666
) {
278
576
    SignedOffset = Op->getArg(0);
279
576
    ExprCursor.take();
280
576
  }
281
689
282
689
  // [Reg, DW_OP_constu, Offset, DW_OP_plus]  --> [DW_OP_breg, Offset]
283
689
  // [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset]
284
689
  // If Reg is a subregister we need to mask it out before subtracting.
285
689
  if (Op && 
Op->getOp() == dwarf::DW_OP_constu666
) {
286
54
    auto N = ExprCursor.peekNext();
287
54
    if (N && (N->getOp() == dwarf::DW_OP_plus ||
288
54
             
(53
N->getOp() == dwarf::DW_OP_minus53
&&
!SubRegisterSizeInBits25
))) {
289
25
      int Offset = Op->getArg(0);
290
25
      SignedOffset = (N->getOp() == dwarf::DW_OP_minus) ? 
-Offset24
:
Offset1
;
291
25
      ExprCursor.consume(2);
292
25
    }
293
54
  }
294
689
295
689
  if (FBReg)
296
489
    addFBReg(SignedOffset);
297
200
  else
298
200
    addBReg(Reg.DwarfRegNo, SignedOffset);
299
689
  DwarfRegs.clear();
300
689
  return true;
301
689
}
302
303
1
void DwarfExpression::addEntryValueExpression(DIExpressionCursor &ExprCursor) {
304
1
  auto Op = ExprCursor.take();
305
1
  assert(Op && Op->getOp() == dwarf::DW_OP_entry_value);
306
1
  assert(!isMemoryLocation() &&
307
1
         "We don't support entry values of memory locations yet");
308
1
309
1
  if (DwarfVersion >= 5)
310
1
    emitOp(dwarf::DW_OP_entry_value);
311
0
  else
312
0
    emitOp(dwarf::DW_OP_GNU_entry_value);
313
1
  emitUnsigned(Op->getArg(0));
314
1
}
315
316
/// Assuming a well-formed expression, match "DW_OP_deref* DW_OP_LLVM_fragment?".
317
26
static bool isMemoryLocation(DIExpressionCursor ExprCursor) {
318
27
  while (ExprCursor) {
319
1
    auto Op = ExprCursor.take();
320
1
    switch (Op->getOp()) {
321
1
    case dwarf::DW_OP_deref:
322
1
    case dwarf::DW_OP_LLVM_fragment:
323
1
      break;
324
1
    default:
325
0
      return false;
326
1
    }
327
1
  }
328
26
  return true;
329
26
}
330
331
void DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor,
332
7.10k
                                    unsigned FragmentOffsetInBits) {
333
7.10k
  // If we need to mask out a subregister, do it now, unless the next
334
7.10k
  // operation would emit an OpPiece anyway.
335
7.10k
  auto N = ExprCursor.peek();
336
7.10k
  if (SubRegisterSizeInBits && 
N142
&&
(N->getOp() != dwarf::DW_OP_LLVM_fragment)22
)
337
5
    maskSubRegister();
338
7.10k
339
7.10k
  Optional<DIExpression::ExprOperand> PrevConvertOp = None;
340
7.10k
341
7.40k
  while (ExprCursor) {
342
4.40k
    auto Op = ExprCursor.take();
343
4.40k
    switch (Op->getOp()) {
344
4.40k
    case dwarf::DW_OP_LLVM_fragment: {
345
4.11k
      unsigned SizeInBits = Op->getArg(1);
346
4.11k
      unsigned FragmentOffset = Op->getArg(0);
347
4.11k
      // The fragment offset must have already been adjusted by emitting an
348
4.11k
      // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
349
4.11k
      // location.
350
4.11k
      assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
351
4.11k
352
4.11k
      // If addMachineReg already emitted DW_OP_piece operations to represent
353
4.11k
      // a super-register by splicing together sub-registers, subtract the size
354
4.11k
      // of the pieces that was already emitted.
355
4.11k
      SizeInBits -= OffsetInBits - FragmentOffset;
356
4.11k
357
4.11k
      // If addMachineReg requested a DW_OP_bit_piece to stencil out a
358
4.11k
      // sub-register that is smaller than the current fragment's size, use it.
359
4.11k
      if (SubRegisterSizeInBits)
360
17
        SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
361
4.11k
362
4.11k
      // Emit a DW_OP_stack_value for implicit location descriptions.
363
4.11k
      if (isImplicitLocation())
364
4.03k
        addStackValue();
365
4.11k
366
4.11k
      // Emit the DW_OP_piece.
367
4.11k
      addOpPiece(SizeInBits, SubRegisterOffsetInBits);
368
4.11k
      setSubRegisterPiece(0, 0);
369
4.11k
      // Reset the location description kind.
370
4.11k
      LocationKind = Unknown;
371
4.11k
      return;
372
4.40k
    }
373
4.40k
    case dwarf::DW_OP_plus_uconst:
374
29
      assert(!isRegisterLocation());
375
29
      emitOp(dwarf::DW_OP_plus_uconst);
376
29
      emitUnsigned(Op->getArg(0));
377
29
      break;
378
4.40k
    case dwarf::DW_OP_plus:
379
3
    case dwarf::DW_OP_minus:
380
3
    case dwarf::DW_OP_mul:
381
3
    case dwarf::DW_OP_div:
382
3
    case dwarf::DW_OP_mod:
383
3
    case dwarf::DW_OP_or:
384
3
    case dwarf::DW_OP_and:
385
3
    case dwarf::DW_OP_xor:
386
3
    case dwarf::DW_OP_shl:
387
3
    case dwarf::DW_OP_shr:
388
3
    case dwarf::DW_OP_shra:
389
3
    case dwarf::DW_OP_lit0:
390
3
    case dwarf::DW_OP_not:
391
3
    case dwarf::DW_OP_dup:
392
3
      emitOp(Op->getOp());
393
3
      break;
394
114
    case dwarf::DW_OP_deref:
395
114
      assert(!isRegisterLocation());
396
114
      if (!isMemoryLocation() && 
::isMemoryLocation(ExprCursor)26
)
397
26
        // Turning this into a memory location description makes the deref
398
26
        // implicit.
399
26
        LocationKind = Memory;
400
88
      else
401
88
        emitOp(dwarf::DW_OP_deref);
402
114
      break;
403
45
    case dwarf::DW_OP_constu:
404
45
      assert(!isRegisterLocation());
405
45
      emitConstu(Op->getArg(0));
406
45
      break;
407
12
    case dwarf::DW_OP_LLVM_convert: {
408
12
      unsigned BitSize = Op->getArg(0);
409
12
      dwarf::TypeKind Encoding = static_cast<dwarf::TypeKind>(Op->getArg(1));
410
12
      if (DwarfVersion >= 5) {
411
8
        emitOp(dwarf::DW_OP_convert);
412
8
        // Reuse the base_type if we already have one in this CU otherwise we
413
8
        // create a new one.
414
8
        unsigned I = 0, E = CU.ExprRefedBaseTypes.size();
415
12
        for (; I != E; 
++I4
)
416
4
          if (CU.ExprRefedBaseTypes[I].BitSize == BitSize &&
417
4
              
CU.ExprRefedBaseTypes[I].Encoding == Encoding0
)
418
0
            break;
419
8
420
8
        if (I == E)
421
8
          CU.ExprRefedBaseTypes.emplace_back(BitSize, Encoding);
422
8
423
8
        // If targeting a location-list; simply emit the index into the raw
424
8
        // byte stream as ULEB128, DwarfDebug::emitDebugLocEntry has been
425
8
        // fitted with means to extract it later.
426
8
        // If targeting a inlined DW_AT_location; insert a DIEBaseTypeRef
427
8
        // (containing the index and a resolve mechanism during emit) into the
428
8
        // DIE value list.
429
8
        emitBaseTypeRef(I);
430
8
      } else {
431
4
        if (PrevConvertOp && 
PrevConvertOp->getArg(0) < BitSize2
) {
432
2
          if (Encoding == dwarf::DW_ATE_signed)
433
2
            emitLegacySExt(PrevConvertOp->getArg(0));
434
0
          else if (Encoding == dwarf::DW_ATE_unsigned)
435
0
            emitLegacyZExt(PrevConvertOp->getArg(0));
436
2
          PrevConvertOp = None;
437
2
        } else {
438
2
          PrevConvertOp = Op;
439
2
        }
440
4
      }
441
12
      break;
442
3
    }
443
23
    case dwarf::DW_OP_stack_value:
444
23
      LocationKind = Implicit;
445
23
      break;
446
35
    case dwarf::DW_OP_swap:
447
35
      assert(!isRegisterLocation());
448
35
      emitOp(dwarf::DW_OP_swap);
449
35
      break;
450
35
    case dwarf::DW_OP_xderef:
451
35
      assert(!isRegisterLocation());
452
35
      emitOp(dwarf::DW_OP_xderef);
453
35
      break;
454
3
    case dwarf::DW_OP_deref_size:
455
0
      emitOp(dwarf::DW_OP_deref_size);
456
0
      emitData1(Op->getArg(0));
457
0
      break;
458
3
    case dwarf::DW_OP_LLVM_tag_offset:
459
2
      TagOffset = Op->getArg(0);
460
2
      break;
461
3
    default:
462
0
      llvm_unreachable("unhandled opcode found in expression");
463
4.40k
    }
464
4.40k
  }
465
7.10k
466
7.10k
  
if (2.99k
isImplicitLocation()2.99k
)
467
67
    // Turn this into an implicit location description.
468
67
    addStackValue();
469
2.99k
}
470
471
/// add masking operations to stencil out a subregister.
472
5
void DwarfExpression::maskSubRegister() {
473
5
  assert(SubRegisterSizeInBits && "no subregister was registered");
474
5
  if (SubRegisterOffsetInBits > 0)
475
0
    addShr(SubRegisterOffsetInBits);
476
5
  uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
477
5
  addAnd(Mask);
478
5
}
479
480
3.07k
void DwarfExpression::finalize() {
481
3.07k
  assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
482
3.07k
  // Emit any outstanding DW_OP_piece operations to mask out subregisters.
483
3.07k
  if (SubRegisterSizeInBits == 0)
484
2.94k
    return;
485
127
  // Don't emit a DW_OP_piece for a subregister at offset 0.
486
127
  if (SubRegisterOffsetInBits == 0)
487
126
    return;
488
1
  addOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits);
489
1
}
490
491
6.04k
void DwarfExpression::addFragmentOffset(const DIExpression *Expr) {
492
6.04k
  if (!Expr || 
!Expr->isFragment()6.04k
)
493
1.92k
    return;
494
4.11k
495
4.11k
  uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
496
4.11k
  assert(FragmentOffset >= OffsetInBits &&
497
4.11k
         "overlapping or duplicate fragments");
498
4.11k
  if (FragmentOffset > OffsetInBits)
499
4.01k
    addOpPiece(FragmentOffset - OffsetInBits);
500
4.11k
  OffsetInBits = FragmentOffset;
501
4.11k
}
502
503
2
void DwarfExpression::emitLegacySExt(unsigned FromBits) {
504
2
  // (((X >> (FromBits - 1)) * (~0)) << FromBits) | X
505
2
  emitOp(dwarf::DW_OP_dup);
506
2
  emitOp(dwarf::DW_OP_constu);
507
2
  emitUnsigned(FromBits - 1);
508
2
  emitOp(dwarf::DW_OP_shr);
509
2
  emitOp(dwarf::DW_OP_lit0);
510
2
  emitOp(dwarf::DW_OP_not);
511
2
  emitOp(dwarf::DW_OP_mul);
512
2
  emitOp(dwarf::DW_OP_constu);
513
2
  emitUnsigned(FromBits);
514
2
  emitOp(dwarf::DW_OP_shl);
515
2
  emitOp(dwarf::DW_OP_or);
516
2
}
517
518
0
void DwarfExpression::emitLegacyZExt(unsigned FromBits) {
519
0
  // (X & (1 << FromBits - 1))
520
0
  emitOp(dwarf::DW_OP_constu);
521
0
  emitUnsigned((1ULL << FromBits) - 1);
522
0
  emitOp(dwarf::DW_OP_and);
523
0
}