Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
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//===- DeadMachineInstructionElim.cpp - Remove dead machine instructions --===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This is an extremely simple MachineInstr-level dead-code-elimination pass.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "dead-mi-elimination"
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STATISTIC(NumDeletes,          "Number of dead instructions deleted");
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namespace {
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  class DeadMachineInstructionElim : public MachineFunctionPass {
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    bool runOnMachineFunction(MachineFunction &MF) override;
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    const TargetRegisterInfo *TRI;
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    const MachineRegisterInfo *MRI;
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    const TargetInstrInfo *TII;
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    BitVector LivePhysRegs;
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  public:
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    static char ID; // Pass identification, replacement for typeid
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77.6k
    DeadMachineInstructionElim() : MachineFunctionPass(ID) {
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77.6k
     initializeDeadMachineInstructionElimPass(*PassRegistry::getPassRegistry());
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    }
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    void getAnalysisUsage(AnalysisUsage &AU) const override {
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      AU.setPreservesCFG();
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      MachineFunctionPass::getAnalysisUsage(AU);
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    }
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  private:
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    bool isDead(const MachineInstr *MI) const;
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  };
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}
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char DeadMachineInstructionElim::ID = 0;
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char &llvm::DeadMachineInstructionElimID = DeadMachineInstructionElim::ID;
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INITIALIZE_PASS(DeadMachineInstructionElim, DEBUG_TYPE,
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                "Remove dead machine instructions", false, false)
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51.1M
bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
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51.1M
  // Technically speaking inline asm without side effects and no defs can still
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51.1M
  // be deleted. But there is so much bad inline asm code out there, we should
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  // let them be.
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  if (MI->isInlineAsm())
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38.5k
    return false;
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51.1M
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51.1M
  // Don't delete frame allocation labels.
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  if (MI->getOpcode() == TargetOpcode::LOCAL_ESCAPE)
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    return false;
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51.1M
  // Don't delete instructions with side effects.
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51.1M
  bool SawStore = false;
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  if (!MI->isSafeToMove(nullptr, SawStore) && 
!MI->isPHI()18.4M
)
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    return false;
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33.9M
  // Examine each operand.
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38.9M
  
for (unsigned i = 0, e = MI->getNumOperands(); 33.9M
i != e;
++i4.94M
) {
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    const MachineOperand &MO = MI->getOperand(i);
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    if (MO.isReg() && 
MO.isDef()36.2M
) {
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      unsigned Reg = MO.getReg();
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      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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        // Don't delete live physreg defs, or any reserved register defs.
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        if (LivePhysRegs.test(Reg) || 
MRI->isReserved(Reg)80.1k
)
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          return false;
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      } else {
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        for (const MachineInstr &Use : MRI->use_nodbg_instructions(Reg)) {
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          if (&Use != MI)
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            // This def has a non-debug use. Don't delete the instruction!
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            return false;
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        }
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      }
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    }
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  }
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  // If there are no defs with uses, the instruction is dead.
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return true303k
;
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}
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bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
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  if (skipFunction(MF.getFunction()))
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    return false;
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  bool AnyChanges = false;
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  MRI = &MF.getRegInfo();
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  TRI = MF.getSubtarget().getRegisterInfo();
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  TII = MF.getSubtarget().getInstrInfo();
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  // Loop over all instructions in all blocks, from bottom to top, so that it's
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  // more likely that chains of dependent but ultimately dead instructions will
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  // be cleaned up.
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  for (MachineBasicBlock &MBB : make_range(MF.rbegin(), MF.rend())) {
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    // Start out assuming that reserved registers are live out of this block.
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    LivePhysRegs = MRI->getReservedRegs();
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    // Add live-ins from successors to LivePhysRegs. Normally, physregs are not
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    // live across blocks, but some targets (x86) can have flags live out of a
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    // block.
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    for (MachineBasicBlock::succ_iterator S = MBB.succ_begin(),
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           E = MBB.succ_end(); S != E; 
S++6.56M
)
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      for (const auto &LI : (*S)->liveins())
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        LivePhysRegs.set(LI.PhysReg);
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    // Now scan the instructions and delete dead ones, tracking physreg
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    // liveness as we go.
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    for (MachineBasicBlock::reverse_iterator MII = MBB.rbegin(),
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         MIE = MBB.rend(); MII != MIE; ) {
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      MachineInstr *MI = &*MII++;
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      // If the instruction is dead, delete it!
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      if (isDead(MI)) {
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        LLVM_DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI);
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        // It is possible that some DBG_VALUE instructions refer to this
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        // instruction.  They get marked as undef and will be deleted
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        // in the live debug variable analysis.
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        MI->eraseFromParentAndMarkDBGValuesForRemoval();
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        AnyChanges = true;
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        ++NumDeletes;
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        continue;
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      }
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      // Record the physreg defs.
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for (unsigned i = 0, e = MI->getNumOperands(); 50.8M
i != e;
++i169M
) {
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        const MachineOperand &MO = MI->getOperand(i);
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        if (MO.isReg() && 
MO.isDef()115M
) {
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          unsigned Reg = MO.getReg();
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          if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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            // Check the subreg set, not the alias set, because a def
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            // of a super-register may still be partially live after
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            // this def.
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            for (MCSubRegIterator SR(Reg, TRI,/*IncludeSelf=*/true);
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                 SR.isValid(); 
++SR46.0M
)
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              LivePhysRegs.reset(*SR);
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          }
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        } else if (MO.isRegMask()) {
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          // Register mask of preserved registers. All clobbers are dead.
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          LivePhysRegs.clearBitsNotInMask(MO.getRegMask());
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        }
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      }
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      // Record the physreg uses, after the defs, in case a physreg is
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      // both defined and used in the same instruction.
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      for (unsigned i = 0, e = MI->getNumOperands(); i != e; 
++i169M
) {
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        const MachineOperand &MO = MI->getOperand(i);
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        if (MO.isReg() && 
MO.isUse()115M
) {
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          unsigned Reg = MO.getReg();
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          if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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            for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); 
++AI98.0M
)
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              LivePhysRegs.set(*AI);
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          }
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        }
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      }
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    }
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  }
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  LivePhysRegs.clear();
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  return AnyChanges;
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}