Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp
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//===- llvm/CodeGen/GlobalISel/RegisterBank.cpp - Register Bank --*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the RegisterBank class.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/Config/llvm-config.h"
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#define DEBUG_TYPE "registerbank"
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using namespace llvm;
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const unsigned RegisterBank::InvalidID = UINT_MAX;
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RegisterBank::RegisterBank(
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    unsigned ID, const char *Name, unsigned Size,
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    const uint32_t *CoveredClasses, unsigned NumRegClasses)
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1.33M
    : ID(ID), Name(Name), Size(Size) {
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1.33M
  ContainedRegClasses.resize(NumRegClasses);
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1.33M
  ContainedRegClasses.setBitsInMask(CoveredClasses);
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1.33M
}
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bool RegisterBank::verify(const TargetRegisterInfo &TRI) const {
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  assert(isValid() && "Invalid register bank");
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  for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) {
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    const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
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    if (!covers(RC))
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      continue;
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    // Verify that the register bank covers all the sub classes of the
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    // classes it covers.
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    // Use a different (slow in that case) method than
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    // RegisterBankInfo to find the subclasses of RC, to make sure
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    // both agree on the covers.
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    for (unsigned SubRCId = 0; SubRCId != End; ++SubRCId) {
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      const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId);
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      if (!RC.hasSubClassEq(&SubRC))
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        continue;
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      // Verify that the Size of the register bank is big enough to cover
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      // all the register classes it covers.
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      assert(getSize() >= TRI.getRegSizeInBits(SubRC) &&
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             "Size is not big enough for all the subclasses!");
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      assert(covers(SubRC) && "Not all subclasses are covered");
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    }
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  }
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  return true;
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}
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6.00M
bool RegisterBank::covers(const TargetRegisterClass &RC) const {
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6.00M
  assert(isValid() && "RB hasn't been initialized yet");
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6.00M
  return ContainedRegClasses.test(RC.getID());
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}
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bool RegisterBank::isValid() const {
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  return ID != InvalidID && Name != nullptr && Size != 0 &&
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         // A register bank that does not cover anything is useless.
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         !ContainedRegClasses.empty();
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}
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3.90M
bool RegisterBank::operator==(const RegisterBank &OtherRB) const {
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3.90M
  // There must be only one instance of a given register bank alive
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  // for the whole compilation.
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  // The RegisterBankInfo is supposed to enforce that.
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  assert((OtherRB.getID() != getID() || &OtherRB == this) &&
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         "ID does not uniquely identify a RegisterBank");
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  return &OtherRB == this;
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}
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const {
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  print(dbgs(), /* IsForDebug */ true, TRI);
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}
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#endif
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void RegisterBank::print(raw_ostream &OS, bool IsForDebug,
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                         const TargetRegisterInfo *TRI) const {
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  OS << getName();
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  if (!IsForDebug)
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    return;
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  OS << "(ID:" << getID() << ", Size:" << getSize() << ")\n"
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     << "isValid:" << isValid() << '\n'
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     << "Number of Covered register classes: " << ContainedRegClasses.count()
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     << '\n';
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  // Print all the subclasses if we can.
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  // This register classes may not be properly initialized yet.
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  if (!TRI || ContainedRegClasses.empty())
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    return;
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  assert(ContainedRegClasses.size() == TRI->getNumRegClasses() &&
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         "TRI does not match the initialization process?");
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  bool IsFirst = true;
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  OS << "Covered register classes:\n";
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  for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) {
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    const TargetRegisterClass &RC = *TRI->getRegClass(RCId);
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    if (!covers(RC))
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      continue;
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    if (!IsFirst)
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      OS << ", ";
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    OS << TRI->getRegClassName(&RC);
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    IsFirst = false;
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  }
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}