Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/LiveRangeEdit.cpp
Line
Count
Source (jump to first uncovered line)
1
//===-- LiveRangeEdit.cpp - Basic tools for editing a register live range -===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// The LiveRangeEdit class represents changes done to a virtual register when it
10
// is spilled or split.
11
//===----------------------------------------------------------------------===//
12
13
#include "llvm/CodeGen/LiveRangeEdit.h"
14
#include "llvm/ADT/Statistic.h"
15
#include "llvm/CodeGen/CalcSpillWeights.h"
16
#include "llvm/CodeGen/LiveIntervals.h"
17
#include "llvm/CodeGen/MachineRegisterInfo.h"
18
#include "llvm/CodeGen/TargetInstrInfo.h"
19
#include "llvm/CodeGen/VirtRegMap.h"
20
#include "llvm/Support/Debug.h"
21
#include "llvm/Support/raw_ostream.h"
22
23
using namespace llvm;
24
25
#define DEBUG_TYPE "regalloc"
26
27
STATISTIC(NumDCEDeleted,     "Number of instructions deleted by DCE");
28
STATISTIC(NumDCEFoldedLoads, "Number of single use loads folded after DCE");
29
STATISTIC(NumFracRanges,     "Number of live ranges fractured by DCE");
30
31
0
void LiveRangeEdit::Delegate::anchor() { }
32
33
LiveInterval &LiveRangeEdit::createEmptyIntervalFrom(unsigned OldReg,
34
534k
                                                     bool createSubRanges) {
35
534k
  unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
36
534k
  if (VRM)
37
534k
    VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
38
534k
39
534k
  LiveInterval &LI = LIS.createEmptyInterval(VReg);
40
534k
  if (Parent && !Parent->isSpillable())
41
2
    LI.markNotSpillable();
42
534k
  if (createSubRanges) {
43
401k
    // Create empty subranges if the OldReg's interval has them. Do not create
44
401k
    // the main range here---it will be constructed later after the subranges
45
401k
    // have been finalized.
46
401k
    LiveInterval &OldLI = LIS.getInterval(OldReg);
47
401k
    VNInfo::Allocator &Alloc = LIS.getVNInfoAllocator();
48
401k
    for (LiveInterval::SubRange &S : OldLI.subranges())
49
918
      LI.createSubRange(Alloc, S.LaneMask);
50
401k
  }
51
534k
  return LI;
52
534k
}
53
54
366k
unsigned LiveRangeEdit::createFrom(unsigned OldReg) {
55
366k
  unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
56
366k
  if (VRM) {
57
366k
    VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
58
366k
  }
59
366k
  // FIXME: Getting the interval here actually computes it.
60
366k
  // In theory, this may not be what we want, but in practice
61
366k
  // the createEmptyIntervalFrom API is used when this is not
62
366k
  // the case. Generally speaking we just want to annotate the
63
366k
  // LiveInterval when it gets created but we cannot do that at
64
366k
  // the moment.
65
366k
  if (Parent && !Parent->isSpillable())
66
0
    LIS.getInterval(VReg).markNotSpillable();
67
366k
  return VReg;
68
366k
}
69
70
bool LiveRangeEdit::checkRematerializable(VNInfo *VNI,
71
                                          const MachineInstr *DefMI,
72
707k
                                          AliasAnalysis *aa) {
73
707k
  assert(DefMI && "Missing instruction");
74
707k
  ScannedRemattable = true;
75
707k
  if (!TII.isTriviallyReMaterializable(*DefMI, aa))
76
350k
    return false;
77
357k
  Remattable.insert(VNI);
78
357k
  return true;
79
357k
}
80
81
570k
void LiveRangeEdit::scanRemattable(AliasAnalysis *aa) {
82
756k
  for (VNInfo *VNI : getParent().valnos) {
83
756k
    if (VNI->isUnused())
84
42
      continue;
85
756k
    unsigned Original = VRM->getOriginal(getReg());
86
756k
    LiveInterval &OrigLI = LIS.getInterval(Original);
87
756k
    VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def);
88
756k
    if (!OrigVNI)
89
0
      continue;
90
756k
    MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def);
91
756k
    if (!DefMI)
92
48.9k
      continue;
93
707k
    checkRematerializable(OrigVNI, DefMI, aa);
94
707k
  }
95
570k
  ScannedRemattable = true;
96
570k
}
97
98
570k
bool LiveRangeEdit::anyRematerializable(AliasAnalysis *aa) {
99
570k
  if (!ScannedRemattable)
100
570k
    scanRemattable(aa);
101
570k
  return !Remattable.empty();
102
570k
}
103
104
/// allUsesAvailableAt - Return true if all registers used by OrigMI at
105
/// OrigIdx are also available with the same value at UseIdx.
106
bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
107
                                       SlotIndex OrigIdx,
108
368k
                                       SlotIndex UseIdx) const {
109
368k
  OrigIdx = OrigIdx.getRegSlot(true);
110
368k
  UseIdx = UseIdx.getRegSlot(true);
111
1.29M
  for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; 
++i927k
) {
112
927k
    const MachineOperand &MO = OrigMI->getOperand(i);
113
927k
    if (!MO.isReg() || 
!MO.getReg()411k
||
!MO.readsReg()375k
)
114
921k
      continue;
115
6.30k
116
6.30k
    // We can't remat physreg uses, unless it is a constant.
117
6.30k
    if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
118
5.64k
      if (MRI.isConstantPhysReg(MO.getReg()))
119
5.64k
        continue;
120
0
      return false;
121
0
    }
122
657
123
657
    LiveInterval &li = LIS.getInterval(MO.getReg());
124
657
    const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
125
657
    if (!OVNI)
126
0
      continue;
127
657
128
657
    // Don't allow rematerialization immediately after the original def.
129
657
    // It would be incorrect if OrigMI redefines the register.
130
657
    // See PR14098.
131
657
    if (SlotIndex::isSameInstr(OrigIdx, UseIdx))
132
1
      return false;
133
656
134
656
    if (OVNI != li.getVNInfoAt(UseIdx))
135
156
      return false;
136
656
  }
137
368k
  
return true368k
;
138
368k
}
139
140
bool LiveRangeEdit::canRematerializeAt(Remat &RM, VNInfo *OrigVNI,
141
756k
                                       SlotIndex UseIdx, bool cheapAsAMove) {
142
756k
  assert(ScannedRemattable && "Call anyRematerializable first");
143
756k
144
756k
  // Use scanRemattable info.
145
756k
  if (!Remattable.count(OrigVNI))
146
268k
    return false;
147
487k
148
487k
  // No defining instruction provided.
149
487k
  SlotIndex DefIdx;
150
487k
  assert(RM.OrigMI && "No defining instruction for remattable value");
151
487k
  DefIdx = LIS.getInstructionIndex(*RM.OrigMI);
152
487k
153
487k
  // If only cheap remats were requested, bail out early.
154
487k
  if (cheapAsAMove && 
!TII.isAsCheapAsAMove(*RM.OrigMI)258k
)
155
120k
    return false;
156
367k
157
367k
  // Verify that all used registers are available with the same values.
158
367k
  if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
159
144
    return false;
160
366k
161
366k
  return true;
162
366k
}
163
164
SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB,
165
                                         MachineBasicBlock::iterator MI,
166
                                         unsigned DestReg,
167
                                         const Remat &RM,
168
                                         const TargetRegisterInfo &tri,
169
365k
                                         bool Late) {
170
365k
  assert(RM.OrigMI && "Invalid remat");
171
365k
  TII.reMaterialize(MBB, MI, DestReg, 0, *RM.OrigMI, tri);
172
365k
  // DestReg of the cloned instruction cannot be Dead. Set isDead of DestReg
173
365k
  // to false anyway in case the isDead flag of RM.OrigMI's dest register
174
365k
  // is true.
175
365k
  (*--MI).getOperand(0).setIsDead(false);
176
365k
  Rematted.insert(RM.ParentVNI);
177
365k
  return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot();
178
365k
}
179
180
843k
void LiveRangeEdit::eraseVirtReg(unsigned Reg) {
181
843k
  if (TheDelegate && 
TheDelegate->LRE_CanEraseVirtReg(Reg)843k
)
182
353k
    LIS.removeInterval(Reg);
183
843k
}
184
185
bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
186
73.4k
                               SmallVectorImpl<MachineInstr*> &Dead) {
187
73.4k
  MachineInstr *DefMI = nullptr, *UseMI = nullptr;
188
73.4k
189
73.4k
  // Check that there is a single def and a single use.
190
79.0k
  for (MachineOperand &MO : MRI.reg_nodbg_operands(LI->reg)) {
191
79.0k
    MachineInstr *MI = MO.getParent();
192
79.0k
    if (MO.isDef()) {
193
74.9k
      if (DefMI && 
DefMI != MI1.97k
)
194
1.97k
        return false;
195
72.9k
      if (!MI->canFoldAsLoad())
196
68.3k
        return false;
197
4.67k
      DefMI = MI;
198
4.67k
    } else 
if (4.07k
!MO.isUndef()4.07k
) {
199
4.07k
      if (UseMI && 
UseMI != MI1.47k
)
200
1.38k
        return false;
201
2.69k
      // FIXME: Targets don't know how to fold subreg uses.
202
2.69k
      if (MO.getSubReg())
203
19
        return false;
204
2.67k
      UseMI = MI;
205
2.67k
    }
206
79.0k
  }
207
73.4k
  
if (1.80k
!DefMI1.80k
||
!UseMI1.30k
)
208
599
    return false;
209
1.20k
210
1.20k
  // Since we're moving the DefMI load, make sure we're not extending any live
211
1.20k
  // ranges.
212
1.20k
  if (!allUsesAvailableAt(DefMI, LIS.getInstructionIndex(*DefMI),
213
1.20k
                          LIS.getInstructionIndex(*UseMI)))
214
13
    return false;
215
1.19k
216
1.19k
  // We also need to make sure it is safe to move the load.
217
1.19k
  // Assume there are stores between DefMI and UseMI.
218
1.19k
  bool SawStore = true;
219
1.19k
  if (!DefMI->isSafeToMove(nullptr, SawStore))
220
47
    return false;
221
1.14k
222
1.14k
  LLVM_DEBUG(dbgs() << "Try to fold single def: " << *DefMI
223
1.14k
                    << "       into single use: " << *UseMI);
224
1.14k
225
1.14k
  SmallVector<unsigned, 8> Ops;
226
1.14k
  if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
227
0
    return false;
228
1.14k
229
1.14k
  MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS);
230
1.14k
  if (!FoldMI)
231
952
    return false;
232
194
  LLVM_DEBUG(dbgs() << "                folded: " << *FoldMI);
233
194
  LIS.ReplaceMachineInstrInMaps(*UseMI, *FoldMI);
234
194
  if (UseMI->isCall())
235
0
    UseMI->getMF()->updateCallSiteInfo(UseMI, FoldMI);
236
194
  UseMI->eraseFromParent();
237
194
  DefMI->addRegisterDead(LI->reg, nullptr);
238
194
  Dead.push_back(DefMI);
239
194
  ++NumDCEFoldedLoads;
240
194
  return true;
241
194
}
242
243
bool LiveRangeEdit::useIsKill(const LiveInterval &LI,
244
20.9k
                              const MachineOperand &MO) const {
245
20.9k
  const MachineInstr &MI = *MO.getParent();
246
20.9k
  SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
247
20.9k
  if (LI.Query(Idx).isKill())
248
15.1k
    return true;
249
5.84k
  const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
250
5.84k
  unsigned SubReg = MO.getSubReg();
251
5.84k
  LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
252
5.84k
  for (const LiveInterval::SubRange &S : LI.subranges()) {
253
0
    if ((S.LaneMask & LaneMask).any() && S.Query(Idx).isKill())
254
0
      return true;
255
0
  }
256
5.84k
  return false;
257
5.84k
}
258
259
/// Find all live intervals that need to shrink, then remove the instruction.
260
void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink,
261
646k
                                     AliasAnalysis *AA) {
262
646k
  assert(MI->allDefsAreDead() && "Def isn't really dead");
263
646k
  SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
264
646k
265
646k
  // Never delete a bundled instruction.
266
646k
  if (MI->isBundled()) {
267
2
    return;
268
2
  }
269
646k
  // Never delete inline asm.
270
646k
  if (MI->isInlineAsm()) {
271
0
    LLVM_DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
272
0
    return;
273
0
  }
274
646k
275
646k
  // Use the same criteria as DeadMachineInstructionElim.
276
646k
  bool SawStore = false;
277
646k
  if (!MI->isSafeToMove(nullptr, SawStore)) {
278
0
    LLVM_DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
279
0
    return;
280
0
  }
281
646k
282
646k
  LLVM_DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
283
646k
284
646k
  // Collect virtual registers to be erased after MI is gone.
285
646k
  SmallVector<unsigned, 8> RegsToErase;
286
646k
  bool ReadsPhysRegs = false;
287
646k
  bool isOrigDef = false;
288
646k
  unsigned Dest;
289
646k
  // Only optimize rematerialize case when the instruction has one def, since
290
646k
  // otherwise we could leave some dead defs in the code.  This case is
291
646k
  // extremely rare.
292
646k
  if (VRM && 
MI->getOperand(0).isReg()295k
&&
MI->getOperand(0).isDef()292k
&&
293
646k
      
MI->getDesc().getNumDefs() == 1273k
) {
294
273k
    Dest = MI->getOperand(0).getReg();
295
273k
    unsigned Original = VRM->getOriginal(Dest);
296
273k
    LiveInterval &OrigLI = LIS.getInterval(Original);
297
273k
    VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
298
273k
    // The original live-range may have been shrunk to
299
273k
    // an empty live-range. It happens when it is dead, but
300
273k
    // we still keep it around to be able to rematerialize
301
273k
    // other values that depend on it.
302
273k
    if (OrigVNI)
303
273k
      isOrigDef = SlotIndex::isSameInstr(OrigVNI->def, Idx);
304
273k
  }
305
646k
306
646k
  // Check for live intervals that may shrink
307
646k
  for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
308
2.18M
         MOE = MI->operands_end(); MOI != MOE; 
++MOI1.53M
) {
309
1.53M
    if (!MOI->isReg())
310
754k
      continue;
311
781k
    unsigned Reg = MOI->getReg();
312
781k
    if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
313
68.8k
      // Check if MI reads any unreserved physregs.
314
68.8k
      if (Reg && 
MOI->readsReg()26.1k
&&
!MRI.isReserved(Reg)4.86k
)
315
3
        ReadsPhysRegs = true;
316
68.8k
      else if (MOI->isDef())
317
21.3k
        LIS.removePhysRegDefAt(Reg, Idx);
318
68.8k
      continue;
319
68.8k
    }
320
712k
    LiveInterval &LI = LIS.getInterval(Reg);
321
712k
322
712k
    // Shrink read registers, unless it is likely to be expensive and
323
712k
    // unlikely to change anything. We typically don't want to shrink the
324
712k
    // PIC base register that has lots of uses everywhere.
325
712k
    // Always shrink COPY uses that probably come from live range splitting.
326
712k
    if ((MI->readsVirtualRegister(Reg) && 
(88.1k
MI->isCopy()88.1k
||
MOI->isDef()21.9k
)) ||
327
712k
        
(646k
MOI->readsReg()646k
&&
(21.9k
MRI.hasOneNonDBGUse(Reg)21.9k
||
useIsKill(LI, *MOI)20.9k
)))
328
82.2k
      ToShrink.insert(&LI);
329
712k
330
712k
    // Remove defined value.
331
712k
    if (MOI->isDef()) {
332
624k
      if (TheDelegate && 
LI.getVNInfoAt(Idx) != nullptr624k
)
333
624k
        TheDelegate->LRE_WillShrinkVirtReg(LI.reg);
334
624k
      LIS.removeVRegDefAt(LI, Idx);
335
624k
      if (LI.empty())
336
561k
        RegsToErase.push_back(Reg);
337
624k
    }
338
712k
  }
339
646k
340
646k
  // Currently, we don't support DCE of physreg live ranges. If MI reads
341
646k
  // any unreserved physregs, don't erase the instruction, but turn it into
342
646k
  // a KILL instead. This way, the physreg live ranges don't end up
343
646k
  // dangling.
344
646k
  // FIXME: It would be better to have something like shrinkToUses() for
345
646k
  // physregs. That could potentially enable more DCE and it would free up
346
646k
  // the physreg. It would not happen often, though.
347
646k
  if (ReadsPhysRegs) {
348
3
    MI->setDesc(TII.get(TargetOpcode::KILL));
349
3
    // Remove all operands that aren't physregs.
350
9
    for (unsigned i = MI->getNumOperands(); i; 
--i6
) {
351
6
      const MachineOperand &MO = MI->getOperand(i-1);
352
6
      if (MO.isReg() && TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
353
3
        continue;
354
3
      MI->RemoveOperand(i-1);
355
3
    }
356
3
    LLVM_DEBUG(dbgs() << "Converted physregs to:\t" << *MI);
357
646k
  } else {
358
646k
    // If the dest of MI is an original reg and MI is reMaterializable,
359
646k
    // don't delete the inst. Replace the dest with a new reg, and keep
360
646k
    // the inst for remat of other siblings. The inst is saved in
361
646k
    // LiveRangeEdit::DeadRemats and will be deleted after all the
362
646k
    // allocations of the func are done.
363
646k
    if (isOrigDef && 
DeadRemats132k
&&
TII.isTriviallyReMaterializable(*MI, AA)132k
) {
364
132k
      LiveInterval &NewLI = createEmptyIntervalFrom(Dest, false);
365
132k
      VNInfo *VNI = NewLI.getNextValue(Idx, LIS.getVNInfoAllocator());
366
132k
      NewLI.addSegment(LiveInterval::Segment(Idx, Idx.getDeadSlot(), VNI));
367
132k
      pop_back();
368
132k
      DeadRemats->insert(MI);
369
132k
      const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
370
132k
      MI->substituteRegister(Dest, NewLI.reg, 0, TRI);
371
132k
      MI->getOperand(0).setIsDead(true);
372
513k
    } else {
373
513k
      if (TheDelegate)
374
513k
        TheDelegate->LRE_WillEraseInstruction(MI);
375
513k
      LIS.RemoveMachineInstrFromMaps(*MI);
376
513k
      MI->eraseFromParent();
377
513k
      ++NumDCEDeleted;
378
513k
    }
379
646k
  }
380
646k
381
646k
  // Erase any virtregs that are now empty and unused. There may be <undef>
382
646k
  // uses around. Keep the empty live range in that case.
383
1.20M
  for (unsigned i = 0, e = RegsToErase.size(); i != e; 
++i561k
) {
384
561k
    unsigned Reg = RegsToErase[i];
385
561k
    if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) {
386
560k
      ToShrink.remove(&LIS.getInterval(Reg));
387
560k
      eraseVirtReg(Reg);
388
560k
    }
389
561k
  }
390
646k
}
391
392
void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr *> &Dead,
393
                                      ArrayRef<unsigned> RegsBeingSpilled,
394
685k
                                      AliasAnalysis *AA) {
395
685k
  ToShrinkSet ToShrink;
396
685k
397
759k
  for (;;) {
398
759k
    // Erase all dead defs.
399
1.40M
    while (!Dead.empty())
400
646k
      eliminateDeadDef(Dead.pop_back_val(), ToShrink, AA);
401
759k
402
759k
    if (ToShrink.empty())
403
685k
      break;
404
73.4k
405
73.4k
    // Shrink just one live interval. Then delete new dead defs.
406
73.4k
    LiveInterval *LI = ToShrink.back();
407
73.4k
    ToShrink.pop_back();
408
73.4k
    if (foldAsLoad(LI, Dead))
409
194
      continue;
410
73.2k
    unsigned VReg = LI->reg;
411
73.2k
    if (TheDelegate)
412
73.2k
      TheDelegate->LRE_WillShrinkVirtReg(VReg);
413
73.2k
    if (!LIS.shrinkToUses(LI, &Dead))
414
64.2k
      continue;
415
9.07k
416
9.07k
    // Don't create new intervals for a register being spilled.
417
9.07k
    // The new intervals would have to be spilled anyway so its not worth it.
418
9.07k
    // Also they currently aren't spilled so creating them and not spilling
419
9.07k
    // them results in incorrect code.
420
9.07k
    bool BeingSpilled = false;
421
15.8k
    for (unsigned i = 0, e = RegsBeingSpilled.size(); i != e; 
++i6.74k
) {
422
6.76k
      if (VReg == RegsBeingSpilled[i]) {
423
23
        BeingSpilled = true;
424
23
        break;
425
23
      }
426
6.76k
    }
427
9.07k
428
9.07k
    if (BeingSpilled) 
continue23
;
429
9.05k
430
9.05k
    // LI may have been separated, create new intervals.
431
9.05k
    LI->RenumberValues();
432
9.05k
    SmallVector<LiveInterval*, 8> SplitLIs;
433
9.05k
    LIS.splitSeparateComponents(*LI, SplitLIs);
434
9.05k
    if (!SplitLIs.empty())
435
5.69k
      ++NumFracRanges;
436
9.05k
437
9.05k
    unsigned Original = VRM ? 
VRM->getOriginal(VReg)9.04k
:
03
;
438
9.05k
    for (const LiveInterval *SplitLI : SplitLIs) {
439
8.11k
      // If LI is an original interval that hasn't been split yet, make the new
440
8.11k
      // intervals their own originals instead of referring to LI. The original
441
8.11k
      // interval must contain all the split products, and LI doesn't.
442
8.11k
      if (Original != VReg && Original != 0)
443
8.11k
        VRM->setIsSplitFromReg(SplitLI->reg, Original);
444
8.11k
      if (TheDelegate)
445
8.11k
        TheDelegate->LRE_DidCloneVirtReg(SplitLI->reg, VReg);
446
8.11k
    }
447
9.05k
  }
448
685k
}
449
450
// Keep track of new virtual registers created via
451
// MachineRegisterInfo::createVirtualRegister.
452
void
453
LiveRangeEdit::MRI_NoteNewVirtualRegister(unsigned VReg)
454
960k
{
455
960k
  if (VRM)
456
960k
    VRM->grow();
457
960k
458
960k
  NewRegs.push_back(VReg);
459
960k
}
460
461
void
462
LiveRangeEdit::calculateRegClassAndHint(MachineFunction &MF,
463
                                        const MachineLoopInfo &Loops,
464
457k
                                        const MachineBlockFrequencyInfo &MBFI) {
465
457k
  VirtRegAuxInfo VRAI(MF, LIS, VRM, Loops, MBFI);
466
1.28M
  for (unsigned I = 0, Size = size(); I < Size; 
++I825k
) {
467
825k
    LiveInterval &LI = LIS.getInterval(get(I));
468
825k
    if (MRI.recomputeRegClass(LI.reg))
469
825k
      LLVM_DEBUG({
470
825k
        const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
471
825k
        dbgs() << "Inflated " << printReg(LI.reg) << " to "
472
825k
               << TRI->getRegClassName(MRI.getRegClass(LI.reg)) << '\n';
473
825k
      });
474
825k
    VRAI.calculateSpillWeightAndHint(LI);
475
825k
  }
476
457k
}