Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/LiveStacks.cpp
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//===-- LiveStacks.cpp - Live Stack Slot Analysis -------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the live stack slot analysis pass. It is analogous to
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// live interval analysis except it's analyzing liveness of stack slots rather
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// than registers.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/LiveStacks.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "livestacks"
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char LiveStacks::ID = 0;
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INITIALIZE_PASS_BEGIN(LiveStacks, DEBUG_TYPE,
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                "Live Stack Slot Analysis", false, false)
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INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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INITIALIZE_PASS_END(LiveStacks, DEBUG_TYPE,
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                "Live Stack Slot Analysis", false, false)
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char &llvm::LiveStacksID = LiveStacks::ID;
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void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
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  AU.setPreservesAll();
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  AU.addPreserved<SlotIndexes>();
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  AU.addRequiredTransitive<SlotIndexes>();
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  MachineFunctionPass::getAnalysisUsage(AU);
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}
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void LiveStacks::releaseMemory() {
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  // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
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  VNInfoAllocator.Reset();
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  S2IMap.clear();
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  S2RCMap.clear();
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}
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bool LiveStacks::runOnMachineFunction(MachineFunction &MF) {
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  TRI = MF.getSubtarget().getRegisterInfo();
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  // FIXME: No analysis is being done right now. We are relying on the
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  // register allocators to provide the information.
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  return false;
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}
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LiveInterval &
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LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
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  assert(Slot >= 0 && "Spill slot indice must be >= 0");
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  SS2IntervalMap::iterator I = S2IMap.find(Slot);
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  if (I == S2IMap.end()) {
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    I = S2IMap.emplace(std::piecewise_construct, std::forward_as_tuple(Slot),
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                       std::forward_as_tuple(
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                           TargetRegisterInfo::index2StackSlot(Slot), 0.0F))
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            .first;
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    S2RCMap.insert(std::make_pair(Slot, RC));
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  } else {
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    // Use the largest common subclass register class.
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    const TargetRegisterClass *OldRC = S2RCMap[Slot];
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    S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
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  }
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  return I->second;
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}
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/// print - Implement the dump method.
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void LiveStacks::print(raw_ostream &OS, const Module*) const {
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  OS << "********** INTERVALS **********\n";
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  for (const_iterator I = begin(), E = end(); I != E; ++I) {
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    I->second.print(OS);
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    int Slot = I->first;
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    const TargetRegisterClass *RC = getIntervalRegClass(Slot);
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    if (RC)
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      OS << " [" << TRI->getRegClassName(RC) << "]\n";
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    else
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      OS << " [Unknown]\n";
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  }
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}