Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/MIRPrinter.cpp
Line
Count
Source (jump to first uncovered line)
1
//===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements the class that prints out the LLVM IR and machine
10
// functions using the MIR serialization format.
11
//
12
//===----------------------------------------------------------------------===//
13
14
#include "llvm/CodeGen/MIRPrinter.h"
15
#include "llvm/ADT/DenseMap.h"
16
#include "llvm/ADT/None.h"
17
#include "llvm/ADT/STLExtras.h"
18
#include "llvm/ADT/SmallBitVector.h"
19
#include "llvm/ADT/SmallPtrSet.h"
20
#include "llvm/ADT/SmallVector.h"
21
#include "llvm/ADT/StringRef.h"
22
#include "llvm/ADT/Twine.h"
23
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
24
#include "llvm/CodeGen/MIRYamlMapping.h"
25
#include "llvm/CodeGen/MachineBasicBlock.h"
26
#include "llvm/CodeGen/MachineConstantPool.h"
27
#include "llvm/CodeGen/MachineFrameInfo.h"
28
#include "llvm/CodeGen/MachineFunction.h"
29
#include "llvm/CodeGen/MachineInstr.h"
30
#include "llvm/CodeGen/MachineJumpTableInfo.h"
31
#include "llvm/CodeGen/MachineMemOperand.h"
32
#include "llvm/CodeGen/MachineOperand.h"
33
#include "llvm/CodeGen/MachineRegisterInfo.h"
34
#include "llvm/CodeGen/PseudoSourceValue.h"
35
#include "llvm/CodeGen/TargetInstrInfo.h"
36
#include "llvm/CodeGen/TargetRegisterInfo.h"
37
#include "llvm/CodeGen/TargetSubtargetInfo.h"
38
#include "llvm/CodeGen/TargetFrameLowering.h"
39
#include "llvm/IR/BasicBlock.h"
40
#include "llvm/IR/Constants.h"
41
#include "llvm/IR/DebugInfo.h"
42
#include "llvm/IR/DebugLoc.h"
43
#include "llvm/IR/Function.h"
44
#include "llvm/IR/GlobalValue.h"
45
#include "llvm/IR/IRPrintingPasses.h"
46
#include "llvm/IR/InstrTypes.h"
47
#include "llvm/IR/Instructions.h"
48
#include "llvm/IR/Intrinsics.h"
49
#include "llvm/IR/Module.h"
50
#include "llvm/IR/ModuleSlotTracker.h"
51
#include "llvm/IR/Value.h"
52
#include "llvm/MC/LaneBitmask.h"
53
#include "llvm/MC/MCContext.h"
54
#include "llvm/MC/MCDwarf.h"
55
#include "llvm/MC/MCSymbol.h"
56
#include "llvm/Support/AtomicOrdering.h"
57
#include "llvm/Support/BranchProbability.h"
58
#include "llvm/Support/Casting.h"
59
#include "llvm/Support/CommandLine.h"
60
#include "llvm/Support/ErrorHandling.h"
61
#include "llvm/Support/Format.h"
62
#include "llvm/Support/LowLevelTypeImpl.h"
63
#include "llvm/Support/YAMLTraits.h"
64
#include "llvm/Support/raw_ostream.h"
65
#include "llvm/Target/TargetIntrinsicInfo.h"
66
#include "llvm/Target/TargetMachine.h"
67
#include <algorithm>
68
#include <cassert>
69
#include <cinttypes>
70
#include <cstdint>
71
#include <iterator>
72
#include <string>
73
#include <utility>
74
#include <vector>
75
76
using namespace llvm;
77
78
static cl::opt<bool> SimplifyMIR(
79
    "simplify-mir", cl::Hidden,
80
    cl::desc("Leave out unnecessary information when printing MIR"));
81
82
namespace {
83
84
/// This structure describes how to print out stack object references.
85
struct FrameIndexOperand {
86
  std::string Name;
87
  unsigned ID;
88
  bool IsFixed;
89
90
  FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
91
1.65k
      : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
92
93
  /// Return an ordinary stack object reference.
94
1.04k
  static FrameIndexOperand create(StringRef Name, unsigned ID) {
95
1.04k
    return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
96
1.04k
  }
97
98
  /// Return a fixed stack object reference.
99
615
  static FrameIndexOperand createFixed(unsigned ID) {
100
615
    return FrameIndexOperand("", ID, /*IsFixed=*/true);
101
615
  }
102
};
103
104
} // end anonymous namespace
105
106
namespace llvm {
107
108
/// This class prints out the machine functions using the MIR serialization
109
/// format.
110
class MIRPrinter {
111
  raw_ostream &OS;
112
  DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
113
  /// Maps from stack object indices to operand indices which will be used when
114
  /// printing frame index machine operands.
115
  DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
116
117
public:
118
11.9k
  MIRPrinter(raw_ostream &OS) : OS(OS) {}
119
120
  void print(const MachineFunction &MF);
121
122
  void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
123
               const TargetRegisterInfo *TRI);
124
  void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
125
               const MachineFrameInfo &MFI);
126
  void convert(yaml::MachineFunction &MF,
127
               const MachineConstantPool &ConstantPool);
128
  void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
129
               const MachineJumpTableInfo &JTI);
130
  void convertStackObjects(yaml::MachineFunction &YMF,
131
                           const MachineFunction &MF, ModuleSlotTracker &MST);
132
  void convertCallSiteObjects(yaml::MachineFunction &YMF,
133
                              const MachineFunction &MF,
134
                              ModuleSlotTracker &MST);
135
136
private:
137
  void initRegisterMaskIds(const MachineFunction &MF);
138
};
139
140
/// This class prints out the machine instructions using the MIR serialization
141
/// format.
142
class MIPrinter {
143
  raw_ostream &OS;
144
  ModuleSlotTracker &MST;
145
  const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
146
  const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
147
  /// Synchronization scope names registered with LLVMContext.
148
  SmallVector<StringRef, 8> SSNs;
149
150
  bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
151
  bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
152
153
public:
154
  MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
155
            const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
156
            const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
157
      : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
158
15.6k
        StackObjectOperandMapping(StackObjectOperandMapping) {}
159
160
  void print(const MachineBasicBlock &MBB);
161
162
  void print(const MachineInstr &MI);
163
  void printStackObjectReference(int FrameIndex);
164
  void print(const MachineInstr &MI, unsigned OpIdx,
165
             const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
166
             LLT TypeToPrint, bool PrintDef = true);
167
};
168
169
} // end namespace llvm
170
171
namespace llvm {
172
namespace yaml {
173
174
/// This struct serializes the LLVM IR module.
175
template <> struct BlockScalarTraits<Module> {
176
2.09k
  static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
177
2.09k
    Mod.print(OS, nullptr);
178
2.09k
  }
179
180
0
  static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
181
0
    llvm_unreachable("LLVM Module is supposed to be parsed separately");
182
0
    return "";
183
0
  }
184
};
185
186
} // end namespace yaml
187
} // end namespace llvm
188
189
static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
190
5.48k
                        const TargetRegisterInfo *TRI) {
191
5.48k
  raw_string_ostream OS(Dest.Value);
192
5.48k
  OS << printReg(Reg, TRI);
193
5.48k
}
194
195
11.9k
void MIRPrinter::print(const MachineFunction &MF) {
196
11.9k
  initRegisterMaskIds(MF);
197
11.9k
198
11.9k
  yaml::MachineFunction YamlMF;
199
11.9k
  YamlMF.Name = MF.getName();
200
11.9k
  YamlMF.Alignment = MF.getAlignment();
201
11.9k
  YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
202
11.9k
  YamlMF.HasWinCFI = MF.hasWinCFI();
203
11.9k
204
11.9k
  YamlMF.Legalized = MF.getProperties().hasProperty(
205
11.9k
      MachineFunctionProperties::Property::Legalized);
206
11.9k
  YamlMF.RegBankSelected = MF.getProperties().hasProperty(
207
11.9k
      MachineFunctionProperties::Property::RegBankSelected);
208
11.9k
  YamlMF.Selected = MF.getProperties().hasProperty(
209
11.9k
      MachineFunctionProperties::Property::Selected);
210
11.9k
  YamlMF.FailedISel = MF.getProperties().hasProperty(
211
11.9k
      MachineFunctionProperties::Property::FailedISel);
212
11.9k
213
11.9k
  convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
214
11.9k
  ModuleSlotTracker MST(MF.getFunction().getParent());
215
11.9k
  MST.incorporateFunction(MF.getFunction());
216
11.9k
  convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
217
11.9k
  convertStackObjects(YamlMF, MF, MST);
218
11.9k
  convertCallSiteObjects(YamlMF, MF, MST);
219
11.9k
  if (const auto *ConstantPool = MF.getConstantPool())
220
11.9k
    convert(YamlMF, *ConstantPool);
221
11.9k
  if (const auto *JumpTableInfo = MF.getJumpTableInfo())
222
13
    convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
223
11.9k
224
11.9k
  const TargetMachine &TM = MF.getTarget();
225
11.9k
  YamlMF.MachineFuncInfo =
226
11.9k
      std::unique_ptr<yaml::MachineFunctionInfo>(TM.convertFuncInfoToYAML(MF));
227
11.9k
228
11.9k
  raw_string_ostream StrOS(YamlMF.Body.Value.Value);
229
11.9k
  bool IsNewlineNeeded = false;
230
15.6k
  for (const auto &MBB : MF) {
231
15.6k
    if (IsNewlineNeeded)
232
3.76k
      StrOS << "\n";
233
15.6k
    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
234
15.6k
        .print(MBB);
235
15.6k
    IsNewlineNeeded = true;
236
15.6k
  }
237
11.9k
  StrOS.flush();
238
11.9k
  yaml::Output Out(OS);
239
11.9k
  if (!SimplifyMIR)
240
11.7k
      Out.setWriteDefaultValues(true);
241
11.9k
  Out << YamlMF;
242
11.9k
}
243
244
static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
245
2
                               const TargetRegisterInfo *TRI) {
246
2
  assert(RegMask && "Can't print an empty register mask");
247
2
  OS << StringRef("CustomRegMask(");
248
2
249
2
  bool IsRegInRegMaskFound = false;
250
566
  for (int I = 0, E = TRI->getNumRegs(); I < E; 
I++564
) {
251
564
    // Check whether the register is asserted in regmask.
252
564
    if (RegMask[I / 32] & (1u << (I % 32))) {
253
124
      if (IsRegInRegMaskFound)
254
122
        OS << ',';
255
124
      OS << printReg(I, TRI);
256
124
      IsRegInRegMaskFound = true;
257
124
    }
258
564
  }
259
2
260
2
  OS << ')';
261
2
}
262
263
static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
264
                                const MachineRegisterInfo &RegInfo,
265
68.7k
                                const TargetRegisterInfo *TRI) {
266
68.7k
  raw_string_ostream OS(Dest.Value);
267
68.7k
  OS << printRegClassOrBank(Reg, RegInfo, TRI);
268
68.7k
}
269
270
template <typename T>
271
static void
272
printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo &DebugVar,
273
8
                        T &Object, ModuleSlotTracker &MST) {
274
8
  std::array<std::string *, 3> Outputs{{&Object.DebugVar.Value,
275
8
                                        &Object.DebugExpr.Value,
276
8
                                        &Object.DebugLoc.Value}};
277
8
  std::array<const Metadata *, 3> Metas{{DebugVar.Var,
278
8
                                        DebugVar.Expr,
279
8
                                        DebugVar.Loc}};
280
32
  for (unsigned i = 0; i < 3; 
++i24
) {
281
24
    raw_string_ostream StrOS(*Outputs[i]);
282
24
    Metas[i]->printAsOperand(StrOS, MST);
283
24
  }
284
8
}
MIRPrinter.cpp:void printStackObjectDbgInfo<llvm::yaml::FixedMachineStackObject>(llvm::MachineFunction::VariableDbgInfo const&, llvm::yaml::FixedMachineStackObject&, llvm::ModuleSlotTracker&)
Line
Count
Source
273
2
                        T &Object, ModuleSlotTracker &MST) {
274
2
  std::array<std::string *, 3> Outputs{{&Object.DebugVar.Value,
275
2
                                        &Object.DebugExpr.Value,
276
2
                                        &Object.DebugLoc.Value}};
277
2
  std::array<const Metadata *, 3> Metas{{DebugVar.Var,
278
2
                                        DebugVar.Expr,
279
2
                                        DebugVar.Loc}};
280
8
  for (unsigned i = 0; i < 3; 
++i6
) {
281
6
    raw_string_ostream StrOS(*Outputs[i]);
282
6
    Metas[i]->printAsOperand(StrOS, MST);
283
6
  }
284
2
}
MIRPrinter.cpp:void printStackObjectDbgInfo<llvm::yaml::MachineStackObject>(llvm::MachineFunction::VariableDbgInfo const&, llvm::yaml::MachineStackObject&, llvm::ModuleSlotTracker&)
Line
Count
Source
273
6
                        T &Object, ModuleSlotTracker &MST) {
274
6
  std::array<std::string *, 3> Outputs{{&Object.DebugVar.Value,
275
6
                                        &Object.DebugExpr.Value,
276
6
                                        &Object.DebugLoc.Value}};
277
6
  std::array<const Metadata *, 3> Metas{{DebugVar.Var,
278
6
                                        DebugVar.Expr,
279
6
                                        DebugVar.Loc}};
280
24
  for (unsigned i = 0; i < 3; 
++i18
) {
281
18
    raw_string_ostream StrOS(*Outputs[i]);
282
18
    Metas[i]->printAsOperand(StrOS, MST);
283
18
  }
284
6
}
285
286
void MIRPrinter::convert(yaml::MachineFunction &MF,
287
                         const MachineRegisterInfo &RegInfo,
288
11.9k
                         const TargetRegisterInfo *TRI) {
289
11.9k
  MF.TracksRegLiveness = RegInfo.tracksLiveness();
290
11.9k
291
11.9k
  // Print the virtual register definitions.
292
80.7k
  for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; 
++I68.8k
) {
293
68.8k
    unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
294
68.8k
    yaml::VirtualRegisterDefinition VReg;
295
68.8k
    VReg.ID = I;
296
68.8k
    if (RegInfo.getVRegName(Reg) != "")
297
84
      continue;
298
68.7k
    ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
299
68.7k
    unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
300
68.7k
    if (PreferredReg)
301
257
      printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
302
68.7k
    MF.VirtualRegisters.push_back(VReg);
303
68.7k
  }
304
11.9k
305
11.9k
  // Print the live ins.
306
11.9k
  for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
307
2.63k
    yaml::MachineFunctionLiveIn LiveIn;
308
2.63k
    printRegMIR(LI.first, LiveIn.Register, TRI);
309
2.63k
    if (LI.second)
310
1.70k
      printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
311
2.63k
    MF.LiveIns.push_back(LiveIn);
312
2.63k
  }
313
11.9k
314
11.9k
  // Prints the callee saved registers.
315
11.9k
  if (RegInfo.isUpdatedCSRsInitialized()) {
316
12
    const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
317
12
    std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
318
425
    for (const MCPhysReg *I = CalleeSavedRegs; *I; 
++I413
) {
319
413
      yaml::FlowStringValue Reg;
320
413
      printRegMIR(*I, Reg, TRI);
321
413
      CalleeSavedRegisters.push_back(Reg);
322
413
    }
323
12
    MF.CalleeSavedRegisters = CalleeSavedRegisters;
324
12
  }
325
11.9k
}
326
327
void MIRPrinter::convert(ModuleSlotTracker &MST,
328
                         yaml::MachineFrameInfo &YamlMFI,
329
11.9k
                         const MachineFrameInfo &MFI) {
330
11.9k
  YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
331
11.9k
  YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
332
11.9k
  YamlMFI.HasStackMap = MFI.hasStackMap();
333
11.9k
  YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
334
11.9k
  YamlMFI.StackSize = MFI.getStackSize();
335
11.9k
  YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
336
11.9k
  YamlMFI.MaxAlignment = MFI.getMaxAlignment();
337
11.9k
  YamlMFI.AdjustsStack = MFI.adjustsStack();
338
11.9k
  YamlMFI.HasCalls = MFI.hasCalls();
339
11.9k
  YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
340
11.9k
    ? 
MFI.getMaxCallFrameSize()2.35k
:
~0u9.58k
;
341
11.9k
  YamlMFI.CVBytesOfCalleeSavedRegisters =
342
11.9k
      MFI.getCVBytesOfCalleeSavedRegisters();
343
11.9k
  YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
344
11.9k
  YamlMFI.HasVAStart = MFI.hasVAStart();
345
11.9k
  YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
346
11.9k
  YamlMFI.LocalFrameSize = MFI.getLocalFrameSize();
347
11.9k
  if (MFI.getSavePoint()) {
348
3
    raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
349
3
    StrOS << printMBBReference(*MFI.getSavePoint());
350
3
  }
351
11.9k
  if (MFI.getRestorePoint()) {
352
3
    raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
353
3
    StrOS << printMBBReference(*MFI.getRestorePoint());
354
3
  }
355
11.9k
}
356
357
void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
358
                                     const MachineFunction &MF,
359
11.9k
                                     ModuleSlotTracker &MST) {
360
11.9k
  const MachineFrameInfo &MFI = MF.getFrameInfo();
361
11.9k
  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
362
11.9k
  // Process fixed stack objects.
363
11.9k
  unsigned ID = 0;
364
12.5k
  for (int I = MFI.getObjectIndexBegin(); I < 0; 
++I, ++ID615
) {
365
615
    if (MFI.isDeadObjectIndex(I))
366
0
      continue;
367
615
368
615
    yaml::FixedMachineStackObject YamlObject;
369
615
    YamlObject.ID = ID;
370
615
    YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
371
615
                          ? 
yaml::FixedMachineStackObject::SpillSlot69
372
615
                          : 
yaml::FixedMachineStackObject::DefaultType546
;
373
615
    YamlObject.Offset = MFI.getObjectOffset(I);
374
615
    YamlObject.Size = MFI.getObjectSize(I);
375
615
    YamlObject.Alignment = MFI.getObjectAlignment(I);
376
615
    YamlObject.StackID = (TargetStackID::Value)MFI.getStackID(I);
377
615
    YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
378
615
    YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
379
615
    YMF.FixedStackObjects.push_back(YamlObject);
380
615
    StackObjectOperandMapping.insert(
381
615
        std::make_pair(I, FrameIndexOperand::createFixed(ID)));
382
615
  }
383
11.9k
384
11.9k
  // Process ordinary stack objects.
385
11.9k
  ID = 0;
386
12.9k
  for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; 
++I, ++ID1.05k
) {
387
1.05k
    if (MFI.isDeadObjectIndex(I))
388
8
      continue;
389
1.04k
390
1.04k
    yaml::MachineStackObject YamlObject;
391
1.04k
    YamlObject.ID = ID;
392
1.04k
    if (const auto *Alloca = MFI.getObjectAllocation(I))
393
195
      YamlObject.Name.Value =
394
195
          Alloca->hasName() ? 
Alloca->getName()169
:
"<unnamed alloca>"26
;
395
1.04k
    YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
396
1.04k
                          ? 
yaml::MachineStackObject::SpillSlot725
397
1.04k
                          : MFI.isVariableSizedObjectIndex(I)
398
318
                                ? 
yaml::MachineStackObject::VariableSized10
399
318
                                : 
yaml::MachineStackObject::DefaultType308
;
400
1.04k
    YamlObject.Offset = MFI.getObjectOffset(I);
401
1.04k
    YamlObject.Size = MFI.getObjectSize(I);
402
1.04k
    YamlObject.Alignment = MFI.getObjectAlignment(I);
403
1.04k
    YamlObject.StackID = (TargetStackID::Value)MFI.getStackID(I);
404
1.04k
405
1.04k
    YMF.StackObjects.push_back(YamlObject);
406
1.04k
    StackObjectOperandMapping.insert(std::make_pair(
407
1.04k
        I, FrameIndexOperand::create(YamlObject.Name.Value, ID)));
408
1.04k
  }
409
11.9k
410
11.9k
  for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
411
474
    if (!CSInfo.isSpilledToReg() && 
MFI.isDeadObjectIndex(CSInfo.getFrameIdx())468
)
412
0
      continue;
413
474
414
474
    yaml::StringValue Reg;
415
474
    printRegMIR(CSInfo.getReg(), Reg, TRI);
416
474
    if (!CSInfo.isSpilledToReg()) {
417
468
      auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
418
468
      assert(StackObjectInfo != StackObjectOperandMapping.end() &&
419
468
             "Invalid stack object index");
420
468
      const FrameIndexOperand &StackObject = StackObjectInfo->second;
421
468
      if (StackObject.IsFixed) {
422
55
        YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
423
55
        YMF.FixedStackObjects[StackObject.ID].CalleeSavedRestored =
424
55
          CSInfo.isRestored();
425
413
      } else {
426
413
        YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
427
413
        YMF.StackObjects[StackObject.ID].CalleeSavedRestored =
428
413
          CSInfo.isRestored();
429
413
      }
430
468
    }
431
474
  }
432
12.0k
  for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; 
++I109
) {
433
109
    auto LocalObject = MFI.getLocalFrameObjectMap(I);
434
109
    auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
435
109
    assert(StackObjectInfo != StackObjectOperandMapping.end() &&
436
109
           "Invalid stack object index");
437
109
    const FrameIndexOperand &StackObject = StackObjectInfo->second;
438
109
    assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
439
109
    YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
440
109
  }
441
11.9k
442
11.9k
  // Print the stack object references in the frame information class after
443
11.9k
  // converting the stack objects.
444
11.9k
  if (MFI.hasStackProtectorIndex()) {
445
4
    raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
446
4
    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
447
4
        .printStackObjectReference(MFI.getStackProtectorIndex());
448
4
  }
449
11.9k
450
11.9k
  // Print the debug variable information.
451
11.9k
  for (const MachineFunction::VariableDbgInfo &DebugVar :
452
11.9k
       MF.getVariableDbgInfo()) {
453
8
    auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
454
8
    assert(StackObjectInfo != StackObjectOperandMapping.end() &&
455
8
           "Invalid stack object index");
456
8
    const FrameIndexOperand &StackObject = StackObjectInfo->second;
457
8
    if (StackObject.IsFixed) {
458
2
      auto &Object = YMF.FixedStackObjects[StackObject.ID];
459
2
      printStackObjectDbgInfo(DebugVar, Object, MST);
460
6
    } else {
461
6
      auto &Object = YMF.StackObjects[StackObject.ID];
462
6
      printStackObjectDbgInfo(DebugVar, Object, MST);
463
6
    }
464
8
  }
465
11.9k
}
466
467
void MIRPrinter::convertCallSiteObjects(yaml::MachineFunction &YMF,
468
                                        const MachineFunction &MF,
469
11.9k
                                        ModuleSlotTracker &MST) {
470
11.9k
  const auto *TRI = MF.getSubtarget().getRegisterInfo();
471
11.9k
  for (auto CSInfo : MF.getCallSitesInfo()) {
472
2
    yaml::CallSiteInfo YmlCS;
473
2
    yaml::CallSiteInfo::MachineInstrLoc CallLocation;
474
2
475
2
    // Prepare instruction position.
476
2
    MachineBasicBlock::const_iterator CallI = CSInfo.first->getIterator();
477
2
    CallLocation.BlockNum = CallI->getParent()->getNumber();
478
2
    // Get call instruction offset from the beginning of block.
479
2
    CallLocation.Offset = std::distance(CallI->getParent()->begin(), CallI);
480
2
    YmlCS.CallLocation = CallLocation;
481
2
    // Construct call arguments and theirs forwarding register info.
482
6
    for (auto ArgReg : CSInfo.second) {
483
6
      yaml::CallSiteInfo::ArgRegPair YmlArgReg;
484
6
      YmlArgReg.ArgNo = ArgReg.ArgNo;
485
6
      printRegMIR(ArgReg.Reg, YmlArgReg.Reg, TRI);
486
6
      YmlCS.ArgForwardingRegs.emplace_back(YmlArgReg);
487
6
    }
488
2
    YMF.CallSitesInfo.push_back(YmlCS);
489
2
  }
490
11.9k
491
11.9k
  // Sort call info by position of call instructions.
492
11.9k
  llvm::sort(YMF.CallSitesInfo.begin(), YMF.CallSitesInfo.end(),
493
11.9k
             [](yaml::CallSiteInfo A, yaml::CallSiteInfo B) {
494
0
               if (A.CallLocation.BlockNum == B.CallLocation.BlockNum)
495
0
                 return A.CallLocation.Offset < B.CallLocation.Offset;
496
0
               return A.CallLocation.BlockNum < B.CallLocation.BlockNum;
497
0
             });
498
11.9k
}
499
500
void MIRPrinter::convert(yaml::MachineFunction &MF,
501
11.9k
                         const MachineConstantPool &ConstantPool) {
502
11.9k
  unsigned ID = 0;
503
11.9k
  for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
504
90
    std::string Str;
505
90
    raw_string_ostream StrOS(Str);
506
90
    if (Constant.isMachineConstantPoolEntry()) {
507
8
      Constant.Val.MachineCPVal->print(StrOS);
508
82
    } else {
509
82
      Constant.Val.ConstVal->printAsOperand(StrOS);
510
82
    }
511
90
512
90
    yaml::MachineConstantPoolValue YamlConstant;
513
90
    YamlConstant.ID = ID++;
514
90
    YamlConstant.Value = StrOS.str();
515
90
    YamlConstant.Alignment = Constant.getAlignment();
516
90
    YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry();
517
90
518
90
    MF.Constants.push_back(YamlConstant);
519
90
  }
520
11.9k
}
521
522
void MIRPrinter::convert(ModuleSlotTracker &MST,
523
                         yaml::MachineJumpTable &YamlJTI,
524
13
                         const MachineJumpTableInfo &JTI) {
525
13
  YamlJTI.Kind = JTI.getEntryKind();
526
13
  unsigned ID = 0;
527
18
  for (const auto &Table : JTI.getJumpTables()) {
528
18
    std::string Str;
529
18
    yaml::MachineJumpTable::Entry Entry;
530
18
    Entry.ID = ID++;
531
238
    for (const auto *MBB : Table.MBBs) {
532
238
      raw_string_ostream StrOS(Str);
533
238
      StrOS << printMBBReference(*MBB);
534
238
      Entry.Blocks.push_back(StrOS.str());
535
238
      Str.clear();
536
238
    }
537
18
    YamlJTI.Entries.push_back(Entry);
538
18
  }
539
13
}
540
541
11.9k
void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
542
11.9k
  const auto *TRI = MF.getSubtarget().getRegisterInfo();
543
11.9k
  unsigned I = 0;
544
11.9k
  for (const uint32_t *Mask : TRI->getRegMasks())
545
172k
    RegisterMaskIds.insert(std::make_pair(Mask, I++));
546
11.9k
}
547
548
void llvm::guessSuccessors(const MachineBasicBlock &MBB,
549
                           SmallVectorImpl<MachineBasicBlock*> &Result,
550
24.8k
                           bool &IsFallthrough) {
551
24.8k
  SmallPtrSet<MachineBasicBlock*,8> Seen;
552
24.8k
553
146k
  for (const MachineInstr &MI : MBB) {
554
146k
    if (MI.isPHI())
555
534
      continue;
556
403k
    
for (const MachineOperand &MO : MI.operands())146k
{
557
403k
      if (!MO.isMBB())
558
402k
        continue;
559
985
      MachineBasicBlock *Succ = MO.getMBB();
560
985
      auto RP = Seen.insert(Succ);
561
985
      if (RP.second)
562
978
        Result.push_back(Succ);
563
985
    }
564
146k
  }
565
24.8k
  MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
566
24.8k
  IsFallthrough = I == MBB.end() || 
!I->isBarrier()24.4k
;
567
24.8k
}
568
569
bool
570
15.6k
MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
571
15.6k
  if (MBB.succ_size() <= 1)
572
14.2k
    return true;
573
1.41k
  if (!MBB.hasSuccessorProbabilities())
574
111
    return true;
575
1.29k
576
1.29k
  SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
577
1.29k
                                              MBB.Probs.end());
578
1.29k
  BranchProbability::normalizeProbabilities(Normalized.begin(),
579
1.29k
                                            Normalized.end());
580
1.29k
  SmallVector<BranchProbability,8> Equal(Normalized.size());
581
1.29k
  BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
582
1.29k
583
1.29k
  return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
584
1.29k
}
585
586
12.1k
bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
587
12.1k
  SmallVector<MachineBasicBlock*,8> GuessedSuccs;
588
12.1k
  bool GuessedFallthrough;
589
12.1k
  guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
590
12.1k
  if (GuessedFallthrough) {
591
4.93k
    const MachineFunction &MF = *MBB.getParent();
592
4.93k
    MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
593
4.93k
    if (NextI != MF.end()) {
594
67
      MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
595
67
      if (!is_contained(GuessedSuccs, Next))
596
66
        GuessedSuccs.push_back(Next);
597
67
    }
598
4.93k
  }
599
12.1k
  if (GuessedSuccs.size() != MBB.succ_size())
600
42
    return false;
601
12.1k
  return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
602
12.1k
}
603
604
15.6k
void MIPrinter::print(const MachineBasicBlock &MBB) {
605
15.6k
  assert(MBB.getNumber() >= 0 && "Invalid MBB number");
606
15.6k
  OS << "bb." << MBB.getNumber();
607
15.6k
  bool HasAttributes = false;
608
15.6k
  if (const auto *BB = MBB.getBasicBlock()) {
609
5.85k
    if (BB->hasName()) {
610
3.61k
      OS << "." << BB->getName();
611
3.61k
    } else {
612
2.23k
      HasAttributes = true;
613
2.23k
      OS << " (";
614
2.23k
      int Slot = MST.getLocalSlot(BB);
615
2.23k
      if (Slot == -1)
616
0
        OS << "<ir-block badref>";
617
2.23k
      else
618
2.23k
        OS << (Twine("%ir-block.") + Twine(Slot)).str();
619
2.23k
    }
620
5.85k
  }
621
15.6k
  if (MBB.hasAddressTaken()) {
622
22
    OS << (HasAttributes ? 
", "0
: " (");
623
22
    OS << "address-taken";
624
22
    HasAttributes = true;
625
22
  }
626
15.6k
  if (MBB.isEHPad()) {
627
7
    OS << (HasAttributes ? 
", "0
: " (");
628
7
    OS << "landing-pad";
629
7
    HasAttributes = true;
630
7
  }
631
15.6k
  if (MBB.getAlignment()) {
632
27
    OS << (HasAttributes ? 
", "2
:
" ("25
);
633
27
    OS << "align " << MBB.getAlignment();
634
27
    HasAttributes = true;
635
27
  }
636
15.6k
  if (HasAttributes)
637
2.28k
    OS << ")";
638
15.6k
  OS << ":\n";
639
15.6k
640
15.6k
  bool HasLineAttributes = false;
641
15.6k
  // Print the successors
642
15.6k
  bool canPredictProbs = canPredictBranchProbabilities(MBB);
643
15.6k
  // Even if the list of successors is empty, if we cannot guess it,
644
15.6k
  // we need to print it to tell the parser that the list is empty.
645
15.6k
  // This is needed, because MI model unreachable as empty blocks
646
15.6k
  // with an empty successor list. If the parser would see that
647
15.6k
  // without the successor list, it would guess the code would
648
15.6k
  // fallthrough.
649
15.6k
  if ((!MBB.succ_empty() && 
!SimplifyMIR3.51k
) ||
!canPredictProbs12.1k
||
650
15.6k
      
!canPredictSuccessors(MBB)12.1k
) {
651
3.53k
    OS.indent(2) << "successors: ";
652
8.47k
    for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; 
++I4.94k
) {
653
4.94k
      if (I != MBB.succ_begin())
654
1.45k
        OS << ", ";
655
4.94k
      OS << printMBBReference(**I);
656
4.94k
      if (!SimplifyMIR || 
!canPredictProbs32
)
657
4.91k
        OS << '('
658
4.91k
           << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
659
4.91k
           << ')';
660
4.94k
    }
661
3.53k
    OS << "\n";
662
3.53k
    HasLineAttributes = true;
663
3.53k
  }
664
15.6k
665
15.6k
  // Print the live in registers.
666
15.6k
  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
667
15.6k
  if (MRI.tracksLiveness() && 
!MBB.livein_empty()7.71k
) {
668
5.26k
    const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
669
5.26k
    OS.indent(2) << "liveins: ";
670
5.26k
    bool First = true;
671
12.0k
    for (const auto &LI : MBB.liveins()) {
672
12.0k
      if (!First)
673
6.80k
        OS << ", ";
674
12.0k
      First = false;
675
12.0k
      OS << printReg(LI.PhysReg, &TRI);
676
12.0k
      if (!LI.LaneMask.all())
677
52
        OS << ":0x" << PrintLaneMask(LI.LaneMask);
678
12.0k
    }
679
5.26k
    OS << "\n";
680
5.26k
    HasLineAttributes = true;
681
5.26k
  }
682
15.6k
683
15.6k
  if (HasLineAttributes)
684
7.88k
    OS << "\n";
685
15.6k
  bool IsInBundle = false;
686
114k
  for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; 
++I98.9k
) {
687
98.9k
    const MachineInstr &MI = *I;
688
98.9k
    if (IsInBundle && 
!MI.isInsideBundle()791
) {
689
103
      OS.indent(2) << "}\n";
690
103
      IsInBundle = false;
691
103
    }
692
98.9k
    OS.indent(IsInBundle ? 
4688
:
298.2k
);
693
98.9k
    print(MI);
694
98.9k
    if (!IsInBundle && 
MI.getFlag(MachineInstr::BundledSucc)98.2k
) {
695
484
      OS << " {";
696
484
      IsInBundle = true;
697
484
    }
698
98.9k
    OS << "\n";
699
98.9k
  }
700
15.6k
  if (IsInBundle)
701
381
    OS.indent(2) << "}\n";
702
15.6k
}
703
704
98.9k
void MIPrinter::print(const MachineInstr &MI) {
705
98.9k
  const auto *MF = MI.getMF();
706
98.9k
  const auto &MRI = MF->getRegInfo();
707
98.9k
  const auto &SubTarget = MF->getSubtarget();
708
98.9k
  const auto *TRI = SubTarget.getRegisterInfo();
709
98.9k
  assert(TRI && "Expected target register info");
710
98.9k
  const auto *TII = SubTarget.getInstrInfo();
711
98.9k
  assert(TII && "Expected target instruction info");
712
98.9k
  if (MI.isCFIInstruction())
713
98.9k
    assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
714
98.9k
715
98.9k
  SmallBitVector PrintedTypes(8);
716
98.9k
  bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies();
717
98.9k
  unsigned I = 0, E = MI.getNumOperands();
718
179k
  for (; I < E && 
MI.getOperand(I).isReg()176k
&&
MI.getOperand(I).isDef()154k
&&
719
179k
         
!MI.getOperand(I).isImplicit()80.9k
;
720
98.9k
       
++I80.6k
) {
721
80.6k
    if (I)
722
3.62k
      OS << ", ";
723
80.6k
    print(MI, I, TRI, ShouldPrintRegisterTies,
724
80.6k
          MI.getTypeToPrint(I, PrintedTypes, MRI),
725
80.6k
          /*PrintDef=*/false);
726
80.6k
  }
727
98.9k
728
98.9k
  if (I)
729
76.9k
    OS << " = ";
730
98.9k
  if (MI.getFlag(MachineInstr::FrameSetup))
731
773
    OS << "frame-setup ";
732
98.9k
  if (MI.getFlag(MachineInstr::FrameDestroy))
733
221
    OS << "frame-destroy ";
734
98.9k
  if (MI.getFlag(MachineInstr::FmNoNans))
735
133
    OS << "nnan ";
736
98.9k
  if (MI.getFlag(MachineInstr::FmNoInfs))
737
56
    OS << "ninf ";
738
98.9k
  if (MI.getFlag(MachineInstr::FmNsz))
739
63
    OS << "nsz ";
740
98.9k
  if (MI.getFlag(MachineInstr::FmArcp))
741
43
    OS << "arcp ";
742
98.9k
  if (MI.getFlag(MachineInstr::FmContract))
743
44
    OS << "contract ";
744
98.9k
  if (MI.getFlag(MachineInstr::FmAfn))
745
40
    OS << "afn ";
746
98.9k
  if (MI.getFlag(MachineInstr::FmReassoc))
747
44
    OS << "reassoc ";
748
98.9k
  if (MI.getFlag(MachineInstr::NoUWrap))
749
21
    OS << "nuw ";
750
98.9k
  if (MI.getFlag(MachineInstr::NoSWrap))
751
67
    OS << "nsw ";
752
98.9k
  if (MI.getFlag(MachineInstr::IsExact))
753
1
    OS << "exact ";
754
98.9k
  if (MI.getFlag(MachineInstr::FPExcept))
755
0
    OS << "fpexcept ";
756
98.9k
757
98.9k
  OS << TII->getName(MI.getOpcode());
758
98.9k
  if (I < E)
759
96.0k
    OS << ' ';
760
98.9k
761
98.9k
  bool NeedComma = false;
762
302k
  for (; I < E; 
++I203k
) {
763
203k
    if (NeedComma)
764
107k
      OS << ", ";
765
203k
    print(MI, I, TRI, ShouldPrintRegisterTies,
766
203k
          MI.getTypeToPrint(I, PrintedTypes, MRI));
767
203k
    NeedComma = true;
768
203k
  }
769
98.9k
770
98.9k
  // Print any optional symbols attached to this instruction as-if they were
771
98.9k
  // operands.
772
98.9k
  if (MCSymbol *PreInstrSymbol = MI.getPreInstrSymbol()) {
773
2
    if (NeedComma)
774
2
      OS << ',';
775
2
    OS << " pre-instr-symbol ";
776
2
    MachineOperand::printSymbol(OS, *PreInstrSymbol);
777
2
    NeedComma = true;
778
2
  }
779
98.9k
  if (MCSymbol *PostInstrSymbol = MI.getPostInstrSymbol()) {
780
2
    if (NeedComma)
781
2
      OS << ',';
782
2
    OS << " post-instr-symbol ";
783
2
    MachineOperand::printSymbol(OS, *PostInstrSymbol);
784
2
    NeedComma = true;
785
2
  }
786
98.9k
787
98.9k
  if (const DebugLoc &DL = MI.getDebugLoc()) {
788
1.73k
    if (NeedComma)
789
1.72k
      OS << ',';
790
1.73k
    OS << " debug-location ";
791
1.73k
    DL->printAsOperand(OS, MST);
792
1.73k
  }
793
98.9k
794
98.9k
  if (!MI.memoperands_empty()) {
795
6.66k
    OS << " :: ";
796
6.66k
    const LLVMContext &Context = MF->getFunction().getContext();
797
6.66k
    const MachineFrameInfo &MFI = MF->getFrameInfo();
798
6.66k
    bool NeedComma = false;
799
6.89k
    for (const auto *Op : MI.memoperands()) {
800
6.89k
      if (NeedComma)
801
235
        OS << ", ";
802
6.89k
      Op->print(OS, MST, SSNs, Context, &MFI, TII);
803
6.89k
      NeedComma = true;
804
6.89k
    }
805
6.66k
  }
806
98.9k
}
807
808
1.07k
void MIPrinter::printStackObjectReference(int FrameIndex) {
809
1.07k
  auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
810
1.07k
  assert(ObjectInfo != StackObjectOperandMapping.end() &&
811
1.07k
         "Invalid frame index");
812
1.07k
  const FrameIndexOperand &Operand = ObjectInfo->second;
813
1.07k
  MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
814
1.07k
                                            Operand.Name);
815
1.07k
}
816
817
void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
818
                      const TargetRegisterInfo *TRI,
819
                      bool ShouldPrintRegisterTies, LLT TypeToPrint,
820
284k
                      bool PrintDef) {
821
284k
  const MachineOperand &Op = MI.getOperand(OpIdx);
822
284k
  switch (Op.getType()) {
823
284k
  case MachineOperand::MO_Immediate:
824
44.7k
    if (MI.isOperandSubregIdx(OpIdx)) {
825
1.54k
      MachineOperand::printTargetFlags(OS, Op);
826
1.54k
      MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
827
1.54k
      break;
828
1.54k
    }
829
43.1k
    LLVM_FALLTHROUGH;
830
280k
  case MachineOperand::MO_Register:
831
280k
  case MachineOperand::MO_CImmediate:
832
280k
  case MachineOperand::MO_FPImmediate:
833
280k
  case MachineOperand::MO_MachineBasicBlock:
834
280k
  case MachineOperand::MO_ConstantPoolIndex:
835
280k
  case MachineOperand::MO_TargetIndex:
836
280k
  case MachineOperand::MO_JumpTableIndex:
837
280k
  case MachineOperand::MO_ExternalSymbol:
838
280k
  case MachineOperand::MO_GlobalAddress:
839
280k
  case MachineOperand::MO_RegisterLiveOut:
840
280k
  case MachineOperand::MO_Metadata:
841
280k
  case MachineOperand::MO_MCSymbol:
842
280k
  case MachineOperand::MO_CFIIndex:
843
280k
  case MachineOperand::MO_IntrinsicID:
844
280k
  case MachineOperand::MO_Predicate:
845
280k
  case MachineOperand::MO_BlockAddress: {
846
280k
    unsigned TiedOperandIdx = 0;
847
280k
    if (ShouldPrintRegisterTies && 
Op.isReg()73
&&
Op.isTied()47
&&
!Op.isDef()28
)
848
14
      TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
849
280k
    const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
850
280k
    Op.print(OS, MST, TypeToPrint, PrintDef, /*IsStandalone=*/false,
851
280k
             ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII);
852
280k
    break;
853
280k
  }
854
280k
  case MachineOperand::MO_FrameIndex:
855
1.07k
    printStackObjectReference(Op.getIndex());
856
1.07k
    break;
857
280k
  case MachineOperand::MO_RegisterMask: {
858
985
    auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
859
985
    if (RegMaskInfo != RegisterMaskIds.end())
860
983
      OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
861
2
    else
862
2
      printCustomRegMask(Op.getRegMask(), OS, TRI);
863
985
    break;
864
280k
  }
865
284k
  }
866
284k
}
867
868
2.09k
void llvm::printMIR(raw_ostream &OS, const Module &M) {
869
2.09k
  yaml::Output Out(OS);
870
2.09k
  Out << const_cast<Module &>(M);
871
2.09k
}
872
873
11.9k
void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
874
11.9k
  MIRPrinter Printer(OS);
875
11.9k
  Printer.print(MF);
876
11.9k
}