Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/MachineOperand.cpp
Line
Count
Source (jump to first uncovered line)
1
//===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
/// \file Methods common to all machine operands.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "llvm/CodeGen/MachineOperand.h"
14
#include "llvm/ADT/StringExtras.h"
15
#include "llvm/Analysis/Loads.h"
16
#include "llvm/Analysis/MemoryLocation.h"
17
#include "llvm/CodeGen/MIRPrinter.h"
18
#include "llvm/CodeGen/MachineFrameInfo.h"
19
#include "llvm/CodeGen/MachineJumpTableInfo.h"
20
#include "llvm/CodeGen/MachineRegisterInfo.h"
21
#include "llvm/CodeGen/TargetInstrInfo.h"
22
#include "llvm/CodeGen/TargetRegisterInfo.h"
23
#include "llvm/Config/llvm-config.h"
24
#include "llvm/IR/Constants.h"
25
#include "llvm/IR/IRPrintingPasses.h"
26
#include "llvm/IR/ModuleSlotTracker.h"
27
#include "llvm/MC/MCDwarf.h"
28
#include "llvm/Target/TargetIntrinsicInfo.h"
29
#include "llvm/Target/TargetMachine.h"
30
31
using namespace llvm;
32
33
static cl::opt<int>
34
    PrintRegMaskNumRegs("print-regmask-num-regs",
35
                        cl::desc("Number of registers to limit to when "
36
                                 "printing regmask operands in IR dumps. "
37
                                 "unlimited = -1"),
38
                        cl::init(32), cl::Hidden);
39
40
43.1M
static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
41
43.1M
  if (const MachineInstr *MI = MO.getParent())
42
43.1M
    if (const MachineBasicBlock *MBB = MI->getParent())
43
42.1M
      if (const MachineFunction *MF = MBB->getParent())
44
42.1M
        return MF;
45
975k
  return nullptr;
46
975k
}
47
42.7M
static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
48
42.7M
  return const_cast<MachineFunction *>(
49
42.7M
      getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
50
42.7M
}
51
52
53.9M
void MachineOperand::setReg(unsigned Reg) {
53
53.9M
  if (getReg() == Reg)
54
12.3M
    return; // No change.
55
41.6M
56
41.6M
  // Clear the IsRenamable bit to keep it conservatively correct.
57
41.6M
  IsRenamable = false;
58
41.6M
59
41.6M
  // Otherwise, we have to change the register.  If this operand is embedded
60
41.6M
  // into a machine function, we need to update the old and new register's
61
41.6M
  // use/def lists.
62
41.6M
  if (MachineFunction *MF = getMFIfAvailable(*this)) {
63
40.6M
    MachineRegisterInfo &MRI = MF->getRegInfo();
64
40.6M
    MRI.removeRegOperandFromUseList(this);
65
40.6M
    SmallContents.RegNo = Reg;
66
40.6M
    MRI.addRegOperandToUseList(this);
67
40.6M
    return;
68
40.6M
  }
69
975k
70
975k
  // Otherwise, just change the register, no problem.  :)
71
975k
  SmallContents.RegNo = Reg;
72
975k
}
73
74
void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
75
8.74M
                                  const TargetRegisterInfo &TRI) {
76
8.74M
  assert(TargetRegisterInfo::isVirtualRegister(Reg));
77
8.74M
  if (SubIdx && 
getSubReg()1.34M
)
78
30.8k
    SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
79
8.74M
  setReg(Reg);
80
8.74M
  if (SubIdx)
81
1.34M
    setSubReg(SubIdx);
82
8.74M
}
83
84
932k
void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
85
932k
  assert(TargetRegisterInfo::isPhysicalRegister(Reg));
86
932k
  if (getSubReg()) {
87
39.3k
    Reg = TRI.getSubReg(Reg, getSubReg());
88
39.3k
    // Note that getSubReg() may return 0 if the sub-register doesn't exist.
89
39.3k
    // That won't happen in legal code.
90
39.3k
    setSubReg(0);
91
39.3k
    if (isDef())
92
39.2k
      setIsUndef(false);
93
39.3k
  }
94
932k
  setReg(Reg);
95
932k
}
96
97
/// Change a def to a use, or a use to a def.
98
9.61k
void MachineOperand::setIsDef(bool Val) {
99
9.61k
  assert(isReg() && "Wrong MachineOperand accessor");
100
9.61k
  assert((!Val || !isDebug()) && "Marking a debug operation as def");
101
9.61k
  if (IsDef == Val)
102
4.68k
    return;
103
4.93k
  assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
104
4.93k
  // MRI may keep uses and defs in different list positions.
105
4.93k
  if (MachineFunction *MF = getMFIfAvailable(*this)) {
106
4.93k
    MachineRegisterInfo &MRI = MF->getRegInfo();
107
4.93k
    MRI.removeRegOperandFromUseList(this);
108
4.93k
    IsDef = Val;
109
4.93k
    MRI.addRegOperandToUseList(this);
110
4.93k
    return;
111
4.93k
  }
112
1
  IsDef = Val;
113
1
}
114
115
59.3M
bool MachineOperand::isRenamable() const {
116
59.3M
  assert(isReg() && "Wrong MachineOperand accessor");
117
59.3M
  assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
118
59.3M
         "isRenamable should only be checked on physical registers");
119
59.3M
  if (!IsRenamable)
120
32.4M
    return false;
121
26.8M
122
26.8M
  const MachineInstr *MI = getParent();
123
26.8M
  if (!MI)
124
0
    return true;
125
26.8M
126
26.8M
  if (isDef())
127
8.33M
    return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
128
18.5M
129
18.5M
  assert(isUse() && "Reg is not def or use");
130
18.5M
  return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
131
18.5M
}
132
133
23.6M
void MachineOperand::setIsRenamable(bool Val) {
134
23.6M
  assert(isReg() && "Wrong MachineOperand accessor");
135
23.6M
  assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
136
23.6M
         "setIsRenamable should only be called on physical registers");
137
23.6M
  IsRenamable = Val;
138
23.6M
}
139
140
// If this operand is currently a register operand, and if this is in a
141
// function, deregister the operand from the register's use/def list.
142
1.12M
void MachineOperand::removeRegFromUses() {
143
1.12M
  if (!isReg() || 
!isOnRegUseList()158k
)
144
965k
    return;
145
158k
146
158k
  if (MachineFunction *MF = getMFIfAvailable(*this))
147
158k
    MF->getRegInfo().removeRegOperandFromUseList(this);
148
158k
}
149
150
/// ChangeToImmediate - Replace this operand with a new immediate operand of
151
/// the specified value.  If an operand is known to be an immediate already,
152
/// the setImm method should be used.
153
1.09M
void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
154
1.09M
  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
155
1.09M
156
1.09M
  removeRegFromUses();
157
1.09M
158
1.09M
  OpKind = MO_Immediate;
159
1.09M
  Contents.ImmVal = ImmVal;
160
1.09M
}
161
162
0
void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
163
0
  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
164
0
165
0
  removeRegFromUses();
166
0
167
0
  OpKind = MO_FPImmediate;
168
0
  Contents.CFP = FPImm;
169
0
}
170
171
void MachineOperand::ChangeToES(const char *SymName,
172
58
                                unsigned char TargetFlags) {
173
58
  assert((!isReg() || !isTied()) &&
174
58
         "Cannot change a tied operand into an external symbol");
175
58
176
58
  removeRegFromUses();
177
58
178
58
  OpKind = MO_ExternalSymbol;
179
58
  Contents.OffsetedInfo.Val.SymbolName = SymName;
180
58
  setOffset(0); // Offset is always 0.
181
58
  setTargetFlags(TargetFlags);
182
58
}
183
184
void MachineOperand::ChangeToGA(const GlobalValue *GV, int64_t Offset,
185
145
                                unsigned char TargetFlags) {
186
145
  assert((!isReg() || !isTied()) &&
187
145
         "Cannot change a tied operand into a global address");
188
145
189
145
  removeRegFromUses();
190
145
191
145
  OpKind = MO_GlobalAddress;
192
145
  Contents.OffsetedInfo.Val.GV = GV;
193
145
  setOffset(Offset);
194
145
  setTargetFlags(TargetFlags);
195
145
}
196
197
0
void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
198
0
  assert((!isReg() || !isTied()) &&
199
0
         "Cannot change a tied operand into an MCSymbol");
200
0
201
0
  removeRegFromUses();
202
0
203
0
  OpKind = MO_MCSymbol;
204
0
  Contents.Sym = Sym;
205
0
}
206
207
33.0k
void MachineOperand::ChangeToFrameIndex(int Idx) {
208
33.0k
  assert((!isReg() || !isTied()) &&
209
33.0k
         "Cannot change a tied operand into a FrameIndex");
210
33.0k
211
33.0k
  removeRegFromUses();
212
33.0k
213
33.0k
  OpKind = MO_FrameIndex;
214
33.0k
  setIndex(Idx);
215
33.0k
}
216
217
void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
218
1
                                         unsigned char TargetFlags) {
219
1
  assert((!isReg() || !isTied()) &&
220
1
         "Cannot change a tied operand into a FrameIndex");
221
1
222
1
  removeRegFromUses();
223
1
224
1
  OpKind = MO_TargetIndex;
225
1
  setIndex(Idx);
226
1
  setOffset(Offset);
227
1
  setTargetFlags(TargetFlags);
228
1
}
229
230
/// ChangeToRegister - Replace this operand with a new register operand of
231
/// the specified value.  If an operand is known to be an register already,
232
/// the setReg method should be used.
233
void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
234
                                      bool isKill, bool isDead, bool isUndef,
235
913k
                                      bool isDebug) {
236
913k
  MachineRegisterInfo *RegInfo = nullptr;
237
913k
  if (MachineFunction *MF = getMFIfAvailable(*this))
238
913k
    RegInfo = &MF->getRegInfo();
239
913k
  // If this operand is already a register operand, remove it from the
240
913k
  // register's use/def lists.
241
913k
  bool WasReg = isReg();
242
913k
  if (RegInfo && 
WasReg913k
)
243
40.9k
    RegInfo->removeRegOperandFromUseList(this);
244
913k
245
913k
  // Change this to a register and set the reg#.
246
913k
  assert(!(isDead && !isDef) && "Dead flag on non-def");
247
913k
  assert(!(isKill && isDef) && "Kill flag on def");
248
913k
  OpKind = MO_Register;
249
913k
  SmallContents.RegNo = Reg;
250
913k
  SubReg_TargetFlags = 0;
251
913k
  IsDef = isDef;
252
913k
  IsImp = isImp;
253
913k
  IsDeadOrKill = isKill | isDead;
254
913k
  IsRenamable = false;
255
913k
  IsUndef = isUndef;
256
913k
  IsInternalRead = false;
257
913k
  IsEarlyClobber = false;
258
913k
  IsDebug = isDebug;
259
913k
  // Ensure isOnRegUseList() returns false.
260
913k
  Contents.Reg.Prev = nullptr;
261
913k
  // Preserve the tie when the operand was already a register.
262
913k
  if (!WasReg)
263
872k
    TiedTo = 0;
264
913k
265
913k
  // If this operand is embedded in a function, add the operand to the
266
913k
  // register's use/def list.
267
913k
  if (RegInfo)
268
913k
    RegInfo->addRegOperandToUseList(this);
269
913k
}
270
271
/// isIdenticalTo - Return true if this operand is identical to the specified
272
/// operand. Note that this should stay in sync with the hash_value overload
273
/// below.
274
108M
bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
275
108M
  if (getType() != Other.getType() ||
276
108M
      
getTargetFlags() != Other.getTargetFlags()107M
)
277
571k
    return false;
278
107M
279
107M
  switch (getType()) {
280
107M
  case MachineOperand::MO_Register:
281
72.4M
    return getReg() == Other.getReg() && 
isDef() == Other.isDef()68.9M
&&
282
72.4M
           
getSubReg() == Other.getSubReg()68.9M
;
283
107M
  case MachineOperand::MO_Immediate:
284
25.8M
    return getImm() == Other.getImm();
285
107M
  case MachineOperand::MO_CImmediate:
286
5
    return getCImm() == Other.getCImm();
287
107M
  case MachineOperand::MO_FPImmediate:
288
370
    return getFPImm() == Other.getFPImm();
289
107M
  case MachineOperand::MO_MachineBasicBlock:
290
1.62M
    return getMBB() == Other.getMBB();
291
107M
  case MachineOperand::MO_FrameIndex:
292
414k
    return getIndex() == Other.getIndex();
293
107M
  case MachineOperand::MO_ConstantPoolIndex:
294
184k
  case MachineOperand::MO_TargetIndex:
295
184k
    return getIndex() == Other.getIndex() && 
getOffset() == Other.getOffset()171k
;
296
184k
  case MachineOperand::MO_JumpTableIndex:
297
10.2k
    return getIndex() == Other.getIndex();
298
5.30M
  case MachineOperand::MO_GlobalAddress:
299
5.30M
    return getGlobal() == Other.getGlobal() && 
getOffset() == Other.getOffset()3.08M
;
300
184k
  case MachineOperand::MO_ExternalSymbol:
301
6.85k
    return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
302
6.85k
           
getOffset() == Other.getOffset()6.59k
;
303
184k
  case MachineOperand::MO_BlockAddress:
304
158
    return getBlockAddress() == Other.getBlockAddress() &&
305
158
           
getOffset() == Other.getOffset()148
;
306
1.47M
  case MachineOperand::MO_RegisterMask:
307
1.47M
  case MachineOperand::MO_RegisterLiveOut: {
308
1.47M
    // Shallow compare of the two RegMasks
309
1.47M
    const uint32_t *RegMask = getRegMask();
310
1.47M
    const uint32_t *OtherRegMask = Other.getRegMask();
311
1.47M
    if (RegMask == OtherRegMask)
312
1.47M
      return true;
313
0
314
0
    if (const MachineFunction *MF = getMFIfAvailable(*this)) {
315
0
      // Calculate the size of the RegMask
316
0
      const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
317
0
      unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
318
0
319
0
      // Deep compare of the two RegMasks
320
0
      return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
321
0
    }
322
0
    // We don't know the size of the RegMask, so we can't deep compare the two
323
0
    // reg masks.
324
0
    return false;
325
0
  }
326
200k
  case MachineOperand::MO_MCSymbol:
327
200k
    return getMCSymbol() == Other.getMCSymbol();
328
0
  case MachineOperand::MO_CFIIndex:
329
0
    return getCFIIndex() == Other.getCFIIndex();
330
430
  case MachineOperand::MO_Metadata:
331
430
    return getMetadata() == Other.getMetadata();
332
0
  case MachineOperand::MO_IntrinsicID:
333
0
    return getIntrinsicID() == Other.getIntrinsicID();
334
0
  case MachineOperand::MO_Predicate:
335
0
    return getPredicate() == Other.getPredicate();
336
0
  }
337
0
  llvm_unreachable("Invalid machine operand type");
338
0
}
339
340
// Note: this must stay exactly in sync with isIdenticalTo above.
341
81.0M
hash_code llvm::hash_value(const MachineOperand &MO) {
342
81.0M
  switch (MO.getType()) {
343
81.0M
  case MachineOperand::MO_Register:
344
47.2M
    // Register operands don't have target flags.
345
47.2M
    return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
346
81.0M
  case MachineOperand::MO_Immediate:
347
25.0M
    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
348
81.0M
  case MachineOperand::MO_CImmediate:
349
24
    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
350
81.0M
  case MachineOperand::MO_FPImmediate:
351
1.01k
    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
352
81.0M
  case MachineOperand::MO_MachineBasicBlock:
353
1.75M
    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
354
81.0M
  case MachineOperand::MO_FrameIndex:
355
518k
    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
356
81.0M
  case MachineOperand::MO_ConstantPoolIndex:
357
394k
  case MachineOperand::MO_TargetIndex:
358
394k
    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
359
394k
                        MO.getOffset());
360
394k
  case MachineOperand::MO_JumpTableIndex:
361
27.4k
    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
362
394k
  case MachineOperand::MO_ExternalSymbol:
363
6.92k
    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
364
6.92k
                        StringRef(MO.getSymbolName()));
365
6.06M
  case MachineOperand::MO_GlobalAddress:
366
6.06M
    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
367
6.06M
                        MO.getOffset());
368
394k
  case MachineOperand::MO_BlockAddress:
369
504
    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
370
504
                        MO.getOffset());
371
394k
  case MachineOperand::MO_RegisterMask:
372
21
  case MachineOperand::MO_RegisterLiveOut:
373
21
    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
374
21
  case MachineOperand::MO_Metadata:
375
0
    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
376
287
  case MachineOperand::MO_MCSymbol:
377
287
    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
378
21
  case MachineOperand::MO_CFIIndex:
379
0
    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
380
21
  case MachineOperand::MO_IntrinsicID:
381
0
    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
382
21
  case MachineOperand::MO_Predicate:
383
0
    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
384
0
  }
385
0
  llvm_unreachable("Invalid machine operand type");
386
0
}
387
388
// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
389
// it.
390
static void tryToGetTargetInfo(const MachineOperand &MO,
391
                               const TargetRegisterInfo *&TRI,
392
50
                               const TargetIntrinsicInfo *&IntrinsicInfo) {
393
50
  if (const MachineFunction *MF = getMFIfAvailable(MO)) {
394
31
    TRI = MF->getSubtarget().getRegisterInfo();
395
31
    IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
396
31
  }
397
50
}
398
399
2
static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
400
2
  const auto *TII = MF.getSubtarget().getInstrInfo();
401
2
  assert(TII && "expected instruction info");
402
2
  auto Indices = TII->getSerializableTargetIndices();
403
2
  auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
404
2
    return I.first == Index;
405
2
  });
406
2
  if (Found != Indices.end())
407
2
    return Found->second;
408
0
  return nullptr;
409
0
}
410
411
6.06k
static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
412
6.06k
  auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
413
10.5k
  for (const auto &I : Flags) {
414
10.5k
    if (I.first == TF) {
415
6.06k
      return I.second;
416
6.06k
    }
417
10.5k
  }
418
6.06k
  
return nullptr0
;
419
6.06k
}
420
421
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
422
1.17k
                             const TargetRegisterInfo *TRI) {
423
1.17k
  if (!TRI) {
424
0
    OS << "%dwarfreg." << DwarfReg;
425
0
    return;
426
0
  }
427
1.17k
428
1.17k
  int Reg = TRI->getLLVMRegNum(DwarfReg, true);
429
1.17k
  if (Reg == -1) {
430
0
    OS << "<badreg>";
431
0
    return;
432
0
  }
433
1.17k
  OS << printReg(Reg, TRI);
434
1.17k
}
435
436
static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
437
24
                                  ModuleSlotTracker &MST) {
438
24
  OS << "%ir-block.";
439
24
  if (BB.hasName()) {
440
22
    printLLVMNameWithoutPrefix(OS, BB.getName());
441
22
    return;
442
22
  }
443
2
  Optional<int> Slot;
444
2
  if (const Function *F = BB.getParent()) {
445
2
    if (F == MST.getCurrentFunction()) {
446
1
      Slot = MST.getLocalSlot(&BB);
447
1
    } else if (const Module *M = F->getParent()) {
448
1
      ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
449
1
      CustomMST.incorporateFunction(*F);
450
1
      Slot = CustomMST.getLocalSlot(&BB);
451
1
    }
452
2
  }
453
2
  if (Slot)
454
2
    MachineOperand::printIRSlotNumber(OS, *Slot);
455
0
  else
456
0
    OS << "<unknown>";
457
2
}
458
459
static void printIRValueReference(raw_ostream &OS, const Value &V,
460
3.91k
                                  ModuleSlotTracker &MST) {
461
3.91k
  if (isa<GlobalValue>(V)) {
462
263
    V.printAsOperand(OS, /*PrintType=*/false, MST);
463
263
    return;
464
263
  }
465
3.64k
  if (isa<Constant>(V)) {
466
863
    // Machine memory operands can load/store to/from constant value pointers.
467
863
    OS << '`';
468
863
    V.printAsOperand(OS, /*PrintType=*/true, MST);
469
863
    OS << '`';
470
863
    return;
471
863
  }
472
2.78k
  OS << "%ir.";
473
2.78k
  if (V.hasName()) {
474
2.58k
    printLLVMNameWithoutPrefix(OS, V.getName());
475
2.58k
    return;
476
2.58k
  }
477
198
  int Slot = MST.getCurrentFunction() ? MST.getLocalSlot(&V) : 
-10
;
478
198
  MachineOperand::printIRSlotNumber(OS, Slot);
479
198
}
480
481
static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
482
                           SyncScope::ID SSID,
483
9.36k
                           SmallVectorImpl<StringRef> &SSNs) {
484
9.36k
  switch (SSID) {
485
9.36k
  case SyncScope::System:
486
9.25k
    break;
487
9.36k
  default:
488
108
    if (SSNs.empty())
489
101
      Context.getSyncScopeNames(SSNs);
490
108
491
108
    OS << "syncscope(\"";
492
108
    printEscapedString(SSNs[SSID], OS);
493
108
    OS << "\") ";
494
108
    break;
495
9.36k
  }
496
9.36k
}
497
498
static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
499
23
                                        unsigned TMMOFlag) {
500
23
  auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
501
44
  for (const auto &I : Flags) {
502
44
    if (I.first == TMMOFlag) {
503
23
      return I.second;
504
23
    }
505
44
  }
506
23
  
return nullptr0
;
507
23
}
508
509
static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
510
4.05k
                            const MachineFrameInfo *MFI) {
511
4.05k
  StringRef Name;
512
4.05k
  if (MFI) {
513
4.05k
    IsFixed = MFI->isFixedObjectIndex(FrameIndex);
514
4.05k
    if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
515
711
      if (Alloca->hasName())
516
711
        Name = Alloca->getName();
517
4.05k
    if (IsFixed)
518
552
      FrameIndex -= MFI->getObjectIndexBegin();
519
4.05k
  }
520
4.05k
  MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
521
4.05k
}
522
523
void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
524
2.78k
                                    const TargetRegisterInfo *TRI) {
525
2.78k
  OS << "%subreg.";
526
2.78k
  if (TRI)
527
2.78k
    OS << TRI->getSubRegIndexName(Index);
528
1
  else
529
1
    OS << Index;
530
2.78k
}
531
532
void MachineOperand::printTargetFlags(raw_ostream &OS,
533
701k
                                      const MachineOperand &Op) {
534
701k
  if (!Op.getTargetFlags())
535
695k
    return;
536
6.09k
  const MachineFunction *MF = getMFIfAvailable(Op);
537
6.09k
  if (!MF)
538
0
    return;
539
6.09k
540
6.09k
  const auto *TII = MF->getSubtarget().getInstrInfo();
541
6.09k
  assert(TII && "expected instruction info");
542
6.09k
  auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
543
6.09k
  OS << "target-flags(";
544
6.09k
  const bool HasDirectFlags = Flags.first;
545
6.09k
  const bool HasBitmaskFlags = Flags.second;
546
6.09k
  if (!HasDirectFlags && 
!HasBitmaskFlags38
) {
547
0
    OS << "<unknown>) ";
548
0
    return;
549
0
  }
550
6.09k
  if (HasDirectFlags) {
551
6.06k
    if (const auto *Name = getTargetFlagName(TII, Flags.first))
552
6.06k
      OS << Name;
553
0
    else
554
0
      OS << "<unknown target flag>";
555
6.06k
  }
556
6.09k
  if (!HasBitmaskFlags) {
557
3.29k
    OS << ") ";
558
3.29k
    return;
559
3.29k
  }
560
2.80k
  bool IsCommaNeeded = HasDirectFlags;
561
2.80k
  unsigned BitMask = Flags.second;
562
2.80k
  auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
563
16.8k
  for (const auto &Mask : BitMasks) {
564
16.8k
    // Check if the flag's bitmask has the bits of the current mask set.
565
16.8k
    if ((BitMask & Mask.first) == Mask.first) {
566
2.80k
      if (IsCommaNeeded)
567
2.76k
        OS << ", ";
568
2.80k
      IsCommaNeeded = true;
569
2.80k
      OS << Mask.second;
570
2.80k
      // Clear the bits which were serialized from the flag's bitmask.
571
2.80k
      BitMask &= ~(Mask.first);
572
2.80k
    }
573
16.8k
  }
574
2.80k
  if (BitMask) {
575
0
    // When the resulting flag's bitmask isn't zero, we know that we didn't
576
0
    // serialize all of the bit flags.
577
0
    if (IsCommaNeeded)
578
0
      OS << ", ";
579
0
    OS << "<unknown bitmask target flag>";
580
0
  }
581
2.80k
  OS << ") ";
582
2.80k
}
583
584
61
void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
585
61
  OS << "<mcsymbol " << Sym << ">";
586
61
}
587
588
void MachineOperand::printStackObjectReference(raw_ostream &OS,
589
                                               unsigned FrameIndex,
590
5.12k
                                               bool IsFixed, StringRef Name) {
591
5.12k
  if (IsFixed) {
592
1.05k
    OS << "%fixed-stack." << FrameIndex;
593
1.05k
    return;
594
1.05k
  }
595
4.07k
596
4.07k
  OS << "%stack." << FrameIndex;
597
4.07k
  if (!Name.empty())
598
937
    OS << '.' << Name;
599
4.07k
}
600
601
28.9k
void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
602
28.9k
  if (Offset == 0)
603
28.3k
    return;
604
627
  if (Offset < 0) {
605
7
    OS << " - " << -Offset;
606
7
    return;
607
7
  }
608
620
  OS << " + " << Offset;
609
620
}
610
611
200
void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
612
200
  if (Slot == -1)
613
0
    OS << "<badref>";
614
200
  else
615
200
    OS << Slot;
616
200
}
617
618
static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
619
1.80k
                     const TargetRegisterInfo *TRI) {
620
1.80k
  switch (CFI.getOperation()) {
621
1.80k
  case MCCFIInstruction::OpSameValue:
622
3
    OS << "same_value ";
623
3
    if (MCSymbol *Label = CFI.getLabel())
624
0
      MachineOperand::printSymbol(OS, *Label);
625
3
    printCFIRegister(CFI.getRegister(), OS, TRI);
626
3
    break;
627
1.80k
  case MCCFIInstruction::OpRememberState:
628
1
    OS << "remember_state ";
629
1
    if (MCSymbol *Label = CFI.getLabel())
630
0
      MachineOperand::printSymbol(OS, *Label);
631
1
    break;
632
1.80k
  case MCCFIInstruction::OpRestoreState:
633
1
    OS << "restore_state ";
634
1
    if (MCSymbol *Label = CFI.getLabel())
635
0
      MachineOperand::printSymbol(OS, *Label);
636
1
    break;
637
1.80k
  case MCCFIInstruction::OpOffset:
638
1.13k
    OS << "offset ";
639
1.13k
    if (MCSymbol *Label = CFI.getLabel())
640
0
      MachineOperand::printSymbol(OS, *Label);
641
1.13k
    printCFIRegister(CFI.getRegister(), OS, TRI);
642
1.13k
    OS << ", " << CFI.getOffset();
643
1.13k
    break;
644
1.80k
  case MCCFIInstruction::OpDefCfaRegister:
645
14
    OS << "def_cfa_register ";
646
14
    if (MCSymbol *Label = CFI.getLabel())
647
0
      MachineOperand::printSymbol(OS, *Label);
648
14
    printCFIRegister(CFI.getRegister(), OS, TRI);
649
14
    break;
650
1.80k
  case MCCFIInstruction::OpDefCfaOffset:
651
608
    OS << "def_cfa_offset ";
652
608
    if (MCSymbol *Label = CFI.getLabel())
653
7
      MachineOperand::printSymbol(OS, *Label);
654
608
    OS << CFI.getOffset();
655
608
    break;
656
1.80k
  case MCCFIInstruction::OpDefCfa:
657
12
    OS << "def_cfa ";
658
12
    if (MCSymbol *Label = CFI.getLabel())
659
0
      MachineOperand::printSymbol(OS, *Label);
660
12
    printCFIRegister(CFI.getRegister(), OS, TRI);
661
12
    OS << ", " << CFI.getOffset();
662
12
    break;
663
1.80k
  case MCCFIInstruction::OpRelOffset:
664
1
    OS << "rel_offset ";
665
1
    if (MCSymbol *Label = CFI.getLabel())
666
0
      MachineOperand::printSymbol(OS, *Label);
667
1
    printCFIRegister(CFI.getRegister(), OS, TRI);
668
1
    OS << ", " << CFI.getOffset();
669
1
    break;
670
1.80k
  case MCCFIInstruction::OpAdjustCfaOffset:
671
16
    OS << "adjust_cfa_offset ";
672
16
    if (MCSymbol *Label = CFI.getLabel())
673
0
      MachineOperand::printSymbol(OS, *Label);
674
16
    OS << CFI.getOffset();
675
16
    break;
676
1.80k
  case MCCFIInstruction::OpRestore:
677
1
    OS << "restore ";
678
1
    if (MCSymbol *Label = CFI.getLabel())
679
0
      MachineOperand::printSymbol(OS, *Label);
680
1
    printCFIRegister(CFI.getRegister(), OS, TRI);
681
1
    break;
682
1.80k
  case MCCFIInstruction::OpEscape: {
683
1
    OS << "escape ";
684
1
    if (MCSymbol *Label = CFI.getLabel())
685
0
      MachineOperand::printSymbol(OS, *Label);
686
1
    if (!CFI.getValues().empty()) {
687
1
      size_t e = CFI.getValues().size() - 1;
688
3
      for (size_t i = 0; i < e; 
++i2
)
689
2
        OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
690
1
      OS << format("0x%02x", uint8_t(CFI.getValues()[e])) << ", ";
691
1
    }
692
1
    break;
693
1.80k
  }
694
1.80k
  case MCCFIInstruction::OpUndefined:
695
1
    OS << "undefined ";
696
1
    if (MCSymbol *Label = CFI.getLabel())
697
0
      MachineOperand::printSymbol(OS, *Label);
698
1
    printCFIRegister(CFI.getRegister(), OS, TRI);
699
1
    break;
700
1.80k
  case MCCFIInstruction::OpRegister:
701
4
    OS << "register ";
702
4
    if (MCSymbol *Label = CFI.getLabel())
703
0
      MachineOperand::printSymbol(OS, *Label);
704
4
    printCFIRegister(CFI.getRegister(), OS, TRI);
705
4
    OS << ", ";
706
4
    printCFIRegister(CFI.getRegister2(), OS, TRI);
707
4
    break;
708
1.80k
  case MCCFIInstruction::OpWindowSave:
709
1
    OS << "window_save ";
710
1
    if (MCSymbol *Label = CFI.getLabel())
711
0
      MachineOperand::printSymbol(OS, *Label);
712
1
    break;
713
1.80k
  case MCCFIInstruction::OpNegateRAState:
714
3
    OS << "negate_ra_sign_state ";
715
3
    if (MCSymbol *Label = CFI.getLabel())
716
0
      MachineOperand::printSymbol(OS, *Label);
717
3
    break;
718
1.80k
  default:
719
0
    // TODO: Print the other CFI Operations.
720
0
    OS << "<unserializable cfi directive>";
721
0
    break;
722
1.80k
  }
723
1.80k
}
724
725
void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
726
19
                           const TargetIntrinsicInfo *IntrinsicInfo) const {
727
19
  print(OS, LLT{}, TRI, IntrinsicInfo);
728
19
}
729
730
void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
731
                           const TargetRegisterInfo *TRI,
732
50
                           const TargetIntrinsicInfo *IntrinsicInfo) const {
733
50
  tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
734
50
  ModuleSlotTracker DummyMST(nullptr);
735
50
  print(OS, DummyMST, TypeToPrint, /*PrintDef=*/false, /*IsStandalone=*/true,
736
50
        /*ShouldPrintRegisterTies=*/true,
737
50
        /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
738
50
}
739
740
void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
741
                           LLT TypeToPrint, bool PrintDef, bool IsStandalone,
742
                           bool ShouldPrintRegisterTies,
743
                           unsigned TiedOperandIdx,
744
                           const TargetRegisterInfo *TRI,
745
700k
                           const TargetIntrinsicInfo *IntrinsicInfo) const {
746
700k
  printTargetFlags(OS, *this);
747
700k
  switch (getType()) {
748
700k
  case MachineOperand::MO_Register: {
749
467k
    unsigned Reg = getReg();
750
467k
    if (isImplicit())
751
137k
      OS << (isDef() ? 
"implicit-def "46.4k
:
"implicit "91.4k
);
752
329k
    else if (PrintDef && 
isDef()164k
)
753
246
      // Print the 'def' flag only when the operand is defined after '='.
754
246
      OS << "def ";
755
467k
    if (isInternalRead())
756
61
      OS << "internal ";
757
467k
    if (isDead())
758
29.7k
      OS << "dead ";
759
467k
    if (isKill())
760
34.8k
      OS << "killed ";
761
467k
    if (isUndef())
762
2.31k
      OS << "undef ";
763
467k
    if (isEarlyClobber())
764
6.72k
      OS << "early-clobber ";
765
467k
    if (TargetRegisterInfo::isPhysicalRegister(getReg()) && 
isRenamable()264k
)
766
18.2k
      OS << "renamable ";
767
467k
    // isDebug() is exactly true for register operands of a DBG_VALUE. So we
768
467k
    // simply infer it when parsing and do not need to print it.
769
467k
770
467k
    const MachineRegisterInfo *MRI = nullptr;
771
467k
    if (TargetRegisterInfo::isVirtualRegister(Reg)) {
772
190k
      if (const MachineFunction *MF = getMFIfAvailable(*this)) {
773
190k
        MRI = &MF->getRegInfo();
774
190k
      }
775
190k
    }
776
467k
777
467k
    OS << printReg(Reg, TRI, 0, MRI);
778
467k
    // Print the sub register.
779
467k
    if (unsigned SubReg = getSubReg()) {
780
2.95k
      if (TRI)
781
2.95k
        OS << '.' << TRI->getSubRegIndexName(SubReg);
782
1
      else
783
1
        OS << ".subreg" << SubReg;
784
2.95k
    }
785
467k
    // Print the register class / bank.
786
467k
    if (TargetRegisterInfo::isVirtualRegister(Reg)) {
787
190k
      if (const MachineFunction *MF = getMFIfAvailable(*this)) {
788
190k
        const MachineRegisterInfo &MRI = MF->getRegInfo();
789
190k
        if (IsStandalone || 
!PrintDef127k
||
MRI.def_empty(Reg)66.0k
) {
790
125k
          OS << ':';
791
125k
          OS << printRegClassOrBank(Reg, MRI, TRI);
792
125k
        }
793
190k
      }
794
190k
    }
795
467k
    // Print ties.
796
467k
    if (ShouldPrintRegisterTies && 
isTied()243k
&&
!isDef()2.07k
)
797
1.03k
      OS << "(tied-def " << TiedOperandIdx << ")";
798
467k
    // Print types.
799
467k
    if (TypeToPrint.isValid())
800
74.4k
      OS << '(' << TypeToPrint << ')';
801
467k
    break;
802
700k
  }
803
700k
  case MachineOperand::MO_Immediate:
804
155k
    OS << getImm();
805
155k
    break;
806
700k
  case MachineOperand::MO_CImmediate:
807
3.27k
    getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
808
3.27k
    break;
809
700k
  case MachineOperand::MO_FPImmediate:
810
112
    getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
811
112
    break;
812
700k
  case MachineOperand::MO_MachineBasicBlock:
813
21.4k
    OS << printMBBReference(*getMBB());
814
21.4k
    break;
815
700k
  case MachineOperand::MO_FrameIndex: {
816
702
    int FrameIndex = getIndex();
817
702
    bool IsFixed = false;
818
702
    const MachineFrameInfo *MFI = nullptr;
819
702
    if (const MachineFunction *MF = getMFIfAvailable(*this))
820
702
      MFI = &MF->getFrameInfo();
821
702
    printFrameIndex(OS, FrameIndex, IsFixed, MFI);
822
702
    break;
823
700k
  }
824
700k
  case MachineOperand::MO_ConstantPoolIndex:
825
132
    OS << "%const." << getIndex();
826
132
    printOperandOffset(OS, getOffset());
827
132
    break;
828
700k
  case MachineOperand::MO_TargetIndex: {
829
4
    OS << "target-index(";
830
4
    const char *Name = "<unknown>";
831
4
    if (const MachineFunction *MF = getMFIfAvailable(*this))
832
2
      if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex()))
833
2
        Name = TargetIndexName;
834
4
    OS << Name << ')';
835
4
    printOperandOffset(OS, getOffset());
836
4
    break;
837
700k
  }
838
700k
  case MachineOperand::MO_JumpTableIndex:
839
8.18k
    OS << printJumpTableEntryReference(getIndex());
840
8.18k
    break;
841
700k
  case MachineOperand::MO_GlobalAddress:
842
18.5k
    getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
843
18.5k
    printOperandOffset(OS, getOffset());
844
18.5k
    break;
845
700k
  case MachineOperand::MO_ExternalSymbol: {
846
891
    StringRef Name = getSymbolName();
847
891
    OS << '&';
848
891
    if (Name.empty()) {
849
16
      OS << "\"\"";
850
875
    } else {
851
875
      printLLVMNameWithoutPrefix(OS, Name);
852
875
    }
853
891
    printOperandOffset(OS, getOffset());
854
891
    break;
855
700k
  }
856
700k
  case MachineOperand::MO_BlockAddress: {
857
24
    OS << "blockaddress(";
858
24
    getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
859
24
                                                     MST);
860
24
    OS << ", ";
861
24
    printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
862
24
    OS << ')';
863
24
    MachineOperand::printOperandOffset(OS, getOffset());
864
24
    break;
865
700k
  }
866
700k
  case MachineOperand::MO_RegisterMask: {
867
17.1k
    OS << "<regmask";
868
17.1k
    if (TRI) {
869
17.1k
      unsigned NumRegsInMask = 0;
870
17.1k
      unsigned NumRegsEmitted = 0;
871
10.7M
      for (unsigned i = 0; i < TRI->getNumRegs(); 
++i10.7M
) {
872
10.7M
        unsigned MaskWord = i / 32;
873
10.7M
        unsigned MaskBit = i % 32;
874
10.7M
        if (getRegMask()[MaskWord] & (1 << MaskBit)) {
875
1.43M
          if (PrintRegMaskNumRegs < 0 ||
876
1.43M
              NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
877
564k
            OS << " " << printReg(i, TRI);
878
564k
            NumRegsEmitted++;
879
564k
          }
880
1.43M
          NumRegsInMask++;
881
1.43M
        }
882
10.7M
      }
883
17.1k
      if (NumRegsEmitted != NumRegsInMask)
884
17.0k
        OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
885
17.1k
    } else {
886
1
      OS << " ...";
887
1
    }
888
17.1k
    OS << ">";
889
17.1k
    break;
890
700k
  }
891
700k
  case MachineOperand::MO_RegisterLiveOut: {
892
2
    const uint32_t *RegMask = getRegLiveOut();
893
2
    OS << "liveout(";
894
2
    if (!TRI) {
895
1
      OS << "<unknown>";
896
1
    } else {
897
1
      bool IsCommaNeeded = false;
898
283
      for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; 
++Reg282
) {
899
282
        if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
900
4
          if (IsCommaNeeded)
901
3
            OS << ", ";
902
4
          OS << printReg(Reg, TRI);
903
4
          IsCommaNeeded = true;
904
4
        }
905
282
      }
906
1
    }
907
2
    OS << ")";
908
2
    break;
909
700k
  }
910
700k
  case MachineOperand::MO_Metadata:
911
2.93k
    getMetadata()->printAsOperand(OS, MST);
912
2.93k
    break;
913
700k
  case MachineOperand::MO_MCSymbol:
914
50
    printSymbol(OS, *getMCSymbol());
915
50
    break;
916
700k
  case MachineOperand::MO_CFIIndex: {
917
1.80k
    if (const MachineFunction *MF = getMFIfAvailable(*this))
918
1.80k
      printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
919
1
    else
920
1
      OS << "<cfi directive>";
921
1.80k
    break;
922
700k
  }
923
700k
  case MachineOperand::MO_IntrinsicID: {
924
346
    Intrinsic::ID ID = getIntrinsicID();
925
346
    if (ID < Intrinsic::num_intrinsics)
926
345
      OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
927
1
    else if (IntrinsicInfo)
928
0
      OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
929
1
    else
930
1
      OS << "intrinsic(" << ID << ')';
931
346
    break;
932
700k
  }
933
700k
  case MachineOperand::MO_Predicate: {
934
1.53k
    auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
935
1.53k
    OS << (CmpInst::isIntPredicate(Pred) ? 
"int"1.29k
:
"float"240
) << "pred("
936
1.53k
       << CmpInst::getPredicateName(Pred) << ')';
937
1.53k
    break;
938
700k
  }
939
700k
  }
940
700k
}
941
942
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
943
LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
944
#endif
945
946
//===----------------------------------------------------------------------===//
947
// MachineMemOperand Implementation
948
//===----------------------------------------------------------------------===//
949
950
/// getAddrSpace - Return the LLVM IR address space number that this pointer
951
/// points into.
952
16.3M
unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
953
954
/// isDereferenceable - Return true if V is always dereferenceable for
955
/// Offset + Size byte.
956
bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
957
17.9k
                                           const DataLayout &DL) const {
958
17.9k
  if (!V.is<const Value *>())
959
1.21k
    return false;
960
16.7k
961
16.7k
  const Value *BasePtr = V.get<const Value *>();
962
16.7k
  if (BasePtr == nullptr)
963
1.67k
    return false;
964
15.0k
965
15.0k
  return isDereferenceableAndAlignedPointer(
966
15.0k
      BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
967
15.0k
}
968
969
/// getConstantPool - Return a MachinePointerInfo record that refers to the
970
/// constant pool.
971
73.6k
MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
972
73.6k
  return MachinePointerInfo(MF.getPSVManager().getConstantPool());
973
73.6k
}
974
975
/// getFixedStack - Return a MachinePointerInfo record that refers to the
976
/// the specified FrameIndex.
977
MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
978
3.43M
                                                     int FI, int64_t Offset) {
979
3.43M
  return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
980
3.43M
}
981
982
420
MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
983
420
  return MachinePointerInfo(MF.getPSVManager().getJumpTable());
984
420
}
985
986
43.1k
MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
987
43.1k
  return MachinePointerInfo(MF.getPSVManager().getGOT());
988
43.1k
}
989
990
MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
991
164k
                                                int64_t Offset, uint8_t ID) {
992
164k
  return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
993
164k
}
994
995
2.60k
MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
996
2.60k
  return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
997
2.60k
}
998
999
MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1000
                                     uint64_t s, uint64_t a,
1001
                                     const AAMDNodes &AAInfo,
1002
                                     const MDNode *Ranges, SyncScope::ID SSID,
1003
                                     AtomicOrdering Ordering,
1004
                                     AtomicOrdering FailureOrdering)
1005
    : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
1006
8.06M
      AAInfo(AAInfo), Ranges(Ranges) {
1007
8.06M
  assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
1008
8.06M
          isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
1009
8.06M
         "invalid pointer value");
1010
8.06M
  assert(getBaseAlignment() == a && a != 0 && "Alignment is not a power of 2!");
1011
8.06M
  assert((isLoad() || isStore()) && "Not a load/store!");
1012
8.06M
1013
8.06M
  AtomicInfo.SSID = static_cast<unsigned>(SSID);
1014
8.06M
  assert(getSyncScopeID() == SSID && "Value truncated");
1015
8.06M
  AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1016
8.06M
  assert(getOrdering() == Ordering && "Value truncated");
1017
8.06M
  AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1018
8.06M
  assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1019
8.06M
}
1020
1021
/// Profile - Gather unique data for the object.
1022
///
1023
0
void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
1024
0
  ID.AddInteger(getOffset());
1025
0
  ID.AddInteger(Size);
1026
0
  ID.AddPointer(getOpaqueValue());
1027
0
  ID.AddInteger(getFlags());
1028
0
  ID.AddInteger(getBaseAlignment());
1029
0
}
1030
1031
48.6k
void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
1032
48.6k
  // The Value and Offset may differ due to CSE. But the flags and size
1033
48.6k
  // should be the same.
1034
48.6k
  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1035
48.6k
  assert(MMO->getSize() == getSize() && "Size mismatch!");
1036
48.6k
1037
48.6k
  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
1038
48.6k
    // Update the alignment value.
1039
48.6k
    BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
1040
48.6k
    // Also update the base and offset, because the new alignment may
1041
48.6k
    // not be applicable with the old ones.
1042
48.6k
    PtrInfo = MMO->PtrInfo;
1043
48.6k
  }
1044
48.6k
}
1045
1046
/// getAlignment - Return the minimum known alignment in bytes of the
1047
/// actual memory reference.
1048
16.7M
uint64_t MachineMemOperand::getAlignment() const {
1049
16.7M
  return MinAlign(getBaseAlignment(), getOffset());
1050
16.7M
}
1051
1052
0
void MachineMemOperand::print(raw_ostream &OS) const {
1053
0
  ModuleSlotTracker DummyMST(nullptr);
1054
0
  print(OS, DummyMST);
1055
0
}
1056
1057
0
void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
1058
0
  SmallVector<StringRef, 0> SSNs;
1059
0
  LLVMContext Ctx;
1060
0
  print(OS, MST, SSNs, Ctx, nullptr, nullptr);
1061
0
}
1062
1063
void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
1064
                              SmallVectorImpl<StringRef> &SSNs,
1065
                              const LLVMContext &Context,
1066
                              const MachineFrameInfo *MFI,
1067
9.36k
                              const TargetInstrInfo *TII) const {
1068
9.36k
  OS << '(';
1069
9.36k
  if (isVolatile())
1070
630
    OS << "volatile ";
1071
9.36k
  if (isNonTemporal())
1072
56
    OS << "non-temporal ";
1073
9.36k
  if (isDereferenceable())
1074
946
    OS << "dereferenceable ";
1075
9.36k
  if (isInvariant())
1076
667
    OS << "invariant ";
1077
9.36k
  if (getFlags() & MachineMemOperand::MOTargetFlag1)
1078
2
    OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)
1079
2
       << "\" ";
1080
9.36k
  if (getFlags() & MachineMemOperand::MOTargetFlag2)
1081
21
    OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)
1082
21
       << "\" ";
1083
9.36k
  if (getFlags() & MachineMemOperand::MOTargetFlag3)
1084
0
    OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)
1085
0
       << "\" ";
1086
9.36k
1087
9.36k
  assert((isLoad() || isStore()) &&
1088
9.36k
         "machine memory operand must be a load or store (or both)");
1089
9.36k
  if (isLoad())
1090
5.34k
    OS << "load ";
1091
9.36k
  if (isStore())
1092
4.34k
    OS << "store ";
1093
9.36k
1094
9.36k
  printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1095
9.36k
1096
9.36k
  if (getOrdering() != AtomicOrdering::NotAtomic)
1097
518
    OS << toIRString(getOrdering()) << ' ';
1098
9.36k
  if (getFailureOrdering() != AtomicOrdering::NotAtomic)
1099
36
    OS << toIRString(getFailureOrdering()) << ' ';
1100
9.36k
1101
9.36k
  if (getSize() == MemoryLocation::UnknownSize)
1102
2
    OS << "unknown-size";
1103
9.35k
  else
1104
9.35k
    OS << getSize();
1105
9.36k
1106
9.36k
  if (const Value *Val = getValue()) {
1107
3.91k
    OS << ((isLoad() && 
isStore()2.22k
) ?
" on "119
:
isLoad() 3.79k
?
" from "2.10k
:
" into "1.68k
);
1108
3.91k
    printIRValueReference(OS, *Val, MST);
1109
5.45k
  } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1110
3.76k
    OS << ((isLoad() && 
isStore()2.05k
) ?
" on "0
: isLoad() ?
" from "2.05k
:
" into "1.70k
);
1111
3.76k
    assert(PVal && "Expected a pseudo source value");
1112
3.76k
    switch (PVal->kind()) {
1113
3.76k
    case PseudoSourceValue::Stack:
1114
227
      OS << "stack";
1115
227
      break;
1116
3.76k
    case PseudoSourceValue::GOT:
1117
37
      OS << "got";
1118
37
      break;
1119
3.76k
    case PseudoSourceValue::JumpTable:
1120
11
      OS << "jump-table";
1121
11
      break;
1122
3.76k
    case PseudoSourceValue::ConstantPool:
1123
85
      OS << "constant-pool";
1124
85
      break;
1125
3.76k
    case PseudoSourceValue::FixedStack: {
1126
3.35k
      int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1127
3.35k
      bool IsFixed = true;
1128
3.35k
      printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1129
3.35k
      break;
1130
3.76k
    }
1131
3.76k
    case PseudoSourceValue::GlobalValueCallEntry:
1132
8
      OS << "call-entry ";
1133
8
      cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1134
8
          OS, /*PrintType=*/false, MST);
1135
8
      break;
1136
3.76k
    case PseudoSourceValue::ExternalSymbolCallEntry:
1137
6
      OS << "call-entry &";
1138
6
      printLLVMNameWithoutPrefix(
1139
6
          OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1140
6
      break;
1141
3.76k
    default:
1142
36
      // FIXME: This is not necessarily the correct MIR serialization format for
1143
36
      // a custom pseudo source value, but at least it allows
1144
36
      // -print-machineinstrs to work on a target with custom pseudo source
1145
36
      // values.
1146
36
      OS << "custom ";
1147
36
      PVal->printCustom(OS);
1148
36
      break;
1149
9.36k
    }
1150
9.36k
  }
1151
9.36k
  MachineOperand::printOperandOffset(OS, getOffset());
1152
9.36k
  if (getBaseAlignment() != getSize())
1153
1.63k
    OS << ", align " << getBaseAlignment();
1154
9.36k
  auto AAInfo = getAAInfo();
1155
9.36k
  if (AAInfo.TBAA) {
1156
770
    OS << ", !tbaa ";
1157
770
    AAInfo.TBAA->printAsOperand(OS, MST);
1158
770
  }
1159
9.36k
  if (AAInfo.Scope) {
1160
1
    OS << ", !alias.scope ";
1161
1
    AAInfo.Scope->printAsOperand(OS, MST);
1162
1
  }
1163
9.36k
  if (AAInfo.NoAlias) {
1164
2
    OS << ", !noalias ";
1165
2
    AAInfo.NoAlias->printAsOperand(OS, MST);
1166
2
  }
1167
9.36k
  if (getRanges()) {
1168
3
    OS << ", !range ";
1169
3
    getRanges()->printAsOperand(OS, MST);
1170
3
  }
1171
9.36k
  // FIXME: Implement addrspace printing/parsing in MIR.
1172
9.36k
  // For now, print this even though parsing it is not available in MIR.
1173
9.36k
  if (unsigned AS = getAddrSpace())
1174
2.07k
    OS << ", addrspace " << AS;
1175
9.36k
1176
9.36k
  OS << ')';
1177
9.36k
}