Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/MachineRegisterInfo.cpp
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Source (jump to first uncovered line)
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//===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// Implementation of the MachineRegisterInfo class.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "llvm/CodeGen/MachineRegisterInfo.h"
14
#include "llvm/ADT/iterator_range.h"
15
#include "llvm/CodeGen/LowLevelType.h"
16
#include "llvm/CodeGen/MachineBasicBlock.h"
17
#include "llvm/CodeGen/MachineFunction.h"
18
#include "llvm/CodeGen/MachineInstr.h"
19
#include "llvm/CodeGen/MachineInstrBuilder.h"
20
#include "llvm/CodeGen/MachineOperand.h"
21
#include "llvm/CodeGen/TargetInstrInfo.h"
22
#include "llvm/CodeGen/TargetRegisterInfo.h"
23
#include "llvm/CodeGen/TargetSubtargetInfo.h"
24
#include "llvm/Config/llvm-config.h"
25
#include "llvm/IR/Attributes.h"
26
#include "llvm/IR/DebugLoc.h"
27
#include "llvm/IR/Function.h"
28
#include "llvm/MC/MCRegisterInfo.h"
29
#include "llvm/Support/Casting.h"
30
#include "llvm/Support/CommandLine.h"
31
#include "llvm/Support/Compiler.h"
32
#include "llvm/Support/ErrorHandling.h"
33
#include "llvm/Support/raw_ostream.h"
34
#include <cassert>
35
36
using namespace llvm;
37
38
static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
39
  cl::init(true), cl::desc("Enable subregister liveness tracking."));
40
41
// Pin the vtable to this file.
42
0
void MachineRegisterInfo::Delegate::anchor() {}
43
44
MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)
45
    : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
46
                                   EnableSubRegLiveness),
47
527k
      IsUpdatedCSRsInitialized(false) {
48
527k
  unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
49
527k
  VRegInfo.reserve(256);
50
527k
  RegAllocHints.reserve(256);
51
527k
  UsedPhysRegMask.resize(NumRegs);
52
527k
  PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
53
527k
}
54
55
/// setRegClass - Set the register class of the specified virtual register.
56
///
57
void
58
9.92M
MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
59
9.92M
  assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
60
9.92M
  VRegInfo[Reg].first = RC;
61
9.92M
}
62
63
void MachineRegisterInfo::setRegBank(unsigned Reg,
64
11.3M
                                     const RegisterBank &RegBank) {
65
11.3M
  VRegInfo[Reg].first = &RegBank;
66
11.3M
}
67
68
static const TargetRegisterClass *
69
constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg,
70
                  const TargetRegisterClass *OldRC,
71
13.6M
                  const TargetRegisterClass *RC, unsigned MinNumRegs) {
72
13.6M
  if (OldRC == RC)
73
9.37M
    return RC;
74
4.28M
  const TargetRegisterClass *NewRC =
75
4.28M
      MRI.getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
76
4.28M
  if (!NewRC || 
NewRC == OldRC4.09M
)
77
2.31M
    return NewRC;
78
1.96M
  if (NewRC->getNumRegs() < MinNumRegs)
79
60
    return nullptr;
80
1.96M
  MRI.setRegClass(Reg, NewRC);
81
1.96M
  return NewRC;
82
1.96M
}
83
84
const TargetRegisterClass *
85
MachineRegisterInfo::constrainRegClass(unsigned Reg,
86
                                       const TargetRegisterClass *RC,
87
13.0M
                                       unsigned MinNumRegs) {
88
13.0M
  return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
89
13.0M
}
90
91
bool
92
MachineRegisterInfo::constrainRegAttrs(unsigned Reg,
93
                                       unsigned ConstrainingReg,
94
1.32M
                                       unsigned MinNumRegs) {
95
1.32M
  const LLT RegTy = getType(Reg);
96
1.32M
  const LLT ConstrainingRegTy = getType(ConstrainingReg);
97
1.32M
  if (RegTy.isValid() && 
ConstrainingRegTy.isValid()692k
&&
98
1.32M
      
RegTy != ConstrainingRegTy692k
)
99
1
    return false;
100
1.32M
  const auto ConstrainingRegCB = getRegClassOrRegBank(ConstrainingReg);
101
1.32M
  if (!ConstrainingRegCB.isNull()) {
102
638k
    const auto RegCB = getRegClassOrRegBank(Reg);
103
638k
    if (RegCB.isNull())
104
2.08k
      setRegClassOrRegBank(Reg, ConstrainingRegCB);
105
636k
    else if (RegCB.is<const TargetRegisterClass *>() !=
106
636k
             ConstrainingRegCB.is<const TargetRegisterClass *>())
107
0
      return false;
108
636k
    else if (RegCB.is<const TargetRegisterClass *>()) {
109
636k
      if (!::constrainRegClass(
110
636k
              *this, Reg, RegCB.get<const TargetRegisterClass *>(),
111
636k
              ConstrainingRegCB.get<const TargetRegisterClass *>(), MinNumRegs))
112
108k
        return false;
113
1
    } else if (RegCB != ConstrainingRegCB)
114
0
      return false;
115
1.22M
  }
116
1.22M
  if (ConstrainingRegTy.isValid())
117
692k
    setType(Reg, ConstrainingRegTy);
118
1.22M
  return true;
119
1.22M
}
120
121
bool
122
834k
MachineRegisterInfo::recomputeRegClass(unsigned Reg) {
123
834k
  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
124
834k
  const TargetRegisterClass *OldRC = getRegClass(Reg);
125
834k
  const TargetRegisterClass *NewRC =
126
834k
      getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC, *MF);
127
834k
128
834k
  // Stop early if there is no room to grow.
129
834k
  if (NewRC == OldRC)
130
797k
    return false;
131
37.6k
132
37.6k
  // Accumulate constraints from all uses.
133
96.2k
  
for (MachineOperand &MO : reg_nodbg_operands(Reg))37.6k
{
134
96.2k
    // Apply the effect of the given operand to NewRC.
135
96.2k
    MachineInstr *MI = MO.getParent();
136
96.2k
    unsigned OpNo = &MO - &MI->getOperand(0);
137
96.2k
    NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
138
96.2k
                                            getTargetRegisterInfo());
139
96.2k
    if (!NewRC || NewRC == OldRC)
140
21.8k
      return false;
141
96.2k
  }
142
37.6k
  setRegClass(Reg, NewRC);
143
15.7k
  return true;
144
37.6k
}
145
146
22.7M
unsigned MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) {
147
22.7M
  unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
148
22.7M
  VRegInfo.grow(Reg);
149
22.7M
  RegAllocHints.grow(Reg);
150
22.7M
  insertVRegByName(Name, Reg);
151
22.7M
  return Reg;
152
22.7M
}
153
154
/// createVirtualRegister - Create and return a new virtual register in the
155
/// function with the specified register class.
156
///
157
Register
158
MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass,
159
8.59M
                                           StringRef Name) {
160
8.59M
  assert(RegClass && "Cannot create register without RegClass!");
161
8.59M
  assert(RegClass->isAllocatable() &&
162
8.59M
         "Virtual register RegClass must be allocatable.");
163
8.59M
164
8.59M
  // New virtual register number.
165
8.59M
  unsigned Reg = createIncompleteVirtualRegister(Name);
166
8.59M
  VRegInfo[Reg].first = RegClass;
167
8.59M
  if (TheDelegate)
168
960k
    TheDelegate->MRI_NoteNewVirtualRegister(Reg);
169
8.59M
  return Reg;
170
8.59M
}
171
172
Register MachineRegisterInfo::cloneVirtualRegister(Register VReg,
173
46.8k
                                                   StringRef Name) {
174
46.8k
  unsigned Reg = createIncompleteVirtualRegister(Name);
175
46.8k
  VRegInfo[Reg].first = VRegInfo[VReg].first;
176
46.8k
  setType(Reg, getType(VReg));
177
46.8k
  if (TheDelegate)
178
0
    TheDelegate->MRI_NoteNewVirtualRegister(Reg);
179
46.8k
  return Reg;
180
46.8k
}
181
182
14.8M
void MachineRegisterInfo::setType(unsigned VReg, LLT Ty) {
183
14.8M
  VRegToType.grow(VReg);
184
14.8M
  VRegToType[VReg] = Ty;
185
14.8M
}
186
187
Register
188
14.0M
MachineRegisterInfo::createGenericVirtualRegister(LLT Ty, StringRef Name) {
189
14.0M
  // New virtual register number.
190
14.0M
  unsigned Reg = createIncompleteVirtualRegister(Name);
191
14.0M
  // FIXME: Should we use a dummy register class?
192
14.0M
  VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
193
14.0M
  setType(Reg, Ty);
194
14.0M
  if (TheDelegate)
195
0
    TheDelegate->MRI_NoteNewVirtualRegister(Reg);
196
14.0M
  return Reg;
197
14.0M
}
198
199
460k
void MachineRegisterInfo::clearVirtRegTypes() { VRegToType.clear(); }
200
201
/// clearVirtRegs - Remove all virtual registers (after physreg assignment).
202
494k
void MachineRegisterInfo::clearVirtRegs() {
203
#ifndef NDEBUG
204
  for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
205
    unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
206
    if (!VRegInfo[Reg].second)
207
      continue;
208
    verifyUseList(Reg);
209
    llvm_unreachable("Remaining virtual register operands");
210
  }
211
#endif
212
  VRegInfo.clear();
213
494k
  for (auto &I : LiveIns)
214
475k
    I.second = 0;
215
494k
}
216
217
0
void MachineRegisterInfo::verifyUseList(unsigned Reg) const {
218
#ifndef NDEBUG
219
  bool Valid = true;
220
  for (MachineOperand &M : reg_operands(Reg)) {
221
    MachineOperand *MO = &M;
222
    MachineInstr *MI = MO->getParent();
223
    if (!MI) {
224
      errs() << printReg(Reg, getTargetRegisterInfo())
225
             << " use list MachineOperand " << MO
226
             << " has no parent instruction.\n";
227
      Valid = false;
228
      continue;
229
    }
230
    MachineOperand *MO0 = &MI->getOperand(0);
231
    unsigned NumOps = MI->getNumOperands();
232
    if (!(MO >= MO0 && MO < MO0+NumOps)) {
233
      errs() << printReg(Reg, getTargetRegisterInfo())
234
             << " use list MachineOperand " << MO
235
             << " doesn't belong to parent MI: " << *MI;
236
      Valid = false;
237
    }
238
    if (!MO->isReg()) {
239
      errs() << printReg(Reg, getTargetRegisterInfo())
240
             << " MachineOperand " << MO << ": " << *MO
241
             << " is not a register\n";
242
      Valid = false;
243
    }
244
    if (MO->getReg() != Reg) {
245
      errs() << printReg(Reg, getTargetRegisterInfo())
246
             << " use-list MachineOperand " << MO << ": "
247
             << *MO << " is the wrong register\n";
248
      Valid = false;
249
    }
250
  }
251
  assert(Valid && "Invalid use list");
252
#endif
253
}
254
255
2.28M
void MachineRegisterInfo::verifyUseLists() const {
256
#ifndef NDEBUG
257
  for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
258
    verifyUseList(TargetRegisterInfo::index2VirtReg(i));
259
  for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
260
    verifyUseList(i);
261
#endif
262
}
263
264
/// Add MO to the linked list of operands for its register.
265
177M
void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
266
177M
  assert(!MO->isOnRegUseList() && "Already on list");
267
177M
  MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
268
177M
  MachineOperand *const Head = HeadRef;
269
177M
270
177M
  // Head points to the first list element.
271
177M
  // Next is NULL on the last list element.
272
177M
  // Prev pointers are circular, so Head->Prev == Last.
273
177M
274
177M
  // Head is NULL for an empty list.
275
177M
  if (!Head) {
276
29.8M
    MO->Contents.Reg.Prev = MO;
277
29.8M
    MO->Contents.Reg.Next = nullptr;
278
29.8M
    HeadRef = MO;
279
29.8M
    return;
280
29.8M
  }
281
147M
  assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
282
147M
283
147M
  // Insert MO between Last and Head in the circular Prev chain.
284
147M
  MachineOperand *Last = Head->Contents.Reg.Prev;
285
147M
  assert(Last && "Inconsistent use list");
286
147M
  assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
287
147M
  Head->Contents.Reg.Prev = MO;
288
147M
  MO->Contents.Reg.Prev = Last;
289
147M
290
147M
  // Def operands always precede uses. This allows def_iterator to stop early.
291
147M
  // Insert def operands at the front, and use operands at the back.
292
147M
  if (MO->isDef()) {
293
46.2M
    // Insert def at the front.
294
46.2M
    MO->Contents.Reg.Next = Head;
295
46.2M
    HeadRef = MO;
296
101M
  } else {
297
101M
    // Insert use at the end.
298
101M
    MO->Contents.Reg.Next = nullptr;
299
101M
    Last->Contents.Reg.Next = MO;
300
101M
  }
301
147M
}
302
303
/// Remove MO from its use-def list.
304
116M
void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
305
116M
  assert(MO->isOnRegUseList() && "Operand not on use list");
306
116M
  MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
307
116M
  MachineOperand *const Head = HeadRef;
308
116M
  assert(Head && "List already empty");
309
116M
310
116M
  // Unlink this from the doubly linked list of operands.
311
116M
  MachineOperand *Next = MO->Contents.Reg.Next;
312
116M
  MachineOperand *Prev = MO->Contents.Reg.Prev;
313
116M
314
116M
  // Prev links are circular, next link is NULL instead of looping back to Head.
315
116M
  if (MO == Head)
316
46.0M
    HeadRef = Next;
317
70.0M
  else
318
70.0M
    Prev->Contents.Reg.Next = Next;
319
116M
320
116M
  (Next ? 
Next78.2M
:
Head37.8M
)->Contents.Reg.Prev = Prev;
321
116M
322
116M
  MO->Contents.Reg.Prev = nullptr;
323
116M
  MO->Contents.Reg.Next = nullptr;
324
116M
}
325
326
/// Move NumOps operands from Src to Dst, updating use-def lists as needed.
327
///
328
/// The Dst range is assumed to be uninitialized memory. (Or it may contain
329
/// operands that won't be destroyed, which is OK because the MO destructor is
330
/// trivial anyway).
331
///
332
/// The Src and Dst ranges may overlap.
333
void MachineRegisterInfo::moveOperands(MachineOperand *Dst,
334
                                       MachineOperand *Src,
335
24.7M
                                       unsigned NumOps) {
336
24.7M
  assert(Src != Dst && NumOps && "Noop moveOperands");
337
24.7M
338
24.7M
  // Copy backwards if Dst is within the Src range.
339
24.7M
  int Stride = 1;
340
24.7M
  if (Dst >= Src && 
Dst < Src + NumOps23.0M
) {
341
5.53M
    Stride = -1;
342
5.53M
    Dst += NumOps - 1;
343
5.53M
    Src += NumOps - 1;
344
5.53M
  }
345
24.7M
346
24.7M
  // Copy one operand at a time.
347
40.9M
  do {
348
40.9M
    new (Dst) MachineOperand(*Src);
349
40.9M
350
40.9M
    // Dst takes Src's place in the use-def chain.
351
40.9M
    if (Src->isReg()) {
352
37.8M
      MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
353
37.8M
      MachineOperand *Prev = Src->Contents.Reg.Prev;
354
37.8M
      MachineOperand *Next = Src->Contents.Reg.Next;
355
37.8M
      assert(Head && "List empty, but operand is chained");
356
37.8M
      assert(Prev && "Operand was not on use-def list");
357
37.8M
358
37.8M
      // Prev links are circular, next link is NULL instead of looping back to
359
37.8M
      // Head.
360
37.8M
      if (Src == Head)
361
15.3M
        Head = Dst;
362
22.5M
      else
363
22.5M
        Prev->Contents.Reg.Next = Dst;
364
37.8M
365
37.8M
      // Update Prev pointer. This also works when Src was pointing to itself
366
37.8M
      // in a 1-element list. In that case Head == Dst.
367
37.8M
      (Next ? 
Next17.2M
:
Head20.6M
)->Contents.Reg.Prev = Dst;
368
37.8M
    }
369
40.9M
370
40.9M
    Dst += Stride;
371
40.9M
    Src += Stride;
372
40.9M
  } while (--NumOps);
373
24.7M
}
374
375
/// replaceRegWith - Replace all instances of FromReg with ToReg in the
376
/// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
377
/// except that it also changes any definitions of the register as well.
378
/// If ToReg is a physical register we apply the sub register to obtain the
379
/// final/proper physical register.
380
1.68M
void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
381
1.68M
  assert(FromReg != ToReg && "Cannot replace a reg with itself");
382
1.68M
383
1.68M
  const TargetRegisterInfo *TRI = getTargetRegisterInfo();
384
1.68M
385
1.68M
  // TODO: This could be more efficient by bulk changing the operands.
386
4.23M
  for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
387
2.54M
    MachineOperand &O = *I;
388
2.54M
    ++I;
389
2.54M
    if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
390
38.2k
      O.substPhysReg(ToReg, *TRI);
391
2.51M
    } else {
392
2.51M
      O.setReg(ToReg);
393
2.51M
    }
394
2.54M
  }
395
1.68M
}
396
397
/// getVRegDef - Return the machine instr that defines the specified virtual
398
/// register or null if none is found.  This assumes that the code is in SSA
399
/// form, so there should only be one definition.
400
65.2M
MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
401
65.2M
  // Since we are in SSA form, we can use the first definition.
402
65.2M
  def_instr_iterator I = def_instr_begin(Reg);
403
65.2M
  assert((I.atEnd() || std::next(I) == def_instr_end()) &&
404
65.2M
         "getVRegDef assumes a single definition or no definition");
405
65.2M
  return !I.atEnd() ? 
&*I65.2M
:
nullptr33.8k
;
406
65.2M
}
407
408
/// getUniqueVRegDef - Return the unique machine instr that defines the
409
/// specified virtual register or null if none is found.  If there are
410
/// multiple definitions or no definition, return null.
411
3.38M
MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const {
412
3.38M
  if (def_empty(Reg)) 
return nullptr1.23k
;
413
3.38M
  def_instr_iterator I = def_instr_begin(Reg);
414
3.38M
  if (std::next(I) != def_instr_end())
415
26.2k
    return nullptr;
416
3.35M
  return &*I;
417
3.35M
}
418
419
19.2M
bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
420
19.2M
  use_nodbg_iterator UI = use_nodbg_begin(RegNo);
421
19.2M
  if (UI == use_nodbg_end())
422
10.3k
    return false;
423
19.2M
  return ++UI == use_nodbg_end();
424
19.2M
}
425
426
237k
bool MachineRegisterInfo::hasOneNonDBGUser(unsigned RegNo) const {
427
237k
  use_instr_nodbg_iterator UI = use_instr_nodbg_begin(RegNo);
428
237k
  if (UI == use_instr_nodbg_end())
429
199
    return false;
430
237k
  return ++UI == use_instr_nodbg_end();
431
237k
}
432
433
/// clearKillFlags - Iterate over all the uses of the given register and
434
/// clear the kill flag from the MachineOperand. This function is used by
435
/// optimization passes which extend register lifetimes and need only
436
/// preserve conservative kill flag information.
437
8.61M
void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
438
8.61M
  for (MachineOperand &MO : use_operands(Reg))
439
29.3M
    MO.setIsKill(false);
440
8.61M
}
441
442
1.98M
bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
443
3.91M
  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; 
++I1.92M
)
444
2.01M
    if (I->first == Reg || 
I->second == Reg1.99M
)
445
98.3k
      return true;
446
1.98M
  
return false1.89M
;
447
1.98M
}
448
449
/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
450
/// corresponding live-in physical register.
451
265
unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
452
396
  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; 
++I131
)
453
395
    if (I->second == VReg)
454
264
      return I->first;
455
265
  
return 01
;
456
265
}
457
458
/// getLiveInVirtReg - If PReg is a live-in physical register, return the
459
/// corresponding live-in physical register.
460
581k
unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
461
1.45M
  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; 
++I874k
)
462
945k
    if (I->first == PReg)
463
70.9k
      return I->second;
464
581k
  
return 0510k
;
465
581k
}
466
467
/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
468
/// into the given entry block.
469
void
470
MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
471
                                      const TargetRegisterInfo &TRI,
472
277k
                                      const TargetInstrInfo &TII) {
473
277k
  // Emit the copies into the top of the block.
474
845k
  for (unsigned i = 0, e = LiveIns.size(); i != e; 
++i567k
)
475
567k
    if (LiveIns[i].second) {
476
562k
      if (use_nodbg_empty(LiveIns[i].second)) {
477
94.5k
        // The livein has no non-dbg uses. Drop it.
478
94.5k
        //
479
94.5k
        // It would be preferable to have isel avoid creating live-in
480
94.5k
        // records for unused arguments in the first place, but it's
481
94.5k
        // complicated by the debug info code for arguments.
482
94.5k
        LiveIns.erase(LiveIns.begin() + i);
483
94.5k
        --i; --e;
484
468k
      } else {
485
468k
        // Emit a copy.
486
468k
        BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
487
468k
                TII.get(TargetOpcode::COPY), LiveIns[i].second)
488
468k
          .addReg(LiveIns[i].first);
489
468k
490
468k
        // Add the register to the entry block live-in set.
491
468k
        EntryMBB->addLiveIn(LiveIns[i].first);
492
468k
      }
493
562k
    } else {
494
4.45k
      // Add the register to the entry block live-in set.
495
4.45k
      EntryMBB->addLiveIn(LiveIns[i].first);
496
4.45k
    }
497
277k
}
498
499
15.6M
LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(unsigned Reg) const {
500
15.6M
  // Lane masks are only defined for vregs.
501
15.6M
  assert(TargetRegisterInfo::isVirtualRegister(Reg));
502
15.6M
  const TargetRegisterClass &TRC = *getRegClass(Reg);
503
15.6M
  return TRC.getLaneMask();
504
15.6M
}
505
506
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
507
LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(unsigned Reg) const {
508
  for (MachineInstr &I : use_instructions(Reg))
509
    I.dump();
510
}
511
#endif
512
513
1.50M
void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
514
1.50M
  ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
515
1.50M
  assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
516
1.50M
         "Invalid ReservedRegs vector from target");
517
1.50M
}
518
519
12.3M
bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
520
12.3M
  assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
521
12.3M
522
12.3M
  const TargetRegisterInfo *TRI = getTargetRegisterInfo();
523
12.3M
  if (TRI->isConstantPhysReg(PhysReg))
524
1.46M
    return true;
525
10.8M
526
10.8M
  // Check if any overlapping register is modified, or allocatable so it may be
527
10.8M
  // used later.
528
10.8M
  for (MCRegAliasIterator AI(PhysReg, TRI, true);
529
17.4M
       AI.isValid(); 
++AI6.60M
)
530
16.5M
    if (!def_empty(*AI) || 
isAllocatable(*AI)10.0M
)
531
9.95M
      return false;
532
10.8M
  
return true939k
;
533
10.8M
}
534
535
bool
536
0
MachineRegisterInfo::isCallerPreservedOrConstPhysReg(unsigned PhysReg) const {
537
0
  const TargetRegisterInfo *TRI = getTargetRegisterInfo();
538
0
  return isConstantPhysReg(PhysReg) ||
539
0
      TRI->isCallerPreservedPhysReg(PhysReg, *MF);
540
0
}
541
542
/// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
543
/// specified register as undefined which causes the DBG_VALUE to be
544
/// deleted during LiveDebugVariables analysis.
545
5.22M
void MachineRegisterInfo::markUsesInDebugValueAsUndef(unsigned Reg) const {
546
5.22M
  // Mark any DBG_VALUE that uses Reg as undef (but don't delete it.)
547
5.22M
  MachineRegisterInfo::use_instr_iterator nextI;
548
5.22M
  for (use_instr_iterator I = use_instr_begin(Reg), E = use_instr_end();
549
6.90M
       I != E; 
I = nextI1.68M
) {
550
1.68M
    nextI = std::next(I);  // I is invalidated by the setReg
551
1.68M
    MachineInstr *UseMI = &*I;
552
1.68M
    if (UseMI->isDebugValue())
553
4
      UseMI->getOperand(0).setReg(0U);
554
1.68M
  }
555
5.22M
}
556
557
122k
static const Function *getCalledFunction(const MachineInstr &MI) {
558
248k
  for (const MachineOperand &MO : MI.operands()) {
559
248k
    if (!MO.isGlobal())
560
146k
      continue;
561
102k
    const Function *Func = dyn_cast<Function>(MO.getGlobal());
562
102k
    if (Func != nullptr)
563
102k
      return Func;
564
102k
  }
565
122k
  
return nullptr19.8k
;
566
122k
}
567
568
1.24M
static bool isNoReturnDef(const MachineOperand &MO) {
569
1.24M
  // Anything which is not a noreturn function is a real def.
570
1.24M
  const MachineInstr &MI = *MO.getParent();
571
1.24M
  if (!MI.isCall())
572
1.03M
    return false;
573
208k
  const MachineBasicBlock &MBB = *MI.getParent();
574
208k
  if (!MBB.succ_empty())
575
61.5k
    return false;
576
146k
  const MachineFunction &MF = *MBB.getParent();
577
146k
  // We need to keep correct unwind information even if the function will
578
146k
  // not return, since the runtime may need it.
579
146k
  if (MF.getFunction().hasFnAttribute(Attribute::UWTable))
580
24.5k
    return false;
581
122k
  const Function *Called = getCalledFunction(MI);
582
122k
  return !(Called == nullptr || 
!Called->hasFnAttribute(Attribute::NoReturn)102k
||
583
122k
           
!Called->hasFnAttribute(Attribute::NoUnwind)238
);
584
122k
}
585
586
bool MachineRegisterInfo::isPhysRegModified(unsigned PhysReg,
587
9.52M
                                            bool SkipNoReturnDef) const {
588
9.52M
  if (UsedPhysRegMask.test(PhysReg))
589
2.54k
    return true;
590
9.52M
  const TargetRegisterInfo *TRI = getTargetRegisterInfo();
591
194M
  for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); 
++AI185M
) {
592
186M
    for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
593
1.24M
      if (!SkipNoReturnDef && isNoReturnDef(MO))
594
27
        continue;
595
1.24M
      return true;
596
1.24M
    }
597
186M
  }
598
9.52M
  
return false8.27M
;
599
9.52M
}
600
601
16.3M
bool MachineRegisterInfo::isPhysRegUsed(unsigned PhysReg) const {
602
16.3M
  if (UsedPhysRegMask.test(PhysReg))
603
54.6k
    return true;
604
16.3M
  const TargetRegisterInfo *TRI = getTargetRegisterInfo();
605
801M
  for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid();
606
785M
       
++AliasReg785M
) {
607
785M
    if (!reg_nodbg_empty(*AliasReg))
608
162k
      return true;
609
785M
  }
610
16.3M
  
return false16.1M
;
611
16.3M
}
612
613
606
void MachineRegisterInfo::disableCalleeSavedRegister(unsigned Reg) {
614
606
615
606
  const TargetRegisterInfo *TRI = getTargetRegisterInfo();
616
606
  assert(Reg && (Reg < TRI->getNumRegs()) &&
617
606
         "Trying to disable an invalid register");
618
606
619
606
  if (!IsUpdatedCSRsInitialized) {
620
133
    const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
621
2.00k
    for (const MCPhysReg *I = CSR; *I; 
++I1.86k
)
622
1.86k
      UpdatedCSRs.push_back(*I);
623
133
624
133
    // Zero value represents the end of the register list
625
133
    // (no more registers should be pushed).
626
133
    UpdatedCSRs.push_back(0);
627
133
628
133
    IsUpdatedCSRsInitialized = true;
629
133
  }
630
606
631
606
  // Remove the register (and its aliases from the list).
632
4.75k
  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); 
++AI4.14k
)
633
4.14k
    UpdatedCSRs.erase(std::remove(UpdatedCSRs.begin(), UpdatedCSRs.end(), *AI),
634
4.14k
                      UpdatedCSRs.end());
635
606
}
636
637
6.03M
const MCPhysReg *MachineRegisterInfo::getCalleeSavedRegs() const {
638
6.03M
  if (IsUpdatedCSRsInitialized)
639
1.70k
    return UpdatedCSRs.data();
640
6.03M
641
6.03M
  return getTargetRegisterInfo()->getCalleeSavedRegs(MF);
642
6.03M
}
643
644
63
void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) {
645
63
  if (IsUpdatedCSRsInitialized)
646
0
    UpdatedCSRs.clear();
647
63
648
63
  for (MCPhysReg Reg : CSRs)
649
1.78k
    UpdatedCSRs.push_back(Reg);
650
63
651
63
  // Zero value represents the end of the register list
652
63
  // (no more registers should be pushed).
653
63
  UpdatedCSRs.push_back(0);
654
63
  IsUpdatedCSRsInitialized = true;
655
63
}
656
657
1.73M
bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
658
1.73M
  const TargetRegisterInfo *TRI = getTargetRegisterInfo();
659
3.17M
  for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); 
++Root1.44M
) {
660
1.73M
    bool IsRootReserved = true;
661
1.73M
    for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
662
2.53M
         Super.isValid(); 
++Super802k
) {
663
2.24M
      unsigned Reg = *Super;
664
2.24M
      if (!isReserved(Reg)) {
665
1.44M
        IsRootReserved = false;
666
1.44M
        break;
667
1.44M
      }
668
2.24M
    }
669
1.73M
    if (IsRootReserved)
670
286k
      return true;
671
1.73M
  }
672
1.73M
  
return false1.44M
;
673
1.73M
}