Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/MachineVerifier.cpp
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Source (jump to first uncovered line)
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//===- MachineVerifier.cpp - Machine Code Verifier ------------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// Pass to verify generated machine code. The following is checked:
10
//
11
// Operand counts: All explicit operands must be present.
12
//
13
// Register classes: All physical and virtual register operands must be
14
// compatible with the register class required by the instruction descriptor.
15
//
16
// Register live intervals: Registers must be defined only once, and must be
17
// defined before use.
18
//
19
// The machine code verifier is enabled from LLVMTargetMachine.cpp with the
20
// command-line option -verify-machineinstrs, or by defining the environment
21
// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
22
// the verifier errors.
23
//===----------------------------------------------------------------------===//
24
25
#include "LiveRangeCalc.h"
26
#include "llvm/ADT/BitVector.h"
27
#include "llvm/ADT/DenseMap.h"
28
#include "llvm/ADT/DenseSet.h"
29
#include "llvm/ADT/DepthFirstIterator.h"
30
#include "llvm/ADT/STLExtras.h"
31
#include "llvm/ADT/SetOperations.h"
32
#include "llvm/ADT/SmallPtrSet.h"
33
#include "llvm/ADT/SmallVector.h"
34
#include "llvm/ADT/StringRef.h"
35
#include "llvm/ADT/Twine.h"
36
#include "llvm/Analysis/EHPersonalities.h"
37
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
38
#include "llvm/CodeGen/LiveInterval.h"
39
#include "llvm/CodeGen/LiveIntervals.h"
40
#include "llvm/CodeGen/LiveStacks.h"
41
#include "llvm/CodeGen/LiveVariables.h"
42
#include "llvm/CodeGen/MachineBasicBlock.h"
43
#include "llvm/CodeGen/MachineFrameInfo.h"
44
#include "llvm/CodeGen/MachineFunction.h"
45
#include "llvm/CodeGen/MachineFunctionPass.h"
46
#include "llvm/CodeGen/MachineInstr.h"
47
#include "llvm/CodeGen/MachineInstrBundle.h"
48
#include "llvm/CodeGen/MachineMemOperand.h"
49
#include "llvm/CodeGen/MachineOperand.h"
50
#include "llvm/CodeGen/MachineRegisterInfo.h"
51
#include "llvm/CodeGen/PseudoSourceValue.h"
52
#include "llvm/CodeGen/SlotIndexes.h"
53
#include "llvm/CodeGen/StackMaps.h"
54
#include "llvm/CodeGen/TargetInstrInfo.h"
55
#include "llvm/CodeGen/TargetOpcodes.h"
56
#include "llvm/CodeGen/TargetRegisterInfo.h"
57
#include "llvm/CodeGen/TargetSubtargetInfo.h"
58
#include "llvm/IR/BasicBlock.h"
59
#include "llvm/IR/Function.h"
60
#include "llvm/IR/InlineAsm.h"
61
#include "llvm/IR/Instructions.h"
62
#include "llvm/MC/LaneBitmask.h"
63
#include "llvm/MC/MCAsmInfo.h"
64
#include "llvm/MC/MCInstrDesc.h"
65
#include "llvm/MC/MCRegisterInfo.h"
66
#include "llvm/MC/MCTargetOptions.h"
67
#include "llvm/Pass.h"
68
#include "llvm/Support/Casting.h"
69
#include "llvm/Support/ErrorHandling.h"
70
#include "llvm/Support/LowLevelTypeImpl.h"
71
#include "llvm/Support/MathExtras.h"
72
#include "llvm/Support/raw_ostream.h"
73
#include "llvm/Target/TargetMachine.h"
74
#include <algorithm>
75
#include <cassert>
76
#include <cstddef>
77
#include <cstdint>
78
#include <iterator>
79
#include <string>
80
#include <utility>
81
82
using namespace llvm;
83
84
namespace {
85
86
  struct MachineVerifier {
87
2.29M
    MachineVerifier(Pass *pass, const char *b) : PASS(pass), Banner(b) {}
88
89
    unsigned verify(MachineFunction &MF);
90
91
    Pass *const PASS;
92
    const char *Banner;
93
    const MachineFunction *MF;
94
    const TargetMachine *TM;
95
    const TargetInstrInfo *TII;
96
    const TargetRegisterInfo *TRI;
97
    const MachineRegisterInfo *MRI;
98
99
    unsigned foundErrors;
100
101
    // Avoid querying the MachineFunctionProperties for each operand.
102
    bool isFunctionRegBankSelected;
103
    bool isFunctionSelected;
104
105
    using RegVector = SmallVector<unsigned, 16>;
106
    using RegMaskVector = SmallVector<const uint32_t *, 4>;
107
    using RegSet = DenseSet<unsigned>;
108
    using RegMap = DenseMap<unsigned, const MachineInstr *>;
109
    using BlockSet = SmallPtrSet<const MachineBasicBlock *, 8>;
110
111
    const MachineInstr *FirstNonPHI;
112
    const MachineInstr *FirstTerminator;
113
    BlockSet FunctionBlocks;
114
115
    BitVector regsReserved;
116
    RegSet regsLive;
117
    RegVector regsDefined, regsDead, regsKilled;
118
    RegMaskVector regMasks;
119
120
    SlotIndex lastIndex;
121
122
    // Add Reg and any sub-registers to RV
123
43.1M
    void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
124
43.1M
      RV.push_back(Reg);
125
43.1M
      if (TargetRegisterInfo::isPhysicalRegister(Reg))
126
45.0M
        
for (MCSubRegIterator SubRegs(Reg, TRI); 23.4M
SubRegs.isValid();
++SubRegs21.5M
)
127
21.5M
          RV.push_back(*SubRegs);
128
43.1M
    }
129
130
    struct BBInfo {
131
      // Is this MBB reachable from the MF entry point?
132
      bool reachable = false;
133
134
      // Vregs that must be live in because they are used without being
135
      // defined. Map value is the user.
136
      RegMap vregsLiveIn;
137
138
      // Regs killed in MBB. They may be defined again, and will then be in both
139
      // regsKilled and regsLiveOut.
140
      RegSet regsKilled;
141
142
      // Regs defined in MBB and live out. Note that vregs passing through may
143
      // be live out without being mentioned here.
144
      RegSet regsLiveOut;
145
146
      // Vregs that pass through MBB untouched. This set is disjoint from
147
      // regsKilled and regsLiveOut.
148
      RegSet vregsPassed;
149
150
      // Vregs that must pass through MBB because they are needed by a successor
151
      // block. This set is disjoint from regsLiveOut.
152
      RegSet vregsRequired;
153
154
      // Set versions of block's predecessor and successor lists.
155
      BlockSet Preds, Succs;
156
157
2.88M
      BBInfo() = default;
158
159
      // Add register to vregsPassed if it belongs there. Return true if
160
      // anything changed.
161
25.0M
      bool addPassed(unsigned Reg) {
162
25.0M
        if (!TargetRegisterInfo::isVirtualRegister(Reg))
163
16.6M
          return false;
164
8.37M
        if (regsKilled.count(Reg) || 
regsLiveOut.count(Reg)8.37M
)
165
464k
          return false;
166
7.91M
        return vregsPassed.insert(Reg).second;
167
7.91M
      }
168
169
      // Same for a full set.
170
1.14M
      bool addPassed(const RegSet &RS) {
171
1.14M
        bool changed = false;
172
26.1M
        for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; 
++I25.0M
)
173
25.0M
          if (addPassed(*I))
174
4.02M
            changed = true;
175
1.14M
        return changed;
176
1.14M
      }
177
178
      // Add register to vregsRequired if it belongs there. Return true if
179
      // anything changed.
180
1.44M
      bool addRequired(unsigned Reg) {
181
1.44M
        if (!TargetRegisterInfo::isVirtualRegister(Reg))
182
0
          return false;
183
1.44M
        if (regsLiveOut.count(Reg))
184
562k
          return false;
185
878k
        return vregsRequired.insert(Reg).second;
186
878k
      }
187
188
      // Same for a full set.
189
181k
      bool addRequired(const RegSet &RS) {
190
181k
        bool changed = false;
191
1.09M
        for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; 
++I911k
)
192
911k
          if (addRequired(*I))
193
243k
            changed = true;
194
181k
        return changed;
195
181k
      }
196
197
      // Same for a full map.
198
850k
      bool addRequired(const RegMap &RM) {
199
850k
        bool changed = false;
200
1.38M
        for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; 
++I529k
)
201
529k
          if (addRequired(I->first))
202
245k
            changed = true;
203
850k
        return changed;
204
850k
      }
205
206
      // Live-out registers are either in regsLiveOut or vregsPassed.
207
224k
      bool isLiveOut(unsigned Reg) const {
208
224k
        return regsLiveOut.count(Reg) || 
vregsPassed.count(Reg)52.2k
;
209
224k
      }
210
    };
211
212
    // Extra register info per MBB.
213
    DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
214
215
16.5M
    bool isReserved(unsigned Reg) {
216
16.5M
      return Reg < regsReserved.size() && regsReserved.test(Reg);
217
16.5M
    }
218
219
1.49M
    bool isAllocatable(unsigned Reg) const {
220
1.49M
      return Reg < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
221
1.49M
             
!regsReserved.test(Reg)1.47M
;
222
1.49M
    }
223
224
    // Analysis information if available
225
    LiveVariables *LiveVars;
226
    LiveIntervals *LiveInts;
227
    LiveStacks *LiveStks;
228
    SlotIndexes *Indexes;
229
230
    void visitMachineFunctionBefore();
231
    void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
232
    void visitMachineBundleBefore(const MachineInstr *MI);
233
234
    bool verifyVectorElementMatch(LLT Ty0, LLT Ty1, const MachineInstr *MI);
235
    void verifyPreISelGenericInstruction(const MachineInstr *MI);
236
    void visitMachineInstrBefore(const MachineInstr *MI);
237
    void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
238
    void visitMachineInstrAfter(const MachineInstr *MI);
239
    void visitMachineBundleAfter(const MachineInstr *MI);
240
    void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
241
    void visitMachineFunctionAfter();
242
243
    void report(const char *msg, const MachineFunction *MF);
244
    void report(const char *msg, const MachineBasicBlock *MBB);
245
    void report(const char *msg, const MachineInstr *MI);
246
    void report(const char *msg, const MachineOperand *MO, unsigned MONum,
247
                LLT MOVRegType = LLT{});
248
249
    void report_context(const LiveInterval &LI) const;
250
    void report_context(const LiveRange &LR, unsigned VRegUnit,
251
                        LaneBitmask LaneMask) const;
252
    void report_context(const LiveRange::Segment &S) const;
253
    void report_context(const VNInfo &VNI) const;
254
    void report_context(SlotIndex Pos) const;
255
    void report_context(MCPhysReg PhysReg) const;
256
    void report_context_liverange(const LiveRange &LR) const;
257
    void report_context_lanemask(LaneBitmask LaneMask) const;
258
    void report_context_vreg(unsigned VReg) const;
259
    void report_context_vreg_regunit(unsigned VRegOrUnit) const;
260
261
    void verifyInlineAsm(const MachineInstr *MI);
262
263
    void checkLiveness(const MachineOperand *MO, unsigned MONum);
264
    void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
265
                            SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
266
                            LaneBitmask LaneMask = LaneBitmask::getNone());
267
    void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
268
                            SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
269
                            bool SubRangeCheck = false,
270
                            LaneBitmask LaneMask = LaneBitmask::getNone());
271
272
    void markReachable(const MachineBasicBlock *MBB);
273
    void calcRegsPassed();
274
    void checkPHIOps(const MachineBasicBlock &MBB);
275
276
    void calcRegsRequired();
277
    void verifyLiveVariables();
278
    void verifyLiveIntervals();
279
    void verifyLiveInterval(const LiveInterval&);
280
    void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned,
281
                              LaneBitmask);
282
    void verifyLiveRangeSegment(const LiveRange&,
283
                                const LiveRange::const_iterator I, unsigned,
284
                                LaneBitmask);
285
    void verifyLiveRange(const LiveRange&, unsigned,
286
                         LaneBitmask LaneMask = LaneBitmask::getNone());
287
288
    void verifyStackFrame();
289
290
    void verifySlotIndexes() const;
291
    void verifyProperties(const MachineFunction &MF);
292
  };
293
294
  struct MachineVerifierPass : public MachineFunctionPass {
295
    static char ID; // Pass ID, replacement for typeid
296
297
    const std::string Banner;
298
299
    MachineVerifierPass(std::string banner = std::string())
300
212k
      : MachineFunctionPass(ID), Banner(std::move(banner)) {
301
212k
        initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
302
212k
      }
303
304
212k
    void getAnalysisUsage(AnalysisUsage &AU) const override {
305
212k
      AU.setPreservesAll();
306
212k
      MachineFunctionPass::getAnalysisUsage(AU);
307
212k
    }
308
309
2.27M
    bool runOnMachineFunction(MachineFunction &MF) override {
310
2.27M
      unsigned FoundErrors = MachineVerifier(this, Banner.c_str()).verify(MF);
311
2.27M
      if (FoundErrors)
312
3
        report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
313
2.27M
      return false;
314
2.27M
    }
315
  };
316
317
} // end anonymous namespace
318
319
char MachineVerifierPass::ID = 0;
320
321
INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
322
                "Verify generated machine code", false, false)
323
324
212k
FunctionPass *llvm::createMachineVerifierPass(const std::string &Banner) {
325
212k
  return new MachineVerifierPass(Banner);
326
212k
}
327
328
bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors)
329
11.3k
    const {
330
11.3k
  MachineFunction &MF = const_cast<MachineFunction&>(*this);
331
11.3k
  unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
332
11.3k
  if (AbortOnErrors && FoundErrors)
333
67
    report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
334
11.2k
  return FoundErrors == 0;
335
11.2k
}
336
337
2.28M
void MachineVerifier::verifySlotIndexes() const {
338
2.28M
  if (Indexes == nullptr)
339
1.95M
    return;
340
339k
341
339k
  // Ensure the IdxMBB list is sorted by slot indexes.
342
339k
  SlotIndex Last;
343
339k
  for (SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin(),
344
763k
       E = Indexes->MBBIndexEnd(); I != E; 
++I423k
) {
345
423k
    assert(!Last.isValid() || I->first > Last);
346
423k
    Last = I->first;
347
423k
  }
348
339k
}
349
350
2.28M
void MachineVerifier::verifyProperties(const MachineFunction &MF) {
351
2.28M
  // If a pass has introduced virtual registers without clearing the
352
2.28M
  // NoVRegs property (or set it without allocating the vregs)
353
2.28M
  // then report an error.
354
2.28M
  if (MF.getProperties().hasProperty(
355
2.28M
          MachineFunctionProperties::Property::NoVRegs) &&
356
2.28M
      
MRI->getNumVirtRegs()1.12M
)
357
0
    report("Function has NoVRegs property but there are VReg operands", &MF);
358
2.28M
}
359
360
2.29M
unsigned MachineVerifier::verify(MachineFunction &MF) {
361
2.29M
  foundErrors = 0;
362
2.29M
363
2.29M
  this->MF = &MF;
364
2.29M
  TM = &MF.getTarget();
365
2.29M
  TII = MF.getSubtarget().getInstrInfo();
366
2.29M
  TRI = MF.getSubtarget().getRegisterInfo();
367
2.29M
  MRI = &MF.getRegInfo();
368
2.29M
369
2.29M
  const bool isFunctionFailedISel = MF.getProperties().hasProperty(
370
2.29M
      MachineFunctionProperties::Property::FailedISel);
371
2.29M
372
2.29M
  // If we're mid-GlobalISel and we already triggered the fallback path then
373
2.29M
  // it's expected that the MIR is somewhat broken but that's ok since we'll
374
2.29M
  // reset it and clear the FailedISel attribute in ResetMachineFunctions.
375
2.29M
  if (isFunctionFailedISel)
376
945
    return foundErrors;
377
2.28M
378
2.28M
  isFunctionRegBankSelected =
379
2.28M
      !isFunctionFailedISel &&
380
2.28M
      MF.getProperties().hasProperty(
381
2.28M
          MachineFunctionProperties::Property::RegBankSelected);
382
2.28M
  isFunctionSelected = !isFunctionFailedISel &&
383
2.28M
                       MF.getProperties().hasProperty(
384
2.28M
                           MachineFunctionProperties::Property::Selected);
385
2.28M
  LiveVars = nullptr;
386
2.28M
  LiveInts = nullptr;
387
2.28M
  LiveStks = nullptr;
388
2.28M
  Indexes = nullptr;
389
2.28M
  if (PASS) {
390
2.27M
    LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
391
2.27M
    // We don't want to verify LiveVariables if LiveIntervals is available.
392
2.27M
    if (!LiveInts)
393
1.98M
      LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
394
2.27M
    LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
395
2.27M
    Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
396
2.27M
  }
397
2.28M
398
2.28M
  verifySlotIndexes();
399
2.28M
400
2.28M
  verifyProperties(MF);
401
2.28M
402
2.28M
  visitMachineFunctionBefore();
403
2.28M
  for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
404
5.17M
       MFI!=MFE; 
++MFI2.88M
) {
405
2.88M
    visitMachineBasicBlockBefore(&*MFI);
406
2.88M
    // Keep track of the current bundle header.
407
2.88M
    const MachineInstr *CurBundle = nullptr;
408
2.88M
    // Do we expect the next instruction to be part of the same bundle?
409
2.88M
    bool InBundle = false;
410
2.88M
411
2.88M
    for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
412
36.3M
           MBBE = MFI->instr_end(); MBBI != MBBE; 
++MBBI33.4M
) {
413
33.4M
      if (MBBI->getParent() != &*MFI) {
414
0
        report("Bad instruction parent pointer", &*MFI);
415
0
        errs() << "Instruction: " << *MBBI;
416
0
        continue;
417
0
      }
418
33.4M
419
33.4M
      // Check for consistent bundle flags.
420
33.4M
      if (InBundle && 
!MBBI->isBundledWithPred()134k
)
421
0
        report("Missing BundledPred flag, "
422
0
               "BundledSucc was set on predecessor",
423
0
               &*MBBI);
424
33.4M
      if (!InBundle && 
MBBI->isBundledWithPred()33.3M
)
425
0
        report("BundledPred flag is set, "
426
0
               "but BundledSucc not set on predecessor",
427
0
               &*MBBI);
428
33.4M
429
33.4M
      // Is this a bundle header?
430
33.4M
      if (!MBBI->isInsideBundle()) {
431
33.3M
        if (CurBundle)
432
30.4M
          visitMachineBundleAfter(CurBundle);
433
33.3M
        CurBundle = &*MBBI;
434
33.3M
        visitMachineBundleBefore(CurBundle);
435
33.3M
      } else 
if (134k
!CurBundle134k
)
436
0
        report("No bundle header", &*MBBI);
437
33.4M
      visitMachineInstrBefore(&*MBBI);
438
168M
      for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; 
++I134M
) {
439
134M
        const MachineInstr &MI = *MBBI;
440
134M
        const MachineOperand &Op = MI.getOperand(I);
441
134M
        if (Op.getParent() != &MI) {
442
0
          // Make sure to use correct addOperand / RemoveOperand / ChangeTo
443
0
          // functions when replacing operands of a MachineInstr.
444
0
          report("Instruction has operand with wrong parent set", &MI);
445
0
        }
446
134M
447
134M
        visitMachineOperand(&Op, I);
448
134M
      }
449
33.4M
450
33.4M
      visitMachineInstrAfter(&*MBBI);
451
33.4M
452
33.4M
      // Was this the last bundled instruction?
453
33.4M
      InBundle = MBBI->isBundledWithSucc();
454
33.4M
    }
455
2.88M
    if (CurBundle)
456
2.86M
      visitMachineBundleAfter(CurBundle);
457
2.88M
    if (InBundle)
458
0
      report("BundledSucc flag set on last instruction in block", &MFI->back());
459
2.88M
    visitMachineBasicBlockAfter(&*MFI);
460
2.88M
  }
461
2.28M
  visitMachineFunctionAfter();
462
2.28M
463
2.28M
  // Clean up.
464
2.28M
  regsLive.clear();
465
2.28M
  regsDefined.clear();
466
2.28M
  regsDead.clear();
467
2.28M
  regsKilled.clear();
468
2.28M
  regMasks.clear();
469
2.28M
  MBBInfoMap.clear();
470
2.28M
471
2.28M
  return foundErrors;
472
2.28M
}
473
474
239
void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
475
239
  assert(MF);
476
239
  errs() << '\n';
477
239
  if (!foundErrors++) {
478
70
    if (Banner)
479
3
      errs() << "# " << Banner << '\n';
480
70
    if (LiveInts != nullptr)
481
2
      LiveInts->print(errs());
482
68
    else
483
68
      MF->print(errs(), Indexes);
484
70
  }
485
239
  errs() << "*** Bad machine code: " << msg << " ***\n"
486
239
      << "- function:    " << MF->getName() << "\n";
487
239
}
488
489
239
void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
490
239
  assert(MBB);
491
239
  report(msg, MBB->getParent());
492
239
  errs() << "- basic block: " << printMBBReference(*MBB) << ' '
493
239
         << MBB->getName() << " (" << (const void *)MBB << ')';
494
239
  if (Indexes)
495
5
    errs() << " [" << Indexes->getMBBStartIdx(MBB)
496
5
        << ';' <<  Indexes->getMBBEndIdx(MBB) << ')';
497
239
  errs() << '\n';
498
239
}
499
500
238
void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
501
238
  assert(MI);
502
238
  report(msg, MI->getParent());
503
238
  errs() << "- instruction: ";
504
238
  if (Indexes && 
Indexes->hasIndex(*MI)5
)
505
5
    errs() << Indexes->getInstructionIndex(*MI) << '\t';
506
238
  MI->print(errs(), /*SkipOpers=*/true);
507
238
}
508
509
void MachineVerifier::report(const char *msg, const MachineOperand *MO,
510
31
                             unsigned MONum, LLT MOVRegType) {
511
31
  assert(MO);
512
31
  report(msg, MO->getParent());
513
31
  errs() << "- operand " << MONum << ":   ";
514
31
  MO->print(errs(), MOVRegType, TRI);
515
31
  errs() << "\n";
516
31
}
517
518
0
void MachineVerifier::report_context(SlotIndex Pos) const {
519
0
  errs() << "- at:          " << Pos << '\n';
520
0
}
521
522
0
void MachineVerifier::report_context(const LiveInterval &LI) const {
523
0
  errs() << "- interval:    " << LI << '\n';
524
0
}
525
526
void MachineVerifier::report_context(const LiveRange &LR, unsigned VRegUnit,
527
0
                                     LaneBitmask LaneMask) const {
528
0
  report_context_liverange(LR);
529
0
  report_context_vreg_regunit(VRegUnit);
530
0
  if (LaneMask.any())
531
0
    report_context_lanemask(LaneMask);
532
0
}
533
534
0
void MachineVerifier::report_context(const LiveRange::Segment &S) const {
535
0
  errs() << "- segment:     " << S << '\n';
536
0
}
537
538
0
void MachineVerifier::report_context(const VNInfo &VNI) const {
539
0
  errs() << "- ValNo:       " << VNI.id << " (def " << VNI.def << ")\n";
540
0
}
541
542
5
void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
543
5
  errs() << "- liverange:   " << LR << '\n';
544
5
}
545
546
0
void MachineVerifier::report_context(MCPhysReg PReg) const {
547
0
  errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
548
0
}
549
550
5
void MachineVerifier::report_context_vreg(unsigned VReg) const {
551
5
  errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
552
5
}
553
554
5
void MachineVerifier::report_context_vreg_regunit(unsigned VRegOrUnit) const {
555
5
  if (TargetRegisterInfo::isVirtualRegister(VRegOrUnit)) {
556
5
    report_context_vreg(VRegOrUnit);
557
5
  } else {
558
0
    errs() << "- regunit:     " << printRegUnit(VRegOrUnit, TRI) << '\n';
559
0
  }
560
5
}
561
562
3
void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
563
3
  errs() << "- lanemask:    " << PrintLaneMask(LaneMask) << '\n';
564
3
}
565
566
3.13M
void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
567
3.13M
  BBInfo &MInfo = MBBInfoMap[MBB];
568
3.13M
  if (!MInfo.reachable) {
569
2.88M
    MInfo.reachable = true;
570
2.88M
    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
571
3.73M
           SuE = MBB->succ_end(); SuI != SuE; 
++SuI850k
)
572
850k
      markReachable(*SuI);
573
2.88M
  }
574
3.13M
}
575
576
2.28M
void MachineVerifier::visitMachineFunctionBefore() {
577
2.28M
  lastIndex = SlotIndex();
578
2.28M
  regsReserved = MRI->reservedRegsFrozen() ? 
MRI->getReservedRegs()2.28M
579
2.28M
                                           : 
TRI->getReservedRegs(*MF)5.76k
;
580
2.28M
581
2.28M
  if (!MF->empty())
582
2.28M
    markReachable(&MF->front());
583
2.28M
584
2.28M
  // Build a set of the basic blocks in the function.
585
2.28M
  FunctionBlocks.clear();
586
2.88M
  for (const auto &MBB : *MF) {
587
2.88M
    FunctionBlocks.insert(&MBB);
588
2.88M
    BBInfo &MInfo = MBBInfoMap[&MBB];
589
2.88M
590
2.88M
    MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
591
2.88M
    if (MInfo.Preds.size() != MBB.pred_size())
592
0
      report("MBB has duplicate entries in its predecessor list.", &MBB);
593
2.88M
594
2.88M
    MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
595
2.88M
    if (MInfo.Succs.size() != MBB.succ_size())
596
0
      report("MBB has duplicate entries in its successor list.", &MBB);
597
2.88M
  }
598
2.28M
599
2.28M
  // Check that the register use lists are sane.
600
2.28M
  MRI->verifyUseLists();
601
2.28M
602
2.28M
  if (!MF->empty())
603
2.28M
    verifyStackFrame();
604
2.28M
}
605
606
// Does iterator point to a and b as the first two elements?
607
static bool matchPair(MachineBasicBlock::const_succ_iterator i,
608
236k
                      const MachineBasicBlock *a, const MachineBasicBlock *b) {
609
236k
  if (*i == a)
610
122k
    return *++i == b;
611
114k
  if (*i == b)
612
114k
    return *++i == a;
613
0
  return false;
614
0
}
615
616
void
617
2.88M
MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
618
2.88M
  FirstTerminator = nullptr;
619
2.88M
  FirstNonPHI = nullptr;
620
2.88M
621
2.88M
  if (!MF->getProperties().hasProperty(
622
2.88M
      MachineFunctionProperties::Property::NoPHIs) && 
MRI->tracksLiveness()968k
) {
623
967k
    // If this block has allocatable physical registers live-in, check that
624
967k
    // it is an entry block or landing pad.
625
1.49M
    for (const auto &LI : MBB->liveins()) {
626
1.49M
      if (isAllocatable(LI.PhysReg) && 
!MBB->isEHPad()1.47M
&&
627
1.49M
          
MBB->getIterator() != MBB->getParent()->begin()1.47M
) {
628
0
        report("MBB has allocatable live-in, but isn't entry or landing-pad.", MBB);
629
0
        report_context(LI.PhysReg);
630
0
      }
631
1.49M
    }
632
967k
  }
633
2.88M
634
2.88M
  // Count the number of landing pad successors.
635
2.88M
  SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
636
2.88M
  for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
637
3.73M
       E = MBB->succ_end(); I != E; 
++I850k
) {
638
850k
    if ((*I)->isEHPad())
639
9.94k
      LandingPadSuccs.insert(*I);
640
850k
    if (!FunctionBlocks.count(*I))
641
0
      report("MBB has successor that isn't part of the function.", MBB);
642
850k
    if (!MBBInfoMap[*I].Preds.count(MBB)) {
643
0
      report("Inconsistent CFG", MBB);
644
0
      errs() << "MBB is not in the predecessor list of the successor "
645
0
             << printMBBReference(*(*I)) << ".\n";
646
0
    }
647
850k
  }
648
2.88M
649
2.88M
  // Check the predecessor list.
650
2.88M
  for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
651
3.73M
       E = MBB->pred_end(); I != E; 
++I850k
) {
652
850k
    if (!FunctionBlocks.count(*I))
653
0
      report("MBB has predecessor that isn't part of the function.", MBB);
654
850k
    if (!MBBInfoMap[*I].Succs.count(MBB)) {
655
0
      report("Inconsistent CFG", MBB);
656
0
      errs() << "MBB is not in the successor list of the predecessor "
657
0
             << printMBBReference(*(*I)) << ".\n";
658
0
    }
659
850k
  }
660
2.88M
661
2.88M
  const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
662
2.88M
  const BasicBlock *BB = MBB->getBasicBlock();
663
2.88M
  const Function &F = MF->getFunction();
664
2.88M
  if (LandingPadSuccs.size() > 1 &&
665
2.88M
      
!(242
AsmInfo242
&&
666
242
        AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
667
242
        
BB0
&&
isa<SwitchInst>(BB->getTerminator())0
) &&
668
2.88M
      
!isScopedEHPersonality(classifyEHPersonality(F.getPersonalityFn()))242
)
669
0
    report("MBB has more than one landing pad successor", MBB);
670
2.88M
671
2.88M
  // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
672
2.88M
  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
673
2.88M
  SmallVector<MachineOperand, 4> Cond;
674
2.88M
  if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
675
2.88M
                          Cond)) {
676
545k
    // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
677
545k
    // check whether its answers match up with reality.
678
545k
    if (!TBB && 
!FBB238k
) {
679
238k
      // Block falls through to its successor.
680
238k
      MachineFunction::const_iterator MBBI = MBB->getIterator();
681
238k
      ++MBBI;
682
238k
      if (MBBI == MF->end()) {
683
43.1k
        // It's possible that the block legitimately ends with a noreturn
684
43.1k
        // call or an unreachable, in which case it won't actually fall
685
43.1k
        // out the bottom of the function.
686
195k
      } else if (MBB->succ_size() == LandingPadSuccs.size()) {
687
11.9k
        // It's possible that the block legitimately ends with a noreturn
688
11.9k
        // call or an unreachable, in which case it won't actually fall
689
11.9k
        // out of the block.
690
183k
      } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
691
0
        report("MBB exits via unconditional fall-through but doesn't have "
692
0
               "exactly one CFG successor!", MBB);
693
183k
      } else if (!MBB->isSuccessor(&*MBBI)) {
694
0
        report("MBB exits via unconditional fall-through but its successor "
695
0
               "differs from its CFG successor!", MBB);
696
0
      }
697
238k
      if (!MBB->empty() && 
MBB->back().isBarrier()215k
&&
698
238k
          
!TII->isPredicated(MBB->back())5
) {
699
0
        report("MBB exits via unconditional fall-through but ends with a "
700
0
               "barrier instruction!", MBB);
701
0
      }
702
238k
      if (!Cond.empty()) {
703
0
        report("MBB exits via unconditional fall-through but has a condition!",
704
0
               MBB);
705
0
      }
706
306k
    } else if (TBB && !FBB && 
Cond.empty()184k
) {
707
69.8k
      // Block unconditionally branches somewhere.
708
69.8k
      // If the block has exactly one successor, that happens to be a
709
69.8k
      // landingpad, accept it as valid control flow.
710
69.8k
      if (MBB->succ_size() != 1+LandingPadSuccs.size() &&
711
69.8k
          
(0
MBB->succ_size() != 10
||
LandingPadSuccs.size() != 10
||
712
0
           *MBB->succ_begin() != *LandingPadSuccs.begin())) {
713
0
        report("MBB exits via unconditional branch but doesn't have "
714
0
               "exactly one CFG successor!", MBB);
715
69.8k
      } else if (!MBB->isSuccessor(TBB)) {
716
1
        report("MBB exits via unconditional branch but the CFG "
717
1
               "successor doesn't match the actual successor!", MBB);
718
1
      }
719
69.8k
      if (MBB->empty()) {
720
0
        report("MBB exits via unconditional branch but doesn't contain "
721
0
               "any instructions!", MBB);
722
69.8k
      } else if (!MBB->back().isBarrier()) {
723
0
        report("MBB exits via unconditional branch but doesn't end with a "
724
0
               "barrier instruction!", MBB);
725
69.8k
      } else if (!MBB->back().isTerminator()) {
726
0
        report("MBB exits via unconditional branch but the branch isn't a "
727
0
               "terminator instruction!", MBB);
728
0
      }
729
236k
    } else if (TBB && !FBB && 
!Cond.empty()114k
) {
730
114k
      // Block conditionally branches somewhere, otherwise falls through.
731
114k
      MachineFunction::const_iterator MBBI = MBB->getIterator();
732
114k
      ++MBBI;
733
114k
      if (MBBI == MF->end()) {
734
0
        report("MBB conditionally falls through out of function!", MBB);
735
114k
      } else if (MBB->succ_size() == 1) {
736
56
        // A conditional branch with only one successor is weird, but allowed.
737
56
        if (&*MBBI != TBB)
738
0
          report("MBB exits via conditional branch/fall-through but only has "
739
0
                 "one CFG successor!", MBB);
740
56
        else if (TBB != *MBB->succ_begin())
741
0
          report("MBB exits via conditional branch/fall-through but the CFG "
742
0
                 "successor don't match the actual successor!", MBB);
743
114k
      } else if (MBB->succ_size() != 2) {
744
0
        report("MBB exits via conditional branch/fall-through but doesn't have "
745
0
               "exactly two CFG successors!", MBB);
746
114k
      } else if (!matchPair(MBB->succ_begin(), TBB, &*MBBI)) {
747
0
        report("MBB exits via conditional branch/fall-through but the CFG "
748
0
               "successors don't match the actual successors!", MBB);
749
0
      }
750
114k
      if (MBB->empty()) {
751
0
        report("MBB exits via conditional branch/fall-through but doesn't "
752
0
               "contain any instructions!", MBB);
753
114k
      } else if (MBB->back().isBarrier()) {
754
0
        report("MBB exits via conditional branch/fall-through but ends with a "
755
0
               "barrier instruction!", MBB);
756
114k
      } else if (!MBB->back().isTerminator()) {
757
0
        report("MBB exits via conditional branch/fall-through but the branch "
758
0
               "isn't a terminator instruction!", MBB);
759
0
      }
760
121k
    } else if (TBB && FBB) {
761
121k
      // Block conditionally branches somewhere, otherwise branches
762
121k
      // somewhere else.
763
121k
      if (MBB->succ_size() == 1) {
764
108
        // A conditional branch with only one successor is weird, but allowed.
765
108
        if (FBB != TBB)
766
0
          report("MBB exits via conditional branch/branch through but only has "
767
0
                 "one CFG successor!", MBB);
768
108
        else if (TBB != *MBB->succ_begin())
769
0
          report("MBB exits via conditional branch/branch through but the CFG "
770
0
                 "successor don't match the actual successor!", MBB);
771
121k
      } else if (MBB->succ_size() != 2) {
772
0
        report("MBB exits via conditional branch/branch but doesn't have "
773
0
               "exactly two CFG successors!", MBB);
774
121k
      } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
775
0
        report("MBB exits via conditional branch/branch but the CFG "
776
0
               "successors don't match the actual successors!", MBB);
777
0
      }
778
121k
      if (MBB->empty()) {
779
0
        report("MBB exits via conditional branch/branch but doesn't "
780
0
               "contain any instructions!", MBB);
781
121k
      } else if (!MBB->back().isBarrier()) {
782
0
        report("MBB exits via conditional branch/branch but doesn't end with a "
783
0
               "barrier instruction!", MBB);
784
121k
      } else if (!MBB->back().isTerminator()) {
785
0
        report("MBB exits via conditional branch/branch but the branch "
786
0
               "isn't a terminator instruction!", MBB);
787
0
      }
788
121k
      if (Cond.empty()) {
789
0
        report("MBB exits via conditional branch/branch but there's no "
790
0
               "condition!", MBB);
791
0
      }
792
121k
    } else {
793
0
      report("AnalyzeBranch returned invalid data!", MBB);
794
0
    }
795
545k
  }
796
2.88M
797
2.88M
  regsLive.clear();
798
2.88M
  if (MRI->tracksLiveness()) {
799
5.61M
    for (const auto &LI : MBB->liveins()) {
800
5.61M
      if (!TargetRegisterInfo::isPhysicalRegister(LI.PhysReg)) {
801
0
        report("MBB live-in list contains non-physical register", MBB);
802
0
        continue;
803
0
      }
804
5.61M
      for (MCSubRegIterator SubRegs(LI.PhysReg, TRI, /*IncludeSelf=*/true);
805
16.8M
           SubRegs.isValid(); 
++SubRegs11.2M
)
806
11.2M
        regsLive.insert(*SubRegs);
807
5.61M
    }
808
2.80M
  }
809
2.88M
810
2.88M
  const MachineFrameInfo &MFI = MF->getFrameInfo();
811
2.88M
  BitVector PR = MFI.getPristineRegs(*MF);
812
24.3M
  for (unsigned I : PR.set_bits()) {
813
24.3M
    for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true);
814
62.8M
         SubRegs.isValid(); 
++SubRegs38.5M
)
815
38.5M
      regsLive.insert(*SubRegs);
816
24.3M
  }
817
2.88M
818
2.88M
  regsKilled.clear();
819
2.88M
  regsDefined.clear();
820
2.88M
821
2.88M
  if (Indexes)
822
423k
    lastIndex = Indexes->getMBBStartIdx(MBB);
823
2.88M
}
824
825
// This function gets called for all bundle headers, including normal
826
// stand-alone unbundled instructions.
827
33.3M
void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
828
33.3M
  if (Indexes && 
Indexes->hasIndex(*MI)4.65M
) {
829
4.65M
    SlotIndex idx = Indexes->getInstructionIndex(*MI);
830
4.65M
    if (!(idx > lastIndex)) {
831
0
      report("Instruction index out of order", MI);
832
0
      errs() << "Last instruction was at " << lastIndex << '\n';
833
0
    }
834
4.65M
    lastIndex = idx;
835
4.65M
  }
836
33.3M
837
33.3M
  // Ensure non-terminators don't follow terminators.
838
33.3M
  // Ignore predicated terminators formed by if conversion.
839
33.3M
  // FIXME: If conversion shouldn't need to violate this rule.
840
33.3M
  if (MI->isTerminator() && 
!TII->isPredicated(*MI)2.85M
) {
841
2.82M
    if (!FirstTerminator)
842
2.65M
      FirstTerminator = MI;
843
30.5M
  } else if (FirstTerminator && 
!MI->isDebugEntryValue()0
) {
844
0
    report("Non-terminator instruction after the first terminator", MI);
845
0
    errs() << "First terminator was:\t" << *FirstTerminator;
846
0
  }
847
33.3M
}
848
849
// The operands on an INLINEASM instruction must follow a template.
850
// Verify that the flag operands make sense.
851
145k
void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
852
145k
  // The first two operands on INLINEASM are the asm string and global flags.
853
145k
  if (MI->getNumOperands() < 2) {
854
0
    report("Too few operands on inline asm", MI);
855
0
    return;
856
0
  }
857
145k
  if (!MI->getOperand(0).isSymbol())
858
0
    report("Asm string must be an external symbol", MI);
859
145k
  if (!MI->getOperand(1).isImm())
860
0
    report("Asm flags must be an immediate", MI);
861
145k
  // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
862
145k
  // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16,
863
145k
  // and Extra_IsConvergent = 32.
864
145k
  if (!isUInt<6>(MI->getOperand(1).getImm()))
865
0
    report("Unknown asm flags", &MI->getOperand(1), 1);
866
145k
867
145k
  static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
868
145k
869
145k
  unsigned OpNo = InlineAsm::MIOp_FirstOperand;
870
145k
  unsigned NumOps;
871
676k
  for (unsigned e = MI->getNumOperands(); OpNo < e; 
OpNo += NumOps530k
) {
872
531k
    const MachineOperand &MO = MI->getOperand(OpNo);
873
531k
    // There may be implicit ops after the fixed operands.
874
531k
    if (!MO.isImm())
875
826
      break;
876
530k
    NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
877
530k
  }
878
145k
879
145k
  if (OpNo > MI->getNumOperands())
880
0
    report("Missing operands in last group", MI);
881
145k
882
145k
  // An optional MDNode follows the groups.
883
145k
  if (OpNo < MI->getNumOperands() && 
MI->getOperand(OpNo).isMetadata()826
)
884
467
    ++OpNo;
885
145k
886
145k
  // All trailing operands must be implicit registers.
887
146k
  for (unsigned e = MI->getNumOperands(); OpNo < e; 
++OpNo555
) {
888
555
    const MachineOperand &MO = MI->getOperand(OpNo);
889
555
    if (!MO.isReg() || !MO.isImplicit())
890
0
      report("Expected implicit register after groups", &MO, OpNo);
891
555
  }
892
145k
}
893
894
/// Check that types are consistent when two operands need to have the same
895
/// number of vector elements.
896
/// \return true if the types are valid.
897
bool MachineVerifier::verifyVectorElementMatch(LLT Ty0, LLT Ty1,
898
10.0k
                                               const MachineInstr *MI) {
899
10.0k
  if (Ty0.isVector() != Ty1.isVector()) {
900
10
    report("operand types must be all-vector or all-scalar", MI);
901
10
    // Generally we try to report as many issues as possible at once, but in
902
10
    // this case it's not clear what should we be comparing the size of the
903
10
    // scalar with: the size of the whole vector or its lane. Instead of
904
10
    // making an arbitrary choice and emitting not so helpful message, let's
905
10
    // avoid the extra noise and stop here.
906
10
    return false;
907
10
  }
908
10.0k
909
10.0k
  if (Ty0.isVector() && 
Ty0.getNumElements() != Ty1.getNumElements()601
) {
910
10
    report("operand types must preserve number of vector elements", MI);
911
10
    return false;
912
10
  }
913
10.0k
914
10.0k
  return true;
915
10.0k
}
916
917
57.8k
void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
918
57.8k
  if (isFunctionSelected)
919
1
    report("Unexpected generic instruction in a Selected function", MI);
920
57.8k
921
57.8k
  const MCInstrDesc &MCID = MI->getDesc();
922
57.8k
  unsigned NumOps = MI->getNumOperands();
923
57.8k
924
57.8k
  // Check types.
925
57.8k
  SmallVector<LLT, 4> Types;
926
57.8k
  for (unsigned I = 0, E = std::min(MCID.getNumOperands(), NumOps);
927
194k
       I != E; 
++I136k
) {
928
136k
    if (!MCID.OpInfo[I].isGenericType())
929
19.6k
      continue;
930
116k
    // Generic instructions specify type equality constraints between some of
931
116k
    // their operands. Make sure these are consistent.
932
116k
    size_t TypeIdx = MCID.OpInfo[I].getGenericTypeIndex();
933
116k
    Types.resize(std::max(TypeIdx + 1, Types.size()));
934
116k
935
116k
    const MachineOperand *MO = &MI->getOperand(I);
936
116k
    if (!MO->isReg()) {
937
6
      report("generic instruction must use register operands", MI);
938
6
      continue;
939
6
    }
940
116k
941
116k
    LLT OpTy = MRI->getType(MO->getReg());
942
116k
    // Don't report a type mismatch if there is no actual mismatch, only a
943
116k
    // type missing, to reduce noise:
944
116k
    if (OpTy.isValid()) {
945
116k
      // Only the first valid type for a type index will be printed: don't
946
116k
      // overwrite it later so it's always clear which type was expected:
947
116k
      if (!Types[TypeIdx].isValid())
948
88.5k
        Types[TypeIdx] = OpTy;
949
28.2k
      else if (Types[TypeIdx] != OpTy)
950
7
        report("Type mismatch in generic instruction", MO, I, OpTy);
951
116k
    } else {
952
5
      // Generic instructions must have types attached to their operands.
953
5
      report("Generic instruction is missing a virtual register type", MO, I);
954
5
    }
955
116k
  }
956
57.8k
957
57.8k
  // Generic opcodes must not have physical register operands.
958
206k
  for (unsigned I = 0; I < MI->getNumOperands(); 
++I148k
) {
959
148k
    const MachineOperand *MO = &MI->getOperand(I);
960
148k
    if (MO->isReg() && 
TargetRegisterInfo::isPhysicalRegister(MO->getReg())126k
)
961
0
      report("Generic instruction cannot have physical register", MO, I);
962
148k
  }
963
57.8k
964
57.8k
  // Avoid out of bounds in checks below. This was already reported earlier.
965
57.8k
  if (MI->getNumOperands() < MCID.getNumOperands())
966
21
    return;
967
57.8k
968
57.8k
  StringRef ErrorInfo;
969
57.8k
  if (!TII->verifyInstruction(*MI, ErrorInfo))
970
0
    report(ErrorInfo.data(), MI);
971
57.8k
972
57.8k
  // Verify properties of various specific instruction types
973
57.8k
  switch (MI->getOpcode()) {
974
57.8k
  case TargetOpcode::G_CONSTANT:
975
7.03k
  case TargetOpcode::G_FCONSTANT: {
976
7.03k
    if (MI->getNumOperands() < MCID.getNumOperands())
977
0
      break;
978
7.03k
979
7.03k
    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
980
7.03k
    if (DstTy.isVector())
981
2
      report("Instruction cannot use a vector result type", MI);
982
7.03k
983
7.03k
    if (MI->getOpcode() == TargetOpcode::G_CONSTANT) {
984
6.56k
      if (!MI->getOperand(1).isCImm()) {
985
2
        report("G_CONSTANT operand must be cimm", MI);
986
2
        break;
987
2
      }
988
6.56k
989
6.56k
      const ConstantInt *CI = MI->getOperand(1).getCImm();
990
6.56k
      if (CI->getBitWidth() != DstTy.getSizeInBits())
991
11
        report("inconsistent constant size", MI);
992
6.56k
    } else {
993
474
      if (!MI->getOperand(1).isFPImm()) {
994
2
        report("G_FCONSTANT operand must be fpimm", MI);
995
2
        break;
996
2
      }
997
472
      const ConstantFP *CF = MI->getOperand(1).getFPImm();
998
472
999
472
      if (APFloat::getSizeInBits(CF->getValueAPF().getSemantics()) !=
1000
472
          DstTy.getSizeInBits()) {
1001
4
        report("inconsistent constant size", MI);
1002
4
      }
1003
472
    }
1004
7.03k
1005
7.03k
    
break7.03k
;
1006
7.03k
  }
1007
8.57k
  case TargetOpcode::G_LOAD:
1008
8.57k
  case TargetOpcode::G_STORE:
1009
8.57k
  case TargetOpcode::G_ZEXTLOAD:
1010
8.57k
  case TargetOpcode::G_SEXTLOAD: {
1011
8.57k
    LLT ValTy = MRI->getType(MI->getOperand(0).getReg());
1012
8.57k
    LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1013
8.57k
    if (!PtrTy.isPointer())
1014
4
      report("Generic memory instruction must access a pointer", MI);
1015
8.57k
1016
8.57k
    // Generic loads and stores must have a single MachineMemOperand
1017
8.57k
    // describing that access.
1018
8.57k
    if (!MI->hasOneMemOperand()) {
1019
2
      report("Generic instruction accessing memory must have one mem operand",
1020
2
             MI);
1021
8.57k
    } else {
1022
8.57k
      const MachineMemOperand &MMO = **MI->memoperands_begin();
1023
8.57k
      if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1024
8.57k
          
MI->getOpcode() == TargetOpcode::G_SEXTLOAD8.45k
) {
1025
237
        if (MMO.getSizeInBits() >= ValTy.getSizeInBits())
1026
4
          report("Generic extload must have a narrower memory type", MI);
1027
8.33k
      } else if (MI->getOpcode() == TargetOpcode::G_LOAD) {
1028
4.79k
        if (MMO.getSize() > ValTy.getSizeInBytes())
1029
1
          report("load memory size cannot exceed result size", MI);
1030
4.79k
      } else 
if (3.54k
MI->getOpcode() == TargetOpcode::G_STORE3.54k
) {
1031
3.54k
        if (ValTy.getSizeInBytes() < MMO.getSize())
1032
1
          report("store memory size cannot exceed value size", MI);
1033
3.54k
      }
1034
8.57k
    }
1035
8.57k
1036
8.57k
    break;
1037
8.57k
  }
1038
8.57k
  case TargetOpcode::G_PHI: {
1039
864
    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1040
864
    if (!DstTy.isValid() ||
1041
864
        !std::all_of(MI->operands_begin() + 1, MI->operands_end(),
1042
3.86k
                     [this, &DstTy](const MachineOperand &MO) {
1043
3.86k
                       if (!MO.isReg())
1044
1.93k
                         return true;
1045
1.93k
                       LLT Ty = MRI->getType(MO.getReg());
1046
1.93k
                       if (!Ty.isValid() || (Ty != DstTy))
1047
1
                         return false;
1048
1.93k
                       return true;
1049
1.93k
                     }))
1050
1
      report("Generic Instruction G_PHI has operands with incompatible/missing "
1051
1
             "types",
1052
1
             MI);
1053
864
    break;
1054
8.57k
  }
1055
8.57k
  case TargetOpcode::G_BITCAST: {
1056
163
    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1057
163
    LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1058
163
    if (!DstTy.isValid() || !SrcTy.isValid())
1059
0
      break;
1060
163
1061
163
    if (SrcTy.isPointer() != DstTy.isPointer())
1062
2
      report("bitcast cannot convert between pointers and other types", MI);
1063
163
1064
163
    if (SrcTy.getSizeInBits() != DstTy.getSizeInBits())
1065
4
      report("bitcast sizes must match", MI);
1066
163
    break;
1067
163
  }
1068
340
  case TargetOpcode::G_INTTOPTR:
1069
340
  case TargetOpcode::G_PTRTOINT:
1070
340
  case TargetOpcode::G_ADDRSPACE_CAST: {
1071
340
    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1072
340
    LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1073
340
    if (!DstTy.isValid() || !SrcTy.isValid())
1074
0
      break;
1075
340
1076
340
    verifyVectorElementMatch(DstTy, SrcTy, MI);
1077
340
1078
340
    DstTy = DstTy.getScalarType();
1079
340
    SrcTy = SrcTy.getScalarType();
1080
340
1081
340
    if (MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1082
166
      if (!DstTy.isPointer())
1083
3
        report("inttoptr result type must be a pointer", MI);
1084
166
      if (SrcTy.isPointer())
1085
1
        report("inttoptr source type must not be a pointer", MI);
1086
174
    } else if (MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1087
128
      if (!SrcTy.isPointer())
1088
2
        report("ptrtoint source type must be a pointer", MI);
1089
128
      if (DstTy.isPointer())
1090
2
        report("ptrtoint result type must not be a pointer", MI);
1091
128
    } else {
1092
46
      assert(MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST);
1093
46
      if (!SrcTy.isPointer() || 
!DstTy.isPointer()44
)
1094
4
        report("addrspacecast types must be pointers", MI);
1095
42
      else {
1096
42
        if (SrcTy.getAddressSpace() == DstTy.getAddressSpace())
1097
2
          report("addrspacecast must convert different address spaces", MI);
1098
42
      }
1099
46
    }
1100
340
1101
340
    break;
1102
340
  }
1103
1.72k
  case TargetOpcode::G_GEP: {
1104
1.72k
    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1105
1.72k
    LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1106
1.72k
    LLT OffsetTy = MRI->getType(MI->getOperand(2).getReg());
1107
1.72k
    if (!DstTy.isValid() || !PtrTy.isValid() || !OffsetTy.isValid())
1108
0
      break;
1109
1.72k
1110
1.72k
    if (!PtrTy.getScalarType().isPointer())
1111
2
      report("gep first operand must be a pointer", MI);
1112
1.72k
1113
1.72k
    if (OffsetTy.getScalarType().isPointer())
1114
1
      report("gep offset operand must not be a pointer", MI);
1115
1.72k
1116
1.72k
    // TODO: Is the offset allowed to be a scalar with a vector?
1117
1.72k
    break;
1118
1.72k
  }
1119
9.65k
  case TargetOpcode::G_SEXT:
1120
9.65k
  case TargetOpcode::G_ZEXT:
1121
9.65k
  case TargetOpcode::G_ANYEXT:
1122
9.65k
  case TargetOpcode::G_TRUNC:
1123
9.65k
  case TargetOpcode::G_FPEXT:
1124
9.65k
  case TargetOpcode::G_FPTRUNC: {
1125
9.65k
    // Number of operands and presense of types is already checked (and
1126
9.65k
    // reported in case of any issues), so no need to report them again. As
1127
9.65k
    // we're trying to report as many issues as possible at once, however, the
1128
9.65k
    // instructions aren't guaranteed to have the right number of operands or
1129
9.65k
    // types attached to them at this point
1130
9.65k
    assert(MCID.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}");
1131
9.65k
    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1132
9.65k
    LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1133
9.65k
    if (!DstTy.isValid() || !SrcTy.isValid())
1134
0
      break;
1135
9.65k
1136
9.65k
    LLT DstElTy = DstTy.getScalarType();
1137
9.65k
    LLT SrcElTy = SrcTy.getScalarType();
1138
9.65k
    if (DstElTy.isPointer() || 
SrcElTy.isPointer()9.65k
)
1139
3
      report("Generic extend/truncate can not operate on pointers", MI);
1140
9.65k
1141
9.65k
    verifyVectorElementMatch(DstTy, SrcTy, MI);
1142
9.65k
1143
9.65k
    unsigned DstSize = DstElTy.getSizeInBits();
1144
9.65k
    unsigned SrcSize = SrcElTy.getSizeInBits();
1145
9.65k
    switch (MI->getOpcode()) {
1146
9.65k
    default:
1147
4.31k
      if (DstSize <= SrcSize)
1148
3
        report("Generic extend has destination type no larger than source", MI);
1149
4.31k
      break;
1150
9.65k
    case TargetOpcode::G_TRUNC:
1151
5.34k
    case TargetOpcode::G_FPTRUNC:
1152
5.34k
      if (DstSize >= SrcSize)
1153
1
        report("Generic truncate has destination type no smaller than source",
1154
1
               MI);
1155
5.34k
      break;
1156
9.65k
    }
1157
9.65k
    break;
1158
9.65k
  }
1159
9.65k
  case TargetOpcode::G_SELECT: {
1160
1.52k
    LLT SelTy = MRI->getType(MI->getOperand(0).getReg());
1161
1.52k
    LLT CondTy = MRI->getType(MI->getOperand(1).getReg());
1162
1.52k
    if (!SelTy.isValid() || !CondTy.isValid())
1163
0
      break;
1164
1.52k
1165
1.52k
    // Scalar condition select on a vector is valid.
1166
1.52k
    if (CondTy.isVector())
1167
29
      verifyVectorElementMatch(SelTy, CondTy, MI);
1168
1.52k
    break;
1169
1.52k
  }
1170
1.52k
  case TargetOpcode::G_MERGE_VALUES: {
1171
1.21k
    // G_MERGE_VALUES should only be used to merge scalars into a larger scalar,
1172
1.21k
    // e.g. s2N = MERGE sN, sN
1173
1.21k
    // Merging multiple scalars into a vector is not allowed, should use
1174
1.21k
    // G_BUILD_VECTOR for that.
1175
1.21k
    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1176
1.21k
    LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1177
1.21k
    if (DstTy.isVector() || 
SrcTy.isVector()1.21k
)
1178
1
      report("G_MERGE_VALUES cannot operate on vectors", MI);
1179
1.21k
1180
1.21k
    const unsigned NumOps = MI->getNumOperands();
1181
1.21k
    if (DstTy.getSizeInBits() != SrcTy.getSizeInBits() * (NumOps - 1))
1182
2
      report("G_MERGE_VALUES result size is inconsistent", MI);
1183
1.21k
1184
2.58k
    for (unsigned I = 2; I != NumOps; 
++I1.37k
) {
1185
1.37k
      if (MRI->getType(MI->getOperand(I).getReg()) != SrcTy)
1186
1
        report("G_MERGE_VALUES source types do not match", MI);
1187
1.37k
    }
1188
1.21k
1189
1.21k
    break;
1190
1.52k
  }
1191
1.52k
  case TargetOpcode::G_UNMERGE_VALUES: {
1192
892
    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1193
892
    LLT SrcTy = MRI->getType(MI->getOperand(MI->getNumOperands()-1).getReg());
1194
892
    // For now G_UNMERGE can split vectors.
1195
3.02k
    for (unsigned i = 0; i < MI->getNumOperands()-1; 
++i2.13k
) {
1196
2.13k
      if (MRI->getType(MI->getOperand(i).getReg()) != DstTy)
1197
0
        report("G_UNMERGE_VALUES destination types do not match", MI);
1198
2.13k
    }
1199
892
    if (SrcTy.getSizeInBits() !=
1200
892
        (DstTy.getSizeInBits() * (MI->getNumOperands() - 1))) {
1201
0
      report("G_UNMERGE_VALUES source operand does not cover dest operands",
1202
0
             MI);
1203
0
    }
1204
892
    break;
1205
1.52k
  }
1206
1.52k
  case TargetOpcode::G_BUILD_VECTOR: {
1207
546
    // Source types must be scalars, dest type a vector. Total size of scalars
1208
546
    // must match the dest vector size.
1209
546
    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1210
546
    LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1211
546
    if (!DstTy.isVector() || 
SrcEltTy.isVector()545
) {
1212
2
      report("G_BUILD_VECTOR must produce a vector from scalar operands", MI);
1213
2
      break;
1214
2
    }
1215
544
1216
544
    if (DstTy.getElementType() != SrcEltTy)
1217
4
      report("G_BUILD_VECTOR result element type must match source type", MI);
1218
544
1219
544
    if (DstTy.getNumElements() != MI->getNumOperands() - 1)
1220
3
      report("G_BUILD_VECTOR must have an operand for each elemement", MI);
1221
544
1222
2.81k
    for (unsigned i = 2; i < MI->getNumOperands(); 
++i2.26k
) {
1223
2.26k
      if (MRI->getType(MI->getOperand(1).getReg()) !=
1224
2.26k
          MRI->getType(MI->getOperand(i).getReg()))
1225
0
        report("G_BUILD_VECTOR source operand types are not homogeneous", MI);
1226
2.26k
    }
1227
544
1228
544
    break;
1229
544
  }
1230
544
  case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1231
1
    // Source types must be scalars, dest type a vector. Scalar types must be
1232
1
    // larger than the dest vector elt type, as this is a truncating operation.
1233
1
    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1234
1
    LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1235
1
    if (!DstTy.isVector() || SrcEltTy.isVector())
1236
0
      report("G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1237
0
             MI);
1238
2
    for (unsigned i = 2; i < MI->getNumOperands(); 
++i1
) {
1239
1
      if (MRI->getType(MI->getOperand(1).getReg()) !=
1240
1
          MRI->getType(MI->getOperand(i).getReg()))
1241
0
        report("G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1242
0
               MI);
1243
1
    }
1244
1
    if (SrcEltTy.getSizeInBits() <= DstTy.getElementType().getSizeInBits())
1245
1
      report("G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1246
1
             "dest elt type",
1247
1
             MI);
1248
1
    break;
1249
544
  }
1250
544
  case TargetOpcode::G_CONCAT_VECTORS: {
1251
209
    // Source types should be vectors, and total size should match the dest
1252
209
    // vector size.
1253
209
    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1254
209
    LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1255
209
    if (!DstTy.isVector() || !SrcTy.isVector())
1256
0
      report("G_CONCAT_VECTOR requires vector source and destination operands",
1257
0
             MI);
1258
486
    for (unsigned i = 2; i < MI->getNumOperands(); 
++i277
) {
1259
277
      if (MRI->getType(MI->getOperand(1).getReg()) !=
1260
277
          MRI->getType(MI->getOperand(i).getReg()))
1261
0
        report("G_CONCAT_VECTOR source operand types are not homogeneous", MI);
1262
277
    }
1263
209
    if (DstTy.getNumElements() !=
1264
209
        SrcTy.getNumElements() * (MI->getNumOperands() - 1))
1265
1
      report("G_CONCAT_VECTOR num dest and source elements should match", MI);
1266
209
    break;
1267
544
  }
1268
4.33k
  case TargetOpcode::G_ICMP:
1269
4.33k
  case TargetOpcode::G_FCMP: {
1270
4.33k
    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1271
4.33k
    LLT SrcTy = MRI->getType(MI->getOperand(2).getReg());
1272
4.33k
1273
4.33k
    if ((DstTy.isVector() != SrcTy.isVector()) ||
1274
4.33k
        
(4.32k
DstTy.isVector()4.32k
&&
DstTy.getNumElements() != SrcTy.getNumElements()430
))
1275
6
      report("Generic vector icmp/fcmp must preserve number of lanes", MI);
1276
4.33k
1277
4.33k
    break;
1278
4.33k
  }
1279
4.33k
  case TargetOpcode::G_EXTRACT: {
1280
297
    const MachineOperand &SrcOp = MI->getOperand(1);
1281
297
    if (!SrcOp.isReg()) {
1282
1
      report("extract source must be a register", MI);
1283
1
      break;
1284
1
    }
1285
296
1286
296
    const MachineOperand &OffsetOp = MI->getOperand(2);
1287
296
    if (!OffsetOp.isImm()) {
1288
1
      report("extract offset must be a constant", MI);
1289
1
      break;
1290
1
    }
1291
295
1292
295
    unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1293
295
    unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1294
295
    if (SrcSize == DstSize)
1295
1
      report("extract source must be larger than result", MI);
1296
295
1297
295
    if (DstSize + OffsetOp.getImm() > SrcSize)
1298
1
      report("extract reads past end of register", MI);
1299
295
    break;
1300
295
  }
1301
295
  case TargetOpcode::G_INSERT: {
1302
238
    const MachineOperand &SrcOp = MI->getOperand(2);
1303
238
    if (!SrcOp.isReg()) {
1304
1
      report("insert source must be a register", MI);
1305
1
      break;
1306
1
    }
1307
237
1308
237
    const MachineOperand &OffsetOp = MI->getOperand(3);
1309
237
    if (!OffsetOp.isImm()) {
1310
2
      report("insert offset must be a constant", MI);
1311
2
      break;
1312
2
    }
1313
235
1314
235
    unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1315
235
    unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1316
235
1317
235
    if (DstSize <= SrcSize)
1318
2
      report("inserted size must be smaller than total register", MI);
1319
235
1320
235
    if (SrcSize + OffsetOp.getImm() > DstSize)
1321
2
      report("insert writes past end of register", MI);
1322
235
1323
235
    break;
1324
235
  }
1325
235
  case TargetOpcode::G_JUMP_TABLE: {
1326
6
    if (!MI->getOperand(1).isJTI())
1327
1
      report("G_JUMP_TABLE source operand must be a jump table index", MI);
1328
6
    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1329
6
    if (!DstTy.isPointer())
1330
2
      report("G_JUMP_TABLE dest operand must have a pointer type", MI);
1331
6
    break;
1332
235
  }
1333
235
  case TargetOpcode::G_BRJT: {
1334
7
    if (!MRI->getType(MI->getOperand(0).getReg()).isPointer())
1335
1
      report("G_BRJT src operand 0 must be a pointer type", MI);
1336
7
1337
7
    if (!MI->getOperand(1).isJTI())
1338
1
      report("G_BRJT src operand 1 must be a jump table index", MI);
1339
7
1340
7
    const auto &IdxOp = MI->getOperand(2);
1341
7
    if (!IdxOp.isReg() || MRI->getType(IdxOp.getReg()).isPointer())
1342
1
      report("G_BRJT src operand 2 must be a scalar reg type", MI);
1343
7
    break;
1344
235
  }
1345
910
  case TargetOpcode::G_INTRINSIC:
1346
910
  case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
1347
910
    // TODO: Should verify number of def and use operands, but the current
1348
910
    // interface requires passing in IR types for mangling.
1349
910
    const MachineOperand &IntrIDOp = MI->getOperand(MI->getNumExplicitDefs());
1350
910
    if (!IntrIDOp.isIntrinsicID()) {
1351
8
      report("G_INTRINSIC first src operand must be an intrinsic ID", MI);
1352
8
      break;
1353
8
    }
1354
902
1355
902
    bool NoSideEffects = MI->getOpcode() == TargetOpcode::G_INTRINSIC;
1356
902
    unsigned IntrID = IntrIDOp.getIntrinsicID();
1357
902
    if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1358
902
      AttributeList Attrs
1359
902
        = Intrinsic::getAttributes(MF->getFunction().getContext(),
1360
902
                                   static_cast<Intrinsic::ID>(IntrID));
1361
902
      bool DeclHasSideEffects = !Attrs.hasFnAttribute(Attribute::ReadNone);
1362
902
      if (NoSideEffects && 
DeclHasSideEffects514
) {
1363
2
        report("G_INTRINSIC used with intrinsic that accesses memory", MI);
1364
2
        break;
1365
2
      }
1366
900
      if (!NoSideEffects && 
!DeclHasSideEffects388
) {
1367
1
        report("G_INTRINSIC_W_SIDE_EFFECTS used with readnone intrinsic", MI);
1368
1
        break;
1369
1
      }
1370
899
    }
1371
899
1372
899
    break;
1373
899
  }
1374
19.2k
  default:
1375
19.2k
    break;
1376
57.8k
  }
1377
57.8k
}
1378
1379
33.4M
void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
1380
33.4M
  const MCInstrDesc &MCID = MI->getDesc();
1381
33.4M
  if (MI->getNumOperands() < MCID.getNumOperands()) {
1382
31
    report("Too few operands", MI);
1383
31
    errs() << MCID.getNumOperands() << " operands expected, but "
1384
31
           << MI->getNumOperands() << " given.\n";
1385
31
  }
1386
33.4M
1387
33.4M
  if (MI->isPHI()) {
1388
119k
    if (MF->getProperties().hasProperty(
1389
119k
            MachineFunctionProperties::Property::NoPHIs))
1390
0
      report("Found PHI instruction with NoPHIs property set", MI);
1391
119k
1392
119k
    if (FirstNonPHI)
1393
1
      report("Found PHI instruction after non-PHI", MI);
1394
33.3M
  } else if (FirstNonPHI == nullptr)
1395
2.86M
    FirstNonPHI = MI;
1396
33.4M
1397
33.4M
  // Check the tied operands.
1398
33.4M
  if (MI->isInlineAsm())
1399
145k
    verifyInlineAsm(MI);
1400
33.4M
1401
33.4M
  // Check the MachineMemOperands for basic consistency.
1402
33.4M
  for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
1403
33.4M
                                  E = MI->memoperands_end();
1404
39.9M
       I != E; 
++I6.45M
) {
1405
6.45M
    if ((*I)->isLoad() && 
!MI->mayLoad()3.80M
)
1406
0
      report("Missing mayLoad flag", MI);
1407
6.45M
    if ((*I)->isStore() && 
!MI->mayStore()2.90M
)
1408
0
      report("Missing mayStore flag", MI);
1409
6.45M
  }
1410
33.4M
1411
33.4M
  // Debug values must not have a slot index.
1412
33.4M
  // Other instructions must have one, unless they are inside a bundle.
1413
33.4M
  if (LiveInts) {
1414
4.12M
    bool mapped = !LiveInts->isNotInMIMap(*MI);
1415
4.12M
    if (MI->isDebugInstr()) {
1416
155
      if (mapped)
1417
0
        report("Debug instruction has a slot index", MI);
1418
4.12M
    } else if (MI->isInsideBundle()) {
1419
22.0k
      if (mapped)
1420
0
        report("Instruction inside bundle has a slot index", MI);
1421
4.10M
    } else {
1422
4.10M
      if (!mapped)
1423
0
        report("Missing slot index", MI);
1424
4.10M
    }
1425
4.12M
  }
1426
33.4M
1427
33.4M
  if (isPreISelGenericOpcode(MCID.getOpcode())) {
1428
57.8k
    verifyPreISelGenericInstruction(MI);
1429
57.8k
    return;
1430
57.8k
  }
1431
33.4M
1432
33.4M
  StringRef ErrorInfo;
1433
33.4M
  if (!TII->verifyInstruction(*MI, ErrorInfo))
1434
29
    report(ErrorInfo.data(), MI);
1435
33.4M
1436
33.4M
  // Verify properties of various specific instruction types
1437
33.4M
  switch (MI->getOpcode()) {
1438
33.4M
  case TargetOpcode::COPY: {
1439
7.54M
    if (foundErrors)
1440
37
      break;
1441
7.54M
    const MachineOperand &DstOp = MI->getOperand(0);
1442
7.54M
    const MachineOperand &SrcOp = MI->getOperand(1);
1443
7.54M
    LLT DstTy = MRI->getType(DstOp.getReg());
1444
7.54M
    LLT SrcTy = MRI->getType(SrcOp.getReg());
1445
7.54M
    if (SrcTy.isValid() && 
DstTy.isValid()21.4k
) {
1446
3.89k
      // If both types are valid, check that the types are the same.
1447
3.89k
      if (SrcTy != DstTy) {
1448
1
        report("Copy Instruction is illegal with mismatching types", MI);
1449
1
        errs() << "Def = " << DstTy << ", Src = " << SrcTy << "\n";
1450
1
      }
1451
3.89k
    }
1452
7.54M
    if (SrcTy.isValid() || 
DstTy.isValid()7.52M
) {
1453
606k
      // If one of them have valid types, let's just check they have the same
1454
606k
      // size.
1455
606k
      unsigned SrcSize = TRI->getRegSizeInBits(SrcOp.getReg(), *MRI);
1456
606k
      unsigned DstSize = TRI->getRegSizeInBits(DstOp.getReg(), *MRI);
1457
606k
      assert(SrcSize && "Expecting size here");
1458
606k
      assert(DstSize && "Expecting size here");
1459
606k
      if (SrcSize != DstSize)
1460
446
        if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
1461
2
          report("Copy Instruction is illegal with mismatching sizes", MI);
1462
2
          errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize
1463
2
                 << "\n";
1464
2
        }
1465
606k
    }
1466
7.54M
    break;
1467
7.54M
  }
1468
7.54M
  case TargetOpcode::STATEPOINT:
1469
3.80k
    if (!MI->getOperand(StatepointOpers::IDPos).isImm() ||
1470
3.80k
        !MI->getOperand(StatepointOpers::NBytesPos).isImm() ||
1471
3.80k
        !MI->getOperand(StatepointOpers::NCallArgsPos).isImm())
1472
0
      report("meta operands to STATEPOINT not constant!", MI);
1473
3.80k
    break;
1474
7.54M
1475
7.54M
    auto VerifyStackMapConstant = [&](unsigned Offset) {
1476
0
      if (!MI->getOperand(Offset).isImm() ||
1477
0
          MI->getOperand(Offset).getImm() != StackMaps::ConstantOp ||
1478
0
          !MI->getOperand(Offset + 1).isImm())
1479
0
        report("stack map constant to STATEPOINT not well formed!", MI);
1480
0
    };
1481
0
    const unsigned VarStart = StatepointOpers(MI).getVarIdx();
1482
0
    VerifyStackMapConstant(VarStart + StatepointOpers::CCOffset);
1483
0
    VerifyStackMapConstant(VarStart + StatepointOpers::FlagsOffset);
1484
0
    VerifyStackMapConstant(VarStart + StatepointOpers::NumDeoptOperandsOffset);
1485
0
1486
0
    // TODO: verify we have properly encoded deopt arguments
1487
0
    break;
1488
33.4M
  }
1489
33.4M
}
1490
1491
void
1492
134M
MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
1493
134M
  const MachineInstr *MI = MO->getParent();
1494
134M
  const MCInstrDesc &MCID = MI->getDesc();
1495
134M
  unsigned NumDefs = MCID.getNumDefs();
1496
134M
  if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
1497
21.7k
    NumDefs = (MONum == 0 && 
MO->isReg()1.40k
) ?
NumDefs280
:
021.5k
;
1498
134M
1499
134M
  // The first MCID.NumDefs operands must be explicit register defines
1500
134M
  if (MONum < NumDefs) {
1501
26.7M
    const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
1502
26.7M
    if (!MO->isReg())
1503
0
      report("Explicit definition must be a register", MO, MONum);
1504
26.7M
    else if (!MO->isDef() && 
!MCOI.isOptionalDef()1.11k
)
1505
5
      report("Explicit definition marked as use", MO, MONum);
1506
26.7M
    else if (MO->isImplicit())
1507
0
      report("Explicit definition marked as implicit", MO, MONum);
1508
108M
  } else if (MONum < MCID.getNumOperands()) {
1509
81.4M
    const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
1510
81.4M
    // Don't check if it's the last operand in a variadic instruction. See,
1511
81.4M
    // e.g., LDM_RET in the arm back end.
1512
81.4M
    if (MO->isReg() &&
1513
81.4M
        
!(37.7M
MI->isVariadic()37.7M
&&
MONum == MCID.getNumOperands()-11.18M
)) {
1514
36.6M
      if (MO->isDef() && 
!MCOI.isOptionalDef()10.5k
)
1515
0
        report("Explicit operand marked as def", MO, MONum);
1516
36.6M
      if (MO->isImplicit())
1517
0
        report("Explicit operand marked as implicit", MO, MONum);
1518
36.6M
    }
1519
81.4M
1520
81.4M
    int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
1521
81.4M
    if (TiedTo != -1) {
1522
829k
      if (!MO->isReg())
1523
0
        report("Tied use must be a register", MO, MONum);
1524
829k
      else if (!MO->isTied())
1525
0
        report("Operand should be tied", MO, MONum);
1526
829k
      else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
1527
0
        report("Tied def doesn't match MCInstrDesc", MO, MONum);
1528
829k
      else if (TargetRegisterInfo::isPhysicalRegister(MO->getReg())) {
1529
500k
        const MachineOperand &MOTied = MI->getOperand(TiedTo);
1530
500k
        if (!MOTied.isReg())
1531
0
          report("Tied counterpart must be a register", &MOTied, TiedTo);
1532
500k
        else if (TargetRegisterInfo::isPhysicalRegister(MOTied.getReg()) &&
1533
500k
                 
MO->getReg() != MOTied.getReg()500k
)
1534
1
          report("Tied physical registers must match.", &MOTied, TiedTo);
1535
500k
      }
1536
80.5M
    } else if (MO->isReg() && 
MO->isTied()36.9M
)
1537
0
      report("Explicit operand should not be tied", MO, MONum);
1538
81.4M
  } else {
1539
26.7M
    // ARM adds %reg0 operands to indicate predicates. We'll allow that.
1540
26.7M
    if (MO->isReg() && 
!MO->isImplicit()22.3M
&&
!MI->isVariadic()2.98M
&&
MO->getReg()0
)
1541
0
      report("Extra explicit operand on non-variadic instruction", MO, MONum);
1542
26.7M
  }
1543
134M
1544
134M
  switch (MO->getType()) {
1545
134M
  case MachineOperand::MO_Register: {
1546
86.8M
    const unsigned Reg = MO->getReg();
1547
86.8M
    if (!Reg)
1548
2.34M
      return;
1549
84.4M
    if (MRI->tracksLiveness() && 
!MI->isDebugValue()81.8M
)
1550
81.8M
      checkLiveness(MO, MONum);
1551
84.4M
1552
84.4M
    // Verify the consistency of tied operands.
1553
84.4M
    if (MO->isTied()) {
1554
1.69M
      unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
1555
1.69M
      const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
1556
1.69M
      if (!OtherMO.isReg())
1557
0
        report("Must be tied to a register", MO, MONum);
1558
1.69M
      if (!OtherMO.isTied())
1559
0
        report("Missing tie flags on tied operand", MO, MONum);
1560
1.69M
      if (MI->findTiedOperandIdx(OtherIdx) != MONum)
1561
0
        report("Inconsistent tie links", MO, MONum);
1562
1.69M
      if (MONum < MCID.getNumDefs()) {
1563
838k
        if (OtherIdx < MCID.getNumOperands()) {
1564
829k
          if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
1565
0
            report("Explicit def tied to explicit use without tie constraint",
1566
0
                   MO, MONum);
1567
829k
        } else {
1568
8.76k
          if (!OtherMO.isImplicit())
1569
0
            report("Explicit def should be tied to implicit use", MO, MONum);
1570
8.76k
        }
1571
838k
      }
1572
1.69M
    }
1573
84.4M
1574
84.4M
    // Verify two-address constraints after leaving SSA form.
1575
84.4M
    unsigned DefIdx;
1576
84.4M
    if (!MRI->isSSA() && 
MO->isUse()49.3M
&&
1577
84.4M
        
MI->isRegTiedToDefOperand(MONum, &DefIdx)31.0M
&&
1578
84.4M
        
Reg != MI->getOperand(DefIdx).getReg()576k
)
1579
0
      report("Two-address instruction operands must be identical", MO, MONum);
1580
84.4M
1581
84.4M
    // Check register classes.
1582
84.4M
    unsigned SubIdx = MO->getSubReg();
1583
84.4M
1584
84.4M
    if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1585
49.2M
      if (SubIdx) {
1586
0
        report("Illegal subregister index for physical register", MO, MONum);
1587
0
        return;
1588
0
      }
1589
49.2M
      if (MONum < MCID.getNumOperands()) {
1590
29.1M
        if (const TargetRegisterClass *DRC =
1591
23.7M
              TII->getRegClass(MCID, MONum, TRI, *MF)) {
1592
23.7M
          if (!DRC->contains(Reg)) {
1593
0
            report("Illegal physical register for instruction", MO, MONum);
1594
0
            errs() << printReg(Reg, TRI) << " is not a "
1595
0
                   << TRI->getRegClassName(DRC) << " register.\n";
1596
0
          }
1597
23.7M
        }
1598
29.1M
      }
1599
49.2M
      if (MO->isRenamable()) {
1600
16.1M
        if (MRI->isReserved(Reg)) {
1601
0
          report("isRenamable set on reserved register", MO, MONum);
1602
0
          return;
1603
0
        }
1604
49.2M
      }
1605
49.2M
      if (MI->isDebugValue() && 
MO->isUse()1.27k
&&
!MO->isDebug()1.27k
) {
1606
0
        report("Use-reg is not IsDebug in a DBG_VALUE", MO, MONum);
1607
0
        return;
1608
0
      }
1609
35.2M
    } else {
1610
35.2M
      // Virtual register.
1611
35.2M
      const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
1612
35.2M
      if (!RC) {
1613
189k
        // This is a generic virtual register.
1614
189k
1615
189k
        // If we're post-Select, we can't have gvregs anymore.
1616
189k
        if (isFunctionSelected) {
1617
1
          report("Generic virtual register invalid in a Selected function",
1618
1
                 MO, MONum);
1619
1
          return;
1620
1
        }
1621
189k
1622
189k
        // The gvreg must have a type and it must not have a SubIdx.
1623
189k
        LLT Ty = MRI->getType(Reg);
1624
189k
        if (!Ty.isValid()) {
1625
0
          report("Generic virtual register must have a valid type", MO,
1626
0
                 MONum);
1627
0
          return;
1628
0
        }
1629
189k
1630
189k
        const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
1631
189k
1632
189k
        // If we're post-RegBankSelect, the gvreg must have a bank.
1633
189k
        if (!RegBank && 
isFunctionRegBankSelected114k
) {
1634
1
          report("Generic virtual register must have a bank in a "
1635
1
                 "RegBankSelected function",
1636
1
                 MO, MONum);
1637
1
          return;
1638
1
        }
1639
189k
1640
189k
        // Make sure the register fits into its register bank if any.
1641
189k
        if (RegBank && 
Ty.isValid()74.8k
&&
1642
189k
            
RegBank->getSize() < Ty.getSizeInBits()74.8k
) {
1643
0
          report("Register bank is too small for virtual register", MO,
1644
0
                 MONum);
1645
0
          errs() << "Register bank " << RegBank->getName() << " too small("
1646
0
                 << RegBank->getSize() << ") to fit " << Ty.getSizeInBits()
1647
0
                 << "-bits\n";
1648
0
          return;
1649
0
        }
1650
189k
        if (SubIdx)  {
1651
1
          report("Generic virtual register does not allow subregister index", MO,
1652
1
                 MONum);
1653
1
          return;
1654
1
        }
1655
189k
1656
189k
        // If this is a target specific instruction and this operand
1657
189k
        // has register class constraint, the virtual register must
1658
189k
        // comply to it.
1659
189k
        if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
1660
189k
            
MONum < MCID.getNumOperands()63.3k
&&
1661
189k
            
TII->getRegClass(MCID, MONum, TRI, *MF)61.1k
) {
1662
0
          report("Virtual register does not match instruction constraint", MO,
1663
0
                 MONum);
1664
0
          errs() << "Expect register class "
1665
0
                 << TRI->getRegClassName(
1666
0
                        TII->getRegClass(MCID, MONum, TRI, *MF))
1667
0
                 << " but got nothing\n";
1668
0
          return;
1669
0
        }
1670
189k
1671
189k
        break;
1672
189k
      }
1673
35.0M
      if (SubIdx) {
1674
4.18M
        const TargetRegisterClass *SRC =
1675
4.18M
          TRI->getSubClassWithSubReg(RC, SubIdx);
1676
4.18M
        if (!SRC) {
1677
0
          report("Invalid subregister index for virtual register", MO, MONum);
1678
0
          errs() << "Register class " << TRI->getRegClassName(RC)
1679
0
              << " does not support subreg index " << SubIdx << "\n";
1680
0
          return;
1681
0
        }
1682
4.18M
        if (RC != SRC) {
1683
0
          report("Invalid register class for subregister index", MO, MONum);
1684
0
          errs() << "Register class " << TRI->getRegClassName(RC)
1685
0
              << " does not fully support subreg index " << SubIdx << "\n";
1686
0
          return;
1687
0
        }
1688
35.0M
      }
1689
35.0M
      if (MONum < MCID.getNumOperands()) {
1690
32.8M
        if (const TargetRegisterClass *DRC =
1691
20.1M
              TII->getRegClass(MCID, MONum, TRI, *MF)) {
1692
20.1M
          if (SubIdx) {
1693
1.52M
            const TargetRegisterClass *SuperRC =
1694
1.52M
                TRI->getLargestLegalSuperClass(RC, *MF);
1695
1.52M
            if (!SuperRC) {
1696
0
              report("No largest legal super class exists.", MO, MONum);
1697
0
              return;
1698
0
            }
1699
1.52M
            DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
1700
1.52M
            if (!DRC) {
1701
0
              report("No matching super-reg register class.", MO, MONum);
1702
0
              return;
1703
0
            }
1704
20.1M
          }
1705
20.1M
          if (!RC->hasSuperClassEq(DRC)) {
1706
0
            report("Illegal virtual register for instruction", MO, MONum);
1707
0
            errs() << "Expected a " << TRI->getRegClassName(DRC)
1708
0
                << " register, but got a " << TRI->getRegClassName(RC)
1709
0
                << " register\n";
1710
0
          }
1711
20.1M
        }
1712
32.8M
      }
1713
35.0M
    }
1714
84.4M
    
break84.2M
;
1715
84.4M
  }
1716
84.4M
1717
84.4M
  case MachineOperand::MO_RegisterMask:
1718
301k
    regMasks.push_back(MO->getRegMask());
1719
301k
    break;
1720
84.4M
1721
84.4M
  case MachineOperand::MO_MachineBasicBlock:
1722
733k
    if (MI->isPHI() && 
!MO->getMBB()->isSuccessor(MI->getParent())224k
)
1723
0
      report("PHI operand is not in the CFG", MO, MONum);
1724
733k
    break;
1725
84.4M
1726
84.4M
  case MachineOperand::MO_FrameIndex:
1727
581k
    if (LiveStks && 
LiveStks->hasInterval(MO->getIndex())63.3k
&&
1728
581k
        
LiveInts10.5k
&&
!LiveInts->isNotInMIMap(*MI)6.30k
) {
1729
6.30k
      int FI = MO->getIndex();
1730
6.30k
      LiveInterval &LI = LiveStks->getInterval(FI);
1731
6.30k
      SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
1732
6.30k
1733
6.30k
      bool stores = MI->mayStore();
1734
6.30k
      bool loads = MI->mayLoad();
1735
6.30k
      // For a memory-to-memory move, we need to check if the frame
1736
6.30k
      // index is used for storing or loading, by inspecting the
1737
6.30k
      // memory operands.
1738
6.30k
      if (stores && 
loads3.03k
) {
1739
381
        for (auto *MMO : MI->memoperands()) {
1740
381
          const PseudoSourceValue *PSV = MMO->getPseudoValue();
1741
381
          if (PSV == nullptr) 
continue18
;
1742
363
          const FixedStackPseudoSourceValue *Value =
1743
363
            dyn_cast<FixedStackPseudoSourceValue>(PSV);
1744
363
          if (Value == nullptr) 
continue0
;
1745
363
          if (Value->getFrameIndex() != FI) 
continue301
;
1746
62
1747
62
          if (MMO->isStore())
1748
12
            loads = false;
1749
50
          else
1750
50
            stores = false;
1751
62
          break;
1752
62
        }
1753
62
        if (loads == stores)
1754
0
          report("Missing fixed stack memoperand.", MI);
1755
62
      }
1756
6.30k
      if (loads && 
!LI.liveAt(Idx.getRegSlot(true))3.31k
) {
1757
0
        report("Instruction loads from dead spill slot", MO, MONum);
1758
0
        errs() << "Live stack: " << LI << '\n';
1759
0
      }
1760
6.30k
      if (stores && 
!LI.liveAt(Idx.getRegSlot())2.98k
) {
1761
0
        report("Instruction stores to dead spill slot", MO, MONum);
1762
0
        errs() << "Live stack: " << LI << '\n';
1763
0
      }
1764
6.30k
    }
1765
581k
    break;
1766
84.4M
1767
84.4M
  default:
1768
46.4M
    break;
1769
134M
  }
1770
134M
}
1771
1772
void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
1773
    unsigned MONum, SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
1774
6.90M
    LaneBitmask LaneMask) {
1775
6.90M
  LiveQueryResult LRQ = LR.Query(UseIdx);
1776
6.90M
  // Check if we have a segment at the use, note however that we only need one
1777
6.90M
  // live subregister range, the others may be dead.
1778
6.90M
  if (!LRQ.valueIn() && 
LaneMask.none()1.04k
) {
1779
0
    report("No live segment at use", MO, MONum);
1780
0
    report_context_liverange(LR);
1781
0
    report_context_vreg_regunit(VRegOrUnit);
1782
0
    report_context(UseIdx);
1783
0
  }
1784
6.90M
  if (MO->isKill() && 
!LRQ.isKill()42
) {
1785
0
    report("Live range continues after kill flag", MO, MONum);
1786
0
    report_context_liverange(LR);
1787
0
    report_context_vreg_regunit(VRegOrUnit);
1788
0
    if (LaneMask.any())
1789
0
      report_context_lanemask(LaneMask);
1790
0
    report_context(UseIdx);
1791
0
  }
1792
6.90M
}
1793
1794
void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
1795
    unsigned MONum, SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
1796
4.43M
    bool SubRangeCheck, LaneBitmask LaneMask) {
1797
4.43M
  if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
1798
4.43M
    assert(VNI && "NULL valno is not allowed");
1799
4.43M
    if (VNI->def != DefIdx) {
1800
0
      report("Inconsistent valno->def", MO, MONum);
1801
0
      report_context_liverange(LR);
1802
0
      report_context_vreg_regunit(VRegOrUnit);
1803
0
      if (LaneMask.any())
1804
0
        report_context_lanemask(LaneMask);
1805
0
      report_context(*VNI);
1806
0
      report_context(DefIdx);
1807
0
    }
1808
4.43M
  } else {
1809
0
    report("No live segment at def", MO, MONum);
1810
0
    report_context_liverange(LR);
1811
0
    report_context_vreg_regunit(VRegOrUnit);
1812
0
    if (LaneMask.any())
1813
0
      report_context_lanemask(LaneMask);
1814
0
    report_context(DefIdx);
1815
0
  }
1816
4.43M
  // Check that, if the dead def flag is present, LiveInts agree.
1817
4.43M
  if (MO->isDead()) {
1818
61.6k
    LiveQueryResult LRQ = LR.Query(DefIdx);
1819
61.6k
    if (!LRQ.isDeadDef()) {
1820
13
      assert(TargetRegisterInfo::isVirtualRegister(VRegOrUnit) &&
1821
13
             "Expecting a virtual register.");
1822
13
      // A dead subreg def only tells us that the specific subreg is dead. There
1823
13
      // could be other non-dead defs of other subregs, or we could have other
1824
13
      // parts of the register being live through the instruction. So unless we
1825
13
      // are checking liveness for a subrange it is ok for the live range to
1826
13
      // continue, given that we have a dead def of a subregister.
1827
13
      if (SubRangeCheck || 
MO->getSubReg() == 010
) {
1828
5
        report("Live range continues after dead def flag", MO, MONum);
1829
5
        report_context_liverange(LR);
1830
5
        report_context_vreg_regunit(VRegOrUnit);
1831
5
        if (LaneMask.any())
1832
3
          report_context_lanemask(LaneMask);
1833
5
      }
1834
13
    }
1835
61.6k
  }
1836
4.43M
}
1837
1838
81.8M
void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
1839
81.8M
  const MachineInstr *MI = MO->getParent();
1840
81.8M
  const unsigned Reg = MO->getReg();
1841
81.8M
1842
81.8M
  // Both use and def operands can read a register.
1843
81.8M
  if (MO->readsReg()) {
1844
51.6M
    if (MO->isKill())
1845
12.4M
      addRegWithSubRegs(regsKilled, Reg);
1846
51.6M
1847
51.6M
    // Check that LiveVars knows this kill.
1848
51.6M
    if (LiveVars && 
TargetRegisterInfo::isVirtualRegister(Reg)617
&&
1849
51.6M
        
MO->isKill()611
) {
1850
516
      LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1851
516
      if (!is_contained(VI.Kills, MI))
1852
0
        report("Kill missing from LiveVariables", MO, MONum);
1853
516
    }
1854
51.6M
1855
51.6M
    // Check LiveInts liveness and kill.
1856
51.6M
    if (LiveInts && 
!LiveInts->isNotInMIMap(*MI)6.81M
) {
1857
6.78M
      SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
1858
6.78M
      // Check the cached regunit intervals.
1859
6.78M
      if (TargetRegisterInfo::isPhysicalRegister(Reg) && 
!isReserved(Reg)2.63M
) {
1860
2.03M
        for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); 
++Units1.11M
) {
1861
1.11M
          if (MRI->isReservedRegUnit(*Units))
1862
28
            continue;
1863
1.11M
          if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
1864
956k
            checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
1865
1.11M
        }
1866
914k
      }
1867
6.78M
1868
6.78M
      if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1869
4.14M
        if (LiveInts->hasInterval(Reg)) {
1870
4.14M
          // This is a virtual register interval.
1871
4.14M
          const LiveInterval &LI = LiveInts->getInterval(Reg);
1872
4.14M
          checkLivenessAtUse(MO, MONum, UseIdx, LI, Reg);
1873
4.14M
1874
4.14M
          if (LI.hasSubRanges() && 
!MO->isDef()1.62M
) {
1875
1.04M
            unsigned SubRegIdx = MO->getSubReg();
1876
1.04M
            LaneBitmask MOMask = SubRegIdx != 0
1877
1.04M
                               ? 
TRI->getSubRegIndexLaneMask(SubRegIdx)674k
1878
1.04M
                               : 
MRI->getMaxLaneMaskForVReg(Reg)374k
;
1879
1.04M
            LaneBitmask LiveInMask;
1880
3.96M
            for (const LiveInterval::SubRange &SR : LI.subranges()) {
1881
3.96M
              if ((MOMask & SR.LaneMask).none())
1882
2.15M
                continue;
1883
1.80M
              checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
1884
1.80M
              LiveQueryResult LRQ = SR.Query(UseIdx);
1885
1.80M
              if (LRQ.valueIn())
1886
1.80M
                LiveInMask |= SR.LaneMask;
1887
1.80M
            }
1888
1.04M
            // At least parts of the register has to be live at the use.
1889
1.04M
            if ((LiveInMask & MOMask).none()) {
1890
0
              report("No live subrange at use", MO, MONum);
1891
0
              report_context(LI);
1892
0
              report_context(UseIdx);
1893
0
            }
1894
1.04M
          }
1895
4.14M
        } else {
1896
0
          report("Virtual register has no live interval", MO, MONum);
1897
0
        }
1898
4.14M
      }
1899
6.78M
    }
1900
51.6M
1901
51.6M
    // Use of a dead register.
1902
51.6M
    if (!regsLive.count(Reg)) {
1903
14.6M
      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1904
13.9M
        // Reserved registers may be used even when 'dead'.
1905
13.9M
        bool Bad = !isReserved(Reg);
1906
13.9M
        // We are fine if just any subregister has a defined value.
1907
13.9M
        if (Bad) {
1908
1.19M
          for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid();
1909
1.19M
               
++SubRegs72.5k
) {
1910
1.19M
            if (regsLive.count(*SubRegs)) {
1911
1.12M
              Bad = false;
1912
1.12M
              break;
1913
1.12M
            }
1914
1.19M
          }
1915
1.12M
        }
1916
13.9M
        // If there is an additional implicit-use of a super register we stop
1917
13.9M
        // here. By definition we are fine if the super register is not
1918
13.9M
        // (completely) dead, if the complete super register is dead we will
1919
13.9M
        // get a report for its operand.
1920
13.9M
        if (Bad) {
1921
4.46k
          for (const MachineOperand &MOP : MI->uses()) {
1922
4.46k
            if (!MOP.isReg() || 
!MOP.isImplicit()2.51k
)
1923
3.30k
              continue;
1924
1.15k
1925
1.15k
            if (!TargetRegisterInfo::isPhysicalRegister(MOP.getReg()))
1926
1
              continue;
1927
1.15k
1928
9.73k
            
for (MCSubRegIterator SubRegs(MOP.getReg(), TRI); 1.15k
SubRegs.isValid();
1929
9.15k
                 
++SubRegs8.58k
) {
1930
9.15k
              if (*SubRegs == Reg) {
1931
570
                Bad = false;
1932
570
                break;
1933
570
              }
1934
9.15k
            }
1935
1.15k
          }
1936
573
        }
1937
13.9M
        if (Bad)
1938
3
          report("Using an undefined physical register", MO, MONum);
1939
13.9M
      } else 
if (681k
MRI->def_empty(Reg)681k
) {
1940
0
        report("Reading virtual register without a def", MO, MONum);
1941
681k
      } else {
1942
681k
        BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1943
681k
        // We don't know which virtual registers are live in, so only complain
1944
681k
        // if vreg was killed in this MBB. Otherwise keep track of vregs that
1945
681k
        // must be live in. PHI instructions are handled separately.
1946
681k
        if (MInfo.regsKilled.count(Reg))
1947
0
          report("Using a killed virtual register", MO, MONum);
1948
681k
        else if (!MI->isPHI())
1949
457k
          MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
1950
681k
      }
1951
14.6M
    }
1952
51.6M
  }
1953
81.8M
1954
81.8M
  if (MO->isDef()) {
1955
30.6M
    // Register defined.
1956
30.6M
    // TODO: verify that earlyclobber ops are not used.
1957
30.6M
    if (MO->isDead())
1958
2.97M
      addRegWithSubRegs(regsDead, Reg);
1959
27.6M
    else
1960
27.6M
      addRegWithSubRegs(regsDefined, Reg);
1961
30.6M
1962
30.6M
    // Verify SSA form.
1963
30.6M
    if (MRI->isSSA() && 
TargetRegisterInfo::isVirtualRegister(Reg)13.6M
&&
1964
30.6M
        
std::next(MRI->def_begin(Reg)) != MRI->def_end()11.4M
)
1965
0
      report("Multiple virtual register defs in SSA form", MO, MONum);
1966
30.6M
1967
30.6M
    // Check LiveInts for a live segment, but only for virtual registers.
1968
30.6M
    if (LiveInts && 
!LiveInts->isNotInMIMap(*MI)3.97M
) {
1969
3.95M
      SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
1970
3.95M
      DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
1971
3.95M
1972
3.95M
      if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1973
3.07M
        if (LiveInts->hasInterval(Reg)) {
1974
3.07M
          const LiveInterval &LI = LiveInts->getInterval(Reg);
1975
3.07M
          checkLivenessAtDef(MO, MONum, DefIdx, LI, Reg);
1976
3.07M
1977
3.07M
          if (LI.hasSubRanges()) {
1978
1.02M
            unsigned SubRegIdx = MO->getSubReg();
1979
1.02M
            LaneBitmask MOMask = SubRegIdx != 0
1980
1.02M
              ? 
TRI->getSubRegIndexLaneMask(SubRegIdx)871k
1981
1.02M
              : 
MRI->getMaxLaneMaskForVReg(Reg)149k
;
1982
3.66M
            for (const LiveInterval::SubRange &SR : LI.subranges()) {
1983
3.66M
              if ((SR.LaneMask & MOMask).none())
1984
2.30M
                continue;
1985
1.35M
              checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, true, SR.LaneMask);
1986
1.35M
            }
1987
1.02M
          }
1988
3.07M
        } else {
1989
0
          report("Virtual register has no Live interval", MO, MONum);
1990
0
        }
1991
3.07M
      }
1992
3.95M
    }
1993
30.6M
  }
1994
81.8M
}
1995
1996
33.4M
void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {}
1997
1998
// This function gets called after visiting all instructions in a bundle. The
1999
// argument points to the bundle header.
2000
// Normal stand-alone instructions are also considered 'bundles', and this
2001
// function is called for all of them.
2002
33.3M
void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
2003
33.3M
  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
2004
33.3M
  set_union(MInfo.regsKilled, regsKilled);
2005
33.3M
  set_subtract(regsLive, regsKilled); regsKilled.clear();
2006
33.3M
  // Kill any masked registers.
2007
33.6M
  while (!regMasks.empty()) {
2008
301k
    const uint32_t *Mask = regMasks.pop_back_val();
2009
7.50M
    for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; 
++I7.20M
)
2010
7.20M
      if (TargetRegisterInfo::isPhysicalRegister(*I) &&
2011
7.20M
          
MachineOperand::clobbersPhysReg(Mask, *I)6.27M
)
2012
1.30M
        regsDead.push_back(*I);
2013
301k
  }
2014
33.3M
  set_subtract(regsLive, regsDead);   regsDead.clear();
2015
33.3M
  set_union(regsLive, regsDefined);   regsDefined.clear();
2016
33.3M
}
2017
2018
void
2019
2.88M
MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
2020
2.88M
  MBBInfoMap[MBB].regsLiveOut = regsLive;
2021
2.88M
  regsLive.clear();
2022
2.88M
2023
2.88M
  if (Indexes) {
2024
423k
    SlotIndex stop = Indexes->getMBBEndIdx(MBB);
2025
423k
    if (!(stop > lastIndex)) {
2026
0
      report("Block ends before last instruction index", MBB);
2027
0
      errs() << "Block ends at " << stop
2028
0
          << " last instruction was at " << lastIndex << '\n';
2029
0
    }
2030
423k
    lastIndex = stop;
2031
423k
  }
2032
2.88M
}
2033
2034
// Calculate the largest possible vregsPassed sets. These are the registers that
2035
// can pass through an MBB live, but may not be live every time. It is assumed
2036
// that all vregsPassed sets are empty before the call.
2037
2.28M
void MachineVerifier::calcRegsPassed() {
2038
2.28M
  // First push live-out regs to successors' vregsPassed. Remember the MBBs that
2039
2.28M
  // have any vregsPassed.
2040
2.28M
  SmallPtrSet<const MachineBasicBlock*, 8> todo;
2041
2.88M
  for (const auto &MBB : *MF) {
2042
2.88M
    BBInfo &MInfo = MBBInfoMap[&MBB];
2043
2.88M
    if (!MInfo.reachable)
2044
2.70k
      continue;
2045
2.88M
    for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
2046
3.73M
           SuE = MBB.succ_end(); SuI != SuE; 
++SuI850k
) {
2047
850k
      BBInfo &SInfo = MBBInfoMap[*SuI];
2048
850k
      if (SInfo.addPassed(MInfo.regsLiveOut))
2049
289k
        todo.insert(*SuI);
2050
850k
    }
2051
2.88M
  }
2052
2.28M
2053
2.28M
  // Iteratively push vregsPassed to successors. This will converge to the same
2054
2.28M
  // final state regardless of DenseSet iteration order.
2055
2.61M
  while (!todo.empty()) {
2056
326k
    const MachineBasicBlock *MBB = *todo.begin();
2057
326k
    todo.erase(MBB);
2058
326k
    BBInfo &MInfo = MBBInfoMap[MBB];
2059
326k
    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
2060
651k
           SuE = MBB->succ_end(); SuI != SuE; 
++SuI325k
) {
2061
325k
      if (*SuI == MBB)
2062
29.9k
        continue;
2063
295k
      BBInfo &SInfo = MBBInfoMap[*SuI];
2064
295k
      if (SInfo.addPassed(MInfo.vregsPassed))
2065
189k
        todo.insert(*SuI);
2066
295k
    }
2067
326k
  }
2068
2.28M
}
2069
2070
// Calculate the set of virtual registers that must be passed through each basic
2071
// block in order to satisfy the requirements of successor blocks. This is very
2072
// similar to calcRegsPassed, only backwards.
2073
2.28M
void MachineVerifier::calcRegsRequired() {
2074
2.28M
  // First push live-in regs to predecessors' vregsRequired.
2075
2.28M
  SmallPtrSet<const MachineBasicBlock*, 8> todo;
2076
2.88M
  for (const auto &MBB : *MF) {
2077
2.88M
    BBInfo &MInfo = MBBInfoMap[&MBB];
2078
2.88M
    for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
2079
3.73M
           PrE = MBB.pred_end(); PrI != PrE; 
++PrI850k
) {
2080
850k
      BBInfo &PInfo = MBBInfoMap[*PrI];
2081
850k
      if (PInfo.addRequired(MInfo.vregsLiveIn))
2082
112k
        todo.insert(*PrI);
2083
850k
    }
2084
2.88M
  }
2085
2.28M
2086
2.28M
  // Iteratively push vregsRequired to predecessors. This will converge to the
2087
2.28M
  // same final state regardless of DenseSet iteration order.
2088
2.43M
  while (!todo.empty()) {
2089
140k
    const MachineBasicBlock *MBB = *todo.begin();
2090
140k
    todo.erase(MBB);
2091
140k
    BBInfo &MInfo = MBBInfoMap[MBB];
2092
140k
    for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
2093
347k
           PrE = MBB->pred_end(); PrI != PrE; 
++PrI206k
) {
2094
206k
      if (*PrI == MBB)
2095
25.0k
        continue;
2096
181k
      BBInfo &SInfo = MBBInfoMap[*PrI];
2097
181k
      if (SInfo.addRequired(MInfo.vregsRequired))
2098
67.2k
        todo.insert(*PrI);
2099
181k
    }
2100
140k
  }
2101
2.28M
}
2102
2103
// Check PHI instructions at the beginning of MBB. It is assumed that
2104
// calcRegsPassed has been run so BBInfo::isLiveOut is valid.
2105
2.88M
void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) {
2106
2.88M
  BBInfo &MInfo = MBBInfoMap[&MBB];
2107
2.88M
2108
2.88M
  SmallPtrSet<const MachineBasicBlock*, 8> seen;
2109
2.98M
  for (const MachineInstr &Phi : MBB) {
2110
2.98M
    if (!Phi.isPHI())
2111
2.86M
      break;
2112
119k
    seen.clear();
2113
119k
2114
119k
    const MachineOperand &MODef = Phi.getOperand(0);
2115
119k
    if (!MODef.isReg() || !MODef.isDef()) {
2116
0
      report("Expected first PHI operand to be a register def", &MODef, 0);
2117
0
      continue;
2118
0
    }
2119
119k
    if (MODef.isTied() || MODef.isImplicit() || MODef.isInternalRead() ||
2120
119k
        MODef.isEarlyClobber() || MODef.isDebug())
2121
0
      report("Unexpected flag on PHI operand", &MODef, 0);
2122
119k
    unsigned DefReg = MODef.getReg();
2123
119k
    if (!TargetRegisterInfo::isVirtualRegister(DefReg))
2124
0
      report("Expected first PHI operand to be a virtual register", &MODef, 0);
2125
119k
2126
343k
    for (unsigned I = 1, E = Phi.getNumOperands(); I != E; 
I += 2224k
) {
2127
224k
      const MachineOperand &MO0 = Phi.getOperand(I);
2128
224k
      if (!MO0.isReg()) {
2129
0
        report("Expected PHI operand to be a register", &MO0, I);
2130
0
        continue;
2131
0
      }
2132
224k
      if (MO0.isImplicit() || MO0.isInternalRead() || MO0.isEarlyClobber() ||
2133
224k
          MO0.isDebug() || MO0.isTied())
2134
0
        report("Unexpected flag on PHI operand", &MO0, I);
2135
224k
2136
224k
      const MachineOperand &MO1 = Phi.getOperand(I + 1);
2137
224k
      if (!MO1.isMBB()) {
2138
0
        report("Expected PHI operand to be a basic block", &MO1, I + 1);
2139
0
        continue;
2140
0
      }
2141
224k
2142
224k
      const MachineBasicBlock &Pre = *MO1.getMBB();
2143
224k
      if (!Pre.isSuccessor(&MBB)) {
2144
0
        report("PHI input is not a predecessor block", &MO1, I + 1);
2145
0
        continue;
2146
0
      }
2147
224k
2148
224k
      if (MInfo.reachable) {
2149
224k
        seen.insert(&Pre);
2150
224k
        BBInfo &PrInfo = MBBInfoMap[&Pre];
2151
224k
        if (!MO0.isUndef() && 
PrInfo.reachable224k
&&
2152
224k
            
!PrInfo.isLiveOut(MO0.getReg())224k
)
2153
2
          report("PHI operand is not live-out from predecessor", &MO0, I);
2154
224k
      }
2155
224k
    }
2156
119k
2157
119k
    // Did we see all predecessors?
2158
119k
    if (MInfo.reachable) {
2159
224k
      for (MachineBasicBlock *Pred : MBB.predecessors()) {
2160
224k
        if (!seen.count(Pred)) {
2161
0
          report("Missing PHI operand", &Phi);
2162
0
          errs() << printMBBReference(*Pred)
2163
0
                 << " is a predecessor according to the CFG.\n";
2164
0
        }
2165
224k
      }
2166
119k
    }
2167
119k
  }
2168
2.88M
}
2169
2170
2.28M
void MachineVerifier::visitMachineFunctionAfter() {
2171
2.28M
  calcRegsPassed();
2172
2.28M
2173
2.28M
  for (const MachineBasicBlock &MBB : *MF)
2174
2.88M
    checkPHIOps(MBB);
2175
2.28M
2176
2.28M
  // Now check liveness info if available
2177
2.28M
  calcRegsRequired();
2178
2.28M
2179
2.28M
  // Check for killed virtual registers that should be live out.
2180
2.88M
  for (const auto &MBB : *MF) {
2181
2.88M
    BBInfo &MInfo = MBBInfoMap[&MBB];
2182
2.88M
    for (RegSet::iterator
2183
3.37M
         I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
2184
2.88M
         
++I488k
)
2185
488k
      if (MInfo.regsKilled.count(*I)) {
2186
0
        report("Virtual register killed in block, but needed live out.", &MBB);
2187
0
        errs() << "Virtual register " << printReg(*I)
2188
0
               << " is used after the block.\n";
2189
0
      }
2190
2.88M
  }
2191
2.28M
2192
2.28M
  if (!MF->empty()) {
2193
2.28M
    BBInfo &MInfo = MBBInfoMap[&MF->front()];
2194
2.28M
    for (RegSet::iterator
2195
2.28M
         I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
2196
2.28M
         
++I0
) {
2197
0
      report("Virtual register defs don't dominate all uses.", MF);
2198
0
      report_context_vreg(*I);
2199
0
    }
2200
2.28M
  }
2201
2.28M
2202
2.28M
  if (LiveVars)
2203
120
    verifyLiveVariables();
2204
2.28M
  if (LiveInts)
2205
289k
    verifyLiveIntervals();
2206
2.28M
2207
2.28M
  for (auto CSInfo : MF->getCallSitesInfo())
2208
1
    if (!CSInfo.first->isCall())
2209
0
      report("Call site info referencing instruction that is not call", MF);
2210
2.28M
}
2211
2212
120
void MachineVerifier::verifyLiveVariables() {
2213
120
  assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
2214
684
  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; 
++i564
) {
2215
564
    unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
2216
564
    LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
2217
794
    for (const auto &MBB : *MF) {
2218
794
      BBInfo &MInfo = MBBInfoMap[&MBB];
2219
794
2220
794
      // Our vregsRequired should be identical to LiveVariables' AliveBlocks
2221
794
      if (MInfo.vregsRequired.count(Reg)) {
2222
1
        if (!VI.AliveBlocks.test(MBB.getNumber())) {
2223
0
          report("LiveVariables: Block missing from AliveBlocks", &MBB);
2224
0
          errs() << "Virtual register " << printReg(Reg)
2225
0
                 << " must be live through the block.\n";
2226
0
        }
2227
793
      } else {
2228
793
        if (VI.AliveBlocks.test(MBB.getNumber())) {
2229
0
          report("LiveVariables: Block should not be in AliveBlocks", &MBB);
2230
0
          errs() << "Virtual register " << printReg(Reg)
2231
0
                 << " is not needed live through the block.\n";
2232
0
        }
2233
793
      }
2234
794
    }
2235
564
  }
2236
120
}
2237
2238
289k
void MachineVerifier::verifyLiveIntervals() {
2239
289k
  assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
2240
6.93M
  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; 
++i6.64M
) {
2241
6.64M
    unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
2242
6.64M
2243
6.64M
    // Spilling and splitting may leave unused registers around. Skip them.
2244
6.64M
    if (MRI->reg_nodbg_empty(Reg))
2245
4.22M
      continue;
2246
2.41M
2247
2.41M
    if (!LiveInts->hasInterval(Reg)) {
2248
0
      report("Missing live interval for virtual register", MF);
2249
0
      errs() << printReg(Reg, TRI) << " still has defs or uses\n";
2250
0
      continue;
2251
0
    }
2252
2.41M
2253
2.41M
    const LiveInterval &LI = LiveInts->getInterval(Reg);
2254
2.41M
    assert(Reg == LI.reg && "Invalid reg to interval mapping");
2255
2.41M
    verifyLiveInterval(LI);
2256
2.41M
  }
2257
289k
2258
289k
  // Verify all the cached regunit intervals.
2259
136M
  for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; 
++i135M
)
2260
135M
    if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
2261
1.38M
      verifyLiveRange(*LR, i);
2262
289k
}
2263
2264
void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
2265
                                           const VNInfo *VNI, unsigned Reg,
2266
5.64M
                                           LaneBitmask LaneMask) {
2267
5.64M
  if (VNI->isUnused())
2268
1.11k
    return;
2269
5.64M
2270
5.64M
  const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
2271
5.64M
2272
5.64M
  if (!DefVNI) {
2273
0
    report("Value not live at VNInfo def and not marked unused", MF);
2274
0
    report_context(LR, Reg, LaneMask);
2275
0
    report_context(*VNI);
2276
0
    return;
2277
0
  }
2278
5.64M
2279
5.64M
  if (DefVNI != VNI) {
2280
0
    report("Live segment at def has different VNInfo", MF);
2281
0
    report_context(LR, Reg, LaneMask);
2282
0
    report_context(*VNI);
2283
0
    return;
2284
0
  }
2285
5.64M
2286
5.64M
  const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
2287
5.64M
  if (!MBB) {
2288
0
    report("Invalid VNInfo definition index", MF);
2289
0
    report_context(LR, Reg, LaneMask);
2290
0
    report_context(*VNI);
2291
0
    return;
2292
0
  }
2293
5.64M
2294
5.64M
  if (VNI->isPHIDef()) {
2295
765k
    if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
2296
0
      report("PHIDef VNInfo is not defined at MBB start", MBB);
2297
0
      report_context(LR, Reg, LaneMask);
2298
0
      report_context(*VNI);
2299
0
    }
2300
765k
    return;
2301
765k
  }
2302
4.87M
2303
4.87M
  // Non-PHI def.
2304
4.87M
  const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
2305
4.87M
  if (!MI) {
2306
0
    report("No instruction at VNInfo def index", MBB);
2307
0
    report_context(LR, Reg, LaneMask);
2308
0
    report_context(*VNI);
2309
0
    return;
2310
0
  }
2311
4.87M
2312
4.87M
  if (Reg != 0) {
2313
4.75M
    bool hasDef = false;
2314
4.75M
    bool isEarlyClobber = false;
2315
25.3M
    for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); 
++MOI20.6M
) {
2316
20.6M
      if (!MOI->isReg() || 
!MOI->isDef()13.3M
)
2317
14.6M
        continue;
2318
5.96M
      if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2319
5.33M
        if (MOI->getReg() != Reg)
2320
858k
          continue;
2321
635k
      } else {
2322
635k
        if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
2323
635k
            
!TRI->hasRegUnit(MOI->getReg(), Reg)540k
)
2324
315k
          continue;
2325
4.79M
      }
2326
4.79M
      if (LaneMask.any() &&
2327
4.79M
          
(TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none()1.37M
)
2328
1.01k
        continue;
2329
4.79M
      hasDef = true;
2330
4.79M
      if (MOI->isEarlyClobber())
2331
63.3k
        isEarlyClobber = true;
2332
4.79M
    }
2333
4.75M
2334
4.75M
    if (!hasDef) {
2335
0
      report("Defining instruction does not modify register", MI);
2336
0
      report_context(LR, Reg, LaneMask);
2337
0
      report_context(*VNI);
2338
0
    }
2339
4.75M
2340
4.75M
    // Early clobber defs begin at USE slots, but other defs must begin at
2341
4.75M
    // DEF slots.
2342
4.75M
    if (isEarlyClobber) {
2343
63.3k
      if (!VNI->def.isEarlyClobber()) {
2344
0
        report("Early clobber def must be at an early-clobber slot", MBB);
2345
0
        report_context(LR, Reg, LaneMask);
2346
0
        report_context(*VNI);
2347
0
      }
2348
4.68M
    } else if (!VNI->def.isRegister()) {
2349
0
      report("Non-PHI, non-early clobber def must be at a register slot", MBB);
2350
0
      report_context(LR, Reg, LaneMask);
2351
0
      report_context(*VNI);
2352
0
    }
2353
4.75M
  }
2354
4.87M
}
2355
2356
void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
2357
                                             const LiveRange::const_iterator I,
2358
                                             unsigned Reg, LaneBitmask LaneMask)
2359
5.66M
{
2360
5.66M
  const LiveRange::Segment &S = *I;
2361
5.66M
  const VNInfo *VNI = S.valno;
2362
5.66M
  assert(VNI && "Live segment has no valno");
2363
5.66M
2364
5.66M
  if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
2365
0
    report("Foreign valno in live segment", MF);
2366
0
    report_context(LR, Reg, LaneMask);
2367
0
    report_context(S);
2368
0
    report_context(*VNI);
2369
0
  }
2370
5.66M
2371
5.66M
  if (VNI->isUnused()) {
2372
0
    report("Live segment valno is marked unused", MF);
2373
0
    report_context(LR, Reg, LaneMask);
2374
0
    report_context(S);
2375
0
  }
2376
5.66M
2377
5.66M
  const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
2378
5.66M
  if (!MBB) {
2379
0
    report("Bad start of live segment, no basic block", MF);
2380
0
    report_context(LR, Reg, LaneMask);
2381
0
    report_context(S);
2382
0
    return;
2383
0
  }
2384
5.66M
  SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
2385
5.66M
  if (S.start != MBBStartIdx && 
S.start != VNI->def4.87M
) {
2386
0
    report("Live segment must begin at MBB entry or valno def", MBB);
2387
0
    report_context(LR, Reg, LaneMask);
2388
0
    report_context(S);
2389
0
  }
2390
5.66M
2391
5.66M
  const MachineBasicBlock *EndMBB =
2392
5.66M
    LiveInts->getMBBFromIndex(S.end.getPrevSlot());
2393
5.66M
  if (!EndMBB) {
2394
0
    report("Bad end of live segment, no basic block", MF);
2395
0
    report_context(LR, Reg, LaneMask);
2396
0
    report_context(S);
2397
0
    return;
2398
0
  }
2399
5.66M
2400
5.66M
  // No more checks for live-out segments.
2401
5.66M
  if (S.end == LiveInts->getMBBEndIdx(EndMBB))
2402
124k
    return;
2403
5.54M
2404
5.54M
  // RegUnit intervals are allowed dead phis.
2405
5.54M
  if (!TargetRegisterInfo::isVirtualRegister(Reg) && 
VNI->isPHIDef()1.16M
&&
2406
5.54M
      
S.start == VNI->def722k
&&
S.end == VNI->def.getDeadSlot()722k
)
2407
2.54k
    return;
2408
5.54M
2409
5.54M
  // The live segment is ending inside EndMBB
2410
5.54M
  const MachineInstr *MI =
2411
5.54M
    LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
2412
5.54M
  if (!MI) {
2413
0
    report("Live segment doesn't end at a valid instruction", EndMBB);
2414
0
    report_context(LR, Reg, LaneMask);
2415
0
    report_context(S);
2416
0
    return;
2417
0
  }
2418
5.54M
2419
5.54M
  // The block slot must refer to a basic block boundary.
2420
5.54M
  if (S.end.isBlock()) {
2421
0
    report("Live segment ends at B slot of an instruction", EndMBB);
2422
0
    report_context(LR, Reg, LaneMask);
2423
0
    report_context(S);
2424
0
  }
2425
5.54M
2426
5.54M
  if (S.end.isDead()) {
2427
309k
    // Segment ends on the dead slot.
2428
309k
    // That means there must be a dead def.
2429
309k
    if (!SlotIndex::isSameInstr(S.start, S.end)) {
2430
0
      report("Live segment ending at dead slot spans instructions", EndMBB);
2431
0
      report_context(LR, Reg, LaneMask);
2432
0
      report_context(S);
2433
0
    }
2434
309k
  }
2435
5.54M
2436
5.54M
  // A live segment can only end at an early-clobber slot if it is being
2437
5.54M
  // redefined by an early-clobber def.
2438
5.54M
  if (S.end.isEarlyClobber()) {
2439
5.58k
    if (I+1 == LR.end() || (I+1)->start != S.end) {
2440
0
      report("Live segment ending at early clobber slot must be "
2441
0
             "redefined by an EC def in the same instruction", EndMBB);
2442
0
      report_context(LR, Reg, LaneMask);
2443
0
      report_context(S);
2444
0
    }
2445
5.58k
  }
2446
5.54M
2447
5.54M
  // The following checks only apply to virtual registers. Physreg liveness
2448
5.54M
  // is too weird to check.
2449
5.54M
  if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2450
4.37M
    // A live segment can end with either a redefinition, a kill flag on a
2451
4.37M
    // use, or a dead flag on a def.
2452
4.37M
    bool hasRead = false;
2453
4.37M
    bool hasSubRegDef = false;
2454
4.37M
    bool hasDeadDef = false;
2455
29.3M
    for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); 
++MOI24.9M
) {
2456
24.9M
      if (!MOI->isReg() || 
MOI->getReg() != Reg14.4M
)
2457
20.4M
        continue;
2458
4.58M
      unsigned Sub = MOI->getSubReg();
2459
4.58M
      LaneBitmask SLM = Sub != 0 ? 
TRI->getSubRegIndexLaneMask(Sub)1.31M
2460
4.58M
                                 : 
LaneBitmask::getAll()3.27M
;
2461
4.58M
      if (MOI->isDef()) {
2462
736k
        if (Sub != 0) {
2463
586k
          hasSubRegDef = true;
2464
586k
          // An operand %0:sub0 reads %0:sub1..n. Invert the lane
2465
586k
          // mask for subregister defs. Read-undef defs will be handled by
2466
586k
          // readsReg below.
2467
586k
          SLM = ~SLM;
2468
586k
        }
2469
736k
        if (MOI->isDead())
2470
65.0k
          hasDeadDef = true;
2471
736k
      }
2472
4.58M
      if (LaneMask.any() && 
(LaneMask & SLM).none()1.40M
)
2473
29.5k
        continue;
2474
4.55M
      if (MOI->readsReg())
2475
4.40M
        hasRead = true;
2476
4.55M
    }
2477
4.37M
    if (S.end.isDead()) {
2478
72.3k
      // Make sure that the corresponding machine operand for a "dead" live
2479
72.3k
      // range has the dead flag. We cannot perform this check for subregister
2480
72.3k
      // liveranges as partially dead values are allowed.
2481
72.3k
      if (LaneMask.none() && 
!hasDeadDef60.6k
) {
2482
0
        report("Instruction ending live segment on dead slot has no dead flag",
2483
0
               MI);
2484
0
        report_context(LR, Reg, LaneMask);
2485
0
        report_context(S);
2486
0
      }
2487
4.30M
    } else {
2488
4.30M
      if (!hasRead) {
2489
7
        // When tracking subregister liveness, the main range must start new
2490
7
        // values on partial register writes, even if there is no read.
2491
7
        if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.any() ||
2492
7
            !hasSubRegDef) {
2493
0
          report("Instruction ending live segment doesn't read the register",
2494
0
                 MI);
2495
0
          report_context(LR, Reg, LaneMask);
2496
0
          report_context(S);
2497
0
        }
2498
7
      }
2499
4.30M
    }
2500
4.37M
  }
2501
5.54M
2502
5.54M
  // Now check all the basic blocks in this live segment.
2503
5.54M
  MachineFunction::const_iterator MFI = MBB->getIterator();
2504
5.54M
  // Is this live segment the beginning of a non-PHIDef VN?
2505
5.54M
  if (S.start == VNI->def && 
!VNI->isPHIDef()5.53M
) {
2506
4.77M
    // Not live-in to any blocks.
2507
4.77M
    if (MBB == EndMBB)
2508
4.72M
      return;
2509
58.4k
    // Skip this block.
2510
58.4k
    ++MFI;
2511
58.4k
  }
2512
5.54M
2513
5.54M
  SmallVector<SlotIndex, 4> Undefs;
2514
819k
  if (LaneMask.any()) {
2515
19.9k
    LiveInterval &OwnerLI = LiveInts->getInterval(Reg);
2516
19.9k
    OwnerLI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
2517
19.9k
  }
2518
819k
2519
899k
  while (true) {
2520
899k
    assert(LiveInts->isLiveInToMBB(LR, &*MFI));
2521
899k
    // We don't know how to track physregs into a landing pad.
2522
899k
    if (!TargetRegisterInfo::isVirtualRegister(Reg) &&
2523
899k
        
MFI->isEHPad()719k
) {
2524
107
      if (&*MFI == EndMBB)
2525
107
        break;
2526
0
      ++MFI;
2527
0
      continue;
2528
0
    }
2529
898k
2530
898k
    // Is VNI a PHI-def in the current block?
2531
898k
    bool IsPHI = VNI->isPHIDef() &&
2532
898k
      
VNI->def == LiveInts->getMBBStartIdx(&*MFI)762k
;
2533
898k
2534
898k
    // Check that VNI is live-out of all predecessors.
2535
898k
    for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
2536
1.16M
         PE = MFI->pred_end(); PI != PE; 
++PI265k
) {
2537
265k
      SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
2538
265k
      const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
2539
265k
2540
265k
      // All predecessors must have a live-out value. However for a phi
2541
265k
      // instruction with subregister intervals
2542
265k
      // only one of the subregisters (not necessarily the current one) needs to
2543
265k
      // be defined.
2544
265k
      if (!PVNI && 
(7
LaneMask.none()7
||
!IsPHI7
)) {
2545
0
        if (LiveRangeCalc::isJointlyDominated(*PI, Undefs, *Indexes))
2546
0
          continue;
2547
0
        report("Register not marked live out of predecessor", *PI);
2548
0
        report_context(LR, Reg, LaneMask);
2549
0
        report_context(*VNI);
2550
0
        errs() << " live into " << printMBBReference(*MFI) << '@'
2551
0
               << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
2552
0
               << PEnd << '\n';
2553
0
        continue;
2554
0
      }
2555
265k
2556
265k
      // Only PHI-defs can take different predecessor values.
2557
265k
      if (!IsPHI && 
PVNI != VNI201k
) {
2558
0
        report("Different value live out of predecessor", *PI);
2559
0
        report_context(LR, Reg, LaneMask);
2560
0
        errs() << "Valno #" << PVNI->id << " live out of "
2561
0
               << printMBBReference(*(*PI)) << '@' << PEnd << "\nValno #"
2562
0
               << VNI->id << " live into " << printMBBReference(*MFI) << '@'
2563
0
               << LiveInts->getMBBStartIdx(&*MFI) << '\n';
2564
0
      }
2565
265k
    }
2566
898k
    if (&*MFI == EndMBB)
2567
819k
      break;
2568
79.1k
    ++MFI;
2569
79.1k
  }
2570
819k
}
2571
2572
void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
2573
5.11M
                                      LaneBitmask LaneMask) {
2574
5.11M
  for (const VNInfo *VNI : LR.valnos)
2575
5.64M
    verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
2576
5.11M
2577
10.7M
  for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; 
++I5.66M
)
2578
5.66M
    verifyLiveRangeSegment(LR, I, Reg, LaneMask);
2579
5.11M
}
2580
2581
2.41M
void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
2582
2.41M
  unsigned Reg = LI.reg;
2583
2.41M
  assert(TargetRegisterInfo::isVirtualRegister(Reg));
2584
2.41M
  verifyLiveRange(LI, Reg);
2585
2.41M
2586
2.41M
  LaneBitmask Mask;
2587
2.41M
  LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
2588
2.41M
  for (const LiveInterval::SubRange &SR : LI.subranges()) {
2589
1.31M
    if ((Mask & SR.LaneMask).any()) {
2590
0
      report("Lane masks of sub ranges overlap in live interval", MF);
2591
0
      report_context(LI);
2592
0
    }
2593
1.31M
    if ((SR.LaneMask & ~MaxMask).any()) {
2594
0
      report("Subrange lanemask is invalid", MF);
2595
0
      report_context(LI);
2596
0
    }
2597
1.31M
    if (SR.empty()) {
2598
0
      report("Subrange must not be empty", MF);
2599
0
      report_context(SR, LI.reg, SR.LaneMask);
2600
0
    }
2601
1.31M
    Mask |= SR.LaneMask;
2602
1.31M
    verifyLiveRange(SR, LI.reg, SR.LaneMask);
2603
1.31M
    if (!LI.covers(SR)) {
2604
0
      report("A Subrange is not covered by the main range", MF);
2605
0
      report_context(LI);
2606
0
    }
2607
1.31M
  }
2608
2.41M
2609
2.41M
  // Check the LI only has one connected component.
2610
2.41M
  ConnectedVNInfoEqClasses ConEQ(*LiveInts);
2611
2.41M
  unsigned NumComp = ConEQ.Classify(LI);
2612
2.41M
  if (NumComp > 1) {
2613
0
    report("Multiple connected components in live interval", MF);
2614
0
    report_context(LI);
2615
0
    for (unsigned comp = 0; comp != NumComp; ++comp) {
2616
0
      errs() << comp << ": valnos";
2617
0
      for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
2618
0
           E = LI.vni_end(); I!=E; ++I)
2619
0
        if (comp == ConEQ.getEqClass(*I))
2620
0
          errs() << ' ' << (*I)->id;
2621
0
      errs() << '\n';
2622
0
    }
2623
0
  }
2624
2.41M
}
2625
2626
namespace {
2627
2628
  // FrameSetup and FrameDestroy can have zero adjustment, so using a single
2629
  // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
2630
  // value is zero.
2631
  // We use a bool plus an integer to capture the stack state.
2632
  struct StackStateOfBB {
2633
5.73M
    StackStateOfBB() = default;
2634
    StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
2635
      EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
2636
0
      ExitIsSetup(ExitSetup) {}
2637
2638
    // Can be negative, which means we are setting up a frame.
2639
    int EntryValue = 0;
2640
    int ExitValue = 0;
2641
    bool EntryIsSetup = false;
2642
    bool ExitIsSetup = false;
2643
  };
2644
2645
} // end anonymous namespace
2646
2647
/// Make sure on every path through the CFG, a FrameSetup <n> is always followed
2648
/// by a FrameDestroy <n>, stack adjustments are identical on all
2649
/// CFG edges to a merge point, and frame is destroyed at end of a return block.
2650
2.28M
void MachineVerifier::verifyStackFrame() {
2651
2.28M
  unsigned FrameSetupOpcode   = TII->getCallFrameSetupOpcode();
2652
2.28M
  unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
2653
2.28M
  if (FrameSetupOpcode == ~0u && 
FrameDestroyOpcode == ~0u29.1k
)
2654
29.1k
    return;
2655
2.26M
2656
2.26M
  SmallVector<StackStateOfBB, 8> SPState;
2657
2.26M
  SPState.resize(MF->getNumBlockIDs());
2658
2.26M
  df_iterator_default_set<const MachineBasicBlock*> Reachable;
2659
2.26M
2660
2.26M
  // Visit the MBBs in DFS order.
2661
2.26M
  for (df_ext_iterator<const MachineFunction *,
2662
2.26M
                       df_iterator_default_set<const MachineBasicBlock *>>
2663
2.26M
       DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
2664
5.11M
       DFI != DFE; 
++DFI2.85M
) {
2665
2.85M
    const MachineBasicBlock *MBB = *DFI;
2666
2.85M
2667
2.85M
    StackStateOfBB BBState;
2668
2.85M
    // Check the exit state of the DFS stack predecessor.
2669
2.85M
    if (DFI.getPathLength() >= 2) {
2670
591k
      const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
2671
591k
      assert(Reachable.count(StackPred) &&
2672
591k
             "DFS stack predecessor is already visited.\n");
2673
591k
      BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
2674
591k
      BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
2675
591k
      BBState.ExitValue = BBState.EntryValue;
2676
591k
      BBState.ExitIsSetup = BBState.EntryIsSetup;
2677
591k
    }
2678
2.85M
2679
2.85M
    // Update stack state by checking contents of MBB.
2680
32.7M
    for (const auto &I : *MBB) {
2681
32.7M
      if (I.getOpcode() == FrameSetupOpcode) {
2682
166k
        if (BBState.ExitIsSetup)
2683
1
          report("FrameSetup is after another FrameSetup", &I);
2684
166k
        BBState.ExitValue -= TII->getFrameTotalSize(I);
2685
166k
        BBState.ExitIsSetup = true;
2686
166k
      }
2687
32.7M
2688
32.7M
      if (I.getOpcode() == FrameDestroyOpcode) {
2689
166k
        int Size = TII->getFrameTotalSize(I);
2690
166k
        if (!BBState.ExitIsSetup)
2691
1
          report("FrameDestroy is not after a FrameSetup", &I);
2692
166k
        int AbsSPAdj = BBState.ExitValue < 0 ? 
-BBState.ExitValue52.7k
:
2693
166k
                                               
BBState.ExitValue113k
;
2694
166k
        if (BBState.ExitIsSetup && 
AbsSPAdj != Size166k
) {
2695
1
          report("FrameDestroy <n> is after FrameSetup <m>", &I);
2696
1
          errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
2697
1
              << AbsSPAdj << ">.\n";
2698
1
        }
2699
166k
        BBState.ExitValue += Size;
2700
166k
        BBState.ExitIsSetup = false;
2701
166k
      }
2702
32.7M
    }
2703
2.85M
    SPState[MBB->getNumber()] = BBState;
2704
2.85M
2705
2.85M
    // Make sure the exit state of any predecessor is consistent with the entry
2706
2.85M
    // state.
2707
2.85M
    for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
2708
3.70M
         E = MBB->pred_end(); I != E; 
++I849k
) {
2709
849k
      if (Reachable.count(*I) &&
2710
849k
          
(728k
SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue728k
||
2711
728k
           SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
2712
0
        report("The exit stack state of a predecessor is inconsistent.", MBB);
2713
0
        errs() << "Predecessor " << printMBBReference(*(*I))
2714
0
               << " has exit state (" << SPState[(*I)->getNumber()].ExitValue
2715
0
               << ", " << SPState[(*I)->getNumber()].ExitIsSetup << "), while "
2716
0
               << printMBBReference(*MBB) << " has entry state ("
2717
0
               << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
2718
0
      }
2719
849k
    }
2720
2.85M
2721
2.85M
    // Make sure the entry state of any successor is consistent with the exit
2722
2.85M
    // state.
2723
2.85M
    for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
2724
3.70M
         E = MBB->succ_end(); I != E; 
++I849k
) {
2725
849k
      if (Reachable.count(*I) &&
2726
849k
          
(183k
SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue183k
||
2727
183k
           SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
2728
0
        report("The entry stack state of a successor is inconsistent.", MBB);
2729
0
        errs() << "Successor " << printMBBReference(*(*I))
2730
0
               << " has entry state (" << SPState[(*I)->getNumber()].EntryValue
2731
0
               << ", " << SPState[(*I)->getNumber()].EntryIsSetup << "), while "
2732
0
               << printMBBReference(*MBB) << " has exit state ("
2733
0
               << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
2734
0
      }
2735
849k
    }
2736
2.85M
2737
2.85M
    // Make sure a basic block with return ends with zero stack adjustment.
2738
2.85M
    if (!MBB->empty() && 
MBB->back().isReturn()2.82M
) {
2739
2.26M
      if (BBState.ExitIsSetup)
2740
0
        report("A return block ends with a FrameSetup.", MBB);
2741
2.26M
      if (BBState.ExitValue)
2742
0
        report("A return block ends with a nonzero stack adjustment.", MBB);
2743
2.26M
    }
2744
2.85M
  }
2745
2.26M
}