Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/PHIElimination.cpp
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//===- PhiElimination.cpp - Eliminate PHI nodes by inserting copies -------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This pass eliminates machine instruction PHI nodes by inserting copy
10
// instructions.  This destroys SSA information, but is the desired input for
11
// some register allocators.
12
//
13
//===----------------------------------------------------------------------===//
14
15
#include "PHIEliminationUtils.h"
16
#include "llvm/ADT/DenseMap.h"
17
#include "llvm/ADT/SmallPtrSet.h"
18
#include "llvm/ADT/Statistic.h"
19
#include "llvm/Analysis/LoopInfo.h"
20
#include "llvm/CodeGen/LiveInterval.h"
21
#include "llvm/CodeGen/LiveIntervals.h"
22
#include "llvm/CodeGen/LiveVariables.h"
23
#include "llvm/CodeGen/MachineBasicBlock.h"
24
#include "llvm/CodeGen/MachineDominators.h"
25
#include "llvm/CodeGen/MachineFunction.h"
26
#include "llvm/CodeGen/MachineFunctionPass.h"
27
#include "llvm/CodeGen/MachineInstr.h"
28
#include "llvm/CodeGen/MachineInstrBuilder.h"
29
#include "llvm/CodeGen/MachineLoopInfo.h"
30
#include "llvm/CodeGen/MachineOperand.h"
31
#include "llvm/CodeGen/MachineRegisterInfo.h"
32
#include "llvm/CodeGen/SlotIndexes.h"
33
#include "llvm/CodeGen/TargetInstrInfo.h"
34
#include "llvm/CodeGen/TargetOpcodes.h"
35
#include "llvm/CodeGen/TargetRegisterInfo.h"
36
#include "llvm/CodeGen/TargetSubtargetInfo.h"
37
#include "llvm/Pass.h"
38
#include "llvm/Support/CommandLine.h"
39
#include "llvm/Support/Debug.h"
40
#include "llvm/Support/raw_ostream.h"
41
#include <cassert>
42
#include <iterator>
43
#include <utility>
44
45
using namespace llvm;
46
47
#define DEBUG_TYPE "phi-node-elimination"
48
49
static cl::opt<bool>
50
DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false),
51
                     cl::Hidden, cl::desc("Disable critical edge splitting "
52
                                          "during PHI elimination"));
53
54
static cl::opt<bool>
55
SplitAllCriticalEdges("phi-elim-split-all-critical-edges", cl::init(false),
56
                      cl::Hidden, cl::desc("Split all critical edges during "
57
                                           "PHI elimination"));
58
59
static cl::opt<bool> NoPhiElimLiveOutEarlyExit(
60
    "no-phi-elim-live-out-early-exit", cl::init(false), cl::Hidden,
61
    cl::desc("Do not use an early exit if isLiveOutPastPHIs returns true."));
62
63
namespace {
64
65
  class PHIElimination : public MachineFunctionPass {
66
    MachineRegisterInfo *MRI; // Machine register information
67
    LiveVariables *LV;
68
    LiveIntervals *LIS;
69
70
  public:
71
    static char ID; // Pass identification, replacement for typeid
72
73
36.3k
    PHIElimination() : MachineFunctionPass(ID) {
74
36.3k
      initializePHIEliminationPass(*PassRegistry::getPassRegistry());
75
36.3k
    }
76
77
    bool runOnMachineFunction(MachineFunction &MF) override;
78
    void getAnalysisUsage(AnalysisUsage &AU) const override;
79
80
  private:
81
    /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
82
    /// in predecessor basic blocks.
83
    bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
84
85
    void LowerPHINode(MachineBasicBlock &MBB,
86
                      MachineBasicBlock::iterator LastPHIIt);
87
88
    /// analyzePHINodes - Gather information about the PHI nodes in
89
    /// here. In particular, we want to map the number of uses of a virtual
90
    /// register which is used in a PHI node. We map that to the BB the
91
    /// vreg is coming from. This is used later to determine when the vreg
92
    /// is killed in the BB.
93
    void analyzePHINodes(const MachineFunction& MF);
94
95
    /// Split critical edges where necessary for good coalescer performance.
96
    bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
97
                       MachineLoopInfo *MLI);
98
99
    // These functions are temporary abstractions around LiveVariables and
100
    // LiveIntervals, so they can go away when LiveVariables does.
101
    bool isLiveIn(unsigned Reg, const MachineBasicBlock *MBB);
102
    bool isLiveOutPastPHIs(unsigned Reg, const MachineBasicBlock *MBB);
103
104
    using BBVRegPair = std::pair<unsigned, unsigned>;
105
    using VRegPHIUse = DenseMap<BBVRegPair, unsigned>;
106
107
    VRegPHIUse VRegPHIUseCount;
108
109
    // Defs of PHI sources which are implicit_def.
110
    SmallPtrSet<MachineInstr*, 4> ImpDefs;
111
112
    // Map reusable lowered PHI node -> incoming join register.
113
    using LoweredPHIMap =
114
        DenseMap<MachineInstr*, unsigned, MachineInstrExpressionTrait>;
115
    LoweredPHIMap LoweredPHIs;
116
  };
117
118
} // end anonymous namespace
119
120
STATISTIC(NumLowered, "Number of phis lowered");
121
STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");
122
STATISTIC(NumReused, "Number of reused lowered phis");
123
124
char PHIElimination::ID = 0;
125
126
char& llvm::PHIEliminationID = PHIElimination::ID;
127
128
42.3k
INITIALIZE_PASS_BEGIN(PHIElimination, DEBUG_TYPE,
129
42.3k
                      "Eliminate PHI nodes for register allocation",
130
42.3k
                      false, false)
131
42.3k
INITIALIZE_PASS_DEPENDENCY(LiveVariables)
132
42.3k
INITIALIZE_PASS_END(PHIElimination, DEBUG_TYPE,
133
                    "Eliminate PHI nodes for register allocation", false, false)
134
135
36.0k
void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
136
36.0k
  AU.addUsedIfAvailable<LiveVariables>();
137
36.0k
  AU.addPreserved<LiveVariables>();
138
36.0k
  AU.addPreserved<SlotIndexes>();
139
36.0k
  AU.addPreserved<LiveIntervals>();
140
36.0k
  AU.addPreserved<MachineDominatorTree>();
141
36.0k
  AU.addPreserved<MachineLoopInfo>();
142
36.0k
  MachineFunctionPass::getAnalysisUsage(AU);
143
36.0k
}
144
145
498k
bool PHIElimination::runOnMachineFunction(MachineFunction &MF) {
146
498k
  MRI = &MF.getRegInfo();
147
498k
  LV = getAnalysisIfAvailable<LiveVariables>();
148
498k
  LIS = getAnalysisIfAvailable<LiveIntervals>();
149
498k
150
498k
  bool Changed = false;
151
498k
152
498k
  // This pass takes the function out of SSA form.
153
498k
  MRI->leaveSSA();
154
498k
155
498k
  // Split critical edges to help the coalescer.
156
498k
  if (
!DisableEdgeSplitting498k
&& (LV ||
LIS8.81k
)) {
157
489k
    MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>();
158
489k
    for (auto &MBB : MF)
159
2.69M
      Changed |= SplitPHIEdges(MF, MBB, MLI);
160
489k
  }
161
498k
162
498k
  // Populate VRegPHIUseCount
163
498k
  analyzePHINodes(MF);
164
498k
165
498k
  // Eliminate PHI instructions by inserting copies into predecessor blocks.
166
498k
  for (auto &MBB : MF)
167
2.84M
    Changed |= EliminatePHINodes(MF, MBB);
168
498k
169
498k
  // Remove dead IMPLICIT_DEF instructions.
170
498k
  for (MachineInstr *DefMI : ImpDefs) {
171
22
    unsigned DefReg = DefMI->getOperand(0).getReg();
172
22
    if (MRI->use_nodbg_empty(DefReg)) {
173
22
      if (LIS)
174
0
        LIS->RemoveMachineInstrFromMaps(*DefMI);
175
22
      DefMI->eraseFromParent();
176
22
    }
177
22
  }
178
498k
179
498k
  // Clean up the lowered PHI instructions.
180
630k
  for (auto &I : LoweredPHIs) {
181
630k
    if (LIS)
182
0
      LIS->RemoveMachineInstrFromMaps(*I.first);
183
630k
    MF.DeleteMachineInstr(I.first);
184
630k
  }
185
498k
186
498k
  LoweredPHIs.clear();
187
498k
  ImpDefs.clear();
188
498k
  VRegPHIUseCount.clear();
189
498k
190
498k
  MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
191
498k
192
498k
  return Changed;
193
498k
}
194
195
/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
196
/// predecessor basic blocks.
197
bool PHIElimination::EliminatePHINodes(MachineFunction &MF,
198
2.84M
                                       MachineBasicBlock &MBB) {
199
2.84M
  if (MBB.empty() || 
!MBB.front().isPHI()2.78M
)
200
2.43M
    return false;   // Quick exit for basic blocks without PHIs.
201
408k
202
408k
  // Get an iterator to the last PHI node.
203
408k
  MachineBasicBlock::iterator LastPHIIt =
204
408k
    std::prev(MBB.SkipPHIsAndLabels(MBB.begin()));
205
408k
206
1.04M
  while (MBB.front().isPHI())
207
633k
    LowerPHINode(MBB, LastPHIIt);
208
408k
209
408k
  return true;
210
408k
}
211
212
/// Return true if all defs of VirtReg are implicit-defs.
213
/// This includes registers with no defs.
214
static bool isImplicitlyDefined(unsigned VirtReg,
215
2.16M
                                const MachineRegisterInfo &MRI) {
216
2.16M
  for (MachineInstr &DI : MRI.def_instructions(VirtReg))
217
2.15M
    if (!DI.isImplicitDef())
218
2.15M
      return false;
219
2.16M
  
return true3.27k
;
220
2.16M
}
221
222
/// Return true if all sources of the phi node are implicit_def's, or undef's.
223
static bool allPhiOperandsUndefined(const MachineInstr &MPhi,
224
633k
                                    const MachineRegisterInfo &MRI) {
225
636k
  for (unsigned I = 1, E = MPhi.getNumOperands(); I != E; 
I += 23.23k
) {
226
636k
    const MachineOperand &MO = MPhi.getOperand(I);
227
636k
    if (!isImplicitlyDefined(MO.getReg(), MRI) && 
!MO.isUndef()633k
)
228
633k
      return false;
229
636k
  }
230
633k
  
return true4
;
231
633k
}
232
/// LowerPHINode - Lower the PHI node at the top of the specified block.
233
void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
234
633k
                                  MachineBasicBlock::iterator LastPHIIt) {
235
633k
  ++NumLowered;
236
633k
237
633k
  MachineBasicBlock::iterator AfterPHIsIt = std::next(LastPHIIt);
238
633k
239
633k
  // Unlink the PHI node from the basic block, but don't delete the PHI yet.
240
633k
  MachineInstr *MPhi = MBB.remove(&*MBB.begin());
241
633k
242
633k
  unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
243
633k
  unsigned DestReg = MPhi->getOperand(0).getReg();
244
633k
  assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
245
633k
  bool isDead = MPhi->getOperand(0).isDead();
246
633k
247
633k
  // Create a new register for the incoming PHI arguments.
248
633k
  MachineFunction &MF = *MBB.getParent();
249
633k
  unsigned IncomingReg = 0;
250
633k
  bool reusedIncoming = false;  // Is IncomingReg reused from an earlier PHI?
251
633k
252
633k
  // Insert a register to register copy at the top of the current block (but
253
633k
  // after any remaining phi nodes) which copies the new incoming register
254
633k
  // into the phi node destination.
255
633k
  const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
256
633k
  if (allPhiOperandsUndefined(*MPhi, *MRI))
257
4
    // If all sources of a PHI node are implicit_def or undef uses, just emit an
258
4
    // implicit_def instead of a copy.
259
4
    BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
260
4
            TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
261
633k
  else {
262
633k
    // Can we reuse an earlier PHI node? This only happens for critical edges,
263
633k
    // typically those created by tail duplication.
264
633k
    unsigned &entry = LoweredPHIs[MPhi];
265
633k
    if (entry) {
266
2.82k
      // An identical PHI node was already lowered. Reuse the incoming register.
267
2.82k
      IncomingReg = entry;
268
2.82k
      reusedIncoming = true;
269
2.82k
      ++NumReused;
270
2.82k
      LLVM_DEBUG(dbgs() << "Reusing " << printReg(IncomingReg) << " for "
271
2.82k
                        << *MPhi);
272
630k
    } else {
273
630k
      const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
274
630k
      entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
275
630k
    }
276
633k
    BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
277
633k
            TII->get(TargetOpcode::COPY), DestReg)
278
633k
      .addReg(IncomingReg);
279
633k
  }
280
633k
281
633k
  // Update live variable information if there is any.
282
633k
  if (LV) {
283
632k
    MachineInstr &PHICopy = *std::prev(AfterPHIsIt);
284
632k
285
632k
    if (IncomingReg) {
286
632k
      LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
287
632k
288
632k
      // Increment use count of the newly created virtual register.
289
632k
      LV->setPHIJoin(IncomingReg);
290
632k
291
632k
      // When we are reusing the incoming register, it may already have been
292
632k
      // killed in this block. The old kill will also have been inserted at
293
632k
      // AfterPHIsIt, so it appears before the current PHICopy.
294
632k
      if (reusedIncoming)
295
2.82k
        if (MachineInstr *OldKill = VI.findKill(&MBB)) {
296
2.42k
          LLVM_DEBUG(dbgs() << "Remove old kill from " << *OldKill);
297
2.42k
          LV->removeVirtualRegisterKilled(IncomingReg, *OldKill);
298
2.42k
          LLVM_DEBUG(MBB.dump());
299
2.42k
        }
300
632k
301
632k
      // Add information to LiveVariables to know that the incoming value is
302
632k
      // killed.  Note that because the value is defined in several places (once
303
632k
      // each for each incoming block), the "def" block and instruction fields
304
632k
      // for the VarInfo is not filled in.
305
632k
      LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
306
632k
    }
307
632k
308
632k
    // Since we are going to be deleting the PHI node, if it is the last use of
309
632k
    // any registers, or if the value itself is dead, we need to move this
310
632k
    // information over to the new copy we just inserted.
311
632k
    LV->removeVirtualRegistersKilled(*MPhi);
312
632k
313
632k
    // If the result is dead, update LV.
314
632k
    if (isDead) {
315
3
      LV->addVirtualRegisterDead(DestReg, PHICopy);
316
3
      LV->removeVirtualRegisterDead(DestReg, *MPhi);
317
3
    }
318
632k
  }
319
633k
320
633k
  // Update LiveIntervals for the new copy or implicit def.
321
633k
  if (LIS) {
322
0
    SlotIndex DestCopyIndex =
323
0
        LIS->InsertMachineInstrInMaps(*std::prev(AfterPHIsIt));
324
0
325
0
    SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
326
0
    if (IncomingReg) {
327
0
      // Add the region from the beginning of MBB to the copy instruction to
328
0
      // IncomingReg's live interval.
329
0
      LiveInterval &IncomingLI = LIS->createEmptyInterval(IncomingReg);
330
0
      VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(MBBStartIndex);
331
0
      if (!IncomingVNI)
332
0
        IncomingVNI = IncomingLI.getNextValue(MBBStartIndex,
333
0
                                              LIS->getVNInfoAllocator());
334
0
      IncomingLI.addSegment(LiveInterval::Segment(MBBStartIndex,
335
0
                                                  DestCopyIndex.getRegSlot(),
336
0
                                                  IncomingVNI));
337
0
    }
338
0
339
0
    LiveInterval &DestLI = LIS->getInterval(DestReg);
340
0
    assert(DestLI.begin() != DestLI.end() &&
341
0
           "PHIs should have nonempty LiveIntervals.");
342
0
    if (DestLI.endIndex().isDead()) {
343
0
      // A dead PHI's live range begins and ends at the start of the MBB, but
344
0
      // the lowered copy, which will still be dead, needs to begin and end at
345
0
      // the copy instruction.
346
0
      VNInfo *OrigDestVNI = DestLI.getVNInfoAt(MBBStartIndex);
347
0
      assert(OrigDestVNI && "PHI destination should be live at block entry.");
348
0
      DestLI.removeSegment(MBBStartIndex, MBBStartIndex.getDeadSlot());
349
0
      DestLI.createDeadDef(DestCopyIndex.getRegSlot(),
350
0
                           LIS->getVNInfoAllocator());
351
0
      DestLI.removeValNo(OrigDestVNI);
352
0
    } else {
353
0
      // Otherwise, remove the region from the beginning of MBB to the copy
354
0
      // instruction from DestReg's live interval.
355
0
      DestLI.removeSegment(MBBStartIndex, DestCopyIndex.getRegSlot());
356
0
      VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot());
357
0
      assert(DestVNI && "PHI destination should be live at its definition.");
358
0
      DestVNI->def = DestCopyIndex.getRegSlot();
359
0
    }
360
0
  }
361
633k
362
633k
  // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
363
2.16M
  for (unsigned i = 1; i != MPhi->getNumOperands(); 
i += 21.52M
)
364
1.52M
    --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
365
1.52M
                                 MPhi->getOperand(i).getReg())];
366
633k
367
633k
  // Now loop over all of the incoming arguments, changing them to copy into the
368
633k
  // IncomingReg register in the corresponding predecessor basic block.
369
633k
  SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
370
2.16M
  for (int i = NumSrcs - 1; i >= 0; 
--i1.52M
) {
371
1.52M
    unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
372
1.52M
    unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
373
1.52M
    bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() ||
374
1.52M
      
isImplicitlyDefined(SrcReg, *MRI)1.52M
;
375
1.52M
    assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
376
1.52M
           "Machine PHI Operands must all be virtual registers!");
377
1.52M
378
1.52M
    // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
379
1.52M
    // path the PHI.
380
1.52M
    MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
381
1.52M
382
1.52M
    // Check to make sure we haven't already emitted the copy for this block.
383
1.52M
    // This can happen because PHI nodes may have multiple entries for the same
384
1.52M
    // basic block.
385
1.52M
    if (!MBBsInsertedInto.insert(&opBlock).second)
386
1.64k
      continue;  // If the copy has already been emitted, we're done.
387
1.52M
388
1.52M
    // Find a safe location to insert the copy, this may be the first terminator
389
1.52M
    // in the block (or end()).
390
1.52M
    MachineBasicBlock::iterator InsertPos =
391
1.52M
      findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
392
1.52M
393
1.52M
    // Insert the copy.
394
1.52M
    MachineInstr *NewSrcInstr = nullptr;
395
1.52M
    if (!reusedIncoming && 
IncomingReg1.51M
) {
396
1.51M
      if (SrcUndef) {
397
3.59k
        // The source register is undefined, so there is no need for a real
398
3.59k
        // COPY, but we still need to ensure joint dominance by defs.
399
3.59k
        // Insert an IMPLICIT_DEF instruction.
400
3.59k
        NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
401
3.59k
                              TII->get(TargetOpcode::IMPLICIT_DEF),
402
3.59k
                              IncomingReg);
403
3.59k
404
3.59k
        // Clean up the old implicit-def, if there even was one.
405
3.59k
        if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
406
38
          if (DefMI->isImplicitDef())
407
38
            ImpDefs.insert(DefMI);
408
1.51M
      } else {
409
1.51M
        NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
410
1.51M
                            TII->get(TargetOpcode::COPY), IncomingReg)
411
1.51M
                        .addReg(SrcReg, 0, SrcSubReg);
412
1.51M
      }
413
1.51M
    }
414
1.52M
415
1.52M
    // We only need to update the LiveVariables kill of SrcReg if this was the
416
1.52M
    // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
417
1.52M
    // out of the predecessor. We can also ignore undef sources.
418
1.52M
    if (LV && 
!SrcUndef1.52M
&&
419
1.52M
        
!VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]1.52M
&&
420
1.52M
        
!LV->isLiveOut(SrcReg, opBlock)1.46M
) {
421
1.32M
      // We want to be able to insert a kill of the register if this PHI (aka,
422
1.32M
      // the copy we just inserted) is the last use of the source value. Live
423
1.32M
      // variable analysis conservatively handles this by saying that the value
424
1.32M
      // is live until the end of the block the PHI entry lives in. If the value
425
1.32M
      // really is dead at the PHI copy, there will be no successor blocks which
426
1.32M
      // have the value live-in.
427
1.32M
428
1.32M
      // Okay, if we now know that the value is not live out of the block, we
429
1.32M
      // can add a kill marker in this block saying that it kills the incoming
430
1.32M
      // value!
431
1.32M
432
1.32M
      // In our final twist, we have to decide which instruction kills the
433
1.32M
      // register.  In most cases this is the copy, however, terminator
434
1.32M
      // instructions at the end of the block may also use the value. In this
435
1.32M
      // case, we should mark the last such terminator as being the killing
436
1.32M
      // block, not the copy.
437
1.32M
      MachineBasicBlock::iterator KillInst = opBlock.end();
438
1.32M
      MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
439
1.32M
      for (MachineBasicBlock::iterator Term = FirstTerm;
440
2.49M
          Term != opBlock.end(); 
++Term1.17M
) {
441
1.17M
        if (Term->readsRegister(SrcReg))
442
39.1k
          KillInst = Term;
443
1.17M
      }
444
1.32M
445
1.32M
      if (KillInst == opBlock.end()) {
446
1.28M
        // No terminator uses the register.
447
1.28M
448
1.28M
        if (reusedIncoming || 
!IncomingReg1.28M
) {
449
5.36k
          // We may have to rewind a bit if we didn't insert a copy this time.
450
5.36k
          KillInst = FirstTerm;
451
7.42k
          while (KillInst != opBlock.begin()) {
452
7.42k
            --KillInst;
453
7.42k
            if (KillInst->isDebugInstr())
454
0
              continue;
455
7.42k
            if (KillInst->readsRegister(SrcReg))
456
5.36k
              break;
457
7.42k
          }
458
1.28M
        } else {
459
1.28M
          // We just inserted this copy.
460
1.28M
          KillInst = std::prev(InsertPos);
461
1.28M
        }
462
1.28M
      }
463
1.32M
      assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
464
1.32M
465
1.32M
      // Finally, mark it killed.
466
1.32M
      LV->addVirtualRegisterKilled(SrcReg, *KillInst);
467
1.32M
468
1.32M
      // This vreg no longer lives all of the way through opBlock.
469
1.32M
      unsigned opBlockNum = opBlock.getNumber();
470
1.32M
      LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
471
1.32M
    }
472
1.52M
473
1.52M
    if (LIS) {
474
0
      if (NewSrcInstr) {
475
0
        LIS->InsertMachineInstrInMaps(*NewSrcInstr);
476
0
        LIS->addSegmentToEndOfBlock(IncomingReg, *NewSrcInstr);
477
0
      }
478
0
479
0
      if (!SrcUndef &&
480
0
          !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) {
481
0
        LiveInterval &SrcLI = LIS->getInterval(SrcReg);
482
0
483
0
        bool isLiveOut = false;
484
0
        for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
485
0
             SE = opBlock.succ_end(); SI != SE; ++SI) {
486
0
          SlotIndex startIdx = LIS->getMBBStartIdx(*SI);
487
0
          VNInfo *VNI = SrcLI.getVNInfoAt(startIdx);
488
0
489
0
          // Definitions by other PHIs are not truly live-in for our purposes.
490
0
          if (VNI && VNI->def != startIdx) {
491
0
            isLiveOut = true;
492
0
            break;
493
0
          }
494
0
        }
495
0
496
0
        if (!isLiveOut) {
497
0
          MachineBasicBlock::iterator KillInst = opBlock.end();
498
0
          MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
499
0
          for (MachineBasicBlock::iterator Term = FirstTerm;
500
0
              Term != opBlock.end(); ++Term) {
501
0
            if (Term->readsRegister(SrcReg))
502
0
              KillInst = Term;
503
0
          }
504
0
505
0
          if (KillInst == opBlock.end()) {
506
0
            // No terminator uses the register.
507
0
508
0
            if (reusedIncoming || !IncomingReg) {
509
0
              // We may have to rewind a bit if we didn't just insert a copy.
510
0
              KillInst = FirstTerm;
511
0
              while (KillInst != opBlock.begin()) {
512
0
                --KillInst;
513
0
                if (KillInst->isDebugInstr())
514
0
                  continue;
515
0
                if (KillInst->readsRegister(SrcReg))
516
0
                  break;
517
0
              }
518
0
            } else {
519
0
              // We just inserted this copy.
520
0
              KillInst = std::prev(InsertPos);
521
0
            }
522
0
          }
523
0
          assert(KillInst->readsRegister(SrcReg) &&
524
0
                 "Cannot find kill instruction");
525
0
526
0
          SlotIndex LastUseIndex = LIS->getInstructionIndex(*KillInst);
527
0
          SrcLI.removeSegment(LastUseIndex.getRegSlot(),
528
0
                              LIS->getMBBEndIdx(&opBlock));
529
0
        }
530
0
      }
531
0
    }
532
1.52M
  }
533
633k
534
633k
  // Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
535
633k
  if (reusedIncoming || 
!IncomingReg630k
) {
536
2.83k
    if (LIS)
537
0
      LIS->RemoveMachineInstrFromMaps(*MPhi);
538
2.83k
    MF.DeleteMachineInstr(MPhi);
539
2.83k
  }
540
633k
}
541
542
/// analyzePHINodes - Gather information about the PHI nodes in here. In
543
/// particular, we want to map the number of uses of a virtual register which is
544
/// used in a PHI node. We map that to the BB the vreg is coming from. This is
545
/// used later to determine when the vreg is killed in the BB.
546
498k
void PHIElimination::analyzePHINodes(const MachineFunction& MF) {
547
498k
  for (const auto &MBB : MF)
548
3.41M
    
for (const auto &BBI : MBB)2.84M
{
549
3.41M
      if (!BBI.isPHI())
550
2.78M
        break;
551
2.16M
      
for (unsigned i = 1, e = BBI.getNumOperands(); 633k
i != e;
i += 21.52M
)
552
1.52M
        ++VRegPHIUseCount[BBVRegPair(BBI.getOperand(i+1).getMBB()->getNumber(),
553
1.52M
                                     BBI.getOperand(i).getReg())];
554
633k
    }
555
498k
}
556
557
bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
558
                                   MachineBasicBlock &MBB,
559
2.69M
                                   MachineLoopInfo *MLI) {
560
2.69M
  if (MBB.empty() || 
!MBB.front().isPHI()2.64M
||
MBB.isEHPad()407k
)
561
2.28M
    return false;   // Quick exit for basic blocks without PHIs.
562
407k
563
407k
  const MachineLoop *CurLoop = MLI ? 
MLI->getLoopFor(&MBB)407k
:
nullptr2
;
564
407k
  bool IsLoopHeader = CurLoop && 
&MBB == CurLoop->getHeader()238k
;
565
407k
566
407k
  bool Changed = false;
567
407k
  for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end();
568
1.04M
       BBI != BBE && 
BBI->isPHI()1.03M
;
++BBI632k
) {
569
2.15M
    for (unsigned i = 1, e = BBI->getNumOperands(); i != e; 
i += 21.52M
) {
570
1.52M
      unsigned Reg = BBI->getOperand(i).getReg();
571
1.52M
      MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
572
1.52M
      // Is there a critical edge from PreMBB to MBB?
573
1.52M
      if (PreMBB->succ_size() == 1)
574
870k
        continue;
575
655k
576
655k
      // Avoid splitting backedges of loops. It would introduce small
577
655k
      // out-of-line blocks into the loop which is very bad for code placement.
578
655k
      if (PreMBB == &MBB && 
!SplitAllCriticalEdges183k
)
579
183k
        continue;
580
472k
      const MachineLoop *PreLoop = MLI ? 
MLI->getLoopFor(PreMBB)472k
:
nullptr1
;
581
472k
      if (IsLoopHeader && 
PreLoop == CurLoop144k
&&
!SplitAllCriticalEdges133k
)
582
133k
        continue;
583
338k
584
338k
      // LV doesn't consider a phi use live-out, so isLiveOut only returns true
585
338k
      // when the source register is live-out for some other reason than a phi
586
338k
      // use. That means the copy we will insert in PreMBB won't be a kill, and
587
338k
      // there is a risk it may not be coalesced away.
588
338k
      //
589
338k
      // If the copy would be a kill, there is no need to split the edge.
590
338k
      bool ShouldSplit = isLiveOutPastPHIs(Reg, PreMBB);
591
338k
      if (!ShouldSplit && 
!NoPhiElimLiveOutEarlyExit161k
)
592
161k
        continue;
593
177k
      if (ShouldSplit) {
594
177k
        LLVM_DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge "
595
177k
                          << printMBBReference(*PreMBB) << " -> "
596
177k
                          << printMBBReference(MBB) << ": " << *BBI);
597
177k
      }
598
177k
599
177k
      // If Reg is not live-in to MBB, it means it must be live-in to some
600
177k
      // other PreMBB successor, and we can avoid the interference by splitting
601
177k
      // the edge.
602
177k
      //
603
177k
      // If Reg *is* live-in to MBB, the interference is inevitable and a copy
604
177k
      // is likely to be left after coalescing. If we are looking at a loop
605
177k
      // exiting edge, split it so we won't insert code in the loop, otherwise
606
177k
      // don't bother.
607
177k
      ShouldSplit = ShouldSplit && 
!isLiveIn(Reg, &MBB)177k
;
608
177k
609
177k
      // Check for a loop exiting edge.
610
177k
      if (!ShouldSplit && 
CurLoop != PreLoop34.5k
) {
611
8.24k
        LLVM_DEBUG({
612
8.24k
          dbgs() << "Split wouldn't help, maybe avoid loop copies?\n";
613
8.24k
          if (PreLoop)
614
8.24k
            dbgs() << "PreLoop: " << *PreLoop;
615
8.24k
          if (CurLoop)
616
8.24k
            dbgs() << "CurLoop: " << *CurLoop;
617
8.24k
        });
618
8.24k
        // This edge could be entering a loop, exiting a loop, or it could be
619
8.24k
        // both: Jumping directly form one loop to the header of a sibling
620
8.24k
        // loop.
621
8.24k
        // Split unless this edge is entering CurLoop from an outer loop.
622
8.24k
        ShouldSplit = PreLoop && 
!PreLoop->contains(CurLoop)8.20k
;
623
8.24k
      }
624
177k
      if (!ShouldSplit && 
!SplitAllCriticalEdges33.6k
)
625
33.6k
        continue;
626
143k
      if (!PreMBB->SplitCriticalEdge(&MBB, *this)) {
627
1.20k
        LLVM_DEBUG(dbgs() << "Failed to split critical edge.\n");
628
1.20k
        continue;
629
1.20k
      }
630
142k
      Changed = true;
631
142k
      ++NumCriticalEdgesSplit;
632
142k
    }
633
632k
  }
634
407k
  return Changed;
635
407k
}
636
637
177k
bool PHIElimination::isLiveIn(unsigned Reg, const MachineBasicBlock *MBB) {
638
177k
  assert((LV || LIS) &&
639
177k
         "isLiveIn() requires either LiveVariables or LiveIntervals");
640
177k
  if (LIS)
641
0
    return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB);
642
177k
  else
643
177k
    return LV->isLiveIn(Reg, *MBB);
644
177k
}
645
646
bool PHIElimination::isLiveOutPastPHIs(unsigned Reg,
647
338k
                                       const MachineBasicBlock *MBB) {
648
338k
  assert((LV || LIS) &&
649
338k
         "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");
650
338k
  // LiveVariables considers uses in PHIs to be in the predecessor basic block,
651
338k
  // so that a register used only in a PHI is not live out of the block. In
652
338k
  // contrast, LiveIntervals considers uses in PHIs to be on the edge rather than
653
338k
  // in the predecessor basic block, so that a register used only in a PHI is live
654
338k
  // out of the block.
655
338k
  if (LIS) {
656
0
    const LiveInterval &LI = LIS->getInterval(Reg);
657
0
    for (const MachineBasicBlock *SI : MBB->successors())
658
0
      if (LI.liveAt(LIS->getMBBStartIdx(SI)))
659
0
        return true;
660
0
    return false;
661
338k
  } else {
662
338k
    return LV->isLiveOut(Reg, *MBB);
663
338k
  }
664
338k
}