Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
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//===---------------------- ProcessImplicitDefs.cpp -----------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/ADT/SetVector.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "processimpdefs"
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namespace {
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/// Process IMPLICIT_DEF instructions and make sure there is one implicit_def
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/// for each use. Add isUndef marker to implicit_def defs and their uses.
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class ProcessImplicitDefs : public MachineFunctionPass {
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  const TargetInstrInfo *TII;
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  const TargetRegisterInfo *TRI;
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  MachineRegisterInfo *MRI;
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  SmallSetVector<MachineInstr*, 16> WorkList;
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  void processImplicitDef(MachineInstr *MI);
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  bool canTurnIntoImplicitDef(MachineInstr *MI);
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public:
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  static char ID;
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  ProcessImplicitDefs() : MachineFunctionPass(ID) {
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    initializeProcessImplicitDefsPass(*PassRegistry::getPassRegistry());
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  }
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  void getAnalysisUsage(AnalysisUsage &au) const override;
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  bool runOnMachineFunction(MachineFunction &MF) override;
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};
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} // end anonymous namespace
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char ProcessImplicitDefs::ID = 0;
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char &llvm::ProcessImplicitDefsID = ProcessImplicitDefs::ID;
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INITIALIZE_PASS(ProcessImplicitDefs, DEBUG_TYPE,
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                "Process Implicit Definitions", false, false)
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void ProcessImplicitDefs::getAnalysisUsage(AnalysisUsage &AU) const {
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  AU.setPreservesCFG();
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  AU.addPreserved<AAResultsWrapperPass>();
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  MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) {
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  if (!MI->isCopyLike() &&
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!MI->isInsertSubreg()152k
&&
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!MI->isRegSequence()21.8k
&&
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!MI->isPHI()17.3k
)
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    return false;
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  for (const MachineOperand &MO : MI->operands())
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    if (MO.isReg() && 
MO.isUse()435k
&&
MO.readsReg()287k
)
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      return false;
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return true10.3k
;
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}
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void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
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  LLVM_DEBUG(dbgs() << "Processing " << *MI);
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  unsigned Reg = MI->getOperand(0).getReg();
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  if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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    // For virtual registers, mark all uses as <undef>, and convert users to
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    // implicit-def when possible.
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    for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
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      MO.setIsUndef();
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      MachineInstr *UserMI = MO.getParent();
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      if (!canTurnIntoImplicitDef(UserMI))
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        continue;
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      LLVM_DEBUG(dbgs() << "Converting to IMPLICIT_DEF: " << *UserMI);
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      UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
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      WorkList.insert(UserMI);
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    }
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    MI->eraseFromParent();
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    return;
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  }
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  // This is a physreg implicit-def.
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  // Look for the first instruction to use or define an alias.
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  MachineBasicBlock::instr_iterator UserMI = MI->getIterator();
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  MachineBasicBlock::instr_iterator UserE = MI->getParent()->instr_end();
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  bool Found = false;
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  for (++UserMI; UserMI != UserE; 
++UserMI31.5k
) {
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    for (MachineOperand &MO : UserMI->operands()) {
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      if (!MO.isReg())
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        continue;
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      unsigned UserReg = MO.getReg();
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      if (!TargetRegisterInfo::isPhysicalRegister(UserReg) ||
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!TRI->regsOverlap(Reg, UserReg)60.0k
)
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        continue;
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      // UserMI uses or redefines Reg. Set <undef> flags on all uses.
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      Found = true;
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      if (MO.isUse())
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        MO.setIsUndef();
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    }
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    if (Found)
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      break;
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  }
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  // If we found the using MI, we can erase the IMPLICIT_DEF.
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  if (Found) {
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    LLVM_DEBUG(dbgs() << "Physreg user: " << *UserMI);
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    MI->eraseFromParent();
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    return;
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  }
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  // Using instr wasn't found, it could be in another block.
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  // Leave the physreg IMPLICIT_DEF, but trim any extra operands.
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  for (unsigned i = MI->getNumOperands() - 1; i; 
--i0
)
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    MI->RemoveOperand(i);
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  LLVM_DEBUG(dbgs() << "Keeping physreg: " << *MI);
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}
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/// processImplicitDefs - Process IMPLICIT_DEF instructions and turn them into
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/// <undef> operands.
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bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &MF) {
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  LLVM_DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n"
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                    << "********** Function: " << MF.getName() << '\n');
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  bool Changed = false;
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  TII = MF.getSubtarget().getInstrInfo();
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  TRI = MF.getSubtarget().getRegisterInfo();
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  MRI = &MF.getRegInfo();
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  assert(MRI->isSSA() && "ProcessImplicitDefs only works on SSA form.");
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  assert(WorkList.empty() && "Inconsistent worklist state");
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  for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end();
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       MFI != MFE; 
++MFI2.68M
) {
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    // Scan the basic block for implicit defs.
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    for (MachineBasicBlock::instr_iterator MBBI = MFI->instr_begin(),
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         MBBE = MFI->instr_end(); MBBI != MBBE; 
++MBBI24.1M
)
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      if (MBBI->isImplicitDef())
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        WorkList.insert(&*MBBI);
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    if (WorkList.empty())
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      continue;
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    LLVM_DEBUG(dbgs() << printMBBReference(*MFI) << " has " << WorkList.size()
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                      << " implicit defs.\n");
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    Changed = true;
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    // Drain the WorkList to recursively process any new implicit defs.
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    do processImplicitDef(WorkList.pop_back_val());
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    while (!WorkList.empty());
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  }
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  return Changed;
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}