Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/RegAllocBase.h
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//===- RegAllocBase.h - basic regalloc interface and driver -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the RegAllocBase class, which is the skeleton of a basic
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// register allocation algorithm and interface for extending it. It provides the
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// building blocks on which to construct other experimental allocators and test
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// the validity of two principles:
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//
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// - If virtual and physical register liveness is modeled using intervals, then
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// on-the-fly interference checking is cheap. Furthermore, interferences can be
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// lazily cached and reused.
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//
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// - Register allocation complexity, and generated code performance is
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// determined by the effectiveness of live range splitting rather than optimal
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// coloring.
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//
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// Following the first principle, interfering checking revolves around the
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// LiveIntervalUnion data structure.
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//
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// To fulfill the second principle, the basic allocator provides a driver for
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// incremental splitting. It essentially punts on the problem of register
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// coloring, instead driving the assignment of virtual to physical registers by
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// the cost of splitting. The basic allocator allows for heuristic reassignment
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// of registers, if a more sophisticated allocator chooses to do that.
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//
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// This framework provides a way to engineer the compile time vs. code
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// quality trade-off without relying on a particular theoretical solver.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_CODEGEN_REGALLOCBASE_H
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#define LLVM_LIB_CODEGEN_REGALLOCBASE_H
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/CodeGen/RegisterClassInfo.h"
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namespace llvm {
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class LiveInterval;
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class LiveIntervals;
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class LiveRegMatrix;
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class MachineInstr;
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class MachineRegisterInfo;
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template<typename T> class SmallVectorImpl;
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class Spiller;
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class TargetRegisterInfo;
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class VirtRegMap;
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/// RegAllocBase provides the register allocation driver and interface that can
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/// be extended to add interesting heuristics.
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///
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/// Register allocators must override the selectOrSplit() method to implement
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/// live range splitting. They must also override enqueue/dequeue to provide an
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/// assignment order.
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class RegAllocBase {
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  virtual void anchor();
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protected:
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  const TargetRegisterInfo *TRI = nullptr;
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  MachineRegisterInfo *MRI = nullptr;
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  VirtRegMap *VRM = nullptr;
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  LiveIntervals *LIS = nullptr;
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  LiveRegMatrix *Matrix = nullptr;
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  RegisterClassInfo RegClassInfo;
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  /// Inst which is a def of an original reg and whose defs are already all
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  /// dead after remat is saved in DeadRemats. The deletion of such inst is
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  /// postponed till all the allocations are done, so its remat expr is
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  /// always available for the remat of all the siblings of the original reg.
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  SmallPtrSet<MachineInstr *, 32> DeadRemats;
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  RegAllocBase() = default;
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  virtual ~RegAllocBase() = default;
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  // A RegAlloc pass should call this before allocatePhysRegs.
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  void init(VirtRegMap &vrm, LiveIntervals &lis, LiveRegMatrix &mat);
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  // The top-level driver. The output is a VirtRegMap that us updated with
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  // physical register assignments.
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  void allocatePhysRegs();
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  // Include spiller post optimization and removing dead defs left because of
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  // rematerialization.
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  virtual void postOptimization();
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  // Get a temporary reference to a Spiller instance.
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  virtual Spiller &spiller() = 0;
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  /// enqueue - Add VirtReg to the priority queue of unassigned registers.
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  virtual void enqueue(LiveInterval *LI) = 0;
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  /// dequeue - Return the next unassigned register, or NULL.
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  virtual LiveInterval *dequeue() = 0;
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  // A RegAlloc pass should override this to provide the allocation heuristics.
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  // Each call must guarantee forward progess by returning an available PhysReg
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  // or new set of split live virtual registers. It is up to the splitter to
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  // converge quickly toward fully spilled live ranges.
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  virtual unsigned selectOrSplit(LiveInterval &VirtReg,
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                                 SmallVectorImpl<unsigned> &splitLVRs) = 0;
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  // Use this group name for NamedRegionTimer.
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  static const char TimerGroupName[];
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  static const char TimerGroupDescription[];
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  /// Method called when the allocator is about to remove a LiveInterval.
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  virtual void aboutToRemoveInterval(LiveInterval &LI) {}
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public:
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  /// VerifyEnabled - True when -verify-regalloc is given.
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  static bool VerifyEnabled;
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private:
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  void seedLiveRegs();
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};
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} // end namespace llvm
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#endif // LLVM_LIB_CODEGEN_REGALLOCBASE_H