/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/RegUsageInfoCollector.cpp
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1 | | //===-- RegUsageInfoCollector.cpp - Register Usage Information Collector --===// |
2 | | // |
3 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | | // See https://llvm.org/LICENSE.txt for license information. |
5 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | | // |
7 | | //===----------------------------------------------------------------------===// |
8 | | /// |
9 | | /// This pass is required to take advantage of the interprocedural register |
10 | | /// allocation infrastructure. |
11 | | /// |
12 | | /// This pass is simple MachineFunction pass which collects register usage |
13 | | /// details by iterating through each physical registers and checking |
14 | | /// MRI::isPhysRegUsed() then creates a RegMask based on this details. |
15 | | /// The pass then stores this RegMask in PhysicalRegisterUsageInfo.cpp |
16 | | /// |
17 | | //===----------------------------------------------------------------------===// |
18 | | |
19 | | #include "llvm/ADT/Statistic.h" |
20 | | #include "llvm/CodeGen/MachineBasicBlock.h" |
21 | | #include "llvm/CodeGen/MachineFunctionPass.h" |
22 | | #include "llvm/CodeGen/MachineInstr.h" |
23 | | #include "llvm/CodeGen/MachineOperand.h" |
24 | | #include "llvm/CodeGen/MachineRegisterInfo.h" |
25 | | #include "llvm/CodeGen/Passes.h" |
26 | | #include "llvm/CodeGen/RegisterUsageInfo.h" |
27 | | #include "llvm/Support/Debug.h" |
28 | | #include "llvm/Support/raw_ostream.h" |
29 | | #include "llvm/CodeGen/TargetFrameLowering.h" |
30 | | |
31 | | using namespace llvm; |
32 | | |
33 | | #define DEBUG_TYPE "ip-regalloc" |
34 | | |
35 | | STATISTIC(NumCSROpt, |
36 | | "Number of functions optimized for callee saved registers"); |
37 | | |
38 | | namespace { |
39 | | |
40 | | class RegUsageInfoCollector : public MachineFunctionPass { |
41 | | public: |
42 | 2.44k | RegUsageInfoCollector() : MachineFunctionPass(ID) { |
43 | 2.44k | PassRegistry &Registry = *PassRegistry::getPassRegistry(); |
44 | 2.44k | initializeRegUsageInfoCollectorPass(Registry); |
45 | 2.44k | } |
46 | | |
47 | 27.5k | StringRef getPassName() const override { |
48 | 27.5k | return "Register Usage Information Collector Pass"; |
49 | 27.5k | } |
50 | | |
51 | 2.40k | void getAnalysisUsage(AnalysisUsage &AU) const override { |
52 | 2.40k | AU.addRequired<PhysicalRegisterUsageInfo>(); |
53 | 2.40k | AU.setPreservesAll(); |
54 | 2.40k | MachineFunctionPass::getAnalysisUsage(AU); |
55 | 2.40k | } |
56 | | |
57 | | bool runOnMachineFunction(MachineFunction &MF) override; |
58 | | |
59 | | // Call determineCalleeSaves and then also set the bits for subregs and |
60 | | // fully saved superregs. |
61 | | static void computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF); |
62 | | |
63 | | static char ID; |
64 | | }; |
65 | | |
66 | | } // end of anonymous namespace |
67 | | |
68 | | char RegUsageInfoCollector::ID = 0; |
69 | | |
70 | 42.3k | INITIALIZE_PASS_BEGIN(RegUsageInfoCollector, "RegUsageInfoCollector", |
71 | 42.3k | "Register Usage Information Collector", false, false) |
72 | 42.3k | INITIALIZE_PASS_DEPENDENCY(PhysicalRegisterUsageInfo) |
73 | 42.3k | INITIALIZE_PASS_END(RegUsageInfoCollector, "RegUsageInfoCollector", |
74 | | "Register Usage Information Collector", false, false) |
75 | | |
76 | 2.44k | FunctionPass *llvm::createRegUsageInfoCollector() { |
77 | 2.44k | return new RegUsageInfoCollector(); |
78 | 2.44k | } |
79 | | |
80 | | // TODO: Move to hook somwehere? |
81 | | |
82 | | // Return true if it is useful to track the used registers for IPRA / no CSR |
83 | | // optimizations. This is not useful for entry points, and computing the |
84 | | // register usage information is expensive. |
85 | 25.1k | static bool isCallableFunction(const MachineFunction &MF) { |
86 | 25.1k | switch (MF.getFunction().getCallingConv()) { |
87 | 25.1k | case CallingConv::AMDGPU_VS: |
88 | 23.0k | case CallingConv::AMDGPU_GS: |
89 | 23.0k | case CallingConv::AMDGPU_PS: |
90 | 23.0k | case CallingConv::AMDGPU_CS: |
91 | 23.0k | case CallingConv::AMDGPU_HS: |
92 | 23.0k | case CallingConv::AMDGPU_ES: |
93 | 23.0k | case CallingConv::AMDGPU_LS: |
94 | 23.0k | case CallingConv::AMDGPU_KERNEL: |
95 | 23.0k | return false; |
96 | 23.0k | default: |
97 | 2.08k | return true; |
98 | 25.1k | } |
99 | 25.1k | } |
100 | | |
101 | 25.1k | bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) { |
102 | 25.1k | MachineRegisterInfo *MRI = &MF.getRegInfo(); |
103 | 25.1k | const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); |
104 | 25.1k | const LLVMTargetMachine &TM = MF.getTarget(); |
105 | 25.1k | |
106 | 25.1k | LLVM_DEBUG(dbgs() << " -------------------- " << getPassName() |
107 | 25.1k | << " -------------------- \nFunction Name : " |
108 | 25.1k | << MF.getName() << '\n'); |
109 | 25.1k | |
110 | 25.1k | // Analyzing the register usage may be expensive on some targets. |
111 | 25.1k | if (!isCallableFunction(MF)) { |
112 | 23.0k | LLVM_DEBUG(dbgs() << "Not analyzing non-callable function\n"); |
113 | 23.0k | return false; |
114 | 23.0k | } |
115 | 2.08k | |
116 | 2.08k | // If there are no callers, there's no point in computing more precise |
117 | 2.08k | // register usage here. |
118 | 2.08k | if (MF.getFunction().use_empty()) { |
119 | 2.01k | LLVM_DEBUG(dbgs() << "Not analyzing function with no callers\n"); |
120 | 2.01k | return false; |
121 | 2.01k | } |
122 | 63 | |
123 | 63 | std::vector<uint32_t> RegMask; |
124 | 63 | |
125 | 63 | // Compute the size of the bit vector to represent all the registers. |
126 | 63 | // The bit vector is broken into 32-bit chunks, thus takes the ceil of |
127 | 63 | // the number of registers divided by 32 for the size. |
128 | 63 | unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs()); |
129 | 63 | RegMask.resize(RegMaskSize, ~((uint32_t)0)); |
130 | 63 | |
131 | 63 | const Function &F = MF.getFunction(); |
132 | 63 | |
133 | 63 | PhysicalRegisterUsageInfo &PRUI = getAnalysis<PhysicalRegisterUsageInfo>(); |
134 | 63 | PRUI.setTargetMachine(TM); |
135 | 63 | |
136 | 63 | LLVM_DEBUG(dbgs() << "Clobbered Registers: "); |
137 | 63 | |
138 | 63 | BitVector SavedRegs; |
139 | 63 | computeCalleeSavedRegs(SavedRegs, MF); |
140 | 63 | |
141 | 63 | const BitVector &UsedPhysRegsMask = MRI->getUsedPhysRegsMask(); |
142 | 7.55k | auto SetRegAsDefined = [&RegMask] (unsigned Reg) { |
143 | 7.55k | RegMask[Reg / 32] &= ~(1u << Reg % 32); |
144 | 7.55k | }; |
145 | 63 | // Scan all the physical registers. When a register is defined in the current |
146 | 63 | // function set it and all the aliasing registers as defined in the regmask. |
147 | 63 | // FIXME: Rewrite to use regunits. |
148 | 190k | for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg190k ) { |
149 | 190k | // Don't count registers that are saved and restored. |
150 | 190k | if (SavedRegs.test(PReg)) |
151 | 81 | continue; |
152 | 190k | // If a register is defined by an instruction mark it as defined together |
153 | 190k | // with all it's unsaved aliases. |
154 | 190k | if (!MRI->def_empty(PReg)) { |
155 | 3.90k | for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI3.72k ) |
156 | 3.72k | if (!SavedRegs.test(*AI)) |
157 | 3.72k | SetRegAsDefined(*AI); |
158 | 179 | continue; |
159 | 179 | } |
160 | 189k | // If a register is in the UsedPhysRegsMask set then mark it as defined. |
161 | 189k | // All clobbered aliases will also be in the set, so we can skip setting |
162 | 189k | // as defined all the aliases here. |
163 | 189k | if (UsedPhysRegsMask.test(PReg)) |
164 | 3.82k | SetRegAsDefined(PReg); |
165 | 189k | } |
166 | 63 | |
167 | 63 | if (TargetFrameLowering::isSafeForNoCSROpt(F)) { |
168 | 1 | ++NumCSROpt; |
169 | 1 | LLVM_DEBUG(dbgs() << MF.getName() |
170 | 1 | << " function optimized for not having CSR.\n"); |
171 | 1 | } |
172 | 63 | |
173 | 63 | LLVM_DEBUG( |
174 | 63 | for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { |
175 | 63 | if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg)) |
176 | 63 | dbgs() << printReg(PReg, TRI) << " "; |
177 | 63 | } |
178 | 63 | |
179 | 63 | dbgs() << " \n----------------------------------------\n"; |
180 | 63 | ); |
181 | 63 | |
182 | 63 | PRUI.storeUpdateRegUsageInfo(F, RegMask); |
183 | 63 | |
184 | 63 | return false; |
185 | 63 | } |
186 | | |
187 | | void RegUsageInfoCollector:: |
188 | 63 | computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF) { |
189 | 63 | const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering(); |
190 | 63 | const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); |
191 | 63 | |
192 | 63 | // Target will return the set of registers that it saves/restores as needed. |
193 | 63 | SavedRegs.clear(); |
194 | 63 | TFI.determineCalleeSaves(MF, SavedRegs); |
195 | 63 | if (SavedRegs.none()) |
196 | 58 | return; |
197 | 5 | |
198 | 5 | // Insert subregs. |
199 | 5 | const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF); |
200 | 386 | for (unsigned i = 0; CSRegs[i]; ++i381 ) { |
201 | 381 | MCPhysReg Reg = CSRegs[i]; |
202 | 381 | if (SavedRegs.test(Reg)) { |
203 | 31 | // Save subregisters |
204 | 80 | for (MCSubRegIterator SR(Reg, &TRI); SR.isValid(); ++SR49 ) |
205 | 49 | SavedRegs.set(*SR); |
206 | 31 | } |
207 | 381 | } |
208 | 5 | } |