Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/RegisterClassInfo.cpp
Line
Count
Source
1
//===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements the RegisterClassInfo class which provides dynamic
10
// information about target register classes. Callee-saved vs. caller-saved and
11
// reserved registers depend on calling conventions and other dynamic
12
// information, so some things cannot be determined statically.
13
//
14
//===----------------------------------------------------------------------===//
15
16
#include "llvm/CodeGen/RegisterClassInfo.h"
17
#include "llvm/ADT/ArrayRef.h"
18
#include "llvm/ADT/BitVector.h"
19
#include "llvm/ADT/SmallVector.h"
20
#include "llvm/CodeGen/MachineFunction.h"
21
#include "llvm/CodeGen/MachineRegisterInfo.h"
22
#include "llvm/CodeGen/TargetFrameLowering.h"
23
#include "llvm/CodeGen/TargetRegisterInfo.h"
24
#include "llvm/CodeGen/TargetSubtargetInfo.h"
25
#include "llvm/MC/MCRegisterInfo.h"
26
#include "llvm/Support/CommandLine.h"
27
#include "llvm/Support/Debug.h"
28
#include "llvm/Support/raw_ostream.h"
29
#include <algorithm>
30
#include <cassert>
31
#include <cstdint>
32
33
using namespace llvm;
34
35
#define DEBUG_TYPE "regalloc"
36
37
static cl::opt<unsigned>
38
StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
39
         cl::desc("Limit all regclasses to N registers"));
40
41
240k
RegisterClassInfo::RegisterClassInfo() = default;
42
43
2.66M
void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
44
2.66M
  bool Update = false;
45
2.66M
  MF = &mf;
46
2.66M
47
2.66M
  // Allocate new array the first time we see a new target.
48
2.66M
  if (MF->getSubtarget().getRegisterInfo() != TRI) {
49
184k
    TRI = MF->getSubtarget().getRegisterInfo();
50
184k
    RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
51
184k
    Update = true;
52
184k
  }
53
2.66M
54
2.66M
  // Does this MF have different CSRs?
55
2.66M
  assert(TRI && "no register info set");
56
2.66M
57
2.66M
  // Get the callee saved registers.
58
2.66M
  const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs();
59
2.66M
  if (Update || 
CSR != CalleeSavedRegs2.48M
) {
60
194k
    // Build a CSRAlias map. Every CSR alias saves the last
61
194k
    // overlapping CSR.
62
194k
    CalleeSavedAliases.resize(TRI->getNumRegs(), 0);
63
3.63M
    for (const MCPhysReg *I = CSR; *I; 
++I3.44M
)
64
76.7M
      
for (MCRegAliasIterator AI(*I, TRI, true); 3.44M
AI.isValid();
++AI73.2M
)
65
73.2M
        CalleeSavedAliases[*AI] = *I;
66
194k
67
194k
    Update = true;
68
194k
  }
69
2.66M
  CalleeSavedRegs = CSR;
70
2.66M
71
2.66M
  // Different reserved registers?
72
2.66M
  const BitVector &RR = MF->getRegInfo().getReservedRegs();
73
2.66M
  if (Reserved.size() != RR.size() || 
RR != Reserved2.48M
) {
74
202k
    Update = true;
75
202k
    Reserved = RR;
76
202k
  }
77
2.66M
78
2.66M
  // Invalidate cached information from previous function.
79
2.66M
  if (Update) {
80
206k
    unsigned NumPSets = TRI->getNumRegPressureSets();
81
206k
    PSetLimits.reset(new unsigned[NumPSets]);
82
206k
    std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
83
206k
    ++Tag;
84
206k
  }
85
2.66M
}
86
87
/// compute - Compute the preferred allocation order for RC with reserved
88
/// registers filtered out. Volatile registers come first followed by CSR
89
/// aliases ordered according to the CSR order specified by the target.
90
1.61M
void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
91
1.61M
  assert(RC && "no register class given");
92
1.61M
  RCInfo &RCI = RegClass[RC->getID()];
93
1.61M
  auto &STI = MF->getSubtarget();
94
1.61M
95
1.61M
  // Raw register count, including all reserved regs.
96
1.61M
  unsigned NumRegs = RC->getNumRegs();
97
1.61M
98
1.61M
  if (!RCI.Order)
99
605k
    RCI.Order.reset(new MCPhysReg[NumRegs]);
100
1.61M
101
1.61M
  unsigned N = 0;
102
1.61M
  SmallVector<MCPhysReg, 16> CSRAlias;
103
1.61M
  unsigned MinCost = 0xff;
104
1.61M
  unsigned LastCost = ~0u;
105
1.61M
  unsigned LastCostChange = 0;
106
1.61M
107
1.61M
  // FIXME: Once targets reserve registers instead of removing them from the
108
1.61M
  // allocation order, we can simply use begin/end here.
109
1.61M
  ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
110
28.7M
  for (unsigned i = 0; i != RawOrder.size(); 
++i27.1M
) {
111
27.1M
    unsigned PhysReg = RawOrder[i];
112
27.1M
    // Remove reserved registers from the allocation order.
113
27.1M
    if (Reserved.test(PhysReg))
114
3.19M
      continue;
115
23.9M
    unsigned Cost = TRI->getCostPerUse(PhysReg);
116
23.9M
    MinCost = std::min(MinCost, Cost);
117
23.9M
118
23.9M
    if (CalleeSavedAliases[PhysReg] &&
119
23.9M
        
!STI.ignoreCSRForAllocationOrder(*MF, PhysReg)5.17M
)
120
5.14M
      // PhysReg aliases a CSR, save it for later.
121
5.14M
      CSRAlias.push_back(PhysReg);
122
18.7M
    else {
123
18.7M
      if (Cost != LastCost)
124
1.53M
        LastCostChange = N;
125
18.7M
      RCI.Order[N++] = PhysReg;
126
18.7M
      LastCost = Cost;
127
18.7M
    }
128
23.9M
  }
129
1.61M
  RCI.NumRegs = N + CSRAlias.size();
130
1.61M
  assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
131
1.61M
132
1.61M
  // CSR aliases go after the volatile registers, preserve the target's order.
133
6.76M
  for (unsigned i = 0, e = CSRAlias.size(); i != e; 
++i5.14M
) {
134
5.14M
    unsigned PhysReg = CSRAlias[i];
135
5.14M
    unsigned Cost = TRI->getCostPerUse(PhysReg);
136
5.14M
    if (Cost != LastCost)
137
243k
      LastCostChange = N;
138
5.14M
    RCI.Order[N++] = PhysReg;
139
5.14M
    LastCost = Cost;
140
5.14M
  }
141
1.61M
142
1.61M
  // Register allocator stress test.  Clip register class to N registers.
143
1.61M
  if (StressRA && 
RCI.NumRegs > StressRA837
)
144
630
    RCI.NumRegs = StressRA;
145
1.61M
146
1.61M
  // Check if RC is a proper sub-class.
147
1.61M
  if (const TargetRegisterClass *Super =
148
1.61M
          TRI->getLargestLegalSuperClass(RC, *MF))
149
1.61M
    if (Super != RC && 
getNumAllocatableRegs(Super) > RCI.NumRegs123k
)
150
106k
      RCI.ProperSubClass = true;
151
1.61M
152
1.61M
  RCI.MinCost = uint8_t(MinCost);
153
1.61M
  RCI.LastCostChange = LastCostChange;
154
1.61M
155
1.61M
  LLVM_DEBUG({
156
1.61M
    dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = [";
157
1.61M
    for (unsigned I = 0; I != RCI.NumRegs; ++I)
158
1.61M
      dbgs() << ' ' << printReg(RCI.Order[I], TRI);
159
1.61M
    dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
160
1.61M
  });
161
1.61M
162
1.61M
  // RCI is now up-to-date.
163
1.61M
  RCI.Tag = Tag;
164
1.61M
}
165
166
/// This is not accurate because two overlapping register sets may have some
167
/// nonoverlapping reserved registers. However, computing the allocation order
168
/// for all register classes would be too expensive.
169
1.33M
unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
170
1.33M
  const TargetRegisterClass *RC = nullptr;
171
1.33M
  unsigned NumRCUnits = 0;
172
145M
  for (const TargetRegisterClass *C : TRI->regclasses()) {
173
145M
    const int *PSetID = TRI->getRegClassPressureSets(C);
174
2.76G
    for (; *PSetID != -1; 
++PSetID2.61G
) {
175
2.63G
      if ((unsigned)*PSetID == Idx)
176
22.6M
        break;
177
2.63G
    }
178
145M
    if (*PSetID == -1)
179
123M
      continue;
180
22.6M
181
22.6M
    // Found a register class that counts against this pressure set.
182
22.6M
    // For efficiency, only compute the set order for the largest set.
183
22.6M
    unsigned NUnits = TRI->getRegClassWeight(C).WeightLimit;
184
22.6M
    if (!RC || 
NUnits > NumRCUnits21.2M
) {
185
3.08M
      RC = C;
186
3.08M
      NumRCUnits = NUnits;
187
3.08M
    }
188
22.6M
  }
189
1.33M
  compute(RC);
190
1.33M
  unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC);
191
1.33M
  return TRI->getRegPressureSetLimit(*MF, Idx) -
192
1.33M
         TRI->getRegClassWeight(RC).RegWeight * NReserved;
193
1.33M
}