Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
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Source (jump to first uncovered line)
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//===-- FunctionLoweringInfo.cpp ------------------------------------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This implements routines for translating functions from LLVM IR into
10
// Machine IR.
11
//
12
//===----------------------------------------------------------------------===//
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14
#include "llvm/CodeGen/FunctionLoweringInfo.h"
15
#include "llvm/CodeGen/Analysis.h"
16
#include "llvm/CodeGen/MachineFrameInfo.h"
17
#include "llvm/CodeGen/MachineFunction.h"
18
#include "llvm/CodeGen/MachineInstrBuilder.h"
19
#include "llvm/CodeGen/MachineRegisterInfo.h"
20
#include "llvm/CodeGen/TargetFrameLowering.h"
21
#include "llvm/CodeGen/TargetInstrInfo.h"
22
#include "llvm/CodeGen/TargetLowering.h"
23
#include "llvm/CodeGen/TargetRegisterInfo.h"
24
#include "llvm/CodeGen/TargetSubtargetInfo.h"
25
#include "llvm/CodeGen/WasmEHFuncInfo.h"
26
#include "llvm/CodeGen/WinEHFuncInfo.h"
27
#include "llvm/IR/DataLayout.h"
28
#include "llvm/IR/DerivedTypes.h"
29
#include "llvm/IR/Function.h"
30
#include "llvm/IR/Instructions.h"
31
#include "llvm/IR/IntrinsicInst.h"
32
#include "llvm/IR/LLVMContext.h"
33
#include "llvm/IR/Module.h"
34
#include "llvm/Support/Debug.h"
35
#include "llvm/Support/ErrorHandling.h"
36
#include "llvm/Support/MathExtras.h"
37
#include "llvm/Support/raw_ostream.h"
38
#include "llvm/Target/TargetOptions.h"
39
#include <algorithm>
40
using namespace llvm;
41
42
#define DEBUG_TYPE "function-lowering-info"
43
44
/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
45
/// PHI nodes or outside of the basic block that defines it, or used by a
46
/// switch or atomic instruction, which may expand to multiple basic blocks.
47
7.12M
static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
48
7.12M
  if (I->use_empty()) 
return false2.15M
;
49
4.96M
  if (isa<PHINode>(I)) 
return true236k
;
50
4.73M
  const BasicBlock *BB = I->getParent();
51
4.73M
  for (const User *U : I->users())
52
5.43M
    if (cast<Instruction>(U)->getParent() != BB || 
isa<PHINode>(U)4.87M
)
53
628k
      return true;
54
4.73M
55
4.73M
  
return false4.10M
;
56
4.73M
}
57
58
7.12M
static ISD::NodeType getPreferredExtendForValue(const Value *V) {
59
7.12M
  // For the users of the source value being used for compare instruction, if
60
7.12M
  // the number of signed predicate is greater than unsigned predicate, we
61
7.12M
  // prefer to use SIGN_EXTEND.
62
7.12M
  //
63
7.12M
  // With this optimization, we would be able to reduce some redundant sign or
64
7.12M
  // zero extension instruction, and eventually more machine CSE opportunities
65
7.12M
  // can be exposed.
66
7.12M
  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
67
7.12M
  unsigned NumOfSigned = 0, NumOfUnsigned = 0;
68
7.12M
  for (const User *U : V->users()) {
69
7.01M
    if (const auto *CI = dyn_cast<CmpInst>(U)) {
70
662k
      NumOfSigned += CI->isSigned();
71
662k
      NumOfUnsigned += CI->isUnsigned();
72
662k
    }
73
7.01M
  }
74
7.12M
  if (NumOfSigned > NumOfUnsigned)
75
92.1k
    ExtendKind = ISD::SIGN_EXTEND;
76
7.12M
77
7.12M
  return ExtendKind;
78
7.12M
}
79
80
void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
81
278k
                               SelectionDAG *DAG) {
82
278k
  Fn = &fn;
83
278k
  MF = &mf;
84
278k
  TLI = MF->getSubtarget().getTargetLowering();
85
278k
  RegInfo = &MF->getRegInfo();
86
278k
  const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
87
278k
  unsigned StackAlign = TFI->getStackAlignment();
88
278k
  DA = DAG->getDivergenceAnalysis();
89
278k
90
278k
  // Check whether the function can return without sret-demotion.
91
278k
  SmallVector<ISD::OutputArg, 4> Outs;
92
278k
  CallingConv::ID CC = Fn->getCallingConv();
93
278k
94
278k
  GetReturnInfo(CC, Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI,
95
278k
                mf.getDataLayout());
96
278k
  CanLowerReturn =
97
278k
      TLI->CanLowerReturn(CC, *MF, Fn->isVarArg(), Outs, Fn->getContext());
98
278k
99
278k
  // If this personality uses funclets, we need to do a bit more work.
100
278k
  DenseMap<const AllocaInst *, TinyPtrVector<int *>> CatchObjects;
101
278k
  EHPersonality Personality = classifyEHPersonality(
102
278k
      Fn->hasPersonalityFn() ? 
Fn->getPersonalityFn()825
:
nullptr277k
);
103
278k
  if (isFuncletEHPersonality(Personality)) {
104
107
    // Calculate state numbers if we haven't already.
105
107
    WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
106
107
    if (Personality == EHPersonality::MSVC_CXX)
107
66
      calculateWinCXXEHStateNumbers(&fn, EHInfo);
108
41
    else if (isAsynchronousEHPersonality(Personality))
109
34
      calculateSEHStateNumbers(&fn, EHInfo);
110
7
    else if (Personality == EHPersonality::CoreCLR)
111
7
      calculateClrEHStateNumbers(&fn, EHInfo);
112
107
113
107
    // Map all BB references in the WinEH data to MBBs.
114
107
    for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
115
74
      for (WinEHHandlerType &H : TBME.HandlerArray) {
116
74
        if (const AllocaInst *AI = H.CatchObj.Alloca)
117
11
          CatchObjects.insert({AI, {}}).first->second.push_back(
118
11
              &H.CatchObj.FrameIndex);
119
63
        else
120
63
          H.CatchObj.FrameIndex = INT_MAX;
121
74
      }
122
67
    }
123
107
  }
124
278k
  if (Personality == EHPersonality::Wasm_CXX) {
125
41
    WasmEHFuncInfo &EHInfo = *MF->getWasmEHFuncInfo();
126
41
    calculateWasmEHInfo(&fn, EHInfo);
127
41
  }
128
278k
129
278k
  // Initialize the mapping of values to registers.  This is only set up for
130
278k
  // instruction values that are used outside of the block that defines
131
278k
  // them.
132
1.20M
  for (const BasicBlock &BB : *Fn) {
133
7.12M
    for (const Instruction &I : BB) {
134
7.12M
      if (const AllocaInst *AI = dyn_cast<AllocaInst>(&I)) {
135
48.4k
        Type *Ty = AI->getAllocatedType();
136
48.4k
        unsigned Align =
137
48.4k
          std::max((unsigned)MF->getDataLayout().getPrefTypeAlignment(Ty),
138
48.4k
                   AI->getAlignment());
139
48.4k
140
48.4k
        // Static allocas can be folded into the initial stack frame
141
48.4k
        // adjustment. For targets that don't realign the stack, don't
142
48.4k
        // do this if there is an extra alignment requirement.
143
48.4k
        if (AI->isStaticAlloca() &&
144
48.4k
            
(47.6k
TFI->isStackRealignable()47.6k
||
(Align <= StackAlign)282
)) {
145
47.6k
          const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
146
47.6k
          uint64_t TySize = MF->getDataLayout().getTypeAllocSize(Ty);
147
47.6k
148
47.6k
          TySize *= CUI->getZExtValue();   // Get total allocated size.
149
47.6k
          if (TySize == 0) 
TySize = 111
; // Don't create zero-sized stack objects.
150
47.6k
          int FrameIndex = INT_MAX;
151
47.6k
          auto Iter = CatchObjects.find(AI);
152
47.6k
          if (Iter != CatchObjects.end() && 
TLI->needsFixedCatchObjects()10
) {
153
5
            FrameIndex = MF->getFrameInfo().CreateFixedObject(
154
5
                TySize, 0, /*IsImmutable=*/false, /*isAliased=*/true);
155
5
            MF->getFrameInfo().setObjectAlignment(FrameIndex, Align);
156
47.5k
          } else {
157
47.5k
            FrameIndex =
158
47.5k
                MF->getFrameInfo().CreateStackObject(TySize, Align, false, AI);
159
47.5k
          }
160
47.6k
161
47.6k
          StaticAllocaMap[AI] = FrameIndex;
162
47.6k
          // Update the catch handler information.
163
47.6k
          if (Iter != CatchObjects.end()) {
164
10
            for (int *CatchObjPtr : Iter->second)
165
11
              *CatchObjPtr = FrameIndex;
166
10
          }
167
47.6k
        } else {
168
803
          // FIXME: Overaligned static allocas should be grouped into
169
803
          // a single dynamic allocation instead of using a separate
170
803
          // stack allocation for each one.
171
803
          if (Align <= StackAlign)
172
713
            Align = 0;
173
803
          // Inform the Frame Information that we have variable-sized objects.
174
803
          MF->getFrameInfo().CreateVariableSizedObject(Align ? 
Align90
:
1713
, AI);
175
803
        }
176
48.4k
      }
177
7.12M
178
7.12M
      // Look for inline asm that clobbers the SP register.
179
7.12M
      if (isa<CallInst>(I) || 
isa<InvokeInst>(I)6.37M
) {
180
751k
        ImmutableCallSite CS(&I);
181
751k
        if (isa<InlineAsm>(CS.getCalledValue())) {
182
20.5k
          unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
183
20.5k
          const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
184
20.5k
          std::vector<TargetLowering::AsmOperandInfo> Ops =
185
20.5k
              TLI->ParseConstraints(Fn->getParent()->getDataLayout(), TRI, CS);
186
102k
          for (TargetLowering::AsmOperandInfo &Op : Ops) {
187
102k
            if (Op.Type == InlineAsm::isClobber) {
188
92.3k
              // Clobbers don't have SDValue operands, hence SDValue().
189
92.3k
              TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
190
92.3k
              std::pair<unsigned, const TargetRegisterClass *> PhysReg =
191
92.3k
                  TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode,
192
92.3k
                                                    Op.ConstraintVT);
193
92.3k
              if (PhysReg.first == SP)
194
73
                MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
195
92.3k
            }
196
102k
          }
197
20.5k
        }
198
751k
      }
199
7.12M
200
7.12M
      // Look for calls to the @llvm.va_start intrinsic. We can omit some
201
7.12M
      // prologue boilerplate for variadic functions that don't examine their
202
7.12M
      // arguments.
203
7.12M
      if (const auto *II = dyn_cast<IntrinsicInst>(&I)) {
204
287k
        if (II->getIntrinsicID() == Intrinsic::vastart)
205
532
          MF->getFrameInfo().setHasVAStart(true);
206
287k
      }
207
7.12M
208
7.12M
      // If we have a musttail call in a variadic function, we need to ensure we
209
7.12M
      // forward implicit register parameters.
210
7.12M
      if (const auto *CI = dyn_cast<CallInst>(&I)) {
211
744k
        if (CI->isMustTailCall() && 
Fn->isVarArg()92
)
212
43
          MF->getFrameInfo().setHasMustTailInVarArgFunc(true);
213
744k
      }
214
7.12M
215
7.12M
      // Mark values used outside their block as exported, by allocating
216
7.12M
      // a virtual register for them.
217
7.12M
      if (isUsedOutsideOfDefiningBlock(&I))
218
865k
        if (!isa<AllocaInst>(I) || 
!StaticAllocaMap.count(cast<AllocaInst>(&I))33.7k
)
219
831k
          InitializeRegForValue(&I);
220
7.12M
221
7.12M
      // Decide the preferred extend type for a value.
222
7.12M
      PreferredExtendType[&I] = getPreferredExtendForValue(&I);
223
7.12M
    }
224
1.20M
  }
225
278k
226
278k
  // Create an initial MachineBasicBlock for each LLVM BasicBlock in F.  This
227
278k
  // also creates the initial PHI MachineInstrs, though none of the input
228
278k
  // operands are populated.
229
1.20M
  for (const BasicBlock &BB : *Fn) {
230
1.20M
    // Don't create MachineBasicBlocks for imaginary EH pad blocks. These blocks
231
1.20M
    // are really data, and no instructions can live here.
232
1.20M
    if (BB.isEHPad()) {
233
3.94k
      const Instruction *PadInst = BB.getFirstNonPHI();
234
3.94k
      // If this is a non-landingpad EH pad, mark this function as using
235
3.94k
      // funclets.
236
3.94k
      // FIXME: SEH catchpads do not create EH scope/funclets, so we could avoid
237
3.94k
      // setting this in such cases in order to improve frame layout.
238
3.94k
      if (!isa<LandingPadInst>(PadInst)) {
239
394
        MF->setHasEHScopes(true);
240
394
        MF->setHasEHFunclets(true);
241
394
        MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
242
394
      }
243
3.94k
      if (isa<CatchSwitchInst>(PadInst)) {
244
160
        assert(&*BB.begin() == PadInst &&
245
160
               "WinEHPrepare failed to remove PHIs from imaginary BBs");
246
160
        continue;
247
160
      }
248
3.78k
      if (isa<FuncletPadInst>(PadInst))
249
3.78k
        assert(&*BB.begin() == PadInst && "WinEHPrepare failed to demote PHIs");
250
3.78k
    }
251
1.20M
252
1.20M
    MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(&BB);
253
1.20M
    MBBMap[&BB] = MBB;
254
1.20M
    MF->push_back(MBB);
255
1.20M
256
1.20M
    // Transfer the address-taken flag. This is necessary because there could
257
1.20M
    // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
258
1.20M
    // the first one should be marked.
259
1.20M
    if (BB.hasAddressTaken())
260
310
      MBB->setHasAddressTaken();
261
1.20M
262
1.20M
    // Mark landing pad blocks.
263
1.20M
    if (BB.isEHPad())
264
3.78k
      MBB->setIsEHPad();
265
1.20M
266
1.20M
    // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
267
1.20M
    // appropriate.
268
1.20M
    for (const PHINode &PN : BB.phis()) {
269
241k
      if (PN.use_empty())
270
4.53k
        continue;
271
236k
272
236k
      // Skip empty types
273
236k
      if (PN.getType()->isEmptyTy())
274
2
        continue;
275
236k
276
236k
      DebugLoc DL = PN.getDebugLoc();
277
236k
      unsigned PHIReg = ValueMap[&PN];
278
236k
      assert(PHIReg && "PHI node does not have an assigned virtual register!");
279
236k
280
236k
      SmallVector<EVT, 4> ValueVTs;
281
236k
      ComputeValueVTs(*TLI, MF->getDataLayout(), PN.getType(), ValueVTs);
282
237k
      for (EVT VT : ValueVTs) {
283
237k
        unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
284
237k
        const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
285
480k
        for (unsigned i = 0; i != NumRegisters; 
++i243k
)
286
243k
          BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
287
237k
        PHIReg += NumRegisters;
288
237k
      }
289
236k
    }
290
1.20M
  }
291
278k
292
278k
  if (isFuncletEHPersonality(Personality)) {
293
107
    WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
294
107
295
107
    // Map all BB references in the WinEH data to MBBs.
296
107
    for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
297
74
      for (WinEHHandlerType &H : TBME.HandlerArray) {
298
74
        if (H.Handler)
299
74
          H.Handler = MBBMap[H.Handler.get<const BasicBlock *>()];
300
74
      }
301
67
    }
302
107
    for (CxxUnwindMapEntry &UME : EHInfo.CxxUnwindMap)
303
158
      if (UME.Cleanup)
304
24
        UME.Cleanup = MBBMap[UME.Cleanup.get<const BasicBlock *>()];
305
107
    for (SEHUnwindMapEntry &UME : EHInfo.SEHUnwindMap) {
306
47
      const auto *BB = UME.Handler.get<const BasicBlock *>();
307
47
      UME.Handler = MBBMap[BB];
308
47
    }
309
107
    for (ClrEHUnwindMapEntry &CME : EHInfo.ClrEHUnwindMap) {
310
19
      const auto *BB = CME.Handler.get<const BasicBlock *>();
311
19
      CME.Handler = MBBMap[BB];
312
19
    }
313
107
  }
314
277k
315
277k
  else if (Personality == EHPersonality::Wasm_CXX) {
316
41
    WasmEHFuncInfo &EHInfo = *MF->getWasmEHFuncInfo();
317
41
    // Map all BB references in the WinEH data to MBBs.
318
41
    DenseMap<BBOrMBB, BBOrMBB> NewMap;
319
41
    for (auto &KV : EHInfo.EHPadUnwindMap) {
320
3
      const auto *Src = KV.first.get<const BasicBlock *>();
321
3
      const auto *Dst = KV.second.get<const BasicBlock *>();
322
3
      NewMap[MBBMap[Src]] = MBBMap[Dst];
323
3
    }
324
41
    EHInfo.EHPadUnwindMap = std::move(NewMap);
325
41
  }
326
278k
}
327
328
/// clear - Clear out all the function-specific state. This returns this
329
/// FunctionLoweringInfo to an empty state, ready to be used for a
330
/// different function.
331
515k
void FunctionLoweringInfo::clear() {
332
515k
  MBBMap.clear();
333
515k
  ValueMap.clear();
334
515k
  VirtReg2Value.clear();
335
515k
  StaticAllocaMap.clear();
336
515k
  LiveOutRegInfo.clear();
337
515k
  VisitedBBs.clear();
338
515k
  ArgDbgValues.clear();
339
515k
  DescribedArgs.clear();
340
515k
  ByValArgFrameIndexMap.clear();
341
515k
  RegFixups.clear();
342
515k
  RegsWithFixups.clear();
343
515k
  StatepointStackSlots.clear();
344
515k
  StatepointSpillMaps.clear();
345
515k
  PreferredExtendType.clear();
346
515k
}
347
348
/// CreateReg - Allocate a single virtual register for the given type.
349
1.09M
unsigned FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) {
350
1.09M
  return RegInfo->createVirtualRegister(
351
1.09M
      MF->getSubtarget().getTargetLowering()->getRegClassFor(VT, isDivergent));
352
1.09M
}
353
354
/// CreateRegs - Allocate the appropriate number of virtual registers of
355
/// the correctly promoted or expanded types.  Assign these registers
356
/// consecutive vreg numbers and return the first assigned number.
357
///
358
/// In the case that the given value has struct or array type, this function
359
/// will assign registers for each member or element.
360
///
361
1.06M
unsigned FunctionLoweringInfo::CreateRegs(Type *Ty, bool isDivergent) {
362
1.06M
  const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
363
1.06M
364
1.06M
  SmallVector<EVT, 4> ValueVTs;
365
1.06M
  ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
366
1.06M
367
1.06M
  unsigned FirstReg = 0;
368
2.13M
  for (unsigned Value = 0, e = ValueVTs.size(); Value != e; 
++Value1.06M
) {
369
1.06M
    EVT ValueVT = ValueVTs[Value];
370
1.06M
    MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
371
1.06M
372
1.06M
    unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
373
2.16M
    for (unsigned i = 0; i != NumRegs; 
++i1.09M
) {
374
1.09M
      unsigned R = CreateReg(RegisterVT, isDivergent);
375
1.09M
      if (!FirstReg) 
FirstReg = R1.06M
;
376
1.09M
    }
377
1.06M
  }
378
1.06M
  return FirstReg;
379
1.06M
}
380
381
1.06M
unsigned FunctionLoweringInfo::CreateRegs(const Value *V) {
382
1.06M
  return CreateRegs(V->getType(), DA && 
!TLI->requiresUniformRegister(*MF, V)12.2k
&&
383
1.06M
                                      
DA->isDivergent(V)12.2k
);
384
1.06M
}
385
386
/// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
387
/// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
388
/// the register's LiveOutInfo is for a smaller bit width, it is extended to
389
/// the larger bit width by zero extension. The bit width must be no smaller
390
/// than the LiveOutInfo's existing bit width.
391
const FunctionLoweringInfo::LiveOutInfo *
392
122k
FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
393
122k
  if (!LiveOutRegInfo.inBounds(Reg))
394
408
    return nullptr;
395
122k
396
122k
  LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
397
122k
  if (!LOI->IsValid)
398
8.14k
    return nullptr;
399
114k
400
114k
  if (BitWidth > LOI->Known.getBitWidth()) {
401
61.2k
    LOI->NumSignBits = 1;
402
61.2k
    LOI->Known = LOI->Known.zext(BitWidth, false /* => any extend */);
403
61.2k
  }
404
114k
405
114k
  return LOI;
406
114k
}
407
408
/// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
409
/// register based on the LiveOutInfo of its operands.
410
117k
void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
411
117k
  Type *Ty = PN->getType();
412
117k
  if (!Ty->isIntegerTy() || 
Ty->isVectorTy()77.6k
)
413
40.1k
    return;
414
77.6k
415
77.6k
  SmallVector<EVT, 1> ValueVTs;
416
77.6k
  ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
417
77.6k
  assert(ValueVTs.size() == 1 &&
418
77.6k
         "PHIs with non-vector integer types should have a single VT.");
419
77.6k
  EVT IntVT = ValueVTs[0];
420
77.6k
421
77.6k
  if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
422
856
    return;
423
76.8k
  IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
424
76.8k
  unsigned BitWidth = IntVT.getSizeInBits();
425
76.8k
426
76.8k
  unsigned DestReg = ValueMap[PN];
427
76.8k
  if (!TargetRegisterInfo::isVirtualRegister(DestReg))
428
4.49k
    return;
429
72.3k
  LiveOutRegInfo.grow(DestReg);
430
72.3k
  LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
431
72.3k
432
72.3k
  Value *V = PN->getIncomingValue(0);
433
72.3k
  if (isa<UndefValue>(V) || 
isa<ConstantExpr>(V)71.8k
) {
434
455
    DestLOI.NumSignBits = 1;
435
455
    DestLOI.Known = KnownBits(BitWidth);
436
455
    return;
437
455
  }
438
71.8k
439
71.8k
  if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
440
19.8k
    APInt Val = CI->getValue().zextOrTrunc(BitWidth);
441
19.8k
    DestLOI.NumSignBits = Val.getNumSignBits();
442
19.8k
    DestLOI.Known.Zero = ~Val;
443
19.8k
    DestLOI.Known.One = Val;
444
52.0k
  } else {
445
52.0k
    assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
446
52.0k
                                "CopyToReg node was created.");
447
52.0k
    unsigned SrcReg = ValueMap[V];
448
52.0k
    if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
449
0
      DestLOI.IsValid = false;
450
0
      return;
451
0
    }
452
52.0k
    const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
453
52.0k
    if (!SrcLOI) {
454
3.60k
      DestLOI.IsValid = false;
455
3.60k
      return;
456
3.60k
    }
457
48.4k
    DestLOI = *SrcLOI;
458
48.4k
  }
459
71.8k
460
71.8k
  assert(DestLOI.Known.Zero.getBitWidth() == BitWidth &&
461
68.2k
         DestLOI.Known.One.getBitWidth() == BitWidth &&
462
68.2k
         "Masks should have the same bit width as the type.");
463
68.2k
464
212k
  for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; 
++i144k
) {
465
149k
    Value *V = PN->getIncomingValue(i);
466
149k
    if (isa<UndefValue>(V) || 
isa<ConstantExpr>(V)149k
) {
467
166
      DestLOI.NumSignBits = 1;
468
166
      DestLOI.Known = KnownBits(BitWidth);
469
166
      return;
470
166
    }
471
149k
472
149k
    if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
473
78.4k
      APInt Val = CI->getValue().zextOrTrunc(BitWidth);
474
78.4k
      DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
475
78.4k
      DestLOI.Known.Zero &= ~Val;
476
78.4k
      DestLOI.Known.One &= Val;
477
78.4k
      continue;
478
78.4k
    }
479
70.8k
480
70.8k
    assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
481
70.8k
                                "its CopyToReg node was created.");
482
70.8k
    unsigned SrcReg = ValueMap[V];
483
70.8k
    if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
484
0
      DestLOI.IsValid = false;
485
0
      return;
486
0
    }
487
70.8k
    const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
488
70.8k
    if (!SrcLOI) {
489
4.94k
      DestLOI.IsValid = false;
490
4.94k
      return;
491
4.94k
    }
492
65.9k
    DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
493
65.9k
    DestLOI.Known.Zero &= SrcLOI->Known.Zero;
494
65.9k
    DestLOI.Known.One &= SrcLOI->Known.One;
495
65.9k
  }
496
68.2k
}
497
498
/// setArgumentFrameIndex - Record frame index for the byval
499
/// argument. This overrides previous frame index entry for this argument,
500
/// if any.
501
void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
502
3.02k
                                                 int FI) {
503
3.02k
  ByValArgFrameIndexMap[A] = FI;
504
3.02k
}
505
506
/// getArgumentFrameIndex - Get frame index for the byval argument.
507
/// If the argument does not have any assigned frame index then 0 is
508
/// returned.
509
559
int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
510
559
  auto I = ByValArgFrameIndexMap.find(A);
511
559
  if (I != ByValArgFrameIndexMap.end())
512
56
    return I->second;
513
503
  LLVM_DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
514
503
  return INT_MAX;
515
503
}
516
517
unsigned FunctionLoweringInfo::getCatchPadExceptionPointerVReg(
518
14
    const Value *CPI, const TargetRegisterClass *RC) {
519
14
  MachineRegisterInfo &MRI = MF->getRegInfo();
520
14
  auto I = CatchPadExceptionPointers.insert({CPI, 0});
521
14
  unsigned &VReg = I.first->second;
522
14
  if (I.second)
523
7
    VReg = MRI.createVirtualRegister(RC);
524
14
  assert(VReg && "null vreg in exception pointer table!");
525
14
  return VReg;
526
14
}
527
528
const Value *
529
8.04k
FunctionLoweringInfo::getValueFromVirtualReg(unsigned Vreg) {
530
8.04k
  if (VirtReg2Value.empty()) {
531
1.21k
    SmallVector<EVT, 4> ValueVTs;
532
10.8k
    for (auto &P : ValueMap) {
533
10.8k
      ValueVTs.clear();
534
10.8k
      ComputeValueVTs(*TLI, Fn->getParent()->getDataLayout(),
535
10.8k
                      P.first->getType(), ValueVTs);
536
10.8k
      unsigned Reg = P.second;
537
11.0k
      for (EVT VT : ValueVTs) {
538
11.0k
        unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
539
22.1k
        for (unsigned i = 0, e = NumRegisters; i != e; 
++i11.1k
)
540
11.1k
          VirtReg2Value[Reg++] = P.first;
541
11.0k
      }
542
10.8k
    }
543
1.21k
  }
544
8.04k
  return VirtReg2Value.lookup(Vreg);
545
8.04k
}