Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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Source (jump to first uncovered line)
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//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This implements the Emit routines for the SelectionDAG class, which creates
10
// MachineInstrs based on the decisions of the SelectionDAG instruction
11
// selection.
12
//
13
//===----------------------------------------------------------------------===//
14
15
#include "InstrEmitter.h"
16
#include "SDNodeDbgValue.h"
17
#include "llvm/ADT/Statistic.h"
18
#include "llvm/CodeGen/MachineConstantPool.h"
19
#include "llvm/CodeGen/MachineFunction.h"
20
#include "llvm/CodeGen/MachineInstrBuilder.h"
21
#include "llvm/CodeGen/MachineRegisterInfo.h"
22
#include "llvm/CodeGen/StackMaps.h"
23
#include "llvm/CodeGen/TargetInstrInfo.h"
24
#include "llvm/CodeGen/TargetLowering.h"
25
#include "llvm/CodeGen/TargetSubtargetInfo.h"
26
#include "llvm/IR/DataLayout.h"
27
#include "llvm/IR/DebugInfo.h"
28
#include "llvm/Support/Debug.h"
29
#include "llvm/Support/ErrorHandling.h"
30
#include "llvm/Support/MathExtras.h"
31
using namespace llvm;
32
33
#define DEBUG_TYPE "instr-emitter"
34
35
/// MinRCSize - Smallest register class we allow when constraining virtual
36
/// registers.  If satisfying all register class constraints would require
37
/// using a smaller register class, emit a COPY to a new virtual register
38
/// instead.
39
const unsigned MinRCSize = 4;
40
41
/// CountResults - The results of target nodes have register or immediate
42
/// operands first, then an optional chain, and optional glue operands (which do
43
/// not go into the resulting MachineInstr).
44
14.0M
unsigned InstrEmitter::CountResults(SDNode *Node) {
45
14.0M
  unsigned N = Node->getNumValues();
46
17.6M
  while (N && 
Node->getValueType(N - 1) == MVT::Glue17.6M
)
47
3.58M
    --N;
48
14.0M
  if (N && 
Node->getValueType(N - 1) == MVT::Other14.0M
)
49
7.52M
    --N;    // Skip over chain result.
50
14.0M
  return N;
51
14.0M
}
52
53
/// countOperands - The inputs to target nodes have any actual inputs first,
54
/// followed by an optional chain operand, then an optional glue operand.
55
/// Compute the number of actual operands that will go into the resulting
56
/// MachineInstr.
57
///
58
/// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
59
/// the chain and glue. These operands may be implicit on the machine instr.
60
static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
61
7.33M
                              unsigned &NumImpUses) {
62
7.33M
  unsigned N = Node->getNumOperands();
63
8.74M
  while (N && 
Node->getOperand(N - 1).getValueType() == MVT::Glue8.68M
)
64
1.41M
    --N;
65
7.33M
  if (N && 
Node->getOperand(N - 1).getValueType() == MVT::Other7.26M
)
66
4.43M
    --N; // Ignore chain if it exists.
67
7.33M
68
7.33M
  // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
69
7.33M
  NumImpUses = N - NumExpUses;
70
8.95M
  for (unsigned I = N; I > NumExpUses; 
--I1.62M
) {
71
1.62M
    if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
72
455k
      continue;
73
1.17M
    if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
74
1.17M
      if (TargetRegisterInfo::isPhysicalRegister(RN->getReg()))
75
1.16M
        continue;
76
9.20k
    NumImpUses = N - I;
77
9.20k
    break;
78
9.20k
  }
79
7.33M
80
7.33M
  return N;
81
7.33M
}
82
83
/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
84
/// implicit physical register output.
85
void InstrEmitter::
86
EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
87
2.53M
                unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
88
2.53M
  unsigned VRBase = 0;
89
2.53M
  if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
90
1.78M
    // Just use the input register directly!
91
1.78M
    SDValue Op(Node, ResNo);
92
1.78M
    if (IsClone)
93
0
      VRBaseMap.erase(Op);
94
1.78M
    bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
95
1.78M
    (void)isNew; // Silence compiler warning.
96
1.78M
    assert(isNew && "Node emitted out of order - early");
97
1.78M
    return;
98
1.78M
  }
99
753k
100
753k
  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
101
753k
  // the CopyToReg'd destination register instead of creating a new vreg.
102
753k
  bool MatchReg = true;
103
753k
  const TargetRegisterClass *UseRC = nullptr;
104
753k
  MVT VT = Node->getSimpleValueType(ResNo);
105
753k
106
753k
  // Stick to the preferred register classes for legal types.
107
753k
  if (TLI->isTypeLegal(VT))
108
753k
    UseRC = TLI->getRegClassFor(VT, Node->isDivergent());
109
753k
110
753k
  if (!IsClone && 
!IsCloned752k
)
111
1.09M
    
for (SDNode *User : Node->uses())751k
{
112
1.09M
      bool Match = true;
113
1.09M
      if (User->getOpcode() == ISD::CopyToReg &&
114
1.09M
          
User->getOperand(2).getNode() == Node622k
&&
115
1.09M
          
User->getOperand(2).getResNo() == ResNo609k
) {
116
602k
        unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
117
602k
        if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
118
115k
          VRBase = DestReg;
119
115k
          Match = false;
120
487k
        } else if (DestReg != SrcReg)
121
106k
          Match = false;
122
602k
      } else {
123
2.42M
        for (unsigned i = 0, e = User->getNumOperands(); i != e; 
++i1.92M
) {
124
1.92M
          SDValue Op = User->getOperand(i);
125
1.92M
          if (Op.getNode() != Node || 
Op.getResNo() != ResNo557k
)
126
1.59M
            continue;
127
328k
          MVT VT = Node->getSimpleValueType(Op.getResNo());
128
328k
          if (VT == MVT::Other || VT == MVT::Glue)
129
0
            continue;
130
328k
          Match = false;
131
328k
          if (User->isMachineOpcode()) {
132
328k
            const MCInstrDesc &II = TII->get(User->getMachineOpcode());
133
328k
            const TargetRegisterClass *RC = nullptr;
134
328k
            if (i+II.getNumDefs() < II.getNumOperands()) {
135
327k
              RC = TRI->getAllocatableClass(
136
327k
                TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
137
327k
            }
138
328k
            if (!UseRC)
139
0
              UseRC = RC;
140
328k
            else if (RC) {
141
324k
              const TargetRegisterClass *ComRC =
142
324k
                TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy);
143
324k
              // If multiple uses expect disjoint register classes, we emit
144
324k
              // copies in AddRegisterOperand.
145
324k
              if (ComRC)
146
324k
                UseRC = ComRC;
147
324k
            }
148
328k
          }
149
328k
        }
150
497k
      }
151
1.09M
      MatchReg &= Match;
152
1.09M
      if (VRBase)
153
115k
        break;
154
1.09M
    }
155
753k
156
753k
  const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
157
753k
  SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
158
753k
159
753k
  // Figure out the register class to create for the destreg.
160
753k
  if (VRBase) {
161
115k
    DstRC = MRI->getRegClass(VRBase);
162
637k
  } else if (UseRC) {
163
637k
    assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
164
637k
           "Incompatible phys register def and uses!");
165
637k
    DstRC = UseRC;
166
637k
  } else {
167
0
    DstRC = TLI->getRegClassFor(VT, Node->isDivergent());
168
0
  }
169
753k
170
753k
  // If all uses are reading from the src physical register and copying the
171
753k
  // register is either impossible or very expensive, then don't create a copy.
172
753k
  if (MatchReg && 
SrcRC->getCopyCost() < 0415k
) {
173
353k
    VRBase = SrcReg;
174
399k
  } else {
175
399k
    // Create the reg, emit the copy.
176
399k
    VRBase = MRI->createVirtualRegister(DstRC);
177
399k
    BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
178
399k
            VRBase).addReg(SrcReg);
179
399k
  }
180
753k
181
753k
  SDValue Op(Node, ResNo);
182
753k
  if (IsClone)
183
625
    VRBaseMap.erase(Op);
184
753k
  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
185
753k
  (void)isNew; // Silence compiler warning.
186
753k
  assert(isNew && "Node emitted out of order - early");
187
753k
}
188
189
void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
190
                                       MachineInstrBuilder &MIB,
191
                                       const MCInstrDesc &II,
192
                                       bool IsClone, bool IsCloned,
193
4.85M
                                       DenseMap<SDValue, unsigned> &VRBaseMap) {
194
4.85M
  assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
195
4.85M
         "IMPLICIT_DEF should have been handled as a special case elsewhere!");
196
4.85M
197
4.85M
  unsigned NumResults = CountResults(Node);
198
8.52M
  for (unsigned i = 0; i < II.getNumDefs(); 
++i3.67M
) {
199
3.67M
    // If the specific node value is only used by a CopyToReg and the dest reg
200
3.67M
    // is a vreg in the same register class, use the CopyToReg'd destination
201
3.67M
    // register instead of creating a new vreg.
202
3.67M
    unsigned VRBase = 0;
203
3.67M
    const TargetRegisterClass *RC =
204
3.67M
      TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
205
3.67M
    // Always let the value type influence the used register class. The
206
3.67M
    // constraints on the instruction may be too lax to represent the value
207
3.67M
    // type correctly. For example, a 64-bit float (X86::FR64) can't live in
208
3.67M
    // the 32-bit float super-class (X86::FR32).
209
3.67M
    if (i < NumResults && 
TLI->isTypeLegal(Node->getSimpleValueType(i))3.66M
) {
210
3.66M
      const TargetRegisterClass *VTRC = TLI->getRegClassFor(
211
3.66M
          Node->getSimpleValueType(i),
212
3.66M
          (Node->isDivergent() || 
(3.62M
RC3.62M
&&
TRI->isDivergentRegClass(RC)3.61M
)));
213
3.66M
      if (RC)
214
3.65M
        VTRC = TRI->getCommonSubClass(RC, VTRC);
215
3.66M
      if (VTRC)
216
3.58M
        RC = VTRC;
217
3.66M
    }
218
3.67M
219
3.67M
    if (II.OpInfo[i].isOptionalDef()) {
220
7.13k
      // Optional def must be a physical register.
221
7.13k
      VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
222
7.13k
      assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
223
7.13k
      MIB.addReg(VRBase, RegState::Define);
224
7.13k
    }
225
3.67M
226
3.67M
    if (!VRBase && 
!IsClone3.66M
&&
!IsCloned3.66M
)
227
5.12M
      
for (SDNode *User : Node->uses())3.66M
{
228
5.12M
        if (User->getOpcode() == ISD::CopyToReg &&
229
5.12M
            
User->getOperand(2).getNode() == Node1.51M
&&
230
5.12M
            
User->getOperand(2).getResNo() == i1.51M
) {
231
1.24M
          unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
232
1.24M
          if (TargetRegisterInfo::isVirtualRegister(Reg)) {
233
599k
            const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
234
599k
            if (RegRC == RC) {
235
213k
              VRBase = Reg;
236
213k
              MIB.addReg(VRBase, RegState::Define);
237
213k
              break;
238
213k
            }
239
599k
          }
240
1.24M
        }
241
5.12M
      }
242
3.67M
243
3.67M
    // Create the result registers for this node and add the result regs to
244
3.67M
    // the machine instruction.
245
3.67M
    if (VRBase == 0) {
246
3.45M
      assert(RC && "Isn't a register operand!");
247
3.45M
      VRBase = MRI->createVirtualRegister(RC);
248
3.45M
      MIB.addReg(VRBase, RegState::Define);
249
3.45M
    }
250
3.67M
251
3.67M
    // If this def corresponds to a result of the SDNode insert the VRBase into
252
3.67M
    // the lookup map.
253
3.67M
    if (i < NumResults) {
254
3.66M
      SDValue Op(Node, i);
255
3.66M
      if (IsClone)
256
319
        VRBaseMap.erase(Op);
257
3.66M
      bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
258
3.66M
      (void)isNew; // Silence compiler warning.
259
3.66M
      assert(isNew && "Node emitted out of order - early");
260
3.66M
    }
261
3.67M
  }
262
4.85M
}
263
264
/// getVR - Return the virtual register corresponding to the specified result
265
/// of the specified node.
266
unsigned InstrEmitter::getVR(SDValue Op,
267
8.88M
                             DenseMap<SDValue, unsigned> &VRBaseMap) {
268
8.88M
  if (Op.isMachineOpcode() &&
269
8.88M
      
Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF5.86M
) {
270
115k
    // Add an IMPLICIT_DEF instruction before every use.
271
115k
    // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
272
115k
    // does not include operand register class info.
273
115k
    const TargetRegisterClass *RC = TLI->getRegClassFor(
274
115k
        Op.getSimpleValueType(), Op.getNode()->isDivergent());
275
115k
    unsigned VReg = MRI->createVirtualRegister(RC);
276
115k
    BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
277
115k
            TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
278
115k
    return VReg;
279
115k
  }
280
8.77M
281
8.77M
  DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
282
8.77M
  assert(I != VRBaseMap.end() && "Node emitted out of order - late");
283
8.77M
  return I->second;
284
8.77M
}
285
286
287
/// AddRegisterOperand - Add the specified register as an operand to the
288
/// specified machine instr. Insert register copies if the register is
289
/// not in the required register class.
290
void
291
InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
292
                                 SDValue Op,
293
                                 unsigned IIOpNum,
294
                                 const MCInstrDesc *II,
295
                                 DenseMap<SDValue, unsigned> &VRBaseMap,
296
5.94M
                                 bool IsDebug, bool IsClone, bool IsCloned) {
297
5.94M
  assert(Op.getValueType() != MVT::Other &&
298
5.94M
         Op.getValueType() != MVT::Glue &&
299
5.94M
         "Chain and glue operands should occur at end of operand list!");
300
5.94M
  // Get/emit the operand.
301
5.94M
  unsigned VReg = getVR(Op, VRBaseMap);
302
5.94M
303
5.94M
  const MCInstrDesc &MCID = MIB->getDesc();
304
5.94M
  bool isOptDef = IIOpNum < MCID.getNumOperands() &&
305
5.94M
    
MCID.OpInfo[IIOpNum].isOptionalDef()5.74M
;
306
5.94M
307
5.94M
  // If the instruction requires a register in a different class, create
308
5.94M
  // a new virtual register and copy the value into it, but first attempt to
309
5.94M
  // shrink VReg's register class within reason.  For example, if VReg == GR32
310
5.94M
  // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
311
5.94M
  if (II) {
312
5.57M
    const TargetRegisterClass *OpRC = nullptr;
313
5.57M
    if (IIOpNum < II->getNumOperands())
314
5.36M
      OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
315
5.57M
316
5.57M
    if (OpRC) {
317
5.36M
      const TargetRegisterClass *ConstrainedRC
318
5.36M
        = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
319
5.36M
      if (!ConstrainedRC) {
320
74.9k
        OpRC = TRI->getAllocatableClass(OpRC);
321
74.9k
        assert(OpRC && "Constraints cannot be fulfilled for allocation");
322
74.9k
        unsigned NewVReg = MRI->createVirtualRegister(OpRC);
323
74.9k
        BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
324
74.9k
                TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
325
74.9k
        VReg = NewVReg;
326
5.28M
      } else {
327
5.28M
        assert(ConstrainedRC->isAllocatable() &&
328
5.28M
           "Constraining an allocatable VReg produced an unallocatable class?");
329
5.28M
      }
330
5.36M
    }
331
5.57M
  }
332
5.94M
333
5.94M
  // If this value has only one use, that use is a kill. This is a
334
5.94M
  // conservative approximation. InstrEmitter does trivial coalescing
335
5.94M
  // with CopyFromReg nodes, so don't emit kill flags for them.
336
5.94M
  // Avoid kill flags on Schedule cloned nodes, since there will be
337
5.94M
  // multiple uses.
338
5.94M
  // Tied operands are never killed, so we need to check that. And that
339
5.94M
  // means we need to determine the index of the operand.
340
5.94M
  bool isKill = Op.hasOneUse() &&
341
5.94M
                
Op.getNode()->getOpcode() != ISD::CopyFromReg3.50M
&&
342
5.94M
                
!IsDebug2.30M
&&
343
5.94M
                
!(2.30M
IsClone2.30M
||
IsCloned2.30M
);
344
5.94M
  if (isKill) {
345
2.30M
    unsigned Idx = MIB->getNumOperands();
346
2.85M
    while (Idx > 0 &&
347
2.85M
           
MIB->getOperand(Idx-1).isReg()2.55M
&&
348
2.85M
           
MIB->getOperand(Idx-1).isImplicit()2.18M
)
349
543k
      --Idx;
350
2.30M
    bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
351
2.30M
    if (isTied)
352
214k
      isKill = false;
353
2.30M
  }
354
5.94M
355
5.94M
  MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
356
5.94M
             getDebugRegState(IsDebug));
357
5.94M
}
358
359
/// AddOperand - Add the specified operand to the specified machine instr.  II
360
/// specifies the instruction information for the node, and IIOpNum is the
361
/// operand number (in the II) that we are adding.
362
void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
363
                              SDValue Op,
364
                              unsigned IIOpNum,
365
                              const MCInstrDesc *II,
366
                              DenseMap<SDValue, unsigned> &VRBaseMap,
367
20.5M
                              bool IsDebug, bool IsClone, bool IsCloned) {
368
20.5M
  if (Op.isMachineOpcode()) {
369
3.63M
    AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
370
3.63M
                       IsDebug, IsClone, IsCloned);
371
16.8M
  } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
372
8.04M
    MIB.addImm(C->getSExtValue());
373
8.85M
  } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
374
303
    MIB.addFPImm(F->getConstantFPValue());
375
8.85M
  } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
376
3.37M
    unsigned VReg = R->getReg();
377
3.37M
    MVT OpVT = Op.getSimpleValueType();
378
3.37M
    const TargetRegisterClass *IIRC =
379
3.37M
        II ? 
TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))3.36M
380
3.37M
           : 
nullptr5.33k
;
381
3.37M
    const TargetRegisterClass *OpRC =
382
3.37M
        TLI->isTypeLegal(OpVT)
383
3.37M
            ? TLI->getRegClassFor(OpVT,
384
3.37M
                                  Op.getNode()->isDivergent() ||
385
3.37M
                                      (IIRC && 
TRI->isDivergentRegClass(IIRC)1.42M
))
386
3.37M
            : 
nullptr94
;
387
3.37M
388
3.37M
    if (OpRC && 
IIRC3.37M
&&
OpRC != IIRC1.42M
&&
389
3.37M
        
TargetRegisterInfo::isVirtualRegister(VReg)1.23M
) {
390
3.59k
      unsigned NewVReg = MRI->createVirtualRegister(IIRC);
391
3.59k
      BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
392
3.59k
               TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
393
3.59k
      VReg = NewVReg;
394
3.59k
    }
395
3.37M
    // Turn additional physreg operands into implicit uses on non-variadic
396
3.37M
    // instructions. This is used by call and return instructions passing
397
3.37M
    // arguments in registers.
398
3.37M
    bool Imp = II && 
(3.36M
IIOpNum >= II->getNumOperands()3.36M
&&
!II->isVariadic()1.16M
);
399
3.37M
    MIB.addReg(VReg, getImplRegState(Imp));
400
5.47M
  } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
401
455k
    MIB.addRegMask(RM->getRegMask());
402
5.02M
  } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
403
986k
    MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
404
986k
                         TGA->getTargetFlags());
405
4.03M
  } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
406
1.23M
    MIB.addMBB(BBNode->getBasicBlock());
407
2.80M
  } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
408
355k
    MIB.addFrameIndex(FI->getIndex());
409
2.44M
  } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
410
5.85k
    MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
411
2.44M
  } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
412
103k
    int Offset = CP->getOffset();
413
103k
    unsigned Align = CP->getAlignment();
414
103k
    Type *Type = CP->getType();
415
103k
    // MachineConstantPool wants an explicit alignment.
416
103k
    if (Align == 0) {
417
0
      Align = MF->getDataLayout().getPrefTypeAlignment(Type);
418
0
      if (Align == 0) {
419
0
        // Alignment of vector types.  FIXME!
420
0
        Align = MF->getDataLayout().getTypeAllocSize(Type);
421
0
      }
422
0
    }
423
103k
424
103k
    unsigned Idx;
425
103k
    MachineConstantPool *MCP = MF->getConstantPool();
426
103k
    if (CP->isMachineConstantPoolEntry())
427
252
      Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
428
102k
    else
429
102k
      Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
430
103k
    MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
431
2.33M
  } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
432
21.7k
    MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
433
2.31M
  } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
434
102
    MIB.addSym(SymNode->getMCSymbol());
435
2.31M
  } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
436
163
    MIB.addBlockAddress(BA->getBlockAddress(),
437
163
                        BA->getOffset(),
438
163
                        BA->getTargetFlags());
439
2.31M
  } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
440
0
    MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
441
2.31M
  } else {
442
2.31M
    assert(Op.getValueType() != MVT::Other &&
443
2.31M
           Op.getValueType() != MVT::Glue &&
444
2.31M
           "Chain and glue operands should occur at end of operand list!");
445
2.31M
    AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
446
2.31M
                       IsDebug, IsClone, IsCloned);
447
2.31M
  }
448
20.5M
}
449
450
unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
451
294k
                                          MVT VT, bool isDivergent, const DebugLoc &DL) {
452
294k
  const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
453
294k
  const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
454
294k
455
294k
  // RC is a sub-class of VRC that supports SubIdx.  Try to constrain VReg
456
294k
  // within reason.
457
294k
  if (RC && 
RC != VRC294k
)
458
6.79k
    RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
459
294k
460
294k
  // VReg has been adjusted.  It can be used with SubIdx operands now.
461
294k
  if (RC)
462
294k
    return VReg;
463
9
464
9
  // VReg couldn't be reasonably constrained.  Emit a COPY to a new virtual
465
9
  // register instead.
466
9
  RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
467
9
  assert(RC && "No legal register class for VT supports that SubIdx");
468
9
  unsigned NewReg = MRI->createVirtualRegister(RC);
469
9
  BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
470
9
    .addReg(VReg);
471
9
  return NewReg;
472
9
}
473
474
/// EmitSubregNode - Generate machine code for subreg nodes.
475
///
476
void InstrEmitter::EmitSubregNode(SDNode *Node,
477
                                  DenseMap<SDValue, unsigned> &VRBaseMap,
478
579k
                                  bool IsClone, bool IsCloned) {
479
579k
  unsigned VRBase = 0;
480
579k
  unsigned Opc = Node->getMachineOpcode();
481
579k
482
579k
  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
483
579k
  // the CopyToReg'd destination register instead of creating a new vreg.
484
704k
  for (SDNode *User : Node->uses()) {
485
704k
    if (User->getOpcode() == ISD::CopyToReg &&
486
704k
        
User->getOperand(2).getNode() == Node166k
) {
487
166k
      unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
488
166k
      if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
489
96.3k
        VRBase = DestReg;
490
96.3k
        break;
491
96.3k
      }
492
166k
    }
493
704k
  }
494
579k
495
579k
  if (Opc == TargetOpcode::EXTRACT_SUBREG) {
496
294k
    // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub.  There are no
497
294k
    // constraints on the %dst register, COPY can target all legal register
498
294k
    // classes.
499
294k
    unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
500
294k
    const TargetRegisterClass *TRC =
501
294k
      TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
502
294k
503
294k
    unsigned Reg;
504
294k
    MachineInstr *DefMI;
505
294k
    RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(0));
506
294k
    if (R && 
TargetRegisterInfo::isPhysicalRegister(R->getReg())1
) {
507
0
      Reg = R->getReg();
508
0
      DefMI = nullptr;
509
294k
    } else {
510
294k
      Reg = R ? 
R->getReg()1
:
getVR(Node->getOperand(0), VRBaseMap)294k
;
511
294k
      DefMI = MRI->getVRegDef(Reg);
512
294k
    }
513
294k
514
294k
    unsigned SrcReg, DstReg, DefSubIdx;
515
294k
    if (DefMI &&
516
294k
        
TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx)265k
&&
517
294k
        
SubIdx == DefSubIdx125
&&
518
294k
        
TRC == MRI->getRegClass(SrcReg)64
) {
519
62
      // Optimize these:
520
62
      // r1025 = s/zext r1024, 4
521
62
      // r1026 = extract_subreg r1025, 4
522
62
      // to a copy
523
62
      // r1026 = copy r1024
524
62
      VRBase = MRI->createVirtualRegister(TRC);
525
62
      BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
526
62
              TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
527
62
      MRI->clearKillFlags(SrcReg);
528
294k
    } else {
529
294k
      // Reg may not support a SubIdx sub-register, and we may need to
530
294k
      // constrain its register class or issue a COPY to a compatible register
531
294k
      // class.
532
294k
      if (TargetRegisterInfo::isVirtualRegister(Reg))
533
294k
        Reg = ConstrainForSubReg(Reg, SubIdx,
534
294k
                                 Node->getOperand(0).getSimpleValueType(),
535
294k
                                 Node->isDivergent(), Node->getDebugLoc());
536
294k
      // Create the destreg if it is missing.
537
294k
      if (VRBase == 0)
538
271k
        VRBase = MRI->createVirtualRegister(TRC);
539
294k
540
294k
      // Create the extract_subreg machine instruction.
541
294k
      MachineInstrBuilder CopyMI =
542
294k
          BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
543
294k
                  TII->get(TargetOpcode::COPY), VRBase);
544
294k
      if (TargetRegisterInfo::isVirtualRegister(Reg))
545
294k
        CopyMI.addReg(Reg, 0, SubIdx);
546
0
      else
547
0
        CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
548
294k
    }
549
294k
  } else 
if (284k
Opc == TargetOpcode::INSERT_SUBREG284k
||
550
284k
             
Opc == TargetOpcode::SUBREG_TO_REG192k
) {
551
284k
    SDValue N0 = Node->getOperand(0);
552
284k
    SDValue N1 = Node->getOperand(1);
553
284k
    SDValue N2 = Node->getOperand(2);
554
284k
    unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
555
284k
556
284k
    // Figure out the register class to create for the destreg.  It should be
557
284k
    // the largest legal register class supporting SubIdx sub-registers.
558
284k
    // RegisterCoalescer will constrain it further if it decides to eliminate
559
284k
    // the INSERT_SUBREG instruction.
560
284k
    //
561
284k
    //   %dst = INSERT_SUBREG %src, %sub, SubIdx
562
284k
    //
563
284k
    // is lowered by TwoAddressInstructionPass to:
564
284k
    //
565
284k
    //   %dst = COPY %src
566
284k
    //   %dst:SubIdx = COPY %sub
567
284k
    //
568
284k
    // There is no constraint on the %src register class.
569
284k
    //
570
284k
    const TargetRegisterClass *SRC =
571
284k
        TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
572
284k
    SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
573
284k
    assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
574
284k
575
284k
    if (VRBase == 0 || 
!SRC->hasSubClassEq(MRI->getRegClass(VRBase))73.5k
)
576
211k
      VRBase = MRI->createVirtualRegister(SRC);
577
284k
578
284k
    // Create the insert_subreg or subreg_to_reg machine instruction.
579
284k
    MachineInstrBuilder MIB =
580
284k
      BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
581
284k
582
284k
    // If creating a subreg_to_reg, then the first input operand
583
284k
    // is an implicit value immediate, otherwise it's a register
584
284k
    if (Opc == TargetOpcode::SUBREG_TO_REG) {
585
192k
      const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
586
192k
      MIB.addImm(SD->getZExtValue());
587
192k
    } else
588
92.5k
      AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
589
92.5k
                 IsClone, IsCloned);
590
284k
    // Add the subregister being inserted
591
284k
    AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
592
284k
               IsClone, IsCloned);
593
284k
    MIB.addImm(SubIdx);
594
284k
    MBB->insert(InsertPos, MIB);
595
284k
  } else
596
284k
    
llvm_unreachable0
("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
597
579k
598
579k
  SDValue Op(Node, 0);
599
579k
  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
600
579k
  (void)isNew; // Silence compiler warning.
601
579k
  assert(isNew && "Node emitted out of order - early");
602
579k
}
603
604
/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
605
/// COPY_TO_REGCLASS is just a normal copy, except that the destination
606
/// register is constrained to be in a particular register class.
607
///
608
void
609
InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
610
62.0k
                                     DenseMap<SDValue, unsigned> &VRBaseMap) {
611
62.0k
  unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
612
62.0k
613
62.0k
  // Create the new VReg in the destination class and emit a copy.
614
62.0k
  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
615
62.0k
  const TargetRegisterClass *DstRC =
616
62.0k
    TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
617
62.0k
  unsigned NewVReg = MRI->createVirtualRegister(DstRC);
618
62.0k
  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
619
62.0k
    NewVReg).addReg(VReg);
620
62.0k
621
62.0k
  SDValue Op(Node, 0);
622
62.0k
  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
623
62.0k
  (void)isNew; // Silence compiler warning.
624
62.0k
  assert(isNew && "Node emitted out of order - early");
625
62.0k
}
626
627
/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
628
///
629
void InstrEmitter::EmitRegSequence(SDNode *Node,
630
                                  DenseMap<SDValue, unsigned> &VRBaseMap,
631
70.9k
                                  bool IsClone, bool IsCloned) {
632
70.9k
  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
633
70.9k
  const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
634
70.9k
  unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
635
70.9k
  const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
636
70.9k
  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
637
70.9k
  unsigned NumOps = Node->getNumOperands();
638
70.9k
  // If the input pattern has a chain, then the root of the corresponding
639
70.9k
  // output pattern will get a chain as well. This can happen to be a
640
70.9k
  // REG_SEQUENCE (which is not "guarded" by countOperands/CountResults).
641
70.9k
  if (NumOps && Node->getOperand(NumOps-1).getValueType() == MVT::Other)
642
0
    --NumOps; // Ignore chain if it exists.
643
70.9k
644
70.9k
  assert((NumOps & 1) == 1 &&
645
70.9k
         "REG_SEQUENCE must have an odd number of operands!");
646
468k
  for (unsigned i = 1; i != NumOps; 
++i397k
) {
647
397k
    SDValue Op = Node->getOperand(i);
648
397k
    if ((i & 1) == 0) {
649
198k
      RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
650
198k
      // Skip physical registers as they don't have a vreg to get and we'll
651
198k
      // insert copies for them in TwoAddressInstructionPass anyway.
652
198k
      if (!R || 
!TargetRegisterInfo::isPhysicalRegister(R->getReg())1.30k
) {
653
197k
        unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
654
197k
        unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
655
197k
        const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
656
197k
        const TargetRegisterClass *SRC =
657
197k
        TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
658
197k
        if (SRC && 
SRC != RC182k
) {
659
5.50k
          MRI->setRegClass(NewVReg, SRC);
660
5.50k
          RC = SRC;
661
5.50k
        }
662
197k
      }
663
198k
    }
664
397k
    AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
665
397k
               IsClone, IsCloned);
666
397k
  }
667
70.9k
668
70.9k
  MBB->insert(InsertPos, MIB);
669
70.9k
  SDValue Op(Node, 0);
670
70.9k
  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
671
70.9k
  (void)isNew; // Silence compiler warning.
672
70.9k
  assert(isNew && "Node emitted out of order - early");
673
70.9k
}
674
675
/// EmitDbgValue - Generate machine instruction for a dbg_value node.
676
///
677
MachineInstr *
678
InstrEmitter::EmitDbgValue(SDDbgValue *SD,
679
4.68k
                           DenseMap<SDValue, unsigned> &VRBaseMap) {
680
4.68k
  MDNode *Var = SD->getVariable();
681
4.68k
  MDNode *Expr = SD->getExpression();
682
4.68k
  DebugLoc DL = SD->getDebugLoc();
683
4.68k
  assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
684
4.68k
         "Expected inlined-at fields to agree");
685
4.68k
686
4.68k
  SD->setIsEmitted();
687
4.68k
688
4.68k
  if (SD->isInvalidated()) {
689
40
    // An invalidated SDNode must generate an undef DBG_VALUE: although the
690
40
    // original value is no longer computed, earlier DBG_VALUEs live ranges
691
40
    // must not leak into later code.
692
40
    auto MIB = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE));
693
40
    MIB.addReg(0U);
694
40
    MIB.addReg(0U, RegState::Debug);
695
40
    MIB.addMetadata(Var);
696
40
    MIB.addMetadata(Expr);
697
40
    return &*MIB;
698
40
  }
699
4.64k
700
4.64k
  if (SD->getKind() == SDDbgValue::FRAMEIX) {
701
61
    // Stack address; this needs to be lowered in target-dependent fashion.
702
61
    // EmitTargetCodeForFrameDebugValue is responsible for allocation.
703
61
    auto FrameMI = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
704
61
                       .addFrameIndex(SD->getFrameIx());
705
61
    if (SD->isIndirect())
706
5
      // Push [fi + 0] onto the DIExpression stack.
707
5
      FrameMI.addImm(0);
708
56
    else
709
56
      // Push fi onto the DIExpression stack.
710
56
      FrameMI.addReg(0);
711
61
    return FrameMI.addMetadata(Var).addMetadata(Expr);
712
61
  }
713
4.58k
  // Otherwise, we're going to create an instruction here.
714
4.58k
  const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
715
4.58k
  MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
716
4.58k
  if (SD->getKind() == SDDbgValue::SDNODE) {
717
344
    SDNode *Node = SD->getSDNode();
718
344
    SDValue Op = SDValue(Node, SD->getResNo());
719
344
    // It's possible we replaced this SDNode with other(s) and therefore
720
344
    // didn't generate code for it.  It's better to catch these cases where
721
344
    // they happen and transfer the debug info, but trying to guarantee that
722
344
    // in all cases would be very fragile; this is a safeguard for any
723
344
    // that were missed.
724
344
    DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
725
344
    if (I==VRBaseMap.end())
726
1
      MIB.addReg(0U);       // undef
727
343
    else
728
343
      AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
729
343
                 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
730
4.23k
  } else if (SD->getKind() == SDDbgValue::VREG) {
731
52
    MIB.addReg(SD->getVReg(), RegState::Debug);
732
4.18k
  } else if (SD->getKind() == SDDbgValue::CONST) {
733
4.18k
    const Value *V = SD->getConst();
734
4.18k
    if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
735
4.13k
      if (CI->getBitWidth() > 64)
736
1
        MIB.addCImm(CI);
737
4.12k
      else
738
4.12k
        MIB.addImm(CI->getSExtValue());
739
4.13k
    } else 
if (const ConstantFP *57
CF57
= dyn_cast<ConstantFP>(V)) {
740
8
      MIB.addFPImm(CF);
741
49
    } else if (isa<ConstantPointerNull>(V)) {
742
12
      // Note: This assumes that all nullptr constants are zero-valued.
743
12
      MIB.addImm(0);
744
37
    } else {
745
37
      // Could be an Undef.  In any case insert an Undef so we can see what we
746
37
      // dropped.
747
37
      MIB.addReg(0U);
748
37
    }
749
4.18k
  } else {
750
0
    // Insert an Undef so we can see what we dropped.
751
0
    MIB.addReg(0U);
752
0
  }
753
4.58k
754
4.58k
  // Indirect addressing is indicated by an Imm as the second parameter.
755
4.58k
  if (SD->isIndirect())
756
10
    MIB.addImm(0U);
757
4.57k
  else
758
4.57k
    MIB.addReg(0U, RegState::Debug);
759
4.58k
760
4.58k
  MIB.addMetadata(Var);
761
4.58k
  MIB.addMetadata(Expr);
762
4.58k
763
4.58k
  return &*MIB;
764
4.58k
}
765
766
MachineInstr *
767
4
InstrEmitter::EmitDbgLabel(SDDbgLabel *SD) {
768
4
  MDNode *Label = SD->getLabel();
769
4
  DebugLoc DL = SD->getDebugLoc();
770
4
  assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&
771
4
         "Expected inlined-at fields to agree");
772
4
773
4
  const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL);
774
4
  MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
775
4
  MIB.addMetadata(Label);
776
4
777
4
  return &*MIB;
778
4
}
779
780
/// EmitMachineNode - Generate machine code for a target-specific node and
781
/// needed dependencies.
782
///
783
void InstrEmitter::
784
EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
785
8.10M
                DenseMap<SDValue, unsigned> &VRBaseMap) {
786
8.10M
  unsigned Opc = Node->getMachineOpcode();
787
8.10M
788
8.10M
  // Handle subreg insert/extract specially
789
8.10M
  if (Opc == TargetOpcode::EXTRACT_SUBREG ||
790
8.10M
      
Opc == TargetOpcode::INSERT_SUBREG7.80M
||
791
8.10M
      
Opc == TargetOpcode::SUBREG_TO_REG7.71M
) {
792
579k
    EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
793
579k
    return;
794
579k
  }
795
7.52M
796
7.52M
  // Handle COPY_TO_REGCLASS specially.
797
7.52M
  if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
798
62.0k
    EmitCopyToRegClassNode(Node, VRBaseMap);
799
62.0k
    return;
800
62.0k
  }
801
7.46M
802
7.46M
  // Handle REG_SEQUENCE specially.
803
7.46M
  if (Opc == TargetOpcode::REG_SEQUENCE) {
804
70.9k
    EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
805
70.9k
    return;
806
70.9k
  }
807
7.39M
808
7.39M
  if (Opc == TargetOpcode::IMPLICIT_DEF)
809
60.6k
    // We want a unique VR for each IMPLICIT_DEF use.
810
60.6k
    return;
811
7.33M
812
7.33M
  const MCInstrDesc &II = TII->get(Opc);
813
7.33M
  unsigned NumResults = CountResults(Node);
814
7.33M
  unsigned NumDefs = II.getNumDefs();
815
7.33M
  const MCPhysReg *ScratchRegs = nullptr;
816
7.33M
817
7.33M
  // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
818
7.33M
  if (Opc == TargetOpcode::STACKMAP || 
Opc == TargetOpcode::PATCHPOINT7.33M
) {
819
286
    // Stackmaps do not have arguments and do not preserve their calling
820
286
    // convention. However, to simplify runtime support, they clobber the same
821
286
    // scratch registers as AnyRegCC.
822
286
    unsigned CC = CallingConv::AnyReg;
823
286
    if (Opc == TargetOpcode::PATCHPOINT) {
824
146
      CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
825
146
      NumDefs = NumResults;
826
146
    }
827
286
    ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
828
286
  }
829
7.33M
830
7.33M
  unsigned NumImpUses = 0;
831
7.33M
  unsigned NodeOperands =
832
7.33M
    countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
833
7.33M
  bool HasPhysRegOuts = NumResults > NumDefs && 
II.getImplicitDefs()!=nullptr1.79M
;
834
#ifndef NDEBUG
835
  unsigned NumMIOperands = NodeOperands + NumResults;
836
  if (II.isVariadic())
837
    assert(NumMIOperands >= II.getNumOperands() &&
838
           "Too few operands for a variadic node!");
839
  else
840
    assert(NumMIOperands >= II.getNumOperands() &&
841
           NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
842
                            NumImpUses &&
843
           "#operands for dag node doesn't match .td file!");
844
#endif
845
846
7.33M
  // Create the new machine instruction.
847
7.33M
  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
848
7.33M
849
7.33M
  // Add result register values for things that are defined by this
850
7.33M
  // instruction.
851
7.33M
  if (NumResults) {
852
4.85M
    CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
853
4.85M
854
4.85M
    // Transfer any IR flags from the SDNode to the MachineInstr
855
4.85M
    MachineInstr *MI = MIB.getInstr();
856
4.85M
    const SDNodeFlags Flags = Node->getFlags();
857
4.85M
    if (Flags.hasNoSignedZeros())
858
3.54k
      MI->setFlag(MachineInstr::MIFlag::FmNsz);
859
4.85M
860
4.85M
    if (Flags.hasAllowReciprocal())
861
3.52k
      MI->setFlag(MachineInstr::MIFlag::FmArcp);
862
4.85M
863
4.85M
    if (Flags.hasNoNaNs())
864
3.76k
      MI->setFlag(MachineInstr::MIFlag::FmNoNans);
865
4.85M
866
4.85M
    if (Flags.hasNoInfs())
867
3.52k
      MI->setFlag(MachineInstr::MIFlag::FmNoInfs);
868
4.85M
869
4.85M
    if (Flags.hasAllowContract())
870
3.52k
      MI->setFlag(MachineInstr::MIFlag::FmContract);
871
4.85M
872
4.85M
    if (Flags.hasApproximateFuncs())
873
3.44k
      MI->setFlag(MachineInstr::MIFlag::FmAfn);
874
4.85M
875
4.85M
    if (Flags.hasAllowReassociation())
876
3.65k
      MI->setFlag(MachineInstr::MIFlag::FmReassoc);
877
4.85M
878
4.85M
    if (Flags.hasNoUnsignedWrap())
879
117k
      MI->setFlag(MachineInstr::MIFlag::NoUWrap);
880
4.85M
881
4.85M
    if (Flags.hasNoSignedWrap())
882
113k
      MI->setFlag(MachineInstr::MIFlag::NoSWrap);
883
4.85M
884
4.85M
    if (Flags.hasExact())
885
3.43k
      MI->setFlag(MachineInstr::MIFlag::IsExact);
886
4.85M
887
4.85M
    if (Flags.hasFPExcept())
888
662
      MI->setFlag(MachineInstr::MIFlag::FPExcept);
889
4.85M
  }
890
7.33M
891
7.33M
  // Emit all of the actual operands of this instruction, adding them to the
892
7.33M
  // instruction as appropriate.
893
7.33M
  bool HasOptPRefs = NumDefs > NumResults;
894
7.33M
  assert((!HasOptPRefs || !HasPhysRegOuts) &&
895
7.33M
         "Unable to cope with optional defs and phys regs defs!");
896
7.33M
  unsigned NumSkip = HasOptPRefs ? 
NumDefs - NumResults7.13k
:
07.32M
;
897
27.0M
  for (unsigned i = NumSkip; i != NodeOperands; 
++i19.7M
)
898
19.7M
    AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
899
19.7M
               VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
900
7.33M
901
7.33M
  // Add scratch registers as implicit def and early clobber
902
7.33M
  if (ScratchRegs)
903
846
    
for (unsigned i = 0; 286
ScratchRegs[i];
++i560
)
904
560
      MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
905
560
                                 RegState::EarlyClobber);
906
7.33M
907
7.33M
  // Set the memory reference descriptions of this instruction now that it is
908
7.33M
  // part of the function.
909
7.33M
  MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands());
910
7.33M
911
7.33M
  // Insert the instruction into position in the block. This needs to
912
7.33M
  // happen before any custom inserter hook is called so that the
913
7.33M
  // hook knows where in the block to insert the replacement code.
914
7.33M
  MBB->insert(InsertPos, MIB);
915
7.33M
916
7.33M
  // The MachineInstr may also define physregs instead of virtregs.  These
917
7.33M
  // physreg values can reach other instructions in different ways:
918
7.33M
  //
919
7.33M
  // 1. When there is a use of a Node value beyond the explicitly defined
920
7.33M
  //    virtual registers, we emit a CopyFromReg for one of the implicitly
921
7.33M
  //    defined physregs.  This only happens when HasPhysRegOuts is true.
922
7.33M
  //
923
7.33M
  // 2. A CopyFromReg reading a physreg may be glued to this instruction.
924
7.33M
  //
925
7.33M
  // 3. A glued instruction may implicitly use a physreg.
926
7.33M
  //
927
7.33M
  // 4. A glued instruction may use a RegisterSDNode operand.
928
7.33M
  //
929
7.33M
  // Collect all the used physreg defs, and make sure that any unused physreg
930
7.33M
  // defs are marked as dead.
931
7.33M
  SmallVector<unsigned, 8> UsedRegs;
932
7.33M
933
7.33M
  // Additional results must be physical register defs.
934
7.33M
  if (HasPhysRegOuts) {
935
3.59M
    for (unsigned i = NumDefs; i < NumResults; 
++i1.79M
) {
936
1.79M
      unsigned Reg = II.getImplicitDefs()[i - NumDefs];
937
1.79M
      if (!Node->hasAnyUseOfValue(i))
938
1.44M
        continue;
939
353k
      // This implicitly defined physreg has a use.
940
353k
      UsedRegs.push_back(Reg);
941
353k
      EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
942
353k
    }
943
1.79M
  }
944
7.33M
945
7.33M
  // Scan the glue chain for any used physregs.
946
7.33M
  if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
947
2.30M
    for (SDNode *F = Node->getGluedUser(); F; 
F = F->getGluedUser()957k
) {
948
957k
      if (F->getOpcode() == ISD::CopyFromReg) {
949
431k
        UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
950
431k
        continue;
951
526k
      } else if (F->getOpcode() == ISD::CopyToReg) {
952
1.28k
        // Skip CopyToReg nodes that are internal to the glue chain.
953
1.28k
        continue;
954
1.28k
      }
955
524k
      // Collect declared implicit uses.
956
524k
      const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
957
524k
      UsedRegs.append(MCID.getImplicitUses(),
958
524k
                      MCID.getImplicitUses() + MCID.getNumImplicitUses());
959
524k
      // In addition to declared implicit uses, we must also check for
960
524k
      // direct RegisterSDNode operands.
961
2.91M
      for (unsigned i = 0, e = F->getNumOperands(); i != e; 
++i2.39M
)
962
2.39M
        if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
963
154k
          unsigned Reg = R->getReg();
964
154k
          if (TargetRegisterInfo::isPhysicalRegister(Reg))
965
62.4k
            UsedRegs.push_back(Reg);
966
154k
        }
967
524k
    }
968
1.34M
  }
969
7.33M
970
7.33M
  // Finally mark unused registers as dead.
971
7.33M
  if (!UsedRegs.empty() || 
II.getImplicitDefs()6.30M
||
II.hasOptionalDef()5.31M
)
972
2.13M
    MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
973
7.33M
974
7.33M
  // Run post-isel target hook to adjust this instruction if needed.
975
7.33M
  if (II.hasPostISelHook())
976
54.3k
    TLI->AdjustInstrPostInstrSelection(*MIB, Node);
977
7.33M
}
978
979
/// EmitSpecialNode - Generate machine code for a target-independent node and
980
/// needed dependencies.
981
void InstrEmitter::
982
EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
983
5.18M
                DenseMap<SDValue, unsigned> &VRBaseMap) {
984
5.18M
  switch (Node->getOpcode()) {
985
5.18M
  default:
986
#ifndef NDEBUG
987
    Node->dump();
988
#endif
989
0
    llvm_unreachable("This target-independent node should have been selected!");
990
5.18M
  case ISD::EntryToken:
991
0
    llvm_unreachable("EntryToken should have been excluded from the schedule!");
992
5.18M
  case ISD::MERGE_VALUES:
993
509k
  case ISD::TokenFactor: // fall thru
994
509k
    break;
995
2.38M
  case ISD::CopyToReg: {
996
2.38M
    unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
997
2.38M
    SDValue SrcVal = Node->getOperand(2);
998
2.38M
    if (TargetRegisterInfo::isVirtualRegister(DestReg) &&
999
2.38M
        
SrcVal.isMachineOpcode()850k
&&
1000
2.38M
        
SrcVal.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF708k
) {
1001
1.84k
      // Instead building a COPY to that vreg destination, build an
1002
1.84k
      // IMPLICIT_DEF instruction instead.
1003
1.84k
      BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1004
1.84k
              TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
1005
1.84k
      break;
1006
1.84k
    }
1007
2.38M
    unsigned SrcReg;
1008
2.38M
    if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
1009
2.16k
      SrcReg = R->getReg();
1010
2.38M
    else
1011
2.38M
      SrcReg = getVR(SrcVal, VRBaseMap);
1012
2.38M
1013
2.38M
    if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
1014
667k
      break;
1015
1.71M
1016
1.71M
    BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
1017
1.71M
            DestReg).addReg(SrcReg);
1018
1.71M
    break;
1019
1.71M
  }
1020
2.18M
  case ISD::CopyFromReg: {
1021
2.18M
    unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1022
2.18M
    EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
1023
2.18M
    break;
1024
1.71M
  }
1025
1.71M
  case ISD::EH_LABEL:
1026
12.6k
  case ISD::ANNOTATION_LABEL: {
1027
12.6k
    unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
1028
12.6k
                       ? 
TargetOpcode::EH_LABEL12.6k
1029
12.6k
                       : 
TargetOpcode::ANNOTATION_LABEL8
;
1030
12.6k
    MCSymbol *S = cast<LabelSDNode>(Node)->getLabel();
1031
12.6k
    BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1032
12.6k
            TII->get(Opc)).addSym(S);
1033
12.6k
    break;
1034
12.6k
  }
1035
12.6k
1036
68.1k
  case ISD::LIFETIME_START:
1037
68.1k
  case ISD::LIFETIME_END: {
1038
68.1k
    unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
1039
34.5k
    
TargetOpcode::LIFETIME_START33.5k
: TargetOpcode::LIFETIME_END;
1040
68.1k
1041
68.1k
    FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1));
1042
68.1k
    BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1043
68.1k
    .addFrameIndex(FI->getIndex());
1044
68.1k
    break;
1045
68.1k
  }
1046
68.1k
1047
68.1k
  case ISD::INLINEASM:
1048
20.4k
  case ISD::INLINEASM_BR: {
1049
20.4k
    unsigned NumOps = Node->getNumOperands();
1050
20.4k
    if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1051
3.35k
      --NumOps;  // Ignore the glue operand.
1052
20.4k
1053
20.4k
    // Create the inline asm machine instruction.
1054
20.4k
    unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR
1055
20.4k
                          ? 
TargetOpcode::INLINEASM_BR5
1056
20.4k
                          : 
TargetOpcode::INLINEASM20.4k
;
1057
20.4k
    MachineInstrBuilder MIB =
1058
20.4k
        BuildMI(*MF, Node->getDebugLoc(), TII->get(TgtOpc));
1059
20.4k
1060
20.4k
    // Add the asm string as an external symbol operand.
1061
20.4k
    SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
1062
20.4k
    const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
1063
20.4k
    MIB.addExternalSymbol(AsmStr);
1064
20.4k
1065
20.4k
    // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
1066
20.4k
    // bits.
1067
20.4k
    int64_t ExtraInfo =
1068
20.4k
      cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
1069
20.4k
                          getZExtValue();
1070
20.4k
    MIB.addImm(ExtraInfo);
1071
20.4k
1072
20.4k
    // Remember to operand index of the group flags.
1073
20.4k
    SmallVector<unsigned, 8> GroupIdx;
1074
20.4k
1075
20.4k
    // Remember registers that are part of early-clobber defs.
1076
20.4k
    SmallVector<unsigned, 8> ECRegs;
1077
20.4k
1078
20.4k
    // Add all of the operand registers to the instruction.
1079
114k
    for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1080
93.5k
      unsigned Flags =
1081
93.5k
        cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1082
93.5k
      const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1083
93.5k
1084
93.5k
      GroupIdx.push_back(MIB->getNumOperands());
1085
93.5k
      MIB.addImm(Flags);
1086
93.5k
      ++i;  // Skip the ID value.
1087
93.5k
1088
93.5k
      switch (InlineAsm::getKind(Flags)) {
1089
93.5k
      
default: 0
llvm_unreachable0
("Bad flags!");
1090
93.5k
        case InlineAsm::Kind_RegDef:
1091
8.63k
        for (unsigned j = 0; j != NumVals; 
++j, ++i4.32k
) {
1092
4.32k
          unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1093
4.32k
          // FIXME: Add dead flags for physical and virtual registers defined.
1094
4.32k
          // For now, mark physical register defs as implicit to help fast
1095
4.32k
          // regalloc. This makes inline asm look a lot like calls.
1096
4.32k
          MIB.addReg(Reg, RegState::Define |
1097
4.32k
                  getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
1098
4.32k
        }
1099
4.30k
        break;
1100
93.5k
      case InlineAsm::Kind_RegDefEarlyClobber:
1101
83.6k
      case InlineAsm::Kind_Clobber:
1102
167k
        for (unsigned j = 0; j != NumVals; 
++j, ++i83.7k
) {
1103
83.7k
          unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1104
83.7k
          MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber |
1105
83.7k
                  getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
1106
83.7k
          ECRegs.push_back(Reg);
1107
83.7k
        }
1108
83.6k
        break;
1109
83.6k
      case InlineAsm::Kind_RegUse:  // Use of register.
1110
5.59k
      case InlineAsm::Kind_Imm:  // Immediate.
1111
5.59k
      case InlineAsm::Kind_Mem:  // Addressing mode.
1112
5.59k
        // The addressing mode has been selected, just add all of the
1113
5.59k
        // operands to the machine instruction.
1114
12.4k
        for (unsigned j = 0; j != NumVals; 
++j, ++i6.88k
)
1115
6.88k
          AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
1116
6.88k
                     /*IsDebug=*/false, IsClone, IsCloned);
1117
5.59k
1118
5.59k
        // Manually set isTied bits.
1119
5.59k
        if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
1120
4.63k
          unsigned DefGroup = 0;
1121
4.63k
          if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
1122
422
            unsigned DefIdx = GroupIdx[DefGroup] + 1;
1123
422
            unsigned UseIdx = GroupIdx.back() + 1;
1124
857
            for (unsigned j = 0; j != NumVals; 
++j435
)
1125
435
              MIB->tieOperands(DefIdx + j, UseIdx + j);
1126
422
          }
1127
4.63k
        }
1128
5.59k
        break;
1129
93.5k
      }
1130
93.5k
    }
1131
20.4k
1132
20.4k
    // GCC inline assembly allows input operands to also be early-clobber
1133
20.4k
    // output operands (so long as the operand is written only after it's
1134
20.4k
    // used), but this does not match the semantics of our early-clobber flag.
1135
20.4k
    // If an early-clobber operand register is also an input operand register,
1136
20.4k
    // then remove the early-clobber flag.
1137
83.7k
    
for (unsigned Reg : ECRegs)20.4k
{
1138
83.7k
      if (MIB->readsRegister(Reg, TRI)) {
1139
42
        MachineOperand *MO = 
1140
42
            MIB->findRegisterDefOperand(Reg, false, false, TRI);
1141
42
        assert(MO && "No def operand for clobbered register?");
1142
42
        MO->setIsEarlyClobber(false);
1143
42
      }
1144
83.7k
    }
1145
20.4k
1146
20.4k
    // Get the mdnode from the asm if it exists and add it to the instruction.
1147
20.4k
    SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
1148
20.4k
    const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1149
20.4k
    if (MD)
1150
7.43k
      MIB.addMetadata(MD);
1151
20.4k
1152
20.4k
    MBB->insert(InsertPos, MIB);
1153
20.4k
    break;
1154
20.4k
  }
1155
5.18M
  }
1156
5.18M
}
1157
1158
/// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1159
/// at the given position in the given block.
1160
InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
1161
                           MachineBasicBlock::iterator insertpos)
1162
    : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1163
      TII(MF->getSubtarget().getInstrInfo()),
1164
      TRI(MF->getSubtarget().getRegisterInfo()),
1165
      TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1166
1.24M
      InsertPos(insertpos) {}