Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
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Count
Source (jump to first uncovered line)
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//===-------- LegalizeTypesGeneric.cpp - Generic type legalization --------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements generic type expansion and splitting for LegalizeTypes.
10
// The routines here perform legalization when the details of the type (such as
11
// whether it is an integer or a float) do not matter.
12
// Expansion is the act of changing a computation in an illegal type to be a
13
// computation in two identical registers of a smaller type.  The Lo/Hi part
14
// is required to be stored first in memory on little/big-endian machines.
15
// Splitting is the act of changing a computation in an illegal type to be a
16
// computation in two not necessarily identical registers of a smaller type.
17
// There are no requirements on how the type is represented in memory.
18
//
19
//===----------------------------------------------------------------------===//
20
21
#include "LegalizeTypes.h"
22
#include "llvm/IR/DataLayout.h"
23
using namespace llvm;
24
25
#define DEBUG_TYPE "legalize-types"
26
27
//===----------------------------------------------------------------------===//
28
// Generic Result Expansion.
29
//===----------------------------------------------------------------------===//
30
31
// These routines assume that the Lo/Hi part is stored first in memory on
32
// little/big-endian machines, followed by the Hi/Lo part.  This means that
33
// they cannot be used as is on vectors, for which Lo is always stored first.
34
void DAGTypeLegalizer::ExpandRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
35
0
                                              SDValue &Lo, SDValue &Hi) {
36
0
  SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
37
0
  GetExpandedOp(Op, Lo, Hi);
38
0
}
39
40
14.1k
void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
41
14.1k
  EVT OutVT = N->getValueType(0);
42
14.1k
  EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
43
14.1k
  SDValue InOp = N->getOperand(0);
44
14.1k
  EVT InVT = InOp.getValueType();
45
14.1k
  SDLoc dl(N);
46
14.1k
47
14.1k
  // Handle some special cases efficiently.
48
14.1k
  switch (getTypeAction(InVT)) {
49
14.1k
    case TargetLowering::TypeLegal:
50
8.34k
    case TargetLowering::TypePromoteInteger:
51
8.34k
      break;
52
8.34k
    case TargetLowering::TypePromoteFloat:
53
0
      llvm_unreachable("Bitcast of a promotion-needing float should never need"
54
8.34k
                       "expansion");
55
8.34k
    case TargetLowering::TypeSoftenFloat: {
56
922
      // Expand the floating point operand only if it was converted to integers.
57
922
      // Otherwise, it is a legal type like f128 that can be saved in a register.
58
922
      auto SoftenedOp = GetSoftenedFloat(InOp);
59
922
      if (isLegalInHWReg(SoftenedOp.getValueType()))
60
60
        break;
61
862
      SplitInteger(SoftenedOp, Lo, Hi);
62
862
      Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
63
862
      Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
64
862
      return;
65
862
    }
66
862
    case TargetLowering::TypeExpandInteger:
67
183
    case TargetLowering::TypeExpandFloat: {
68
183
      auto &DL = DAG.getDataLayout();
69
183
      // Convert the expanded pieces of the input.
70
183
      GetExpandedOp(InOp, Lo, Hi);
71
183
      if (TLI.hasBigEndianPartOrdering(InVT, DL) !=
72
183
          TLI.hasBigEndianPartOrdering(OutVT, DL))
73
58
        std::swap(Lo, Hi);
74
183
      Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
75
183
      Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
76
183
      return;
77
183
    }
78
2.12k
    case TargetLowering::TypeSplitVector:
79
2.12k
      GetSplitVector(InOp, Lo, Hi);
80
2.12k
      if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout()))
81
13
        std::swap(Lo, Hi);
82
2.12k
      Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
83
2.12k
      Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
84
2.12k
      return;
85
2.52k
    case TargetLowering::TypeScalarizeVector:
86
2.52k
      // Convert the element instead.
87
2.52k
      SplitInteger(BitConvertToInteger(GetScalarizedVector(InOp)), Lo, Hi);
88
2.52k
      Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
89
2.52k
      Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
90
2.52k
      return;
91
183
    case TargetLowering::TypeWidenVector: {
92
1
      assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST");
93
1
      InOp = GetWidenedVector(InOp);
94
1
      EVT LoVT, HiVT;
95
1
      std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(InVT);
96
1
      std::tie(Lo, Hi) = DAG.SplitVector(InOp, dl, LoVT, HiVT);
97
1
      if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout()))
98
0
        std::swap(Lo, Hi);
99
1
      Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
100
1
      Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
101
1
      return;
102
8.40k
    }
103
8.40k
  }
104
8.40k
105
8.40k
  if (InVT.isVector() && 
OutVT.isInteger()7.95k
) {
106
7.95k
    // Handle cases like i64 = BITCAST v1i64 on x86, where the operand
107
7.95k
    // is legal but the result is not.
108
7.95k
    unsigned NumElems = 2;
109
7.95k
    EVT ElemVT = NOutVT;
110
7.95k
    EVT NVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, NumElems);
111
7.95k
112
7.95k
    // If <ElemVT * N> is not a legal type, try <ElemVT/2 * (N*2)>.
113
14.6k
    while (!isTypeLegal(NVT)) {
114
6.67k
      unsigned NewSizeInBits = ElemVT.getSizeInBits() / 2;
115
6.67k
      // If the element size is smaller than byte, bail.
116
6.67k
      if (NewSizeInBits < 8)
117
7
        break;
118
6.66k
      NumElems *= 2;
119
6.66k
      ElemVT = EVT::getIntegerVT(*DAG.getContext(), NewSizeInBits);
120
6.66k
      NVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, NumElems);
121
6.66k
    }
122
7.95k
123
7.95k
    if (isTypeLegal(NVT)) {
124
7.94k
      SDValue CastInOp = DAG.getNode(ISD::BITCAST, dl, NVT, InOp);
125
7.94k
126
7.94k
      SmallVector<SDValue, 8> Vals;
127
44.7k
      for (unsigned i = 0; i < NumElems; 
++i36.7k
)
128
36.7k
        Vals.push_back(DAG.getNode(
129
36.7k
            ISD::EXTRACT_VECTOR_ELT, dl, ElemVT, CastInOp,
130
36.7k
            DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
131
7.94k
132
7.94k
      // Build Lo, Hi pair by pairing extracted elements if needed.
133
7.94k
      unsigned Slot = 0;
134
28.8k
      for (unsigned e = Vals.size(); e - Slot > 2; 
Slot += 2, e += 120.9k
) {
135
20.9k
        // Each iteration will BUILD_PAIR two nodes and append the result until
136
20.9k
        // there are only two nodes left, i.e. Lo and Hi.
137
20.9k
        SDValue LHS = Vals[Slot];
138
20.9k
        SDValue RHS = Vals[Slot + 1];
139
20.9k
140
20.9k
        if (DAG.getDataLayout().isBigEndian())
141
2
          std::swap(LHS, RHS);
142
20.9k
143
20.9k
        Vals.push_back(DAG.getNode(
144
20.9k
            ISD::BUILD_PAIR, dl,
145
20.9k
            EVT::getIntegerVT(*DAG.getContext(), LHS.getValueSizeInBits() << 1),
146
20.9k
            LHS, RHS));
147
20.9k
      }
148
7.94k
      Lo = Vals[Slot++];
149
7.94k
      Hi = Vals[Slot++];
150
7.94k
151
7.94k
      if (DAG.getDataLayout().isBigEndian())
152
60
        std::swap(Lo, Hi);
153
7.94k
154
7.94k
      return;
155
7.94k
    }
156
465
  }
157
465
158
465
  // Lower the bit-convert to a store/load from the stack.
159
465
  assert(NOutVT.isByteSized() && "Expanded type not byte sized!");
160
465
161
465
  // Create the stack frame object.  Make sure it is aligned for both
162
465
  // the source and expanded destination types.
163
465
  unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(
164
465
      NOutVT.getTypeForEVT(*DAG.getContext()));
165
465
  SDValue StackPtr = DAG.CreateStackTemporary(InVT, Alignment);
166
465
  int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
167
465
  MachinePointerInfo PtrInfo =
168
465
      MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
169
465
170
465
  // Emit a store to the stack slot.
171
465
  SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, StackPtr, PtrInfo);
172
465
173
465
  // Load the first half from the stack slot.
174
465
  Lo = DAG.getLoad(NOutVT, dl, Store, StackPtr, PtrInfo);
175
465
176
465
  // Increment the pointer to the other half.
177
465
  unsigned IncrementSize = NOutVT.getSizeInBits() / 8;
178
465
  StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
179
465
                         DAG.getConstant(IncrementSize, dl,
180
465
                                         StackPtr.getValueType()));
181
465
182
465
  // Load the second half from the stack slot.
183
465
  Hi = DAG.getLoad(NOutVT, dl, Store, StackPtr,
184
465
                   PtrInfo.getWithOffset(IncrementSize),
185
465
                   MinAlign(Alignment, IncrementSize));
186
465
187
465
  // Handle endianness of the load.
188
465
  if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout()))
189
130
    std::swap(Lo, Hi);
190
465
}
191
192
void DAGTypeLegalizer::ExpandRes_BUILD_PAIR(SDNode *N, SDValue &Lo,
193
29.9k
                                            SDValue &Hi) {
194
29.9k
  // Return the operands.
195
29.9k
  Lo = N->getOperand(0);
196
29.9k
  Hi = N->getOperand(1);
197
29.9k
}
198
199
void DAGTypeLegalizer::ExpandRes_EXTRACT_ELEMENT(SDNode *N, SDValue &Lo,
200
2.85k
                                                 SDValue &Hi) {
201
2.85k
  GetExpandedOp(N->getOperand(0), Lo, Hi);
202
2.85k
  SDValue Part = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() ?
203
1.42k
                   Hi : 
Lo1.42k
;
204
2.85k
205
2.85k
  assert(Part.getValueType() == N->getValueType(0) &&
206
2.85k
         "Type twice as big as expanded type not itself expanded!");
207
2.85k
208
2.85k
  GetPairElements(Part, Lo, Hi);
209
2.85k
}
210
211
void DAGTypeLegalizer::ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo,
212
2.30k
                                                    SDValue &Hi) {
213
2.30k
  SDValue OldVec = N->getOperand(0);
214
2.30k
  unsigned OldElts = OldVec.getValueType().getVectorNumElements();
215
2.30k
  EVT OldEltVT = OldVec.getValueType().getVectorElementType();
216
2.30k
  SDLoc dl(N);
217
2.30k
218
2.30k
  // Convert to a vector of the expanded element type, for example
219
2.30k
  // <3 x i64> -> <6 x i32>.
220
2.30k
  EVT OldVT = N->getValueType(0);
221
2.30k
  EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT);
222
2.30k
223
2.30k
  if (OldVT != OldEltVT) {
224
3
    // The result of EXTRACT_VECTOR_ELT may be larger than the element type of
225
3
    // the input vector.  If so, extend the elements of the input vector to the
226
3
    // same bitwidth as the result before expanding.
227
3
    assert(OldEltVT.bitsLT(OldVT) && "Result type smaller then element type!");
228
3
    EVT NVecVT = EVT::getVectorVT(*DAG.getContext(), OldVT, OldElts);
229
3
    OldVec = DAG.getNode(ISD::ANY_EXTEND, dl, NVecVT, N->getOperand(0));
230
3
  }
231
2.30k
232
2.30k
  SDValue NewVec = DAG.getNode(ISD::BITCAST, dl,
233
2.30k
                               EVT::getVectorVT(*DAG.getContext(),
234
2.30k
                                                NewVT, 2*OldElts),
235
2.30k
                               OldVec);
236
2.30k
237
2.30k
  // Extract the elements at 2 * Idx and 2 * Idx + 1 from the new vector.
238
2.30k
  SDValue Idx = N->getOperand(1);
239
2.30k
240
2.30k
  Idx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, Idx);
241
2.30k
  Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx);
242
2.30k
243
2.30k
  Idx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
244
2.30k
                    DAG.getConstant(1, dl, Idx.getValueType()));
245
2.30k
  Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx);
246
2.30k
247
2.30k
  if (DAG.getDataLayout().isBigEndian())
248
148
    std::swap(Lo, Hi);
249
2.30k
}
250
251
void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDValue &Lo,
252
8.51k
                                            SDValue &Hi) {
253
8.51k
  assert(ISD::isNormalLoad(N) && "This routine only for normal loads!");
254
8.51k
  SDLoc dl(N);
255
8.51k
256
8.51k
  LoadSDNode *LD = cast<LoadSDNode>(N);
257
8.51k
  EVT ValueVT = LD->getValueType(0);
258
8.51k
  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT);
259
8.51k
  SDValue Chain = LD->getChain();
260
8.51k
  SDValue Ptr = LD->getBasePtr();
261
8.51k
  unsigned Alignment = LD->getAlignment();
262
8.51k
  AAMDNodes AAInfo = LD->getAAInfo();
263
8.51k
264
8.51k
  assert(NVT.isByteSized() && "Expanded type not byte sized!");
265
8.51k
266
8.51k
  Lo = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getPointerInfo(), Alignment,
267
8.51k
                   LD->getMemOperand()->getFlags(), AAInfo);
268
8.51k
269
8.51k
  // Increment the pointer to the other half.
270
8.51k
  unsigned IncrementSize = NVT.getSizeInBits() / 8;
271
8.51k
  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
272
8.51k
                    DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
273
8.51k
  Hi = DAG.getLoad(NVT, dl, Chain, Ptr,
274
8.51k
                   LD->getPointerInfo().getWithOffset(IncrementSize),
275
8.51k
                   MinAlign(Alignment, IncrementSize),
276
8.51k
                   LD->getMemOperand()->getFlags(), AAInfo);
277
8.51k
278
8.51k
  // Build a factor node to remember that this load is independent of the
279
8.51k
  // other one.
280
8.51k
  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
281
8.51k
                      Hi.getValue(1));
282
8.51k
283
8.51k
  // Handle endianness of the load.
284
8.51k
  if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
285
387
    std::swap(Lo, Hi);
286
8.51k
287
8.51k
  // Modified the chain - switch anything that used the old chain to use
288
8.51k
  // the new one.
289
8.51k
  ReplaceValueWith(SDValue(N, 1), Chain);
290
8.51k
}
291
292
21
void DAGTypeLegalizer::ExpandRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi) {
293
21
  EVT OVT = N->getValueType(0);
294
21
  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), OVT);
295
21
  SDValue Chain = N->getOperand(0);
296
21
  SDValue Ptr = N->getOperand(1);
297
21
  SDLoc dl(N);
298
21
  const unsigned Align = N->getConstantOperandVal(3);
299
21
300
21
  Lo = DAG.getVAArg(NVT, dl, Chain, Ptr, N->getOperand(2), Align);
301
21
  Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, N->getOperand(2), 0);
302
21
  Chain = Hi.getValue(1);
303
21
304
21
  // Handle endianness of the load.
305
21
  if (TLI.hasBigEndianPartOrdering(OVT, DAG.getDataLayout()))
306
8
    std::swap(Lo, Hi);
307
21
308
21
  // Modified the chain - switch anything that used the old chain to use
309
21
  // the new one.
310
21
  ReplaceValueWith(SDValue(N, 1), Chain);
311
21
}
312
313
314
//===--------------------------------------------------------------------===//
315
// Generic Operand Expansion.
316
//===--------------------------------------------------------------------===//
317
318
void DAGTypeLegalizer::IntegerToVector(SDValue Op, unsigned NumElements,
319
                                       SmallVectorImpl<SDValue> &Ops,
320
60.7k
                                       EVT EltVT) {
321
60.7k
  assert(Op.getValueType().isInteger());
322
60.7k
  SDLoc DL(Op);
323
60.7k
  SDValue Parts[2];
324
60.7k
325
60.7k
  if (NumElements > 1) {
326
25.9k
    NumElements >>= 1;
327
25.9k
    SplitInteger(Op, Parts[0], Parts[1]);
328
25.9k
    if (DAG.getDataLayout().isBigEndian())
329
92
      std::swap(Parts[0], Parts[1]);
330
25.9k
    IntegerToVector(Parts[0], NumElements, Ops, EltVT);
331
25.9k
    IntegerToVector(Parts[1], NumElements, Ops, EltVT);
332
34.8k
  } else {
333
34.8k
    Ops.push_back(DAG.getNode(ISD::BITCAST, DL, EltVT, Op));
334
34.8k
  }
335
60.7k
}
336
337
9.51k
SDValue DAGTypeLegalizer::ExpandOp_BITCAST(SDNode *N) {
338
9.51k
  SDLoc dl(N);
339
9.51k
  if (N->getValueType(0).isVector() &&
340
9.51k
      
N->getOperand(0).getValueType().isInteger()8.83k
) {
341
8.83k
    // An illegal expanding type is being converted to a legal vector type.
342
8.83k
    // Make a two element vector out of the expanded parts and convert that
343
8.83k
    // instead, but only if the new vector type is legal (otherwise there
344
8.83k
    // is no point, and it might create expansion loops).  For example, on
345
8.83k
    // x86 this turns v1i64 = BITCAST i64 into v1i64 = BITCAST v2i32.
346
8.83k
    //
347
8.83k
    // FIXME: I'm not sure why we are first trying to split the input into
348
8.83k
    // a 2 element vector, so I'm leaving it here to maintain the current
349
8.83k
    // behavior.
350
8.83k
    unsigned NumElts = 2;
351
8.83k
    EVT OVT = N->getOperand(0).getValueType();
352
8.83k
    EVT NVT = EVT::getVectorVT(*DAG.getContext(),
353
8.83k
                               TLI.getTypeToTransformTo(*DAG.getContext(), OVT),
354
8.83k
                               NumElts);
355
8.83k
    if (!isTypeLegal(NVT)) {
356
2.41k
      // If we can't find a legal type by splitting the integer in half,
357
2.41k
      // then we can use the node's value type.
358
2.41k
      NumElts = N->getValueType(0).getVectorNumElements();
359
2.41k
      NVT = N->getValueType(0);
360
2.41k
    }
361
8.83k
362
8.83k
    SmallVector<SDValue, 8> Ops;
363
8.83k
    IntegerToVector(N->getOperand(0), NumElts, Ops, NVT.getVectorElementType());
364
8.83k
365
8.83k
    SDValue Vec =
366
8.83k
        DAG.getBuildVector(NVT, dl, makeArrayRef(Ops.data(), NumElts));
367
8.83k
    return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), Vec);
368
8.83k
  }
369
685
370
685
  // Otherwise, store to a temporary and load out again as the new type.
371
685
  return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
372
685
}
373
374
2.52k
SDValue DAGTypeLegalizer::ExpandOp_BUILD_VECTOR(SDNode *N) {
375
2.52k
  // The vector type is legal but the element type needs expansion.
376
2.52k
  EVT VecVT = N->getValueType(0);
377
2.52k
  unsigned NumElts = VecVT.getVectorNumElements();
378
2.52k
  EVT OldVT = N->getOperand(0).getValueType();
379
2.52k
  EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT);
380
2.52k
  SDLoc dl(N);
381
2.52k
382
2.52k
  assert(OldVT == VecVT.getVectorElementType() &&
383
2.52k
         "BUILD_VECTOR operand type doesn't match vector element type!");
384
2.52k
385
2.52k
  // Build a vector of twice the length out of the expanded elements.
386
2.52k
  // For example <3 x i64> -> <6 x i32>.
387
2.52k
  SmallVector<SDValue, 16> NewElts;
388
2.52k
  NewElts.reserve(NumElts*2);
389
2.52k
390
9.91k
  for (unsigned i = 0; i < NumElts; 
++i7.38k
) {
391
7.38k
    SDValue Lo, Hi;
392
7.38k
    GetExpandedOp(N->getOperand(i), Lo, Hi);
393
7.38k
    if (DAG.getDataLayout().isBigEndian())
394
309
      std::swap(Lo, Hi);
395
7.38k
    NewElts.push_back(Lo);
396
7.38k
    NewElts.push_back(Hi);
397
7.38k
  }
398
2.52k
399
2.52k
  EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NewElts.size());
400
2.52k
  SDValue NewVec = DAG.getBuildVector(NewVecVT, dl, NewElts);
401
2.52k
402
2.52k
  // Convert the new vector to the old vector type.
403
2.52k
  return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec);
404
2.52k
}
405
406
38.2k
SDValue DAGTypeLegalizer::ExpandOp_EXTRACT_ELEMENT(SDNode *N) {
407
38.2k
  SDValue Lo, Hi;
408
38.2k
  GetExpandedOp(N->getOperand(0), Lo, Hi);
409
38.2k
  return cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() ? 
Hi19.1k
:
Lo19.1k
;
410
38.2k
}
411
412
22
SDValue DAGTypeLegalizer::ExpandOp_INSERT_VECTOR_ELT(SDNode *N) {
413
22
  // The vector type is legal but the element type needs expansion.
414
22
  EVT VecVT = N->getValueType(0);
415
22
  unsigned NumElts = VecVT.getVectorNumElements();
416
22
  SDLoc dl(N);
417
22
418
22
  SDValue Val = N->getOperand(1);
419
22
  EVT OldEVT = Val.getValueType();
420
22
  EVT NewEVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldEVT);
421
22
422
22
  assert(OldEVT == VecVT.getVectorElementType() &&
423
22
         "Inserted element type doesn't match vector element type!");
424
22
425
22
  // Bitconvert to a vector of twice the length with elements of the expanded
426
22
  // type, insert the expanded vector elements, and then convert back.
427
22
  EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewEVT, NumElts*2);
428
22
  SDValue NewVec = DAG.getNode(ISD::BITCAST, dl,
429
22
                               NewVecVT, N->getOperand(0));
430
22
431
22
  SDValue Lo, Hi;
432
22
  GetExpandedOp(Val, Lo, Hi);
433
22
  if (DAG.getDataLayout().isBigEndian())
434
6
    std::swap(Lo, Hi);
435
22
436
22
  SDValue Idx = N->getOperand(2);
437
22
  Idx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, Idx);
438
22
  NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx);
439
22
  Idx = DAG.getNode(ISD::ADD, dl,
440
22
                    Idx.getValueType(), Idx,
441
22
                    DAG.getConstant(1, dl, Idx.getValueType()));
442
22
  NewVec =  DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx);
443
22
444
22
  // Convert the new vector to the old vector type.
445
22
  return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec);
446
22
}
447
448
270
SDValue DAGTypeLegalizer::ExpandOp_SCALAR_TO_VECTOR(SDNode *N) {
449
270
  SDLoc dl(N);
450
270
  EVT VT = N->getValueType(0);
451
270
  assert(VT.getVectorElementType() == N->getOperand(0).getValueType() &&
452
270
         "SCALAR_TO_VECTOR operand type doesn't match vector element type!");
453
270
  unsigned NumElts = VT.getVectorNumElements();
454
270
  SmallVector<SDValue, 16> Ops(NumElts);
455
270
  Ops[0] = N->getOperand(0);
456
270
  SDValue UndefVal = DAG.getUNDEF(Ops[0].getValueType());
457
588
  for (unsigned i = 1; i < NumElts; 
++i318
)
458
318
    Ops[i] = UndefVal;
459
270
  return DAG.getBuildVector(VT, dl, Ops);
460
270
}
461
462
8.13k
SDValue DAGTypeLegalizer::ExpandOp_NormalStore(SDNode *N, unsigned OpNo) {
463
8.13k
  assert(ISD::isNormalStore(N) && "This routine only for normal stores!");
464
8.13k
  assert(OpNo == 1 && "Can only expand the stored value so far");
465
8.13k
  SDLoc dl(N);
466
8.13k
467
8.13k
  StoreSDNode *St = cast<StoreSDNode>(N);
468
8.13k
  EVT ValueVT = St->getValue().getValueType();
469
8.13k
  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT);
470
8.13k
  SDValue Chain = St->getChain();
471
8.13k
  SDValue Ptr = St->getBasePtr();
472
8.13k
  unsigned Alignment = St->getAlignment();
473
8.13k
  AAMDNodes AAInfo = St->getAAInfo();
474
8.13k
475
8.13k
  assert(NVT.isByteSized() && "Expanded type not byte sized!");
476
8.13k
  unsigned IncrementSize = NVT.getSizeInBits() / 8;
477
8.13k
478
8.13k
  SDValue Lo, Hi;
479
8.13k
  GetExpandedOp(St->getValue(), Lo, Hi);
480
8.13k
481
8.13k
  if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
482
512
    std::swap(Lo, Hi);
483
8.13k
484
8.13k
  Lo = DAG.getStore(Chain, dl, Lo, Ptr, St->getPointerInfo(), Alignment,
485
8.13k
                    St->getMemOperand()->getFlags(), AAInfo);
486
8.13k
487
8.13k
  Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
488
8.13k
  Hi = DAG.getStore(Chain, dl, Hi, Ptr,
489
8.13k
                    St->getPointerInfo().getWithOffset(IncrementSize),
490
8.13k
                    MinAlign(Alignment, IncrementSize),
491
8.13k
                    St->getMemOperand()->getFlags(), AAInfo);
492
8.13k
493
8.13k
  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
494
8.13k
}
495
496
497
//===--------------------------------------------------------------------===//
498
// Generic Result Splitting.
499
//===--------------------------------------------------------------------===//
500
501
// Be careful to make no assumptions about which of Lo/Hi is stored first in
502
// memory (for vectors it is always Lo first followed by Hi in the following
503
// bytes; for integers and floats it is Lo first if and only if the machine is
504
// little-endian).
505
506
void DAGTypeLegalizer::SplitRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
507
48
                                             SDValue &Lo, SDValue &Hi) {
508
48
  SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
509
48
  GetSplitOp(Op, Lo, Hi);
510
48
}
511
512
static std::pair<SDValue, SDValue> SplitVSETCC(const SDNode *N,
513
122
                                               SelectionDAG &DAG) {
514
122
  SDLoc DL(N);
515
122
  EVT LoVT, HiVT;
516
122
  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
517
122
518
122
  // Split the inputs.
519
122
  SDValue Lo, Hi, LL, LH, RL, RH;
520
122
  std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
521
122
  std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
522
122
523
122
  Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
524
122
  Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
525
122
526
122
  return std::make_pair(Lo, Hi);
527
122
}
528
529
2.45k
void DAGTypeLegalizer::SplitRes_SELECT(SDNode *N, SDValue &Lo, SDValue &Hi) {
530
2.45k
  SDValue LL, LH, RL, RH, CL, CH;
531
2.45k
  SDLoc dl(N);
532
2.45k
  GetSplitOp(N->getOperand(1), LL, LH);
533
2.45k
  GetSplitOp(N->getOperand(2), RL, RH);
534
2.45k
535
2.45k
  SDValue Cond = N->getOperand(0);
536
2.45k
  CL = CH = Cond;
537
2.45k
  if (Cond.getValueType().isVector()) {
538
946
    if (SDValue Res = WidenVSELECTAndMask(N))
539
389
      std::tie(CL, CH) = DAG.SplitVector(Res->getOperand(0), dl);
540
557
    // It seems to improve code to generate two narrow SETCCs as opposed to
541
557
    // splitting a wide result vector.
542
557
    else if (Cond.getOpcode() == ISD::SETCC)
543
122
      std::tie(CL, CH) = SplitVSETCC(Cond.getNode(), DAG);
544
435
    // Check if there are already splitted versions of the vector available and
545
435
    // use those instead of splitting the mask operand again.
546
435
    else if (getTypeAction(Cond.getValueType()) ==
547
435
             TargetLowering::TypeSplitVector)
548
394
      GetSplitVector(Cond, CL, CH);
549
41
    else
550
41
      std::tie(CL, CH) = DAG.SplitVector(Cond, dl);
551
946
  }
552
2.45k
553
2.45k
  Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), CL, LL, RL);
554
2.45k
  Hi = DAG.getNode(N->getOpcode(), dl, LH.getValueType(), CH, LH, RH);
555
2.45k
}
556
557
void DAGTypeLegalizer::SplitRes_SELECT_CC(SDNode *N, SDValue &Lo,
558
670
                                          SDValue &Hi) {
559
670
  SDValue LL, LH, RL, RH;
560
670
  SDLoc dl(N);
561
670
  GetSplitOp(N->getOperand(2), LL, LH);
562
670
  GetSplitOp(N->getOperand(3), RL, RH);
563
670
564
670
  Lo = DAG.getNode(ISD::SELECT_CC, dl, LL.getValueType(), N->getOperand(0),
565
670
                   N->getOperand(1), LL, RL, N->getOperand(4));
566
670
  Hi = DAG.getNode(ISD::SELECT_CC, dl, LH.getValueType(), N->getOperand(0),
567
670
                   N->getOperand(1), LH, RH, N->getOperand(4));
568
670
}
569
570
4.93k
void DAGTypeLegalizer::SplitRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi) {
571
4.93k
  EVT LoVT, HiVT;
572
4.93k
  std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
573
4.93k
  Lo = DAG.getUNDEF(LoVT);
574
4.93k
  Hi = DAG.getUNDEF(HiVT);
575
4.93k
}