Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
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//===- ScheduleDAGVLIW.cpp - SelectionDAG list scheduler for VLIW -*- C++ -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements a top-down list scheduler, using standard algorithms.
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// The basic approach uses a priority queue of available nodes to schedule.
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// One at a time, nodes are taken from the priority queue (thus in priority
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// order), checked for legality to schedule, and emitted if legal.
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//
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// Nodes may not be legal to schedule either due to structural hazards (e.g.
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// pipeline or resource constraints) or because an input to the instruction has
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// not completed execution.
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//
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//===----------------------------------------------------------------------===//
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#include "ScheduleDAGSDNodes.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LatencyPriorityQueue.h"
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#include "llvm/CodeGen/ResourcePriorityQueue.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include <climits>
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using namespace llvm;
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#define DEBUG_TYPE "pre-RA-sched"
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STATISTIC(NumNoops , "Number of noops inserted");
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STATISTIC(NumStalls, "Number of pipeline stalls");
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static RegisterScheduler
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  VLIWScheduler("vliw-td", "VLIW scheduler",
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                createVLIWDAGScheduler);
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namespace {
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//===----------------------------------------------------------------------===//
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/// ScheduleDAGVLIW - The actual DFA list scheduler implementation.  This
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/// supports / top-down scheduling.
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///
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class ScheduleDAGVLIW : public ScheduleDAGSDNodes {
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private:
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  /// AvailableQueue - The priority queue to use for the available SUnits.
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  ///
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  SchedulingPriorityQueue *AvailableQueue;
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  /// PendingQueue - This contains all of the instructions whose operands have
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  /// been issued, but their results are not ready yet (due to the latency of
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  /// the operation).  Once the operands become available, the instruction is
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  /// added to the AvailableQueue.
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  std::vector<SUnit*> PendingQueue;
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  /// HazardRec - The hazard recognizer to use.
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  ScheduleHazardRecognizer *HazardRec;
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  /// AA - AliasAnalysis for making memory reference queries.
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  AliasAnalysis *AA;
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public:
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  ScheduleDAGVLIW(MachineFunction &mf,
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                  AliasAnalysis *aa,
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                  SchedulingPriorityQueue *availqueue)
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    : ScheduleDAGSDNodes(mf), AvailableQueue(availqueue), AA(aa) {
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    const TargetSubtargetInfo &STI = mf.getSubtarget();
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    HazardRec = STI.getInstrInfo()->CreateTargetHazardRecognizer(&STI, this);
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  }
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  ~ScheduleDAGVLIW() override {
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    delete HazardRec;
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    delete AvailableQueue;
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  }
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  void Schedule() override;
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private:
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  void releaseSucc(SUnit *SU, const SDep &D);
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  void releaseSuccessors(SUnit *SU);
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  void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
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  void listScheduleTopDown();
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};
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}  // end anonymous namespace
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/// Schedule - Schedule the DAG using list scheduling.
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void ScheduleDAGVLIW::Schedule() {
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  LLVM_DEBUG(dbgs() << "********** List Scheduling " << printMBBReference(*BB)
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                    << " '" << BB->getName() << "' **********\n");
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  // Build the scheduling graph.
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  BuildSchedGraph(AA);
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  AvailableQueue->initNodes(SUnits);
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  listScheduleTopDown();
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  AvailableQueue->releaseState();
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}
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//===----------------------------------------------------------------------===//
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//  Top-Down Scheduling
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//===----------------------------------------------------------------------===//
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/// releaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
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/// the PendingQueue if the count reaches zero. Also update its cycle bound.
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void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) {
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  SUnit *SuccSU = D.getSUnit();
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#ifndef NDEBUG
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  if (SuccSU->NumPredsLeft == 0) {
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    dbgs() << "*** Scheduling failed! ***\n";
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    dumpNode(*SuccSU);
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    dbgs() << " has been released too many times!\n";
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    llvm_unreachable(nullptr);
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  }
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#endif
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  assert(!D.isWeak() && "unexpected artificial DAG edge");
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  --SuccSU->NumPredsLeft;
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  SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency());
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  // If all the node's predecessors are scheduled, this node is ready
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  // to be scheduled. Ignore the special ExitSU node.
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  if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) {
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    PendingQueue.push_back(SuccSU);
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  }
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}
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void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) {
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  // Top down: release successors.
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  for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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       I != E; ++I) {
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    assert(!I->isAssignedRegDep() &&
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           "The list-td scheduler doesn't yet support physreg dependencies!");
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    releaseSucc(SU, *I);
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  }
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}
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/// scheduleNodeTopDown - Add the node to the schedule. Decrement the pending
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/// count of its successors. If a successor pending count is zero, add it to
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/// the Available queue.
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void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
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  LLVM_DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: ");
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  LLVM_DEBUG(dumpNode(*SU));
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  Sequence.push_back(SU);
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  assert(CurCycle >= SU->getDepth() && "Node scheduled above its depth!");
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  SU->setDepthToAtLeast(CurCycle);
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  releaseSuccessors(SU);
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  SU->isScheduled = true;
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  AvailableQueue->scheduledNode(SU);
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}
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/// listScheduleTopDown - The main loop of list scheduling for top-down
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/// schedulers.
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void ScheduleDAGVLIW::listScheduleTopDown() {
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  unsigned CurCycle = 0;
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  // Release any successors of the special Entry node.
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  releaseSuccessors(&EntrySU);
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  // All leaves to AvailableQueue.
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  for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
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    // It is available if it has no predecessors.
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    if (SUnits[i].Preds.empty()) {
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      AvailableQueue->push(&SUnits[i]);
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      SUnits[i].isAvailable = true;
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    }
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  }
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  // While AvailableQueue is not empty, grab the node with the highest
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  // priority. If it is not ready put it back.  Schedule the node.
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  std::vector<SUnit*> NotReady;
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  Sequence.reserve(SUnits.size());
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  while (!AvailableQueue->empty() || !PendingQueue.empty()) {
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    // Check to see if any of the pending instructions are ready to issue.  If
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    // so, add them to the available queue.
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    for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
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      if (PendingQueue[i]->getDepth() == CurCycle) {
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        AvailableQueue->push(PendingQueue[i]);
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        PendingQueue[i]->isAvailable = true;
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        PendingQueue[i] = PendingQueue.back();
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        PendingQueue.pop_back();
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        --i; --e;
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      }
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      else {
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        assert(PendingQueue[i]->getDepth() > CurCycle && "Negative latency?");
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      }
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    }
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    // If there are no instructions available, don't try to issue anything, and
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    // don't advance the hazard recognizer.
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    if (AvailableQueue->empty()) {
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      // Reset DFA state.
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      AvailableQueue->scheduledNode(nullptr);
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      ++CurCycle;
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      continue;
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    }
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    SUnit *FoundSUnit = nullptr;
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    bool HasNoopHazards = false;
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    while (!AvailableQueue->empty()) {
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      SUnit *CurSUnit = AvailableQueue->pop();
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      ScheduleHazardRecognizer::HazardType HT =
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        HazardRec->getHazardType(CurSUnit, 0/*no stalls*/);
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      if (HT == ScheduleHazardRecognizer::NoHazard) {
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        FoundSUnit = CurSUnit;
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        break;
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      }
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      // Remember if this is a noop hazard.
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      HasNoopHazards |= HT == ScheduleHazardRecognizer::NoopHazard;
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      NotReady.push_back(CurSUnit);
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    }
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    // Add the nodes that aren't ready back onto the available list.
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    if (!NotReady.empty()) {
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      AvailableQueue->push_all(NotReady);
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      NotReady.clear();
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    }
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    // If we found a node to schedule, do it now.
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    if (FoundSUnit) {
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      scheduleNodeTopDown(FoundSUnit, CurCycle);
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      HazardRec->EmitInstruction(FoundSUnit);
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      // If this is a pseudo-op node, we don't want to increment the current
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      // cycle.
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      if (FoundSUnit->Latency)  // Don't increment CurCycle for pseudo-ops!
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        ++CurCycle;
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    } else if (!HasNoopHazards) {
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      // Otherwise, we have a pipeline stall, but no other problem, just advance
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      // the current cycle and try again.
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      LLVM_DEBUG(dbgs() << "*** Advancing cycle, no work to do\n");
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      HazardRec->AdvanceCycle();
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      ++NumStalls;
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      ++CurCycle;
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    } else {
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      // Otherwise, we have no instructions to issue and we have instructions
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      // that will fault if we don't do this right.  This is the case for
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      // processors without pipeline interlocks and other cases.
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      LLVM_DEBUG(dbgs() << "*** Emitting noop\n");
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      HazardRec->EmitNoop();
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      Sequence.push_back(nullptr);   // NULL here means noop
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      ++NumNoops;
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      ++CurCycle;
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    }
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  }
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#ifndef NDEBUG
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  VerifyScheduledSequence(/*isBottomUp=*/false);
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#endif
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}
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//===----------------------------------------------------------------------===//
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//                         Public Constructor Functions
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//===----------------------------------------------------------------------===//
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/// createVLIWDAGScheduler - This creates a top-down list scheduler.
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ScheduleDAGSDNodes *
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llvm::createVLIWDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
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  return new ScheduleDAGVLIW(*IS->MF, IS->AA, new ResourcePriorityQueue(IS));
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}