Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/TargetSubtargetInfo.cpp
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//===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file describes the general parts of a Subtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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using namespace llvm;
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TargetSubtargetInfo::TargetSubtargetInfo(
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    const Triple &TT, StringRef CPU, StringRef FS,
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    ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetSubTypeKV> PD,
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    const MCWriteProcResEntry *WPR,
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    const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
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    const InstrStage *IS, const unsigned *OC, const unsigned *FP)
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    : MCSubtargetInfo(TT, CPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) {
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}
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TargetSubtargetInfo::~TargetSubtargetInfo() = default;
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bool TargetSubtargetInfo::enableAtomicExpand() const {
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  return true;
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}
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bool TargetSubtargetInfo::enableIndirectBrExpand() const {
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  return false;
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}
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bool TargetSubtargetInfo::enableMachineScheduler() const {
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  return false;
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}
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bool TargetSubtargetInfo::enableJoinGlobalCopies() const {
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  return enableMachineScheduler();
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}
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bool TargetSubtargetInfo::enableRALocalReassignment(
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    CodeGenOpt::Level OptLevel) const {
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  return true;
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}
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bool TargetSubtargetInfo::enableAdvancedRASplitCost() const {
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  return false;
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}
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bool TargetSubtargetInfo::enablePostRAScheduler() const {
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  return getSchedModel().PostRAScheduler;
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}
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bool TargetSubtargetInfo::useAA() const {
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  return false;
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}
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void TargetSubtargetInfo::mirFileLoaded(MachineFunction &MF) const { }