Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/MC/MCSchedule.cpp
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//===- MCSchedule.cpp - Scheduling ------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the default scheduling model.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCSchedule.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include <type_traits>
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using namespace llvm;
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static_assert(std::is_pod<MCSchedModel>::value,
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              "We shouldn't have a static constructor here");
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const MCSchedModel MCSchedModel::Default = {DefaultIssueWidth,
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                                            DefaultMicroOpBufferSize,
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                                            DefaultLoopMicroOpBufferSize,
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                                            DefaultLoadLatency,
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                                            DefaultHighLatency,
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                                            DefaultMispredictPenalty,
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                                            false,
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                                            true,
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                                            0,
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                                            nullptr,
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                                            nullptr,
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                                            0,
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                                            0,
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                                            nullptr,
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                                            nullptr};
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int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI,
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12.3M
                                      const MCSchedClassDesc &SCDesc) {
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  int Latency = 0;
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  for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries;
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24.9M
       DefIdx != DefEnd; 
++DefIdx12.5M
) {
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    // Lookup the definition's write latency in SubtargetInfo.
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    const MCWriteLatencyEntry *WLEntry =
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        STI.getWriteLatencyEntry(&SCDesc, DefIdx);
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    // Early exit if we found an invalid latency.
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    if (WLEntry->Cycles < 0)
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      return WLEntry->Cycles;
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    Latency = std::max(Latency, static_cast<int>(WLEntry->Cycles));
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  }
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  return Latency;
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}
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int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI,
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                                      unsigned SchedClass) const {
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  const MCSchedClassDesc &SCDesc = *getSchedClassDesc(SchedClass);
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  if (!SCDesc.isValid())
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    return 0;
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  if (!SCDesc.isVariant())
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    return MCSchedModel::computeInstrLatency(STI, SCDesc);
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0
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  llvm_unreachable("unsupported variant scheduling class");
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0
}
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int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI,
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                                      const MCInstrInfo &MCII,
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                                      const MCInst &Inst) const {
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  unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
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  const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass);
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  if (!SCDesc->isValid())
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    return 0;
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  unsigned CPUID = getProcessorID();
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  while (SCDesc->isVariant()) {
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    SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID);
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    SCDesc = getSchedClassDesc(SchedClass);
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  }
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  if (SchedClass)
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    return MCSchedModel::computeInstrLatency(STI, *SCDesc);
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  llvm_unreachable("unsupported variant scheduling class");
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0
}
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double
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MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI,
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                                      const MCSchedClassDesc &SCDesc) {
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  Optional<double> Throughput;
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  const MCSchedModel &SM = STI.getSchedModel();
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  const MCWriteProcResEntry *I = STI.getWriteProcResBegin(&SCDesc);
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  const MCWriteProcResEntry *E = STI.getWriteProcResEnd(&SCDesc);
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  for (; I != E; 
++I176k
) {
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    if (!I->Cycles)
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      continue;
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    unsigned NumUnits = SM.getProcResource(I->ProcResourceIdx)->NumUnits;
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    double Temp = NumUnits * 1.0 / I->Cycles;
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    Throughput = Throughput ? 
std::min(Throughput.getValue(), Temp)138k
:
Temp37.2k
;
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  }
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  if (Throughput.hasValue())
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    return 1.0 / Throughput.getValue();
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  // If no throughput value was calculated, assume that we can execute at the
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  // maximum issue width scaled by number of micro-ops for the schedule class.
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  return ((double)SCDesc.NumMicroOps) / SM.IssueWidth;
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}
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double
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MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI,
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                                      const MCInstrInfo &MCII,
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                                      const MCInst &Inst) const {
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  unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
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  const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass);
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  // If there's no valid class, assume that the instruction executes/completes
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  // at the maximum issue width.
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  if (!SCDesc->isValid())
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    return 1.0 / IssueWidth;
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  unsigned CPUID = getProcessorID();
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  while (SCDesc->isVariant()) {
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    SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID);
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    SCDesc = getSchedClassDesc(SchedClass);
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  }
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  if (SchedClass)
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    return MCSchedModel::getReciprocalThroughput(STI, *SCDesc);
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  llvm_unreachable("unsupported variant scheduling class");
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}
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double
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MCSchedModel::getReciprocalThroughput(unsigned SchedClass,
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                                      const InstrItineraryData &IID) {
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  Optional<double> Throughput;
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  const InstrStage *I = IID.beginStage(SchedClass);
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  const InstrStage *E = IID.endStage(SchedClass);
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  for (; I != E; ++I) {
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    if (!I->getCycles())
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      continue;
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    double Temp = countPopulation(I->getUnits()) * 1.0 / I->getCycles();
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    Throughput = Throughput ? std::min(Throughput.getValue(), Temp) : Temp;
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  }
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  if (Throughput.hasValue())
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    return 1.0 / Throughput.getValue();
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  // If there are no execution resources specified for this class, then assume
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  // that it can execute at the maximum default issue width.
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  return 1.0 / DefaultIssueWidth;
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}
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unsigned
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MCSchedModel::getForwardingDelayCycles(ArrayRef<MCReadAdvanceEntry> Entries,
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                                       unsigned WriteResourceID) {
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  if (Entries.empty())
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    return 0;
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  int DelayCycles = 0;
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  for (const MCReadAdvanceEntry &E : Entries) {
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    if (E.WriteResourceID != WriteResourceID)
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      continue;
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    DelayCycles = std::min(DelayCycles, E.Cycles);
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  }
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  return std::abs(DelayCycles);
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}