Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Support/Host.cpp
Line
Count
Source (jump to first uncovered line)
1
//===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
//  This file implements the operating system Host concept.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#include "llvm/Support/Host.h"
14
#include "llvm/Support/TargetParser.h"
15
#include "llvm/ADT/SmallSet.h"
16
#include "llvm/ADT/SmallVector.h"
17
#include "llvm/ADT/StringRef.h"
18
#include "llvm/ADT/StringSwitch.h"
19
#include "llvm/ADT/Triple.h"
20
#include "llvm/Config/llvm-config.h"
21
#include "llvm/Support/Debug.h"
22
#include "llvm/Support/FileSystem.h"
23
#include "llvm/Support/MemoryBuffer.h"
24
#include "llvm/Support/raw_ostream.h"
25
#include <assert.h>
26
#include <string.h>
27
28
// Include the platform-specific parts of this class.
29
#ifdef LLVM_ON_UNIX
30
#include "Unix/Host.inc"
31
#endif
32
#ifdef _WIN32
33
#include "Windows/Host.inc"
34
#endif
35
#ifdef _MSC_VER
36
#include <intrin.h>
37
#endif
38
#if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
39
#include <mach/host_info.h>
40
#include <mach/mach.h>
41
#include <mach/mach_host.h>
42
#include <mach/machine.h>
43
#endif
44
45
#define DEBUG_TYPE "host-detection"
46
47
//===----------------------------------------------------------------------===//
48
//
49
//  Implementations of the CPU detection routines
50
//
51
//===----------------------------------------------------------------------===//
52
53
using namespace llvm;
54
55
static std::unique_ptr<llvm::MemoryBuffer>
56
0
    LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() {
57
0
  llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text =
58
0
      llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
59
0
  if (std::error_code EC = Text.getError()) {
60
0
    llvm::errs() << "Can't read "
61
0
                 << "/proc/cpuinfo: " << EC.message() << "\n";
62
0
    return nullptr;
63
0
  }
64
0
  return std::move(*Text);
65
0
}
66
67
0
StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) {
68
0
  // Access to the Processor Version Register (PVR) on PowerPC is privileged,
69
0
  // and so we must use an operating-system interface to determine the current
70
0
  // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
71
0
  const char *generic = "generic";
72
0
73
0
  // The cpu line is second (after the 'processor: 0' line), so if this
74
0
  // buffer is too small then something has changed (or is wrong).
75
0
  StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin();
76
0
  StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end();
77
0
78
0
  StringRef::const_iterator CIP = CPUInfoStart;
79
0
80
0
  StringRef::const_iterator CPUStart = 0;
81
0
  size_t CPULen = 0;
82
0
83
0
  // We need to find the first line which starts with cpu, spaces, and a colon.
84
0
  // After the colon, there may be some additional spaces and then the cpu type.
85
0
  while (CIP < CPUInfoEnd && CPUStart == 0) {
86
0
    if (CIP < CPUInfoEnd && *CIP == '\n')
87
0
      ++CIP;
88
0
89
0
    if (CIP < CPUInfoEnd && *CIP == 'c') {
90
0
      ++CIP;
91
0
      if (CIP < CPUInfoEnd && *CIP == 'p') {
92
0
        ++CIP;
93
0
        if (CIP < CPUInfoEnd && *CIP == 'u') {
94
0
          ++CIP;
95
0
          while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
96
0
            ++CIP;
97
0
98
0
          if (CIP < CPUInfoEnd && *CIP == ':') {
99
0
            ++CIP;
100
0
            while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
101
0
              ++CIP;
102
0
103
0
            if (CIP < CPUInfoEnd) {
104
0
              CPUStart = CIP;
105
0
              while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
106
0
                                          *CIP != ',' && *CIP != '\n'))
107
0
                ++CIP;
108
0
              CPULen = CIP - CPUStart;
109
0
            }
110
0
          }
111
0
        }
112
0
      }
113
0
    }
114
0
115
0
    if (CPUStart == 0)
116
0
      while (CIP < CPUInfoEnd && *CIP != '\n')
117
0
        ++CIP;
118
0
  }
119
0
120
0
  if (CPUStart == 0)
121
0
    return generic;
122
0
123
0
  return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
124
0
      .Case("604e", "604e")
125
0
      .Case("604", "604")
126
0
      .Case("7400", "7400")
127
0
      .Case("7410", "7400")
128
0
      .Case("7447", "7400")
129
0
      .Case("7455", "7450")
130
0
      .Case("G4", "g4")
131
0
      .Case("POWER4", "970")
132
0
      .Case("PPC970FX", "970")
133
0
      .Case("PPC970MP", "970")
134
0
      .Case("G5", "g5")
135
0
      .Case("POWER5", "g5")
136
0
      .Case("A2", "a2")
137
0
      .Case("POWER6", "pwr6")
138
0
      .Case("POWER7", "pwr7")
139
0
      .Case("POWER8", "pwr8")
140
0
      .Case("POWER8E", "pwr8")
141
0
      .Case("POWER8NVL", "pwr8")
142
0
      .Case("POWER9", "pwr9")
143
0
      .Default(generic);
144
0
}
145
146
26
StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
147
26
  // The cpuid register on arm is not accessible from user space. On Linux,
148
26
  // it is exposed through the /proc/cpuinfo file.
149
26
150
26
  // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line
151
26
  // in all cases.
152
26
  SmallVector<StringRef, 32> Lines;
153
26
  ProcCpuinfoContent.split(Lines, "\n");
154
26
155
26
  // Look for the CPU implementer line.
156
26
  StringRef Implementer;
157
26
  StringRef Hardware;
158
232
  for (unsigned I = 0, E = Lines.size(); I != E; 
++I206
) {
159
206
    if (Lines[I].startswith("CPU implementer"))
160
40
      Implementer = Lines[I].substr(15).ltrim("\t :");
161
206
    if (Lines[I].startswith("Hardware"))
162
2
      Hardware = Lines[I].substr(8).ltrim("\t :");
163
206
  }
164
26
165
26
  if (Implementer == "0x41") { // ARM Ltd.
166
4
    // MSM8992/8994 may give cpu part for the core that the kernel is running on,
167
4
    // which is undeterministic and wrong. Always return cortex-a53 for these SoC.
168
4
    if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996"))
169
0
      return "cortex-a53";
170
4
171
4
172
4
    // Look for the CPU part line.
173
26
    
for (unsigned I = 0, E = Lines.size(); 4
I != E;
++I22
)
174
26
      if (Lines[I].startswith("CPU part"))
175
4
        // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
176
4
        // values correspond to the "Part number" in the CP15/c0 register. The
177
4
        // contents are specified in the various processor manuals.
178
4
        return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
179
4
            .Case("0x926", "arm926ej-s")
180
4
            .Case("0xb02", "mpcore")
181
4
            .Case("0xb36", "arm1136j-s")
182
4
            .Case("0xb56", "arm1156t2-s")
183
4
            .Case("0xb76", "arm1176jz-s")
184
4
            .Case("0xc08", "cortex-a8")
185
4
            .Case("0xc09", "cortex-a9")
186
4
            .Case("0xc0f", "cortex-a15")
187
4
            .Case("0xc20", "cortex-m0")
188
4
            .Case("0xc23", "cortex-m3")
189
4
            .Case("0xc24", "cortex-m4")
190
4
            .Case("0xd04", "cortex-a35")
191
4
            .Case("0xd03", "cortex-a53")
192
4
            .Case("0xd07", "cortex-a57")
193
4
            .Case("0xd08", "cortex-a72")
194
4
            .Case("0xd09", "cortex-a73")
195
4
            .Case("0xd0a", "cortex-a75")
196
4
            .Case("0xd0b", "cortex-a76")
197
4
            .Default("generic");
198
4
  }
199
26
200
26
  
if (22
Implementer == "0x42"22
||
Implementer == "0x43"18
) { // Broadcom | Cavium.
201
80
    for (unsigned I = 0, E = Lines.size(); I != E; 
++I70
) {
202
80
      if (Lines[I].startswith("CPU part")) {
203
10
        return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
204
10
          .Case("0x516", "thunderx2t99")
205
10
          .Case("0x0516", "thunderx2t99")
206
10
          .Case("0xaf", "thunderx2t99")
207
10
          .Case("0x0af", "thunderx2t99")
208
10
          .Case("0xa1", "thunderxt88")
209
10
          .Case("0x0a1", "thunderxt88")
210
10
          .Default("generic");
211
10
      }
212
80
    }
213
10
  }
214
22
215
22
  
if (12
Implementer == "0x48"12
) // HiSilicon Technologies, Inc.
216
1
    // Look for the CPU part line.
217
2
    
for (unsigned I = 0, E = Lines.size(); 1
I != E;
++I1
)
218
2
      if (Lines[I].startswith("CPU part"))
219
1
        // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
220
1
        // values correspond to the "Part number" in the CP15/c0 register. The
221
1
        // contents are specified in the various processor manuals.
222
1
        return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
223
1
          .Case("0xd01", "tsv110")
224
1
          .Default("generic");
225
12
226
12
  
if (11
Implementer == "0x51"11
) // Qualcomm Technologies, Inc.
227
6
    // Look for the CPU part line.
228
12
    
for (unsigned I = 0, E = Lines.size(); 6
I != E;
++I6
)
229
12
      if (Lines[I].startswith("CPU part"))
230
6
        // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
231
6
        // values correspond to the "Part number" in the CP15/c0 register. The
232
6
        // contents are specified in the various processor manuals.
233
6
        return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
234
6
            .Case("0x06f", "krait") // APQ8064
235
6
            .Case("0x201", "kryo")
236
6
            .Case("0x205", "kryo")
237
6
            .Case("0x211", "kryo")
238
6
            .Case("0x800", "cortex-a73")
239
6
            .Case("0x801", "cortex-a73")
240
6
            .Case("0x802", "cortex-a73")
241
6
            .Case("0x803", "cortex-a73")
242
6
            .Case("0x804", "cortex-a73")
243
6
            .Case("0x805", "cortex-a73")
244
6
            .Case("0xc00", "falkor")
245
6
            .Case("0xc01", "saphira")
246
6
            .Default("generic");
247
11
248
11
  
if (5
Implementer == "0x53"5
) { // Samsung Electronics Co., Ltd.
249
3
    // The Exynos chips have a convoluted ID scheme that doesn't seem to follow
250
3
    // any predictive pattern across variants and parts.
251
3
    unsigned Variant = 0, Part = 0;
252
3
253
3
    // Look for the CPU variant line, whose value is a 1 digit hexadecimal
254
3
    // number, corresponding to the Variant bits in the CP15/C0 register.
255
3
    for (auto I : Lines)
256
42
      if (I.consume_front("CPU variant"))
257
6
        I.ltrim("\t :").getAsInteger(0, Variant);
258
3
259
3
    // Look for the CPU part line, whose value is a 3 digit hexadecimal
260
3
    // number, corresponding to the PartNum bits in the CP15/C0 register.
261
3
    for (auto I : Lines)
262
42
      if (I.consume_front("CPU part"))
263
6
        I.ltrim("\t :").getAsInteger(0, Part);
264
3
265
3
    unsigned Exynos = (Variant << 12) | Part;
266
3
    switch (Exynos) {
267
3
    default:
268
1
      // Default by falling through to Exynos M1.
269
1
      LLVM_FALLTHROUGH;
270
1
271
2
    case 0x1001:
272
2
      return "exynos-m1";
273
1
274
1
    case 0x4001:
275
1
      return "exynos-m2";
276
2
    }
277
2
  }
278
2
279
2
  return "generic";
280
2
}
281
282
0
StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) {
283
0
  // STIDP is a privileged operation, so use /proc/cpuinfo instead.
284
0
285
0
  // The "processor 0:" line comes after a fair amount of other information,
286
0
  // including a cache breakdown, but this should be plenty.
287
0
  SmallVector<StringRef, 32> Lines;
288
0
  ProcCpuinfoContent.split(Lines, "\n");
289
0
290
0
  // Look for the CPU features.
291
0
  SmallVector<StringRef, 32> CPUFeatures;
292
0
  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
293
0
    if (Lines[I].startswith("features")) {
294
0
      size_t Pos = Lines[I].find(":");
295
0
      if (Pos != StringRef::npos) {
296
0
        Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' ');
297
0
        break;
298
0
      }
299
0
    }
300
0
301
0
  // We need to check for the presence of vector support independently of
302
0
  // the machine type, since we may only use the vector register set when
303
0
  // supported by the kernel (and hypervisor).
304
0
  bool HaveVectorSupport = false;
305
0
  for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
306
0
    if (CPUFeatures[I] == "vx")
307
0
      HaveVectorSupport = true;
308
0
  }
309
0
310
0
  // Now check the processor machine type.
311
0
  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
312
0
    if (Lines[I].startswith("processor ")) {
313
0
      size_t Pos = Lines[I].find("machine = ");
314
0
      if (Pos != StringRef::npos) {
315
0
        Pos += sizeof("machine = ") - 1;
316
0
        unsigned int Id;
317
0
        if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
318
0
          if (Id >= 8561 && HaveVectorSupport)
319
0
            return "arch13";
320
0
          if (Id >= 3906 && HaveVectorSupport)
321
0
            return "z14";
322
0
          if (Id >= 2964 && HaveVectorSupport)
323
0
            return "z13";
324
0
          if (Id >= 2827)
325
0
            return "zEC12";
326
0
          if (Id >= 2817)
327
0
            return "z196";
328
0
        }
329
0
      }
330
0
      break;
331
0
    }
332
0
  }
333
0
334
0
  return "generic";
335
0
}
336
337
0
StringRef sys::detail::getHostCPUNameForBPF() {
338
0
#if !defined(__linux__) || !defined(__x86_64__)
339
0
  return "generic";
340
#else
341
  uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
342
      /* BPF_MOV64_IMM(BPF_REG_0, 0) */
343
    { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
344
      /* BPF_MOV64_IMM(BPF_REG_2, 1) */
345
      0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
346
      /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
347
      0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
348
      /* BPF_MOV64_IMM(BPF_REG_0, 1) */
349
      0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
350
      /* BPF_EXIT_INSN() */
351
      0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
352
353
  uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
354
      /* BPF_MOV64_IMM(BPF_REG_0, 0) */
355
    { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
356
      /* BPF_MOV64_IMM(BPF_REG_2, 1) */
357
      0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
358
      /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
359
      0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
360
      /* BPF_MOV64_IMM(BPF_REG_0, 1) */
361
      0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
362
      /* BPF_EXIT_INSN() */
363
      0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
364
365
  struct bpf_prog_load_attr {
366
    uint32_t prog_type;
367
    uint32_t insn_cnt;
368
    uint64_t insns;
369
    uint64_t license;
370
    uint32_t log_level;
371
    uint32_t log_size;
372
    uint64_t log_buf;
373
    uint32_t kern_version;
374
    uint32_t prog_flags;
375
  } attr = {};
376
  attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
377
  attr.insn_cnt = 5;
378
  attr.insns = (uint64_t)v3_insns;
379
  attr.license = (uint64_t)"DUMMY";
380
381
  int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr,
382
                   sizeof(attr));
383
  if (fd >= 0) {
384
    close(fd);
385
    return "v3";
386
  }
387
388
  /* Clear the whole attr in case its content changed by syscall. */
389
  memset(&attr, 0, sizeof(attr));
390
  attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
391
  attr.insn_cnt = 5;
392
  attr.insns = (uint64_t)v2_insns;
393
  attr.license = (uint64_t)"DUMMY";
394
  fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr));
395
  if (fd >= 0) {
396
    close(fd);
397
    return "v2";
398
  }
399
  return "v1";
400
#endif
401
}
402
403
#if defined(__i386__) || defined(_M_IX86) || \
404
    defined(__x86_64__) || defined(_M_X64)
405
406
enum VendorSignatures {
407
  SIG_INTEL = 0x756e6547 /* Genu */,
408
  SIG_AMD = 0x68747541 /* Auth */
409
};
410
411
// The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
412
// Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
413
// support. Consequently, for i386, the presence of CPUID is checked first
414
// via the corresponding eflags bit.
415
// Removal of cpuid.h header motivated by PR30384
416
// Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp
417
// or test-suite, but are used in external projects e.g. libstdcxx
418
42
static bool isCpuIdSupported() {
419
42
#if defined(__GNUC__) || defined(__clang__)
420
#if defined(__i386__)
421
  int __cpuid_supported;
422
  __asm__("  pushfl\n"
423
          "  popl   %%eax\n"
424
          "  movl   %%eax,%%ecx\n"
425
          "  xorl   $0x00200000,%%eax\n"
426
          "  pushl  %%eax\n"
427
          "  popfl\n"
428
          "  pushfl\n"
429
          "  popl   %%eax\n"
430
          "  movl   $0,%0\n"
431
          "  cmpl   %%eax,%%ecx\n"
432
          "  je     1f\n"
433
          "  movl   $1,%0\n"
434
          "1:"
435
          : "=r"(__cpuid_supported)
436
          :
437
          : "eax", "ecx");
438
  if (!__cpuid_supported)
439
    return false;
440
#endif
441
  return true;
442
42
#endif
443
42
  
return true0
;
444
42
}
445
446
/// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
447
/// the specified arguments.  If we can't run cpuid on the host, return true.
448
static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
449
168
                               unsigned *rECX, unsigned *rEDX) {
450
168
#if defined(__GNUC__) || defined(__clang__)
451
168
#if defined(__x86_64__)
452
168
  // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
453
168
  // FIXME: should we save this for Clang?
454
168
  __asm__("movq\t%%rbx, %%rsi\n\t"
455
168
          "cpuid\n\t"
456
168
          "xchgq\t%%rbx, %%rsi\n\t"
457
168
          : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
458
168
          : "a"(value));
459
168
  return false;
460
#elif defined(__i386__)
461
  __asm__("movl\t%%ebx, %%esi\n\t"
462
          "cpuid\n\t"
463
          "xchgl\t%%ebx, %%esi\n\t"
464
          : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
465
          : "a"(value));
466
  return false;
467
#else
468
  return true;
469
#endif
470
#elif defined(_MSC_VER)
471
  // The MSVC intrinsic is portable across x86 and x64.
472
  int registers[4];
473
  __cpuid(registers, value);
474
  *rEAX = registers[0];
475
  *rEBX = registers[1];
476
  *rECX = registers[2];
477
  *rEDX = registers[3];
478
  return false;
479
#else
480
  return true;
481
#endif
482
}
483
484
/// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
485
/// the 4 values in the specified arguments.  If we can't run cpuid on the host,
486
/// return true.
487
static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
488
                                 unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
489
42
                                 unsigned *rEDX) {
490
42
#if defined(__GNUC__) || defined(__clang__)
491
42
#if defined(__x86_64__)
492
42
  // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
493
42
  // FIXME: should we save this for Clang?
494
42
  __asm__("movq\t%%rbx, %%rsi\n\t"
495
42
          "cpuid\n\t"
496
42
          "xchgq\t%%rbx, %%rsi\n\t"
497
42
          : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
498
42
          : "a"(value), "c"(subleaf));
499
42
  return false;
500
#elif defined(__i386__)
501
  __asm__("movl\t%%ebx, %%esi\n\t"
502
          "cpuid\n\t"
503
          "xchgl\t%%ebx, %%esi\n\t"
504
          : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
505
          : "a"(value), "c"(subleaf));
506
  return false;
507
#else
508
  return true;
509
#endif
510
#elif defined(_MSC_VER)
511
  int registers[4];
512
  __cpuidex(registers, value, subleaf);
513
  *rEAX = registers[0];
514
  *rEBX = registers[1];
515
  *rECX = registers[2];
516
  *rEDX = registers[3];
517
  return false;
518
#else
519
  return true;
520
#endif
521
}
522
523
// Read control register 0 (XCR0). Used to detect features such as AVX.
524
42
static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
525
42
#if defined(__GNUC__) || defined(__clang__)
526
42
  // Check xgetbv; this uses a .byte sequence instead of the instruction
527
42
  // directly because older assemblers do not include support for xgetbv and
528
42
  // there is no easy way to conditionally compile based on the assembler used.
529
42
  __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
530
42
  return false;
531
#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
532
  unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
533
  *rEAX = Result;
534
  *rEDX = Result >> 32;
535
  return false;
536
#else
537
  return true;
538
#endif
539
}
540
541
static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
542
42
                                 unsigned *Model) {
543
42
  *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
544
42
  *Model = (EAX >> 4) & 0xf;  // Bits 4 - 7
545
42
  if (*Family == 6 || 
*Family == 0xf0
) {
546
42
    if (*Family == 0xf)
547
0
      // Examine extended family ID if family ID is F.
548
0
      *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
549
42
    // Examine extended model ID if family ID is 6 or F.
550
42
    *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
551
42
  }
552
42
}
553
554
static void
555
getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
556
                                unsigned Brand_id, unsigned Features,
557
                                unsigned Features2, unsigned Features3,
558
42
                                unsigned *Type, unsigned *Subtype) {
559
42
  if (Brand_id != 0)
560
0
    return;
561
42
  switch (Family) {
562
42
  case 3:
563
0
    *Type = X86::INTEL_i386;
564
0
    break;
565
42
  case 4:
566
0
    *Type = X86::INTEL_i486;
567
0
    break;
568
42
  case 5:
569
0
    if (Features & (1 << X86::FEATURE_MMX)) {
570
0
      *Type = X86::INTEL_PENTIUM_MMX;
571
0
      break;
572
0
    }
573
0
    *Type = X86::INTEL_PENTIUM;
574
0
    break;
575
42
  case 6:
576
42
    switch (Model) {
577
42
    case 0x01: // Pentium Pro processor
578
0
      *Type = X86::INTEL_PENTIUM_PRO;
579
0
      break;
580
42
    case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor,
581
0
               // model 03
582
0
    case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor,
583
0
               // model 05, and Intel Celeron processor, model 05
584
0
    case 0x06: // Celeron processor, model 06
585
0
      *Type = X86::INTEL_PENTIUM_II;
586
0
      break;
587
0
    case 0x07: // Pentium III processor, model 07, and Pentium III Xeon
588
0
               // processor, model 07
589
0
    case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor,
590
0
               // model 08, and Celeron processor, model 08
591
0
    case 0x0a: // Pentium III Xeon processor, model 0Ah
592
0
    case 0x0b: // Pentium III processor, model 0Bh
593
0
      *Type = X86::INTEL_PENTIUM_III;
594
0
      break;
595
0
    case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09.
596
0
    case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model
597
0
               // 0Dh. All processors are manufactured using the 90 nm process.
598
0
    case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579
599
0
               // Integrated Processor with Intel QuickAssist Technology
600
0
      *Type = X86::INTEL_PENTIUM_M;
601
0
      break;
602
0
    case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model
603
0
               // 0Eh. All processors are manufactured using the 65 nm process.
604
0
      *Type = X86::INTEL_CORE_DUO;
605
0
      break;   // yonah
606
0
    case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
607
0
               // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
608
0
               // mobile processor, Intel Core 2 Extreme processor, Intel
609
0
               // Pentium Dual-Core processor, Intel Xeon processor, model
610
0
               // 0Fh. All processors are manufactured using the 65 nm process.
611
0
    case 0x16: // Intel Celeron processor model 16h. All processors are
612
0
               // manufactured using the 65 nm process
613
0
      *Type = X86::INTEL_CORE2; // "core2"
614
0
      *Subtype = X86::INTEL_CORE2_65;
615
0
      break;
616
0
    case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
617
0
               // 17h. All processors are manufactured using the 45 nm process.
618
0
               //
619
0
               // 45nm: Penryn , Wolfdale, Yorkfield (XE)
620
0
    case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
621
0
               // the 45 nm process.
622
0
      *Type = X86::INTEL_CORE2; // "penryn"
623
0
      *Subtype = X86::INTEL_CORE2_45;
624
0
      break;
625
0
    case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
626
0
               // processors are manufactured using the 45 nm process.
627
0
    case 0x1e: // Intel(R) Core(TM) i7 CPU         870  @ 2.93GHz.
628
0
               // As found in a Summer 2010 model iMac.
629
0
    case 0x1f:
630
0
    case 0x2e:             // Nehalem EX
631
0
      *Type = X86::INTEL_COREI7; // "nehalem"
632
0
      *Subtype = X86::INTEL_COREI7_NEHALEM;
633
0
      break;
634
0
    case 0x25: // Intel Core i7, laptop version.
635
0
    case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
636
0
               // processors are manufactured using the 32 nm process.
637
0
    case 0x2f: // Westmere EX
638
0
      *Type = X86::INTEL_COREI7; // "westmere"
639
0
      *Subtype = X86::INTEL_COREI7_WESTMERE;
640
0
      break;
641
0
    case 0x2a: // Intel Core i7 processor. All processors are manufactured
642
0
               // using the 32 nm process.
643
0
    case 0x2d:
644
0
      *Type = X86::INTEL_COREI7; //"sandybridge"
645
0
      *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
646
0
      break;
647
0
    case 0x3a:
648
0
    case 0x3e:             // Ivy Bridge EP
649
0
      *Type = X86::INTEL_COREI7; // "ivybridge"
650
0
      *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
651
0
      break;
652
0
653
0
    // Haswell:
654
42
    case 0x3c:
655
42
    case 0x3f:
656
42
    case 0x45:
657
42
    case 0x46:
658
42
      *Type = X86::INTEL_COREI7; // "haswell"
659
42
      *Subtype = X86::INTEL_COREI7_HASWELL;
660
42
      break;
661
42
662
42
    // Broadwell:
663
42
    case 0x3d:
664
0
    case 0x47:
665
0
    case 0x4f:
666
0
    case 0x56:
667
0
      *Type = X86::INTEL_COREI7; // "broadwell"
668
0
      *Subtype = X86::INTEL_COREI7_BROADWELL;
669
0
      break;
670
0
671
0
    // Skylake:
672
0
    case 0x4e:              // Skylake mobile
673
0
    case 0x5e:              // Skylake desktop
674
0
    case 0x8e:              // Kaby Lake mobile
675
0
    case 0x9e:              // Kaby Lake desktop
676
0
      *Type = X86::INTEL_COREI7; // "skylake"
677
0
      *Subtype = X86::INTEL_COREI7_SKYLAKE;
678
0
      break;
679
0
680
0
    // Skylake Xeon:
681
0
    case 0x55:
682
0
      *Type = X86::INTEL_COREI7;
683
0
      if (Features3 & (1 << (X86::FEATURE_AVX512BF16 - 64)))
684
0
        *Subtype = X86::INTEL_COREI7_COOPERLAKE; // "cooperlake"
685
0
      else if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32)))
686
0
        *Subtype = X86::INTEL_COREI7_CASCADELAKE; // "cascadelake"
687
0
      else
688
0
        *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512"
689
0
      break;
690
0
691
0
    // Cannonlake:
692
0
    case 0x66:
693
0
      *Type = X86::INTEL_COREI7;
694
0
      *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake"
695
0
      break;
696
0
697
0
    // Icelake:
698
0
    case 0x7d:
699
0
    case 0x7e:
700
0
      *Type = X86::INTEL_COREI7;
701
0
      *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; // "icelake-client"
702
0
      break;
703
0
704
0
    // Icelake Xeon:
705
0
    case 0x6a:
706
0
    case 0x6c:
707
0
      *Type = X86::INTEL_COREI7;
708
0
      *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; // "icelake-server"
709
0
      break;
710
0
711
0
    case 0x1c: // Most 45 nm Intel Atom processors
712
0
    case 0x26: // 45 nm Atom Lincroft
713
0
    case 0x27: // 32 nm Atom Medfield
714
0
    case 0x35: // 32 nm Atom Midview
715
0
    case 0x36: // 32 nm Atom Midview
716
0
      *Type = X86::INTEL_BONNELL;
717
0
      break; // "bonnell"
718
0
719
0
    // Atom Silvermont codes from the Intel software optimization guide.
720
0
    case 0x37:
721
0
    case 0x4a:
722
0
    case 0x4d:
723
0
    case 0x5a:
724
0
    case 0x5d:
725
0
    case 0x4c: // really airmont
726
0
      *Type = X86::INTEL_SILVERMONT;
727
0
      break; // "silvermont"
728
0
    // Goldmont:
729
0
    case 0x5c: // Apollo Lake
730
0
    case 0x5f: // Denverton
731
0
      *Type = X86::INTEL_GOLDMONT;
732
0
      break; // "goldmont"
733
0
    case 0x7a:
734
0
      *Type = X86::INTEL_GOLDMONT_PLUS;
735
0
      break;
736
0
    case 0x86:
737
0
      *Type = X86::INTEL_TREMONT;
738
0
      break;
739
0
740
0
    case 0x57:
741
0
      *Type = X86::INTEL_KNL; // knl
742
0
      break;
743
0
744
0
    case 0x85:
745
0
      *Type = X86::INTEL_KNM; // knm
746
0
      break;
747
0
748
0
    default: // Unknown family 6 CPU, try to guess.
749
0
      if (Features & (1 << X86::FEATURE_AVX512VBMI2)) {
750
0
        *Type = X86::INTEL_COREI7;
751
0
        *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
752
0
        break;
753
0
      }
754
0
755
0
      if (Features & (1 << X86::FEATURE_AVX512VBMI)) {
756
0
        *Type = X86::INTEL_COREI7;
757
0
        *Subtype = X86::INTEL_COREI7_CANNONLAKE;
758
0
        break;
759
0
      }
760
0
761
0
      if (Features3 & (1 << (X86::FEATURE_AVX512BF16 - 64))) {
762
0
        *Type = X86::INTEL_COREI7;
763
0
        *Subtype = X86::INTEL_COREI7_COOPERLAKE;
764
0
        break;
765
0
      }
766
0
767
0
      if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) {
768
0
        *Type = X86::INTEL_COREI7;
769
0
        *Subtype = X86::INTEL_COREI7_CASCADELAKE;
770
0
        break;
771
0
      }
772
0
773
0
      if (Features & (1 << X86::FEATURE_AVX512VL)) {
774
0
        *Type = X86::INTEL_COREI7;
775
0
        *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
776
0
        break;
777
0
      }
778
0
779
0
      if (Features & (1 << X86::FEATURE_AVX512ER)) {
780
0
        *Type = X86::INTEL_KNL; // knl
781
0
        break;
782
0
      }
783
0
784
0
      if (Features3 & (1 << (X86::FEATURE_CLFLUSHOPT - 64))) {
785
0
        if (Features3 & (1 << (X86::FEATURE_SHA - 64))) {
786
0
          *Type = X86::INTEL_GOLDMONT;
787
0
        } else {
788
0
          *Type = X86::INTEL_COREI7;
789
0
          *Subtype = X86::INTEL_COREI7_SKYLAKE;
790
0
        }
791
0
        break;
792
0
      }
793
0
      if (Features3 & (1 << (X86::FEATURE_ADX - 64))) {
794
0
        *Type = X86::INTEL_COREI7;
795
0
        *Subtype = X86::INTEL_COREI7_BROADWELL;
796
0
        break;
797
0
      }
798
0
      if (Features & (1 << X86::FEATURE_AVX2)) {
799
0
        *Type = X86::INTEL_COREI7;
800
0
        *Subtype = X86::INTEL_COREI7_HASWELL;
801
0
        break;
802
0
      }
803
0
      if (Features & (1 << X86::FEATURE_AVX)) {
804
0
        *Type = X86::INTEL_COREI7;
805
0
        *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
806
0
        break;
807
0
      }
808
0
      if (Features & (1 << X86::FEATURE_SSE4_2)) {
809
0
        if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) {
810
0
          *Type = X86::INTEL_SILVERMONT;
811
0
        } else {
812
0
          *Type = X86::INTEL_COREI7;
813
0
          *Subtype = X86::INTEL_COREI7_NEHALEM;
814
0
        }
815
0
        break;
816
0
      }
817
0
      if (Features & (1 << X86::FEATURE_SSE4_1)) {
818
0
        *Type = X86::INTEL_CORE2; // "penryn"
819
0
        *Subtype = X86::INTEL_CORE2_45;
820
0
        break;
821
0
      }
822
0
      if (Features & (1 << X86::FEATURE_SSSE3)) {
823
0
        if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) {
824
0
          *Type = X86::INTEL_BONNELL; // "bonnell"
825
0
        } else {
826
0
          *Type = X86::INTEL_CORE2; // "core2"
827
0
          *Subtype = X86::INTEL_CORE2_65;
828
0
        }
829
0
        break;
830
0
      }
831
0
      if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) {
832
0
        *Type = X86::INTEL_CORE2; // "core2"
833
0
        *Subtype = X86::INTEL_CORE2_65;
834
0
        break;
835
0
      }
836
0
      if (Features & (1 << X86::FEATURE_SSE3)) {
837
0
        *Type = X86::INTEL_CORE_DUO;
838
0
        break;
839
0
      }
840
0
      if (Features & (1 << X86::FEATURE_SSE2)) {
841
0
        *Type = X86::INTEL_PENTIUM_M;
842
0
        break;
843
0
      }
844
0
      if (Features & (1 << X86::FEATURE_SSE)) {
845
0
        *Type = X86::INTEL_PENTIUM_III;
846
0
        break;
847
0
      }
848
0
      if (Features & (1 << X86::FEATURE_MMX)) {
849
0
        *Type = X86::INTEL_PENTIUM_II;
850
0
        break;
851
0
      }
852
0
      *Type = X86::INTEL_PENTIUM_PRO;
853
0
      break;
854
42
    }
855
42
    break;
856
42
  case 15: {
857
0
    if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) {
858
0
      *Type = X86::INTEL_NOCONA;
859
0
      break;
860
0
    }
861
0
    if (Features & (1 << X86::FEATURE_SSE3)) {
862
0
      *Type = X86::INTEL_PRESCOTT;
863
0
      break;
864
0
    }
865
0
    *Type = X86::INTEL_PENTIUM_IV;
866
0
    break;
867
0
  }
868
0
  default:
869
0
    break; /*"generic"*/
870
42
  }
871
42
}
872
873
static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
874
                                          unsigned Features, unsigned *Type,
875
0
                                          unsigned *Subtype) {
876
0
  // FIXME: this poorly matches the generated SubtargetFeatureKV table.  There
877
0
  // appears to be no way to generate the wide variety of AMD-specific targets
878
0
  // from the information returned from CPUID.
879
0
  switch (Family) {
880
0
  case 4:
881
0
    *Type = X86::AMD_i486;
882
0
    break;
883
0
  case 5:
884
0
    *Type = X86::AMDPENTIUM;
885
0
    switch (Model) {
886
0
    case 6:
887
0
    case 7:
888
0
      *Subtype = X86::AMDPENTIUM_K6;
889
0
      break; // "k6"
890
0
    case 8:
891
0
      *Subtype = X86::AMDPENTIUM_K62;
892
0
      break; // "k6-2"
893
0
    case 9:
894
0
    case 13:
895
0
      *Subtype = X86::AMDPENTIUM_K63;
896
0
      break; // "k6-3"
897
0
    case 10:
898
0
      *Subtype = X86::AMDPENTIUM_GEODE;
899
0
      break; // "geode"
900
0
    }
901
0
    break;
902
0
  case 6:
903
0
    if (Features & (1 << X86::FEATURE_SSE)) {
904
0
      *Type = X86::AMD_ATHLON_XP;
905
0
      break; // "athlon-xp"
906
0
    }
907
0
    *Type = X86::AMD_ATHLON;
908
0
    break; // "athlon"
909
0
  case 15:
910
0
    if (Features & (1 << X86::FEATURE_SSE3)) {
911
0
      *Type = X86::AMD_K8SSE3;
912
0
      break; // "k8-sse3"
913
0
    }
914
0
    *Type = X86::AMD_K8;
915
0
    break; // "k8"
916
0
  case 16:
917
0
    *Type = X86::AMDFAM10H; // "amdfam10"
918
0
    switch (Model) {
919
0
    case 2:
920
0
      *Subtype = X86::AMDFAM10H_BARCELONA;
921
0
      break;
922
0
    case 4:
923
0
      *Subtype = X86::AMDFAM10H_SHANGHAI;
924
0
      break;
925
0
    case 8:
926
0
      *Subtype = X86::AMDFAM10H_ISTANBUL;
927
0
      break;
928
0
    }
929
0
    break;
930
0
  case 20:
931
0
    *Type = X86::AMD_BTVER1;
932
0
    break; // "btver1";
933
0
  case 21:
934
0
    *Type = X86::AMDFAM15H;
935
0
    if (Model >= 0x60 && Model <= 0x7f) {
936
0
      *Subtype = X86::AMDFAM15H_BDVER4;
937
0
      break; // "bdver4"; 60h-7Fh: Excavator
938
0
    }
939
0
    if (Model >= 0x30 && Model <= 0x3f) {
940
0
      *Subtype = X86::AMDFAM15H_BDVER3;
941
0
      break; // "bdver3"; 30h-3Fh: Steamroller
942
0
    }
943
0
    if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) {
944
0
      *Subtype = X86::AMDFAM15H_BDVER2;
945
0
      break; // "bdver2"; 02h, 10h-1Fh: Piledriver
946
0
    }
947
0
    if (Model <= 0x0f) {
948
0
      *Subtype = X86::AMDFAM15H_BDVER1;
949
0
      break; // "bdver1"; 00h-0Fh: Bulldozer
950
0
    }
951
0
    break;
952
0
  case 22:
953
0
    *Type = X86::AMD_BTVER2;
954
0
    break; // "btver2"
955
0
  case 23:
956
0
    *Type = X86::AMDFAM17H;
957
0
    if (Model >= 0x30 && Model <= 0x3f) {
958
0
      *Subtype = X86::AMDFAM17H_ZNVER2;
959
0
      break; // "znver2"; 30h-3fh: Zen2
960
0
    }
961
0
    if (Model <= 0x0f) {
962
0
      *Subtype = X86::AMDFAM17H_ZNVER1;
963
0
      break; // "znver1"; 00h-0Fh: Zen1
964
0
    }
965
0
    break;
966
0
  default:
967
0
    break; // "generic"
968
0
  }
969
0
}
970
971
static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
972
                                 unsigned *FeaturesOut, unsigned *Features2Out,
973
42
                                 unsigned *Features3Out) {
974
42
  unsigned Features = 0;
975
42
  unsigned Features2 = 0;
976
42
  unsigned Features3 = 0;
977
42
  unsigned EAX, EBX;
978
42
979
756
  auto setFeature = [&](unsigned F) {
980
756
    if (F < 32)
981
672
      Features |= 1U << (F & 0x1f);
982
84
    else if (F < 64)
983
0
      Features2 |= 1U << ((F - 32) & 0x1f);
984
84
    else if (F < 96)
985
84
      Features3 |= 1U << ((F - 64) & 0x1f);
986
84
    else
987
84
      
llvm_unreachable0
("Unexpected FeatureBit");
988
756
  };
989
42
990
42
  if ((EDX >> 15) & 1)
991
42
    setFeature(X86::FEATURE_CMOV);
992
42
  if ((EDX >> 23) & 1)
993
42
    setFeature(X86::FEATURE_MMX);
994
42
  if ((EDX >> 25) & 1)
995
42
    setFeature(X86::FEATURE_SSE);
996
42
  if ((EDX >> 26) & 1)
997
42
    setFeature(X86::FEATURE_SSE2);
998
42
999
42
  if ((ECX >> 0) & 1)
1000
42
    setFeature(X86::FEATURE_SSE3);
1001
42
  if ((ECX >> 1) & 1)
1002
42
    setFeature(X86::FEATURE_PCLMUL);
1003
42
  if ((ECX >> 9) & 1)
1004
42
    setFeature(X86::FEATURE_SSSE3);
1005
42
  if ((ECX >> 12) & 1)
1006
42
    setFeature(X86::FEATURE_FMA);
1007
42
  if ((ECX >> 19) & 1)
1008
42
    setFeature(X86::FEATURE_SSE4_1);
1009
42
  if ((ECX >> 20) & 1)
1010
42
    setFeature(X86::FEATURE_SSE4_2);
1011
42
  if ((ECX >> 23) & 1)
1012
42
    setFeature(X86::FEATURE_POPCNT);
1013
42
  if ((ECX >> 25) & 1)
1014
42
    setFeature(X86::FEATURE_AES);
1015
42
1016
42
  if ((ECX >> 22) & 1)
1017
42
    setFeature(X86::FEATURE_MOVBE);
1018
42
1019
42
  // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1020
42
  // indicates that the AVX registers will be saved and restored on context
1021
42
  // switch, then we have full AVX support.
1022
42
  const unsigned AVXBits = (1 << 27) | (1 << 28);
1023
42
  bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
1024
42
                ((EAX & 0x6) == 0x6);
1025
42
  bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
1026
42
1027
42
  if (HasAVX)
1028
42
    setFeature(X86::FEATURE_AVX);
1029
42
1030
42
  bool HasLeaf7 =
1031
42
      MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1032
42
1033
42
  if (HasLeaf7 && ((EBX >> 3) & 1))
1034
42
    setFeature(X86::FEATURE_BMI);
1035
42
  if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
1036
42
    setFeature(X86::FEATURE_AVX2);
1037
42
  if (HasLeaf7 && ((EBX >> 9) & 1))
1038
42
    setFeature(X86::FEATURE_BMI2);
1039
42
  if (HasLeaf7 && ((EBX >> 16) & 1) && 
HasAVX512Save0
)
1040
0
    setFeature(X86::FEATURE_AVX512F);
1041
42
  if (HasLeaf7 && ((EBX >> 17) & 1) && 
HasAVX512Save0
)
1042
0
    setFeature(X86::FEATURE_AVX512DQ);
1043
42
  if (HasLeaf7 && ((EBX >> 19) & 1))
1044
0
    setFeature(X86::FEATURE_ADX);
1045
42
  if (HasLeaf7 && ((EBX >> 21) & 1) && 
HasAVX512Save0
)
1046
0
    setFeature(X86::FEATURE_AVX512IFMA);
1047
42
  if (HasLeaf7 && ((EBX >> 23) & 1))
1048
0
    setFeature(X86::FEATURE_CLFLUSHOPT);
1049
42
  if (HasLeaf7 && ((EBX >> 26) & 1) && 
HasAVX512Save0
)
1050
0
    setFeature(X86::FEATURE_AVX512PF);
1051
42
  if (HasLeaf7 && ((EBX >> 27) & 1) && 
HasAVX512Save0
)
1052
0
    setFeature(X86::FEATURE_AVX512ER);
1053
42
  if (HasLeaf7 && ((EBX >> 28) & 1) && 
HasAVX512Save0
)
1054
0
    setFeature(X86::FEATURE_AVX512CD);
1055
42
  if (HasLeaf7 && ((EBX >> 29) & 1))
1056
0
    setFeature(X86::FEATURE_SHA);
1057
42
  if (HasLeaf7 && ((EBX >> 30) & 1) && 
HasAVX512Save0
)
1058
0
    setFeature(X86::FEATURE_AVX512BW);
1059
42
  if (HasLeaf7 && ((EBX >> 31) & 1) && 
HasAVX512Save0
)
1060
0
    setFeature(X86::FEATURE_AVX512VL);
1061
42
1062
42
  if (HasLeaf7 && ((ECX >> 1) & 1) && 
HasAVX512Save0
)
1063
0
    setFeature(X86::FEATURE_AVX512VBMI);
1064
42
  if (HasLeaf7 && ((ECX >> 6) & 1) && 
HasAVX512Save0
)
1065
0
    setFeature(X86::FEATURE_AVX512VBMI2);
1066
42
  if (HasLeaf7 && ((ECX >> 8) & 1))
1067
0
    setFeature(X86::FEATURE_GFNI);
1068
42
  if (HasLeaf7 && ((ECX >> 10) & 1) && 
HasAVX0
)
1069
0
    setFeature(X86::FEATURE_VPCLMULQDQ);
1070
42
  if (HasLeaf7 && ((ECX >> 11) & 1) && 
HasAVX512Save0
)
1071
0
    setFeature(X86::FEATURE_AVX512VNNI);
1072
42
  if (HasLeaf7 && ((ECX >> 12) & 1) && 
HasAVX512Save0
)
1073
0
    setFeature(X86::FEATURE_AVX512BITALG);
1074
42
  if (HasLeaf7 && ((ECX >> 14) & 1) && 
HasAVX512Save0
)
1075
0
    setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1076
42
1077
42
  if (HasLeaf7 && ((EDX >> 2) & 1) && 
HasAVX512Save0
)
1078
0
    setFeature(X86::FEATURE_AVX5124VNNIW);
1079
42
  if (HasLeaf7 && ((EDX >> 3) & 1) && 
HasAVX512Save0
)
1080
0
    setFeature(X86::FEATURE_AVX5124FMAPS);
1081
42
1082
42
  unsigned MaxExtLevel;
1083
42
  getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1084
42
1085
42
  bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1086
42
                     !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1087
42
  if (HasExtLeaf1 && ((ECX >> 6) & 1))
1088
0
    setFeature(X86::FEATURE_SSE4_A);
1089
42
  if (HasExtLeaf1 && ((ECX >> 11) & 1))
1090
0
    setFeature(X86::FEATURE_XOP);
1091
42
  if (HasExtLeaf1 && ((ECX >> 16) & 1))
1092
0
    setFeature(X86::FEATURE_FMA4);
1093
42
1094
42
  if (HasExtLeaf1 && ((EDX >> 29) & 1))
1095
42
    setFeature(X86::FEATURE_EM64T);
1096
42
1097
42
  *FeaturesOut  = Features;
1098
42
  *Features2Out = Features2;
1099
42
  *Features3Out = Features3;
1100
42
}
1101
1102
42
StringRef sys::getHostCPUName() {
1103
42
  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1104
42
  unsigned MaxLeaf, Vendor;
1105
42
1106
42
#if defined(__GNUC__) || defined(__clang__)
1107
42
  //FIXME: include cpuid.h from clang or copy __get_cpuid_max here
1108
42
  // and simplify it to not invoke __cpuid (like cpu_model.c in
1109
42
  // compiler-rt/lib/builtins/cpu_model.c?
1110
42
  // Opting for the second option.
1111
42
  if(!isCpuIdSupported())
1112
0
    return "generic";
1113
42
#endif
1114
42
  if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1)
1115
0
    return "generic";
1116
42
  getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1117
42
1118
42
  unsigned Brand_id = EBX & 0xff;
1119
42
  unsigned Family = 0, Model = 0;
1120
42
  unsigned Features = 0, Features2 = 0, Features3 = 0;
1121
42
  detectX86FamilyModel(EAX, &Family, &Model);
1122
42
  getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2, &Features3);
1123
42
1124
42
  unsigned Type = 0;
1125
42
  unsigned Subtype = 0;
1126
42
1127
42
  if (Vendor == SIG_INTEL) {
1128
42
    getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features,
1129
42
                                    Features2, Features3, &Type, &Subtype);
1130
42
  } else 
if (0
Vendor == SIG_AMD0
) {
1131
0
    getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype);
1132
0
  }
1133
42
1134
42
  // Check subtypes first since those are more specific.
1135
42
#define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \
1136
546
  if (Subtype == X86::ENUM) \
1137
546
    
return ARCHNAME42
;
1138
504
#include 
"llvm/Support/X86TargetParser.def"42
1139
504
1140
504
  // Now check types.
1141
504
#define X86_CPU_TYPE(ARCHNAME, ENUM) \
1142
504
  
if (0
Type == X86::ENUM0
) \
1143
0
    return ARCHNAME;
1144
504
#include 
"llvm/Support/X86TargetParser.def"0
1145
0
1146
0
  return "generic";
1147
0
}
1148
1149
#elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
1150
StringRef sys::getHostCPUName() {
1151
  host_basic_info_data_t hostInfo;
1152
  mach_msg_type_number_t infoCount;
1153
1154
  infoCount = HOST_BASIC_INFO_COUNT;
1155
  mach_port_t hostPort = mach_host_self();
1156
  host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1157
            &infoCount);
1158
  mach_port_deallocate(mach_task_self(), hostPort);
1159
1160
  if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1161
    return "generic";
1162
1163
  switch (hostInfo.cpu_subtype) {
1164
  case CPU_SUBTYPE_POWERPC_601:
1165
    return "601";
1166
  case CPU_SUBTYPE_POWERPC_602:
1167
    return "602";
1168
  case CPU_SUBTYPE_POWERPC_603:
1169
    return "603";
1170
  case CPU_SUBTYPE_POWERPC_603e:
1171
    return "603e";
1172
  case CPU_SUBTYPE_POWERPC_603ev:
1173
    return "603ev";
1174
  case CPU_SUBTYPE_POWERPC_604:
1175
    return "604";
1176
  case CPU_SUBTYPE_POWERPC_604e:
1177
    return "604e";
1178
  case CPU_SUBTYPE_POWERPC_620:
1179
    return "620";
1180
  case CPU_SUBTYPE_POWERPC_750:
1181
    return "750";
1182
  case CPU_SUBTYPE_POWERPC_7400:
1183
    return "7400";
1184
  case CPU_SUBTYPE_POWERPC_7450:
1185
    return "7450";
1186
  case CPU_SUBTYPE_POWERPC_970:
1187
    return "970";
1188
  default:;
1189
  }
1190
1191
  return "generic";
1192
}
1193
#elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
1194
StringRef sys::getHostCPUName() {
1195
  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1196
  StringRef Content = P ? P->getBuffer() : "";
1197
  return detail::getHostCPUNameForPowerPC(Content);
1198
}
1199
#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1200
StringRef sys::getHostCPUName() {
1201
  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1202
  StringRef Content = P ? P->getBuffer() : "";
1203
  return detail::getHostCPUNameForARM(Content);
1204
}
1205
#elif defined(__linux__) && defined(__s390x__)
1206
StringRef sys::getHostCPUName() {
1207
  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1208
  StringRef Content = P ? P->getBuffer() : "";
1209
  return detail::getHostCPUNameForS390x(Content);
1210
}
1211
#else
1212
StringRef sys::getHostCPUName() { return "generic"; }
1213
#endif
1214
1215
#if defined(__linux__) && defined(__x86_64__)
1216
// On Linux, the number of physical cores can be computed from /proc/cpuinfo,
1217
// using the number of unique physical/core id pairs. The following
1218
// implementation reads the /proc/cpuinfo format on an x86_64 system.
1219
static int computeHostNumPhysicalCores() {
1220
  // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be
1221
  // mmapped because it appears to have 0 size.
1222
  llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text =
1223
      llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
1224
  if (std::error_code EC = Text.getError()) {
1225
    llvm::errs() << "Can't read "
1226
                 << "/proc/cpuinfo: " << EC.message() << "\n";
1227
    return -1;
1228
  }
1229
  SmallVector<StringRef, 8> strs;
1230
  (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1,
1231
                             /*KeepEmpty=*/false);
1232
  int CurPhysicalId = -1;
1233
  int CurCoreId = -1;
1234
  SmallSet<std::pair<int, int>, 32> UniqueItems;
1235
  for (auto &Line : strs) {
1236
    Line = Line.trim();
1237
    if (!Line.startswith("physical id") && !Line.startswith("core id"))
1238
      continue;
1239
    std::pair<StringRef, StringRef> Data = Line.split(':');
1240
    auto Name = Data.first.trim();
1241
    auto Val = Data.second.trim();
1242
    if (Name == "physical id") {
1243
      assert(CurPhysicalId == -1 &&
1244
             "Expected a core id before seeing another physical id");
1245
      Val.getAsInteger(10, CurPhysicalId);
1246
    }
1247
    if (Name == "core id") {
1248
      assert(CurCoreId == -1 &&
1249
             "Expected a physical id before seeing another core id");
1250
      Val.getAsInteger(10, CurCoreId);
1251
    }
1252
    if (CurPhysicalId != -1 && CurCoreId != -1) {
1253
      UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId));
1254
      CurPhysicalId = -1;
1255
      CurCoreId = -1;
1256
    }
1257
  }
1258
  return UniqueItems.size();
1259
}
1260
#elif defined(__APPLE__) && defined(__x86_64__)
1261
#include <sys/param.h>
1262
#include <sys/sysctl.h>
1263
1264
// Gets the number of *physical cores* on the machine.
1265
3.35k
static int computeHostNumPhysicalCores() {
1266
3.35k
  uint32_t count;
1267
3.35k
  size_t len = sizeof(count);
1268
3.35k
  sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0);
1269
3.35k
  if (count < 1) {
1270
0
    int nm[2];
1271
0
    nm[0] = CTL_HW;
1272
0
    nm[1] = HW_AVAILCPU;
1273
0
    sysctl(nm, 2, &count, &len, NULL, 0);
1274
0
    if (count < 1)
1275
0
      return -1;
1276
3.35k
  }
1277
3.35k
  return count;
1278
3.35k
}
1279
#else
1280
// On other systems, return -1 to indicate unknown.
1281
static int computeHostNumPhysicalCores() { return -1; }
1282
#endif
1283
1284
3.37k
int sys::getHostNumPhysicalCores() {
1285
3.37k
  static int NumCores = computeHostNumPhysicalCores();
1286
3.37k
  return NumCores;
1287
3.37k
}
1288
1289
#if defined(__i386__) || defined(_M_IX86) || \
1290
    defined(__x86_64__) || defined(_M_X64)
1291
0
bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1292
0
  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1293
0
  unsigned MaxLevel;
1294
0
  union {
1295
0
    unsigned u[3];
1296
0
    char c[12];
1297
0
  } text;
1298
0
1299
0
  if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) ||
1300
0
      MaxLevel < 1)
1301
0
    return false;
1302
0
1303
0
  getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1304
0
1305
0
  Features["cx8"]    = (EDX >>  8) & 1;
1306
0
  Features["cmov"]   = (EDX >> 15) & 1;
1307
0
  Features["mmx"]    = (EDX >> 23) & 1;
1308
0
  Features["fxsr"]   = (EDX >> 24) & 1;
1309
0
  Features["sse"]    = (EDX >> 25) & 1;
1310
0
  Features["sse2"]   = (EDX >> 26) & 1;
1311
0
1312
0
  Features["sse3"]   = (ECX >>  0) & 1;
1313
0
  Features["pclmul"] = (ECX >>  1) & 1;
1314
0
  Features["ssse3"]  = (ECX >>  9) & 1;
1315
0
  Features["cx16"]   = (ECX >> 13) & 1;
1316
0
  Features["sse4.1"] = (ECX >> 19) & 1;
1317
0
  Features["sse4.2"] = (ECX >> 20) & 1;
1318
0
  Features["movbe"]  = (ECX >> 22) & 1;
1319
0
  Features["popcnt"] = (ECX >> 23) & 1;
1320
0
  Features["aes"]    = (ECX >> 25) & 1;
1321
0
  Features["rdrnd"]  = (ECX >> 30) & 1;
1322
0
1323
0
  // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1324
0
  // indicates that the AVX registers will be saved and restored on context
1325
0
  // switch, then we have full AVX support.
1326
0
  bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) &&
1327
0
                    !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6);
1328
0
  // AVX512 requires additional context to be saved by the OS.
1329
0
  bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
1330
0
1331
0
  Features["avx"]   = HasAVXSave;
1332
0
  Features["fma"]   = ((ECX >> 12) & 1) && HasAVXSave;
1333
0
  // Only enable XSAVE if OS has enabled support for saving YMM state.
1334
0
  Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave;
1335
0
  Features["f16c"]  = ((ECX >> 29) & 1) && HasAVXSave;
1336
0
1337
0
  unsigned MaxExtLevel;
1338
0
  getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1339
0
1340
0
  bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1341
0
                     !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1342
0
  Features["sahf"]   = HasExtLeaf1 && ((ECX >>  0) & 1);
1343
0
  Features["lzcnt"]  = HasExtLeaf1 && ((ECX >>  5) & 1);
1344
0
  Features["sse4a"]  = HasExtLeaf1 && ((ECX >>  6) & 1);
1345
0
  Features["prfchw"] = HasExtLeaf1 && ((ECX >>  8) & 1);
1346
0
  Features["xop"]    = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
1347
0
  Features["lwp"]    = HasExtLeaf1 && ((ECX >> 15) & 1);
1348
0
  Features["fma4"]   = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
1349
0
  Features["tbm"]    = HasExtLeaf1 && ((ECX >> 21) & 1);
1350
0
  Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
1351
0
1352
0
  Features["64bit"]  = HasExtLeaf1 && ((EDX >> 29) & 1);
1353
0
1354
0
  // Miscellaneous memory related features, detected by
1355
0
  // using the 0x80000008 leaf of the CPUID instruction
1356
0
  bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1357
0
                     !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1358
0
  Features["clzero"]   = HasExtLeaf8 && ((EBX >> 0) & 1);
1359
0
  Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1);
1360
0
1361
0
  bool HasLeaf7 =
1362
0
      MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1363
0
1364
0
  Features["fsgsbase"]   = HasLeaf7 && ((EBX >>  0) & 1);
1365
0
  Features["sgx"]        = HasLeaf7 && ((EBX >>  2) & 1);
1366
0
  Features["bmi"]        = HasLeaf7 && ((EBX >>  3) & 1);
1367
0
  // AVX2 is only supported if we have the OS save support from AVX.
1368
0
  Features["avx2"]       = HasLeaf7 && ((EBX >>  5) & 1) && HasAVXSave;
1369
0
  Features["bmi2"]       = HasLeaf7 && ((EBX >>  8) & 1);
1370
0
  Features["invpcid"]    = HasLeaf7 && ((EBX >> 10) & 1);
1371
0
  Features["rtm"]        = HasLeaf7 && ((EBX >> 11) & 1);
1372
0
  Features["mpx"]        = HasLeaf7 && ((EBX >> 14) & 1);
1373
0
  // AVX512 is only supported if the OS supports the context save for it.
1374
0
  Features["avx512f"]    = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
1375
0
  Features["avx512dq"]   = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
1376
0
  Features["rdseed"]     = HasLeaf7 && ((EBX >> 18) & 1);
1377
0
  Features["adx"]        = HasLeaf7 && ((EBX >> 19) & 1);
1378
0
  Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
1379
0
  Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
1380
0
  Features["clwb"]       = HasLeaf7 && ((EBX >> 24) & 1);
1381
0
  Features["avx512pf"]   = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
1382
0
  Features["avx512er"]   = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
1383
0
  Features["avx512cd"]   = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
1384
0
  Features["sha"]        = HasLeaf7 && ((EBX >> 29) & 1);
1385
0
  Features["avx512bw"]   = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
1386
0
  Features["avx512vl"]   = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
1387
0
1388
0
  Features["prefetchwt1"]     = HasLeaf7 && ((ECX >>  0) & 1);
1389
0
  Features["avx512vbmi"]      = HasLeaf7 && ((ECX >>  1) & 1) && HasAVX512Save;
1390
0
  Features["pku"]             = HasLeaf7 && ((ECX >>  4) & 1);
1391
0
  Features["waitpkg"]         = HasLeaf7 && ((ECX >>  5) & 1);
1392
0
  Features["avx512vbmi2"]     = HasLeaf7 && ((ECX >>  6) & 1) && HasAVX512Save;
1393
0
  Features["shstk"]           = HasLeaf7 && ((ECX >>  7) & 1);
1394
0
  Features["gfni"]            = HasLeaf7 && ((ECX >>  8) & 1);
1395
0
  Features["vaes"]            = HasLeaf7 && ((ECX >>  9) & 1) && HasAVXSave;
1396
0
  Features["vpclmulqdq"]      = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave;
1397
0
  Features["avx512vnni"]      = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save;
1398
0
  Features["avx512bitalg"]    = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save;
1399
0
  Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
1400
0
  Features["rdpid"]           = HasLeaf7 && ((ECX >> 22) & 1);
1401
0
  Features["cldemote"]        = HasLeaf7 && ((ECX >> 25) & 1);
1402
0
  Features["movdiri"]         = HasLeaf7 && ((ECX >> 27) & 1);
1403
0
  Features["movdir64b"]       = HasLeaf7 && ((ECX >> 28) & 1);
1404
0
  Features["enqcmd"]          = HasLeaf7 && ((ECX >> 29) & 1);
1405
0
1406
0
  // There are two CPUID leafs which information associated with the pconfig
1407
0
  // instruction:
1408
0
  // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th
1409
0
  // bit of EDX), while the EAX=0x1b leaf returns information on the
1410
0
  // availability of specific pconfig leafs.
1411
0
  // The target feature here only refers to the the first of these two.
1412
0
  // Users might need to check for the availability of specific pconfig
1413
0
  // leaves using cpuid, since that information is ignored while
1414
0
  // detecting features using the "-march=native" flag.
1415
0
  // For more info, see X86 ISA docs.
1416
0
  Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
1417
0
  bool HasLeaf7Subleaf1 =
1418
0
      MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1419
0
  Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
1420
0
1421
0
  bool HasLeafD = MaxLevel >= 0xd &&
1422
0
                  !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1423
0
1424
0
  // Only enable XSAVE if OS has enabled support for saving YMM state.
1425
0
  Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave;
1426
0
  Features["xsavec"]   = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;
1427
0
  Features["xsaves"]   = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;
1428
0
1429
0
  bool HasLeaf14 = MaxLevel >= 0x14 &&
1430
0
                  !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1431
0
1432
0
  Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1);
1433
0
1434
0
  return true;
1435
0
}
1436
#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1437
bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1438
  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1439
  if (!P)
1440
    return false;
1441
1442
  SmallVector<StringRef, 32> Lines;
1443
  P->getBuffer().split(Lines, "\n");
1444
1445
  SmallVector<StringRef, 32> CPUFeatures;
1446
1447
  // Look for the CPU features.
1448
  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1449
    if (Lines[I].startswith("Features")) {
1450
      Lines[I].split(CPUFeatures, ' ');
1451
      break;
1452
    }
1453
1454
#if defined(__aarch64__)
1455
  // Keep track of which crypto features we have seen
1456
  enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1457
  uint32_t crypto = 0;
1458
#endif
1459
1460
  for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
1461
    StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
1462
#if defined(__aarch64__)
1463
                                   .Case("asimd", "neon")
1464
                                   .Case("fp", "fp-armv8")
1465
                                   .Case("crc32", "crc")
1466
#else
1467
                                   .Case("half", "fp16")
1468
                                   .Case("neon", "neon")
1469
                                   .Case("vfpv3", "vfp3")
1470
                                   .Case("vfpv3d16", "d16")
1471
                                   .Case("vfpv4", "vfp4")
1472
                                   .Case("idiva", "hwdiv-arm")
1473
                                   .Case("idivt", "hwdiv")
1474
#endif
1475
                                   .Default("");
1476
1477
#if defined(__aarch64__)
1478
    // We need to check crypto separately since we need all of the crypto
1479
    // extensions to enable the subtarget feature
1480
    if (CPUFeatures[I] == "aes")
1481
      crypto |= CAP_AES;
1482
    else if (CPUFeatures[I] == "pmull")
1483
      crypto |= CAP_PMULL;
1484
    else if (CPUFeatures[I] == "sha1")
1485
      crypto |= CAP_SHA1;
1486
    else if (CPUFeatures[I] == "sha2")
1487
      crypto |= CAP_SHA2;
1488
#endif
1489
1490
    if (LLVMFeatureStr != "")
1491
      Features[LLVMFeatureStr] = true;
1492
  }
1493
1494
#if defined(__aarch64__)
1495
  // If we have all crypto bits we can add the feature
1496
  if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1497
    Features["crypto"] = true;
1498
#endif
1499
1500
  return true;
1501
}
1502
#else
1503
bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
1504
#endif
1505
1506
118k
std::string sys::getProcessTriple() {
1507
118k
  std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
1508
118k
  Triple PT(Triple::normalize(TargetTripleString));
1509
118k
1510
118k
  if (sizeof(void *) == 8 && PT.isArch32Bit())
1511
0
    PT = PT.get64BitArchVariant();
1512
118k
  if (sizeof(void *) == 4 && 
PT.isArch64Bit()0
)
1513
0
    PT = PT.get32BitArchVariant();
1514
118k
1515
118k
  return PT.str();
1516
118k
}