Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp
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//===-- AArch64A53Fix835769.cpp -------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// This pass changes code to work around Cortex-A53 erratum 835769.
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// It works around it by inserting a nop instruction in code sequences that
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// in some circumstances may trigger the erratum.
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// It inserts a nop instruction between a sequence of the following 2 classes
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// of instructions:
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// instr 1: mem-instr (including loads, stores and prefetches).
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// instr 2: non-SIMD integer multiply-accumulate writing 64-bit X registers.
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "aarch64-fix-cortex-a53-835769"
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STATISTIC(NumNopsAdded, "Number of Nops added to work around erratum 835769");
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//===----------------------------------------------------------------------===//
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// Helper functions
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// Is the instruction a match for the instruction that comes first in the
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// sequence of instructions that can trigger the erratum?
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static bool isFirstInstructionInSequence(MachineInstr *MI) {
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  // Must return true if this instruction is a load, a store or a prefetch.
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  switch (MI->getOpcode()) {
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  case AArch64::PRFMl:
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0
  case AArch64::PRFMroW:
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  case AArch64::PRFMroX:
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  case AArch64::PRFMui:
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  case AArch64::PRFUMi:
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    return true;
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  default:
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    return MI->mayLoadOrStore();
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  }
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}
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// Is the instruction a match for the instruction that comes second in the
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// sequence that can trigger the erratum?
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static bool isSecondInstructionInSequence(MachineInstr *MI) {
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  // Must return true for non-SIMD integer multiply-accumulates, writing
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  // to a 64-bit register.
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  switch (MI->getOpcode()) {
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  // Erratum cannot be triggered when the destination register is 32 bits,
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  // therefore only include the following.
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  case AArch64::MSUBXrrr:
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  case AArch64::MADDXrrr:
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  case AArch64::SMADDLrrr:
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  case AArch64::SMSUBLrrr:
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  case AArch64::UMADDLrrr:
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  case AArch64::UMSUBLrrr:
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    // Erratum can only be triggered by multiply-adds, not by regular
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    // non-accumulating multiplies, i.e. when Ra=XZR='11111'
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    return MI->getOperand(3).getReg() != AArch64::XZR;
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  default:
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    return false;
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  }
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}
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//===----------------------------------------------------------------------===//
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namespace {
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class AArch64A53Fix835769 : public MachineFunctionPass {
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  const TargetInstrInfo *TII;
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public:
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  static char ID;
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  explicit AArch64A53Fix835769() : MachineFunctionPass(ID) {
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    initializeAArch64A53Fix835769Pass(*PassRegistry::getPassRegistry());
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  }
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  bool runOnMachineFunction(MachineFunction &F) override;
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  MachineFunctionProperties getRequiredProperties() const override {
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    return MachineFunctionProperties().set(
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        MachineFunctionProperties::Property::NoVRegs);
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  }
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  StringRef getPassName() const override {
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    return "Workaround A53 erratum 835769 pass";
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  }
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  void getAnalysisUsage(AnalysisUsage &AU) const override {
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    AU.setPreservesCFG();
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    MachineFunctionPass::getAnalysisUsage(AU);
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  }
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private:
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  bool runOnBasicBlock(MachineBasicBlock &MBB);
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};
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char AArch64A53Fix835769::ID = 0;
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} // end anonymous namespace
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INITIALIZE_PASS(AArch64A53Fix835769, "aarch64-fix-cortex-a53-835769-pass",
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                "AArch64 fix for A53 erratum 835769", false, false)
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//===----------------------------------------------------------------------===//
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bool
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AArch64A53Fix835769::runOnMachineFunction(MachineFunction &F) {
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  LLVM_DEBUG(dbgs() << "***** AArch64A53Fix835769 *****\n");
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  bool Changed = false;
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  TII = F.getSubtarget().getInstrInfo();
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  for (auto &MBB : F) {
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    Changed |= runOnBasicBlock(MBB);
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  }
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  return Changed;
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}
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// Return the block that was fallen through to get to MBB, if any,
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// otherwise nullptr.
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static MachineBasicBlock *getBBFallenThrough(MachineBasicBlock *MBB,
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                                             const TargetInstrInfo *TII) {
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  // Get the previous machine basic block in the function.
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  MachineFunction::iterator MBBI(MBB);
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  // Can't go off top of function.
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  if (MBBI == MBB->getParent()->begin())
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    return nullptr;
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  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
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  SmallVector<MachineOperand, 2> Cond;
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  MachineBasicBlock *PrevBB = &*std::prev(MBBI);
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  for (MachineBasicBlock *S : MBB->predecessors())
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    if (S == PrevBB && !TII->analyzeBranch(*PrevBB, TBB, FBB, Cond) && !TBB &&
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        !FBB)
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      return S;
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  return nullptr;
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}
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// Iterate through fallen through blocks trying to find a previous non-pseudo if
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// there is one, otherwise return nullptr. Only look for instructions in
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// previous blocks, not the current block, since we only use this to look at
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// previous blocks.
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static MachineInstr *getLastNonPseudo(MachineBasicBlock &MBB,
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                                      const TargetInstrInfo *TII) {
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  MachineBasicBlock *FMBB = &MBB;
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  // If there is no non-pseudo in the current block, loop back around and try
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  // the previous block (if there is one).
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  while ((FMBB = getBBFallenThrough(FMBB, TII))) {
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    for (MachineInstr &I : make_range(FMBB->rbegin(), FMBB->rend()))
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      if (!I.isPseudo())
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        return &I;
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  }
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  // There was no previous non-pseudo in the fallen through blocks
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  return nullptr;
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}
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static void insertNopBeforeInstruction(MachineBasicBlock &MBB, MachineInstr* MI,
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                                       const TargetInstrInfo *TII) {
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  // If we are the first instruction of the block, put the NOP at the end of
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  // the previous fallthrough block
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  if (MI == &MBB.front()) {
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    MachineInstr *I = getLastNonPseudo(MBB, TII);
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    assert(I && "Expected instruction");
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    DebugLoc DL = I->getDebugLoc();
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    BuildMI(I->getParent(), DL, TII->get(AArch64::HINT)).addImm(0);
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  }
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  else {
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    DebugLoc DL = MI->getDebugLoc();
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    BuildMI(MBB, MI, DL, TII->get(AArch64::HINT)).addImm(0);
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  }
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  ++NumNopsAdded;
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}
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bool
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AArch64A53Fix835769::runOnBasicBlock(MachineBasicBlock &MBB) {
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  bool Changed = false;
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  LLVM_DEBUG(dbgs() << "Running on MBB: " << MBB
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                    << " - scanning instructions...\n");
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  // First, scan the basic block, looking for a sequence of 2 instructions
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  // that match the conditions under which the erratum may trigger.
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  // List of terminating instructions in matching sequences
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  std::vector<MachineInstr*> Sequences;
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  unsigned Idx = 0;
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  MachineInstr *PrevInstr = nullptr;
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  // Try and find the last non-pseudo instruction in any fallen through blocks,
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  // if there isn't one, then we use nullptr to represent that.
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  PrevInstr = getLastNonPseudo(MBB, TII);
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  for (auto &MI : MBB) {
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    MachineInstr *CurrInstr = &MI;
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    LLVM_DEBUG(dbgs() << "  Examining: " << MI);
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    if (PrevInstr) {
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      LLVM_DEBUG(dbgs() << "    PrevInstr: " << *PrevInstr
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                        << "    CurrInstr: " << *CurrInstr
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                        << "    isFirstInstructionInSequence(PrevInstr): "
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                        << isFirstInstructionInSequence(PrevInstr) << "\n"
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                        << "    isSecondInstructionInSequence(CurrInstr): "
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                        << isSecondInstructionInSequence(CurrInstr) << "\n");
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      if (isFirstInstructionInSequence(PrevInstr) &&
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isSecondInstructionInSequence(CurrInstr)3
) {
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        LLVM_DEBUG(dbgs() << "   ** pattern found at Idx " << Idx << "!\n");
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        Sequences.push_back(CurrInstr);
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      }
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    }
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    if (!CurrInstr->isPseudo())
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      PrevInstr = CurrInstr;
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    ++Idx;
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  }
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  LLVM_DEBUG(dbgs() << "Scan complete, " << Sequences.size()
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                    << " occurrences of pattern found.\n");
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  // Then update the basic block, inserting nops between the detected sequences.
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  for (auto &MI : Sequences) {
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    Changed = true;
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    insertNopBeforeInstruction(MBB, MI, TII);
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  }
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  return Changed;
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}
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// Factory function used by AArch64TargetMachine to add the pass to
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// the passmanager.
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FunctionPass *llvm::createAArch64A53Fix835769() {
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  return new AArch64A53Fix835769();
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}