Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
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Source (jump to first uncovered line)
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//===-- AArch64ConditionalCompares.cpp --- CCMP formation for AArch64 -----===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file implements the AArch64ConditionalCompares pass which reduces
10
// branching and code size by using the conditional compare instructions CCMP,
11
// CCMN, and FCMP.
12
//
13
// The CFG transformations for forming conditional compares are very similar to
14
// if-conversion, and this pass should run immediately before the early
15
// if-conversion pass.
16
//
17
//===----------------------------------------------------------------------===//
18
19
#include "AArch64.h"
20
#include "llvm/ADT/DepthFirstIterator.h"
21
#include "llvm/ADT/SetVector.h"
22
#include "llvm/ADT/SmallPtrSet.h"
23
#include "llvm/ADT/Statistic.h"
24
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
25
#include "llvm/CodeGen/MachineDominators.h"
26
#include "llvm/CodeGen/MachineFunction.h"
27
#include "llvm/CodeGen/MachineFunctionPass.h"
28
#include "llvm/CodeGen/MachineInstrBuilder.h"
29
#include "llvm/CodeGen/MachineLoopInfo.h"
30
#include "llvm/CodeGen/MachineRegisterInfo.h"
31
#include "llvm/CodeGen/MachineTraceMetrics.h"
32
#include "llvm/CodeGen/Passes.h"
33
#include "llvm/CodeGen/TargetInstrInfo.h"
34
#include "llvm/CodeGen/TargetRegisterInfo.h"
35
#include "llvm/CodeGen/TargetSubtargetInfo.h"
36
#include "llvm/Support/CommandLine.h"
37
#include "llvm/Support/Debug.h"
38
#include "llvm/Support/raw_ostream.h"
39
40
using namespace llvm;
41
42
#define DEBUG_TYPE "aarch64-ccmp"
43
44
// Absolute maximum number of instructions allowed per speculated block.
45
// This bypasses all other heuristics, so it should be set fairly high.
46
static cl::opt<unsigned> BlockInstrLimit(
47
    "aarch64-ccmp-limit", cl::init(30), cl::Hidden,
48
    cl::desc("Maximum number of instructions per speculated block."));
49
50
// Stress testing mode - disable heuristics.
51
static cl::opt<bool> Stress("aarch64-stress-ccmp", cl::Hidden,
52
                            cl::desc("Turn all knobs to 11"));
53
54
STATISTIC(NumConsidered, "Number of ccmps considered");
55
STATISTIC(NumPhiRejs, "Number of ccmps rejected (PHI)");
56
STATISTIC(NumPhysRejs, "Number of ccmps rejected (Physregs)");
57
STATISTIC(NumPhi2Rejs, "Number of ccmps rejected (PHI2)");
58
STATISTIC(NumHeadBranchRejs, "Number of ccmps rejected (Head branch)");
59
STATISTIC(NumCmpBranchRejs, "Number of ccmps rejected (CmpBB branch)");
60
STATISTIC(NumCmpTermRejs, "Number of ccmps rejected (CmpBB is cbz...)");
61
STATISTIC(NumImmRangeRejs, "Number of ccmps rejected (Imm out of range)");
62
STATISTIC(NumLiveDstRejs, "Number of ccmps rejected (Cmp dest live)");
63
STATISTIC(NumMultNZCVUses, "Number of ccmps rejected (NZCV used)");
64
STATISTIC(NumUnknNZCVDefs, "Number of ccmps rejected (NZCV def unknown)");
65
66
STATISTIC(NumSpeculateRejs, "Number of ccmps rejected (Can't speculate)");
67
68
STATISTIC(NumConverted, "Number of ccmp instructions created");
69
STATISTIC(NumCompBranches, "Number of cbz/cbnz branches converted");
70
71
//===----------------------------------------------------------------------===//
72
//                                 SSACCmpConv
73
//===----------------------------------------------------------------------===//
74
//
75
// The SSACCmpConv class performs ccmp-conversion on SSA form machine code
76
// after determining if it is possible. The class contains no heuristics;
77
// external code should be used to determine when ccmp-conversion is a good
78
// idea.
79
//
80
// CCmp-formation works on a CFG representing chained conditions, typically
81
// from C's short-circuit || and && operators:
82
//
83
//   From:         Head            To:         Head
84
//                 / |                         CmpBB
85
//                /  |                         / |
86
//               |  CmpBB                     /  |
87
//               |  / |                    Tail  |
88
//               | /  |                      |   |
89
//              Tail  |                      |   |
90
//                |   |                      |   |
91
//               ... ...                    ... ...
92
//
93
// The Head block is terminated by a br.cond instruction, and the CmpBB block
94
// contains compare + br.cond. Tail must be a successor of both.
95
//
96
// The cmp-conversion turns the compare instruction in CmpBB into a conditional
97
// compare, and merges CmpBB into Head, speculatively executing its
98
// instructions. The AArch64 conditional compare instructions have an immediate
99
// operand that specifies the NZCV flag values when the condition is false and
100
// the compare isn't executed. This makes it possible to chain compares with
101
// different condition codes.
102
//
103
// Example:
104
//
105
//    if (a == 5 || b == 17)
106
//      foo();
107
//
108
//    Head:
109
//       cmp  w0, #5
110
//       b.eq Tail
111
//    CmpBB:
112
//       cmp  w1, #17
113
//       b.eq Tail
114
//    ...
115
//    Tail:
116
//      bl _foo
117
//
118
//  Becomes:
119
//
120
//    Head:
121
//       cmp  w0, #5
122
//       ccmp w1, #17, 4, ne  ; 4 = nZcv
123
//       b.eq Tail
124
//    ...
125
//    Tail:
126
//      bl _foo
127
//
128
// The ccmp condition code is the one that would cause the Head terminator to
129
// branch to CmpBB.
130
//
131
// FIXME: It should also be possible to speculate a block on the critical edge
132
// between Head and Tail, just like if-converting a diamond.
133
//
134
// FIXME: Handle PHIs in Tail by turning them into selects (if-conversion).
135
136
namespace {
137
class SSACCmpConv {
138
  MachineFunction *MF;
139
  const TargetInstrInfo *TII;
140
  const TargetRegisterInfo *TRI;
141
  MachineRegisterInfo *MRI;
142
  const MachineBranchProbabilityInfo *MBPI;
143
144
public:
145
  /// The first block containing a conditional branch, dominating everything
146
  /// else.
147
  MachineBasicBlock *Head;
148
149
  /// The block containing cmp+br.cond with a successor shared with Head.
150
  MachineBasicBlock *CmpBB;
151
152
  /// The common successor for Head and CmpBB.
153
  MachineBasicBlock *Tail;
154
155
  /// The compare instruction in CmpBB that can be converted to a ccmp.
156
  MachineInstr *CmpMI;
157
158
private:
159
  /// The branch condition in Head as determined by AnalyzeBranch.
160
  SmallVector<MachineOperand, 4> HeadCond;
161
162
  /// The condition code that makes Head branch to CmpBB.
163
  AArch64CC::CondCode HeadCmpBBCC;
164
165
  /// The branch condition in CmpBB.
166
  SmallVector<MachineOperand, 4> CmpBBCond;
167
168
  /// The condition code that makes CmpBB branch to Tail.
169
  AArch64CC::CondCode CmpBBTailCC;
170
171
  /// Check if the Tail PHIs are trivially convertible.
172
  bool trivialTailPHIs();
173
174
  /// Remove CmpBB from the Tail PHIs.
175
  void updateTailPHIs();
176
177
  /// Check if an operand defining DstReg is dead.
178
  bool isDeadDef(unsigned DstReg);
179
180
  /// Find the compare instruction in MBB that controls the conditional branch.
181
  /// Return NULL if a convertible instruction can't be found.
182
  MachineInstr *findConvertibleCompare(MachineBasicBlock *MBB);
183
184
  /// Return true if all non-terminator instructions in MBB can be safely
185
  /// speculated.
186
  bool canSpeculateInstrs(MachineBasicBlock *MBB, const MachineInstr *CmpMI);
187
188
public:
189
  /// runOnMachineFunction - Initialize per-function data structures.
190
  void runOnMachineFunction(MachineFunction &MF,
191
257k
                            const MachineBranchProbabilityInfo *MBPI) {
192
257k
    this->MF = &MF;
193
257k
    this->MBPI = MBPI;
194
257k
    TII = MF.getSubtarget().getInstrInfo();
195
257k
    TRI = MF.getSubtarget().getRegisterInfo();
196
257k
    MRI = &MF.getRegInfo();
197
257k
  }
198
199
  /// If the sub-CFG headed by MBB can be cmp-converted, initialize the
200
  /// internal state, and return true.
201
  bool canConvert(MachineBasicBlock *MBB);
202
203
  /// Cmo-convert the last block passed to canConvertCmp(), assuming
204
  /// it is possible. Add any erased blocks to RemovedBlocks.
205
  void convert(SmallVectorImpl<MachineBasicBlock *> &RemovedBlocks);
206
207
  /// Return the expected code size delta if the conversion into a
208
  /// conditional compare is performed.
209
  int expectedCodeSizeDelta() const;
210
};
211
} // end anonymous namespace
212
213
// Check that all PHIs in Tail are selecting the same value from Head and CmpBB.
214
// This means that no if-conversion is required when merging CmpBB into Head.
215
189k
bool SSACCmpConv::trivialTailPHIs() {
216
206k
  for (auto &I : *Tail) {
217
206k
    if (!I.isPHI())
218
117k
      break;
219
89.8k
    unsigned HeadReg = 0, CmpBBReg = 0;
220
89.8k
    // PHI operands come in (VReg, MBB) pairs.
221
2.01M
    for (unsigned oi = 1, oe = I.getNumOperands(); oi != oe; 
oi += 21.92M
) {
222
1.92M
      MachineBasicBlock *MBB = I.getOperand(oi + 1).getMBB();
223
1.92M
      unsigned Reg = I.getOperand(oi).getReg();
224
1.92M
      if (MBB == Head) {
225
89.8k
        assert((!HeadReg || HeadReg == Reg) && "Inconsistent PHI operands");
226
89.8k
        HeadReg = Reg;
227
89.8k
      }
228
1.92M
      if (MBB == CmpBB) {
229
89.8k
        assert((!CmpBBReg || CmpBBReg == Reg) && "Inconsistent PHI operands");
230
89.8k
        CmpBBReg = Reg;
231
89.8k
      }
232
1.92M
    }
233
89.8k
    if (HeadReg != CmpBBReg)
234
68.5k
      return false;
235
89.8k
  }
236
189k
  
return true120k
;
237
189k
}
238
239
// Assuming that trivialTailPHIs() is true, update the Tail PHIs by simply
240
// removing the CmpBB operands. The Head operands will be identical.
241
2.58k
void SSACCmpConv::updateTailPHIs() {
242
3.35k
  for (auto &I : *Tail) {
243
3.35k
    if (!I.isPHI())
244
2.54k
      break;
245
813
    // I is a PHI. It can have multiple entries for CmpBB.
246
13.6k
    
for (unsigned oi = I.getNumOperands(); 813
oi > 2;
oi -= 212.8k
) {
247
12.8k
      // PHI operands are (Reg, MBB) at (oi-2, oi-1).
248
12.8k
      if (I.getOperand(oi - 1).getMBB() == CmpBB) {
249
842
        I.RemoveOperand(oi - 1);
250
842
        I.RemoveOperand(oi - 2);
251
842
      }
252
12.8k
    }
253
813
  }
254
2.58k
}
255
256
// This pass runs before the AArch64DeadRegisterDefinitions pass, so compares
257
// are still writing virtual registers without any uses.
258
48.9k
bool SSACCmpConv::isDeadDef(unsigned DstReg) {
259
48.9k
  // Writes to the zero register are dead.
260
48.9k
  if (DstReg == AArch64::WZR || 
DstReg == AArch64::XZR21.0k
)
261
37.6k
    return true;
262
11.3k
  if (!TargetRegisterInfo::isVirtualRegister(DstReg))
263
0
    return false;
264
11.3k
  // A virtual register def without any uses will be marked dead later, and
265
11.3k
  // eventually replaced by the zero register.
266
11.3k
  return MRI->use_nodbg_empty(DstReg);
267
11.3k
}
268
269
// Parse a condition code returned by AnalyzeBranch, and compute the CondCode
270
// corresponding to TBB.
271
// Return
272
208k
static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) {
273
208k
  // A normal br.cond simply has the condition code.
274
208k
  if (Cond[0].getImm() != -1) {
275
118k
    assert(Cond.size() == 1 && "Unknown Cond array format");
276
118k
    CC = (AArch64CC::CondCode)(int)Cond[0].getImm();
277
118k
    return true;
278
118k
  }
279
90.1k
  // For tbz and cbz instruction, the opcode is next.
280
90.1k
  switch (Cond[1].getImm()) {
281
90.1k
  default:
282
36.7k
    // This includes tbz / tbnz branches which can't be converted to
283
36.7k
    // ccmp + br.cond.
284
36.7k
    return false;
285
90.1k
  case AArch64::CBZW:
286
32.3k
  case AArch64::CBZX:
287
32.3k
    assert(Cond.size() == 3 && "Unknown Cond array format");
288
32.3k
    CC = AArch64CC::EQ;
289
32.3k
    return true;
290
32.3k
  case AArch64::CBNZW:
291
21.0k
  case AArch64::CBNZX:
292
21.0k
    assert(Cond.size() == 3 && "Unknown Cond array format");
293
21.0k
    CC = AArch64CC::NE;
294
21.0k
    return true;
295
90.1k
  }
296
90.1k
}
297
298
76.8k
MachineInstr *SSACCmpConv::findConvertibleCompare(MachineBasicBlock *MBB) {
299
76.8k
  MachineBasicBlock::iterator I = MBB->getFirstTerminator();
300
76.8k
  if (I == MBB->end())
301
0
    return nullptr;
302
76.8k
  // The terminator must be controlled by the flags.
303
76.8k
  if (!I->readsRegister(AArch64::NZCV)) {
304
23.7k
    switch (I->getOpcode()) {
305
23.7k
    case AArch64::CBZW:
306
23.7k
    case AArch64::CBZX:
307
23.7k
    case AArch64::CBNZW:
308
23.7k
    case AArch64::CBNZX:
309
23.7k
      // These can be converted into a ccmp against #0.
310
23.7k
      return &*I;
311
0
    }
312
0
    ++NumCmpTermRejs;
313
0
    LLVM_DEBUG(dbgs() << "Flags not used by terminator: " << *I);
314
0
    return nullptr;
315
0
  }
316
53.0k
317
53.0k
  // Now find the instruction controlling the terminator.
318
53.0k
  
for (MachineBasicBlock::iterator B = MBB->begin(); 53.0k
I != B;) {
319
53.0k
    --I;
320
53.0k
    assert(!I->isTerminator() && "Spurious terminator");
321
53.0k
    switch (I->getOpcode()) {
322
53.0k
    // cmp is an alias for subs with a dead destination register.
323
53.0k
    case AArch64::SUBSWri:
324
7.31k
    case AArch64::SUBSXri:
325
7.31k
    // cmn is an alias for adds with a dead destination register.
326
7.31k
    case AArch64::ADDSWri:
327
7.31k
    case AArch64::ADDSXri:
328
7.31k
      // Check that the immediate operand is within range, ccmp wants a uimm5.
329
7.31k
      // Rd = SUBSri Rn, imm, shift
330
7.31k
      if (I->getOperand(3).getImm() || 
!isUInt<5>(I->getOperand(2).getImm())7.29k
) {
331
2.96k
        LLVM_DEBUG(dbgs() << "Immediate out of range for ccmp: " << *I);
332
2.96k
        ++NumImmRangeRejs;
333
2.96k
        return nullptr;
334
2.96k
      }
335
4.34k
      LLVM_FALLTHROUGH;
336
48.9k
    case AArch64::SUBSWrr:
337
48.9k
    case AArch64::SUBSXrr:
338
48.9k
    case AArch64::ADDSWrr:
339
48.9k
    case AArch64::ADDSXrr:
340
48.9k
      if (isDeadDef(I->getOperand(0).getReg()))
341
48.9k
        return &*I;
342
2
      LLVM_DEBUG(dbgs() << "Can't convert compare with live destination: "
343
2
                        << *I);
344
2
      ++NumLiveDstRejs;
345
2
      return nullptr;
346
1.03k
    case AArch64::FCMPSrr:
347
1.03k
    case AArch64::FCMPDrr:
348
1.03k
    case AArch64::FCMPESrr:
349
1.03k
    case AArch64::FCMPEDrr:
350
1.03k
      return &*I;
351
89
    }
352
89
353
89
    // Check for flag reads and clobbers.
354
89
    MIOperands::PhysRegInfo PRI =
355
89
        MIOperands(*I).analyzePhysReg(AArch64::NZCV, TRI);
356
89
357
89
    if (PRI.Read) {
358
0
      // The ccmp doesn't produce exactly the same flags as the original
359
0
      // compare, so reject the transform if there are uses of the flags
360
0
      // besides the terminators.
361
0
      LLVM_DEBUG(dbgs() << "Can't create ccmp with multiple uses: " << *I);
362
0
      ++NumMultNZCVUses;
363
0
      return nullptr;
364
0
    }
365
89
366
89
    if (PRI.Defined || 
PRI.Clobbered3
) {
367
86
      LLVM_DEBUG(dbgs() << "Not convertible compare: " << *I);
368
86
      ++NumUnknNZCVDefs;
369
86
      return nullptr;
370
86
    }
371
89
  }
372
53.0k
  
LLVM_DEBUG0
(dbgs() << "Flags not defined in " << printMBBReference(*MBB)
373
0
                    << '\n');
374
0
  return nullptr;
375
53.0k
}
376
377
/// Determine if all the instructions in MBB can safely
378
/// be speculated. The terminators are not considered.
379
///
380
/// Only CmpMI is allowed to clobber the flags.
381
///
382
bool SSACCmpConv::canSpeculateInstrs(MachineBasicBlock *MBB,
383
73.7k
                                     const MachineInstr *CmpMI) {
384
73.7k
  // Reject any live-in physregs. It's probably NZCV/EFLAGS, and very hard to
385
73.7k
  // get right.
386
73.7k
  if (!MBB->livein_empty()) {
387
0
    LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " has live-ins.\n");
388
0
    return false;
389
0
  }
390
73.7k
391
73.7k
  unsigned InstrCount = 0;
392
73.7k
393
73.7k
  // Check all instructions, except the terminators. It is assumed that
394
73.7k
  // terminators never have side effects or define any used register values.
395
90.9k
  for (auto &I : make_range(MBB->begin(), MBB->getFirstTerminator())) {
396
90.9k
    if (I.isDebugInstr())
397
0
      continue;
398
90.9k
399
90.9k
    if (++InstrCount > BlockInstrLimit && 
!Stress0
) {
400
0
      LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " has more than "
401
0
                        << BlockInstrLimit << " instructions.\n");
402
0
      return false;
403
0
    }
404
90.9k
405
90.9k
    // There shouldn't normally be any phis in a single-predecessor block.
406
90.9k
    if (I.isPHI()) {
407
0
      LLVM_DEBUG(dbgs() << "Can't hoist: " << I);
408
0
      return false;
409
0
    }
410
90.9k
411
90.9k
    // Don't speculate loads. Note that it may be possible and desirable to
412
90.9k
    // speculate GOT or constant pool loads that are guaranteed not to trap,
413
90.9k
    // but we don't support that for now.
414
90.9k
    if (I.mayLoad()) {
415
51.1k
      LLVM_DEBUG(dbgs() << "Won't speculate load: " << I);
416
51.1k
      return false;
417
51.1k
    }
418
39.7k
419
39.7k
    // We never speculate stores, so an AA pointer isn't necessary.
420
39.7k
    bool DontMoveAcrossStore = true;
421
39.7k
    if (!I.isSafeToMove(nullptr, DontMoveAcrossStore)) {
422
4.93k
      LLVM_DEBUG(dbgs() << "Can't speculate: " << I);
423
4.93k
      return false;
424
4.93k
    }
425
34.8k
426
34.8k
    // Only CmpMI is allowed to clobber the flags.
427
34.8k
    if (&I != CmpMI && 
I.modifiesRegister(AArch64::NZCV, TRI)23.4k
) {
428
2.17k
      LLVM_DEBUG(dbgs() << "Clobbers flags: " << I);
429
2.17k
      return false;
430
2.17k
    }
431
34.8k
  }
432
73.7k
  
return true15.4k
;
433
73.7k
}
434
435
/// Analyze the sub-cfg rooted in MBB, and return true if it is a potential
436
/// candidate for cmp-conversion. Fill out the internal state.
437
///
438
2.00M
bool SSACCmpConv::canConvert(MachineBasicBlock *MBB) {
439
2.00M
  Head = MBB;
440
2.00M
  Tail = CmpBB = nullptr;
441
2.00M
442
2.00M
  if (Head->succ_size() != 2)
443
950k
    return false;
444
1.05M
  MachineBasicBlock *Succ0 = Head->succ_begin()[0];
445
1.05M
  MachineBasicBlock *Succ1 = Head->succ_begin()[1];
446
1.05M
447
1.05M
  // CmpBB can only have a single predecessor. Tail is allowed many.
448
1.05M
  if (Succ0->pred_size() != 1)
449
499k
    std::swap(Succ0, Succ1);
450
1.05M
451
1.05M
  // Succ0 is our candidate for CmpBB.
452
1.05M
  if (Succ0->pred_size() != 1 || 
Succ0->succ_size() != 2881k
)
453
647k
    return false;
454
407k
455
407k
  CmpBB = Succ0;
456
407k
  Tail = Succ1;
457
407k
458
407k
  if (!CmpBB->isSuccessor(Tail))
459
218k
    return false;
460
189k
461
189k
  // The CFG topology checks out.
462
189k
  LLVM_DEBUG(dbgs() << "\nTriangle: " << printMBBReference(*Head) << " -> "
463
189k
                    << printMBBReference(*CmpBB) << " -> "
464
189k
                    << printMBBReference(*Tail) << '\n');
465
189k
  ++NumConsidered;
466
189k
467
189k
  // Tail is allowed to have many predecessors, but we can't handle PHIs yet.
468
189k
  //
469
189k
  // FIXME: Real PHIs could be if-converted as long as the CmpBB values are
470
189k
  // defined before The CmpBB cmp clobbers the flags. Alternatively, it should
471
189k
  // always be safe to sink the ccmp down to immediately before the CmpBB
472
189k
  // terminators.
473
189k
  if (!trivialTailPHIs()) {
474
68.5k
    LLVM_DEBUG(dbgs() << "Can't handle phis in Tail.\n");
475
68.5k
    ++NumPhiRejs;
476
68.5k
    return false;
477
68.5k
  }
478
120k
479
120k
  if (!Tail->livein_empty()) {
480
5.49k
    LLVM_DEBUG(dbgs() << "Can't handle live-in physregs in Tail.\n");
481
5.49k
    ++NumPhysRejs;
482
5.49k
    return false;
483
5.49k
  }
484
115k
485
115k
  // CmpBB should never have PHIs since Head is its only predecessor.
486
115k
  // FIXME: Clean them up if it happens.
487
115k
  if (!CmpBB->empty() && CmpBB->front().isPHI()) {
488
0
    LLVM_DEBUG(dbgs() << "Can't handle phis in CmpBB.\n");
489
0
    ++NumPhi2Rejs;
490
0
    return false;
491
0
  }
492
115k
493
115k
  if (!CmpBB->livein_empty()) {
494
1
    LLVM_DEBUG(dbgs() << "Can't handle live-in physregs in CmpBB.\n");
495
1
    ++NumPhysRejs;
496
1
    return false;
497
1
  }
498
115k
499
115k
  // The branch we're looking to eliminate must be analyzable.
500
115k
  HeadCond.clear();
501
115k
  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
502
115k
  if (TII->analyzeBranch(*Head, TBB, FBB, HeadCond)) {
503
23
    LLVM_DEBUG(dbgs() << "Head branch not analyzable.\n");
504
23
    ++NumHeadBranchRejs;
505
23
    return false;
506
23
  }
507
115k
508
115k
  // This is weird, probably some sort of degenerate CFG, or an edge to a
509
115k
  // landing pad.
510
115k
  if (!TBB || HeadCond.empty()) {
511
0
    LLVM_DEBUG(
512
0
        dbgs() << "AnalyzeBranch didn't find conditional branch in Head.\n");
513
0
    ++NumHeadBranchRejs;
514
0
    return false;
515
0
  }
516
115k
517
115k
  if (!parseCond(HeadCond, HeadCmpBBCC)) {
518
20.3k
    LLVM_DEBUG(dbgs() << "Unsupported branch type on Head\n");
519
20.3k
    ++NumHeadBranchRejs;
520
20.3k
    return false;
521
20.3k
  }
522
94.8k
523
94.8k
  // Make sure the branch direction is right.
524
94.8k
  if (TBB != CmpBB) {
525
90.0k
    assert(TBB == Tail && "Unexpected TBB");
526
90.0k
    HeadCmpBBCC = AArch64CC::getInvertedCondCode(HeadCmpBBCC);
527
90.0k
  }
528
94.8k
529
94.8k
  CmpBBCond.clear();
530
94.8k
  TBB = FBB = nullptr;
531
94.8k
  if (TII->analyzeBranch(*CmpBB, TBB, FBB, CmpBBCond)) {
532
16
    LLVM_DEBUG(dbgs() << "CmpBB branch not analyzable.\n");
533
16
    ++NumCmpBranchRejs;
534
16
    return false;
535
16
  }
536
94.8k
537
94.8k
  if (!TBB || CmpBBCond.empty()) {
538
1.63k
    LLVM_DEBUG(
539
1.63k
        dbgs() << "AnalyzeBranch didn't find conditional branch in CmpBB.\n");
540
1.63k
    ++NumCmpBranchRejs;
541
1.63k
    return false;
542
1.63k
  }
543
93.2k
544
93.2k
  if (!parseCond(CmpBBCond, CmpBBTailCC)) {
545
16.3k
    LLVM_DEBUG(dbgs() << "Unsupported branch type on CmpBB\n");
546
16.3k
    ++NumCmpBranchRejs;
547
16.3k
    return false;
548
16.3k
  }
549
76.8k
550
76.8k
  if (TBB != Tail)
551
25.7k
    CmpBBTailCC = AArch64CC::getInvertedCondCode(CmpBBTailCC);
552
76.8k
553
76.8k
  LLVM_DEBUG(dbgs() << "Head->CmpBB on "
554
76.8k
                    << AArch64CC::getCondCodeName(HeadCmpBBCC)
555
76.8k
                    << ", CmpBB->Tail on "
556
76.8k
                    << AArch64CC::getCondCodeName(CmpBBTailCC) << '\n');
557
76.8k
558
76.8k
  CmpMI = findConvertibleCompare(CmpBB);
559
76.8k
  if (!CmpMI)
560
3.05k
    return false;
561
73.7k
562
73.7k
  if (!canSpeculateInstrs(CmpBB, CmpMI)) {
563
58.2k
    ++NumSpeculateRejs;
564
58.2k
    return false;
565
58.2k
  }
566
15.4k
  return true;
567
15.4k
}
568
569
2.58k
void SSACCmpConv::convert(SmallVectorImpl<MachineBasicBlock *> &RemovedBlocks) {
570
2.58k
  LLVM_DEBUG(dbgs() << "Merging " << printMBBReference(*CmpBB) << " into "
571
2.58k
                    << printMBBReference(*Head) << ":\n"
572
2.58k
                    << *CmpBB);
573
2.58k
574
2.58k
  // All CmpBB instructions are moved into Head, and CmpBB is deleted.
575
2.58k
  // Update the CFG first.
576
2.58k
  updateTailPHIs();
577
2.58k
578
2.58k
  // Save successor probabilties before removing CmpBB and Tail from their
579
2.58k
  // parents.
580
2.58k
  BranchProbability Head2CmpBB = MBPI->getEdgeProbability(Head, CmpBB);
581
2.58k
  BranchProbability CmpBB2Tail = MBPI->getEdgeProbability(CmpBB, Tail);
582
2.58k
583
2.58k
  Head->removeSuccessor(CmpBB);
584
2.58k
  CmpBB->removeSuccessor(Tail);
585
2.58k
586
2.58k
  // If Head and CmpBB had successor probabilties, udpate the probabilities to
587
2.58k
  // reflect the ccmp-conversion.
588
2.58k
  if (Head->hasSuccessorProbabilities() && 
CmpBB->hasSuccessorProbabilities()2.37k
) {
589
2.37k
590
2.37k
    // Head is allowed two successors. We've removed CmpBB, so the remaining
591
2.37k
    // successor is Tail. We need to increase the successor probability for
592
2.37k
    // Tail to account for the CmpBB path we removed.
593
2.37k
    //
594
2.37k
    // Pr(Tail|Head) += Pr(CmpBB|Head) * Pr(Tail|CmpBB).
595
2.37k
    assert(*Head->succ_begin() == Tail && "Head successor is not Tail");
596
2.37k
    BranchProbability Head2Tail = MBPI->getEdgeProbability(Head, Tail);
597
2.37k
    Head->setSuccProbability(Head->succ_begin(),
598
2.37k
                             Head2Tail + Head2CmpBB * CmpBB2Tail);
599
2.37k
600
2.37k
    // We will transfer successors of CmpBB to Head in a moment without
601
2.37k
    // normalizing the successor probabilities. Set the successor probabilites
602
2.37k
    // before doing so.
603
2.37k
    //
604
2.37k
    // Pr(I|Head) = Pr(CmpBB|Head) * Pr(I|CmpBB).
605
4.74k
    for (auto I = CmpBB->succ_begin(), E = CmpBB->succ_end(); I != E; 
++I2.37k
) {
606
2.37k
      BranchProbability CmpBB2I = MBPI->getEdgeProbability(CmpBB, *I);
607
2.37k
      CmpBB->setSuccProbability(I, Head2CmpBB * CmpBB2I);
608
2.37k
    }
609
2.37k
  }
610
2.58k
611
2.58k
  Head->transferSuccessorsAndUpdatePHIs(CmpBB);
612
2.58k
  DebugLoc TermDL = Head->getFirstTerminator()->getDebugLoc();
613
2.58k
  TII->removeBranch(*Head);
614
2.58k
615
2.58k
  // If the Head terminator was one of the cbz / tbz branches with built-in
616
2.58k
  // compare, we need to insert an explicit compare instruction in its place.
617
2.58k
  if (HeadCond[0].getImm() == -1) {
618
886
    ++NumCompBranches;
619
886
    unsigned Opc = 0;
620
886
    switch (HeadCond[1].getImm()) {
621
886
    case AArch64::CBZW:
622
643
    case AArch64::CBNZW:
623
643
      Opc = AArch64::SUBSWri;
624
643
      break;
625
643
    case AArch64::CBZX:
626
243
    case AArch64::CBNZX:
627
243
      Opc = AArch64::SUBSXri;
628
243
      break;
629
243
    default:
630
0
      llvm_unreachable("Cannot convert Head branch");
631
886
    }
632
886
    const MCInstrDesc &MCID = TII->get(Opc);
633
886
    // Create a dummy virtual register for the SUBS def.
634
886
    unsigned DestReg =
635
886
        MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF));
636
886
    // Insert a SUBS Rn, #0 instruction instead of the cbz / cbnz.
637
886
    BuildMI(*Head, Head->end(), TermDL, MCID)
638
886
        .addReg(DestReg, RegState::Define | RegState::Dead)
639
886
        .add(HeadCond[2])
640
886
        .addImm(0)
641
886
        .addImm(0);
642
886
    // SUBS uses the GPR*sp register classes.
643
886
    MRI->constrainRegClass(HeadCond[2].getReg(),
644
886
                           TII->getRegClass(MCID, 1, TRI, *MF));
645
886
  }
646
2.58k
647
2.58k
  Head->splice(Head->end(), CmpBB, CmpBB->begin(), CmpBB->end());
648
2.58k
649
2.58k
  // Now replace CmpMI with a ccmp instruction that also considers the incoming
650
2.58k
  // flags.
651
2.58k
  unsigned Opc = 0;
652
2.58k
  unsigned FirstOp = 1;   // First CmpMI operand to copy.
653
2.58k
  bool isZBranch = false; // CmpMI is a cbz/cbnz instruction.
654
2.58k
  switch (CmpMI->getOpcode()) {
655
2.58k
  default:
656
0
    llvm_unreachable("Unknown compare opcode");
657
2.58k
  
case AArch64::SUBSWri: Opc = AArch64::CCMPWi; break239
;
658
2.58k
  
case AArch64::SUBSWrr: Opc = AArch64::CCMPWr; break675
;
659
2.58k
  
case AArch64::SUBSXri: Opc = AArch64::CCMPXi; break19
;
660
2.58k
  
case AArch64::SUBSXrr: Opc = AArch64::CCMPXr; break795
;
661
2.58k
  
case AArch64::ADDSWri: Opc = AArch64::CCMNWi; break9
;
662
2.58k
  
case AArch64::ADDSWrr: Opc = AArch64::CCMNWr; break0
;
663
2.58k
  
case AArch64::ADDSXri: Opc = AArch64::CCMNXi; break4
;
664
2.58k
  
case AArch64::ADDSXrr: Opc = AArch64::CCMNXr; break0
;
665
2.58k
  
case AArch64::FCMPSrr: Opc = AArch64::FCCMPSrr; FirstOp = 0; break236
;
666
2.58k
  
case AArch64::FCMPDrr: Opc = AArch64::FCCMPDrr; FirstOp = 0; break62
;
667
2.58k
  
case AArch64::FCMPESrr: Opc = AArch64::FCCMPESrr; FirstOp = 0; break0
;
668
2.58k
  
case AArch64::FCMPEDrr: Opc = AArch64::FCCMPEDrr; FirstOp = 0; break0
;
669
2.58k
  case AArch64::CBZW:
670
214
  case AArch64::CBNZW:
671
214
    Opc = AArch64::CCMPWi;
672
214
    FirstOp = 0;
673
214
    isZBranch = true;
674
214
    break;
675
331
  case AArch64::CBZX:
676
331
  case AArch64::CBNZX:
677
331
    Opc = AArch64::CCMPXi;
678
331
    FirstOp = 0;
679
331
    isZBranch = true;
680
331
    break;
681
2.58k
  }
682
2.58k
683
2.58k
  // The ccmp instruction should set the flags according to the comparison when
684
2.58k
  // Head would have branched to CmpBB.
685
2.58k
  // The NZCV immediate operand should provide flags for the case where Head
686
2.58k
  // would have branched to Tail. These flags should cause the new Head
687
2.58k
  // terminator to branch to tail.
688
2.58k
  unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(CmpBBTailCC);
689
2.58k
  const MCInstrDesc &MCID = TII->get(Opc);
690
2.58k
  MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(),
691
2.58k
                         TII->getRegClass(MCID, 0, TRI, *MF));
692
2.58k
  if (CmpMI->getOperand(FirstOp + 1).isReg())
693
1.76k
    MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(),
694
1.76k
                           TII->getRegClass(MCID, 1, TRI, *MF));
695
2.58k
  MachineInstrBuilder MIB = BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), MCID)
696
2.58k
                                .add(CmpMI->getOperand(FirstOp)); // Register Rn
697
2.58k
  if (isZBranch)
698
545
    MIB.addImm(0); // cbz/cbnz Rn -> ccmp Rn, #0
699
2.03k
  else
700
2.03k
    MIB.add(CmpMI->getOperand(FirstOp + 1)); // Register Rm / Immediate
701
2.58k
  MIB.addImm(NZCV).addImm(HeadCmpBBCC);
702
2.58k
703
2.58k
  // If CmpMI was a terminator, we need a new conditional branch to replace it.
704
2.58k
  // This now becomes a Head terminator.
705
2.58k
  if (isZBranch) {
706
545
    bool isNZ = CmpMI->getOpcode() == AArch64::CBNZW ||
707
545
                
CmpMI->getOpcode() == AArch64::CBNZX445
;
708
545
    BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), TII->get(AArch64::Bcc))
709
545
        .addImm(isNZ ? 
AArch64CC::NE306
:
AArch64CC::EQ239
)
710
545
        .add(CmpMI->getOperand(1)); // Branch target.
711
545
  }
712
2.58k
  CmpMI->eraseFromParent();
713
2.58k
  Head->updateTerminator();
714
2.58k
715
2.58k
  RemovedBlocks.push_back(CmpBB);
716
2.58k
  CmpBB->eraseFromParent();
717
2.58k
  LLVM_DEBUG(dbgs() << "Result:\n" << *Head);
718
2.58k
  ++NumConverted;
719
2.58k
}
720
721
0
int SSACCmpConv::expectedCodeSizeDelta() const {
722
0
  int delta = 0;
723
0
  // If the Head terminator was one of the cbz / tbz branches with built-in
724
0
  // compare, we need to insert an explicit compare instruction in its place
725
0
  // plus a branch instruction.
726
0
  if (HeadCond[0].getImm() == -1) {
727
0
    switch (HeadCond[1].getImm()) {
728
0
    case AArch64::CBZW:
729
0
    case AArch64::CBNZW:
730
0
    case AArch64::CBZX:
731
0
    case AArch64::CBNZX:
732
0
      // Therefore delta += 1
733
0
      delta = 1;
734
0
      break;
735
0
    default:
736
0
      llvm_unreachable("Cannot convert Head branch");
737
0
    }
738
0
  }
739
0
  // If the Cmp terminator was one of the cbz / tbz branches with
740
0
  // built-in compare, it will be turned into a compare instruction
741
0
  // into Head, but we do not save any instruction.
742
0
  // Otherwise, we save the branch instruction.
743
0
  switch (CmpMI->getOpcode()) {
744
0
  default:
745
0
    --delta;
746
0
    break;
747
0
  case AArch64::CBZW:
748
0
  case AArch64::CBNZW:
749
0
  case AArch64::CBZX:
750
0
  case AArch64::CBNZX:
751
0
    break;
752
0
  }
753
0
  return delta;
754
0
}
755
756
//===----------------------------------------------------------------------===//
757
//                       AArch64ConditionalCompares Pass
758
//===----------------------------------------------------------------------===//
759
760
namespace {
761
class AArch64ConditionalCompares : public MachineFunctionPass {
762
  const MachineBranchProbabilityInfo *MBPI;
763
  const TargetInstrInfo *TII;
764
  const TargetRegisterInfo *TRI;
765
  MCSchedModel SchedModel;
766
  // Does the proceeded function has Oz attribute.
767
  bool MinSize;
768
  MachineRegisterInfo *MRI;
769
  MachineDominatorTree *DomTree;
770
  MachineLoopInfo *Loops;
771
  MachineTraceMetrics *Traces;
772
  MachineTraceMetrics::Ensemble *MinInstr;
773
  SSACCmpConv CmpConv;
774
775
public:
776
  static char ID;
777
8.62k
  AArch64ConditionalCompares() : MachineFunctionPass(ID) {
778
8.62k
    initializeAArch64ConditionalComparesPass(*PassRegistry::getPassRegistry());
779
8.62k
  }
780
  void getAnalysisUsage(AnalysisUsage &AU) const override;
781
  bool runOnMachineFunction(MachineFunction &MF) override;
782
265k
  StringRef getPassName() const override {
783
265k
    return "AArch64 Conditional Compares";
784
265k
  }
785
786
private:
787
  bool tryConvert(MachineBasicBlock *);
788
  void updateDomTree(ArrayRef<MachineBasicBlock *> Removed);
789
  void updateLoops(ArrayRef<MachineBasicBlock *> Removed);
790
  void invalidateTraces();
791
  bool shouldConvert();
792
};
793
} // end anonymous namespace
794
795
char AArch64ConditionalCompares::ID = 0;
796
797
101k
INITIALIZE_PASS_BEGIN(AArch64ConditionalCompares, "aarch64-ccmp",
798
101k
                      "AArch64 CCMP Pass", false, false)
799
101k
INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
800
101k
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
801
101k
INITIALIZE_PASS_DEPENDENCY(MachineTraceMetrics)
802
101k
INITIALIZE_PASS_END(AArch64ConditionalCompares, "aarch64-ccmp",
803
                    "AArch64 CCMP Pass", false, false)
804
805
8.62k
FunctionPass *llvm::createAArch64ConditionalCompares() {
806
8.62k
  return new AArch64ConditionalCompares();
807
8.62k
}
808
809
8.58k
void AArch64ConditionalCompares::getAnalysisUsage(AnalysisUsage &AU) const {
810
8.58k
  AU.addRequired<MachineBranchProbabilityInfo>();
811
8.58k
  AU.addRequired<MachineDominatorTree>();
812
8.58k
  AU.addPreserved<MachineDominatorTree>();
813
8.58k
  AU.addRequired<MachineLoopInfo>();
814
8.58k
  AU.addPreserved<MachineLoopInfo>();
815
8.58k
  AU.addRequired<MachineTraceMetrics>();
816
8.58k
  AU.addPreserved<MachineTraceMetrics>();
817
8.58k
  MachineFunctionPass::getAnalysisUsage(AU);
818
8.58k
}
819
820
/// Update the dominator tree after if-conversion erased some blocks.
821
void AArch64ConditionalCompares::updateDomTree(
822
2.58k
    ArrayRef<MachineBasicBlock *> Removed) {
823
2.58k
  // convert() removes CmpBB which was previously dominated by Head.
824
2.58k
  // CmpBB children should be transferred to Head.
825
2.58k
  MachineDomTreeNode *HeadNode = DomTree->getNode(CmpConv.Head);
826
2.58k
  for (MachineBasicBlock *RemovedMBB : Removed) {
827
2.58k
    MachineDomTreeNode *Node = DomTree->getNode(RemovedMBB);
828
2.58k
    assert(Node != HeadNode && "Cannot erase the head node");
829
2.58k
    assert(Node->getIDom() == HeadNode && "CmpBB should be dominated by Head");
830
3.89k
    while (Node->getNumChildren())
831
1.31k
      DomTree->changeImmediateDominator(Node->getChildren().back(), HeadNode);
832
2.58k
    DomTree->eraseNode(RemovedMBB);
833
2.58k
  }
834
2.58k
}
835
836
/// Update LoopInfo after if-conversion.
837
void
838
2.58k
AArch64ConditionalCompares::updateLoops(ArrayRef<MachineBasicBlock *> Removed) {
839
2.58k
  if (!Loops)
840
0
    return;
841
2.58k
  for (MachineBasicBlock *RemovedMBB : Removed)
842
2.58k
    Loops->removeBlock(RemovedMBB);
843
2.58k
}
844
845
/// Invalidate MachineTraceMetrics before if-conversion.
846
2.58k
void AArch64ConditionalCompares::invalidateTraces() {
847
2.58k
  Traces->invalidate(CmpConv.Head);
848
2.58k
  Traces->invalidate(CmpConv.CmpBB);
849
2.58k
}
850
851
/// Apply cost model and heuristics to the if-conversion in IfConv.
852
/// Return true if the conversion is a good idea.
853
///
854
15.4k
bool AArch64ConditionalCompares::shouldConvert() {
855
15.4k
  // Stress testing mode disables all cost considerations.
856
15.4k
  if (Stress)
857
10
    return true;
858
15.4k
  if (!MinInstr)
859
6.71k
    MinInstr = Traces->getEnsemble(MachineTraceMetrics::TS_MinInstrCount);
860
15.4k
861
15.4k
  // Head dominates CmpBB, so it is always included in its trace.
862
15.4k
  MachineTraceMetrics::Trace Trace = MinInstr->getTrace(CmpConv.CmpBB);
863
15.4k
864
15.4k
  // If code size is the main concern
865
15.4k
  if (MinSize) {
866
0
    int CodeSizeDelta = CmpConv.expectedCodeSizeDelta();
867
0
    LLVM_DEBUG(dbgs() << "Code size delta:  " << CodeSizeDelta << '\n');
868
0
    // If we are minimizing the code size, do the conversion whatever
869
0
    // the cost is.
870
0
    if (CodeSizeDelta < 0)
871
0
      return true;
872
0
    if (CodeSizeDelta > 0) {
873
0
      LLVM_DEBUG(dbgs() << "Code size is increasing, give up on this one.\n");
874
0
      return false;
875
0
    }
876
15.4k
    // CodeSizeDelta == 0, continue with the regular heuristics
877
15.4k
  }
878
15.4k
879
15.4k
  // Heuristic: The compare conversion delays the execution of the branch
880
15.4k
  // instruction because we must wait for the inputs to the second compare as
881
15.4k
  // well. The branch has no dependent instructions, but delaying it increases
882
15.4k
  // the cost of a misprediction.
883
15.4k
  //
884
15.4k
  // Set a limit on the delay we will accept.
885
15.4k
  unsigned DelayLimit = SchedModel.MispredictPenalty * 3 / 4;
886
15.4k
887
15.4k
  // Instruction depths can be computed for all trace instructions above CmpBB.
888
15.4k
  unsigned HeadDepth =
889
15.4k
      Trace.getInstrCycles(*CmpConv.Head->getFirstTerminator()).Depth;
890
15.4k
  unsigned CmpBBDepth =
891
15.4k
      Trace.getInstrCycles(*CmpConv.CmpBB->getFirstTerminator()).Depth;
892
15.4k
  LLVM_DEBUG(dbgs() << "Head depth:  " << HeadDepth
893
15.4k
                    << "\nCmpBB depth: " << CmpBBDepth << '\n');
894
15.4k
  if (CmpBBDepth > HeadDepth + DelayLimit) {
895
149
    LLVM_DEBUG(dbgs() << "Branch delay would be larger than " << DelayLimit
896
149
                      << " cycles.\n");
897
149
    return false;
898
149
  }
899
15.3k
900
15.3k
  // Check the resource depth at the bottom of CmpBB - these instructions will
901
15.3k
  // be speculated.
902
15.3k
  unsigned ResDepth = Trace.getResourceDepth(true);
903
15.3k
  LLVM_DEBUG(dbgs() << "Resources:   " << ResDepth << '\n');
904
15.3k
905
15.3k
  // Heuristic: The speculatively executed instructions must all be able to
906
15.3k
  // merge into the Head block. The Head critical path should dominate the
907
15.3k
  // resource cost of the speculated instructions.
908
15.3k
  if (ResDepth > HeadDepth) {
909
12.7k
    LLVM_DEBUG(dbgs() << "Too many instructions to speculate.\n");
910
12.7k
    return false;
911
12.7k
  }
912
2.57k
  return true;
913
2.57k
}
914
915
2.00M
bool AArch64ConditionalCompares::tryConvert(MachineBasicBlock *MBB) {
916
2.00M
  bool Changed = false;
917
2.00M
  while (CmpConv.canConvert(MBB) && 
shouldConvert()15.4k
) {
918
2.58k
    invalidateTraces();
919
2.58k
    SmallVector<MachineBasicBlock *, 4> RemovedBlocks;
920
2.58k
    CmpConv.convert(RemovedBlocks);
921
2.58k
    Changed = true;
922
2.58k
    updateDomTree(RemovedBlocks);
923
2.58k
    updateLoops(RemovedBlocks);
924
2.58k
  }
925
2.00M
  return Changed;
926
2.00M
}
927
928
257k
bool AArch64ConditionalCompares::runOnMachineFunction(MachineFunction &MF) {
929
257k
  LLVM_DEBUG(dbgs() << "********** AArch64 Conditional Compares **********\n"
930
257k
                    << "********** Function: " << MF.getName() << '\n');
931
257k
  if (skipFunction(MF.getFunction()))
932
16
    return false;
933
257k
934
257k
  TII = MF.getSubtarget().getInstrInfo();
935
257k
  TRI = MF.getSubtarget().getRegisterInfo();
936
257k
  SchedModel = MF.getSubtarget().getSchedModel();
937
257k
  MRI = &MF.getRegInfo();
938
257k
  DomTree = &getAnalysis<MachineDominatorTree>();
939
257k
  Loops = getAnalysisIfAvailable<MachineLoopInfo>();
940
257k
  MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
941
257k
  Traces = &getAnalysis<MachineTraceMetrics>();
942
257k
  MinInstr = nullptr;
943
257k
  MinSize = MF.getFunction().hasMinSize();
944
257k
945
257k
  bool Changed = false;
946
257k
  CmpConv.runOnMachineFunction(MF, MBPI);
947
257k
948
257k
  // Visit blocks in dominator tree pre-order. The pre-order enables multiple
949
257k
  // cmp-conversions from the same head block.
950
257k
  // Note that updateDomTree() modifies the children of the DomTree node
951
257k
  // currently being visited. The df_iterator supports that; it doesn't look at
952
257k
  // child_begin() / child_end() until after a node has been visited.
953
257k
  for (auto *I : depth_first(DomTree))
954
2.00M
    if (tryConvert(I->getBlock()))
955
2.09k
      Changed = true;
956
257k
957
257k
  return Changed;
958
257k
}