Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AArch64/AArch64ISelLowering.h
Line
Count
Source (jump to first uncovered line)
1
//==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file defines the interfaces that AArch64 uses to lower LLVM code into a
10
// selection DAG.
11
//
12
//===----------------------------------------------------------------------===//
13
14
#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
15
#define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
16
17
#include "AArch64.h"
18
#include "llvm/CodeGen/CallingConvLower.h"
19
#include "llvm/CodeGen/SelectionDAG.h"
20
#include "llvm/CodeGen/TargetLowering.h"
21
#include "llvm/IR/CallingConv.h"
22
#include "llvm/IR/Instruction.h"
23
24
namespace llvm {
25
26
namespace AArch64ISD {
27
28
enum NodeType : unsigned {
29
  FIRST_NUMBER = ISD::BUILTIN_OP_END,
30
  WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
31
  CALL,         // Function call.
32
33
  // Produces the full sequence of instructions for getting the thread pointer
34
  // offset of a variable into X0, using the TLSDesc model.
35
  TLSDESC_CALLSEQ,
36
  ADRP,     // Page address of a TargetGlobalAddress operand.
37
  ADR,      // ADR
38
  ADDlow,   // Add the low 12 bits of a TargetGlobalAddress operand.
39
  LOADgot,  // Load from automatically generated descriptor (e.g. Global
40
            // Offset Table, TLS record).
41
  RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand.
42
  BRCOND,   // Conditional branch instruction; "b.cond".
43
  CSEL,
44
  FCSEL, // Conditional move instruction.
45
  CSINV, // Conditional select invert.
46
  CSNEG, // Conditional select negate.
47
  CSINC, // Conditional select increment.
48
49
  // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on
50
  // ELF.
51
  THREAD_POINTER,
52
  ADC,
53
  SBC, // adc, sbc instructions
54
55
  // Arithmetic instructions which write flags.
56
  ADDS,
57
  SUBS,
58
  ADCS,
59
  SBCS,
60
  ANDS,
61
62
  // Conditional compares. Operands: left,right,falsecc,cc,flags
63
  CCMP,
64
  CCMN,
65
  FCCMP,
66
67
  // Floating point comparison
68
  FCMP,
69
70
  // Scalar extract
71
  EXTR,
72
73
  // Scalar-to-vector duplication
74
  DUP,
75
  DUPLANE8,
76
  DUPLANE16,
77
  DUPLANE32,
78
  DUPLANE64,
79
80
  // Vector immedate moves
81
  MOVI,
82
  MOVIshift,
83
  MOVIedit,
84
  MOVImsl,
85
  FMOV,
86
  MVNIshift,
87
  MVNImsl,
88
89
  // Vector immediate ops
90
  BICi,
91
  ORRi,
92
93
  // Vector bit select: similar to ISD::VSELECT but not all bits within an
94
  // element must be identical.
95
  BSL,
96
97
  // Vector arithmetic negation
98
  NEG,
99
100
  // Vector shuffles
101
  ZIP1,
102
  ZIP2,
103
  UZP1,
104
  UZP2,
105
  TRN1,
106
  TRN2,
107
  REV16,
108
  REV32,
109
  REV64,
110
  EXT,
111
112
  // Vector shift by scalar
113
  VSHL,
114
  VLSHR,
115
  VASHR,
116
117
  // Vector shift by scalar (again)
118
  SQSHL_I,
119
  UQSHL_I,
120
  SQSHLU_I,
121
  SRSHR_I,
122
  URSHR_I,
123
124
  // Vector comparisons
125
  CMEQ,
126
  CMGE,
127
  CMGT,
128
  CMHI,
129
  CMHS,
130
  FCMEQ,
131
  FCMGE,
132
  FCMGT,
133
134
  // Vector zero comparisons
135
  CMEQz,
136
  CMGEz,
137
  CMGTz,
138
  CMLEz,
139
  CMLTz,
140
  FCMEQz,
141
  FCMGEz,
142
  FCMGTz,
143
  FCMLEz,
144
  FCMLTz,
145
146
  // Vector across-lanes addition
147
  // Only the lower result lane is defined.
148
  SADDV,
149
  UADDV,
150
151
  // Vector across-lanes min/max
152
  // Only the lower result lane is defined.
153
  SMINV,
154
  UMINV,
155
  SMAXV,
156
  UMAXV,
157
158
  // Vector bitwise negation
159
  NOT,
160
161
  // Vector bitwise selection
162
  BIT,
163
164
  // Compare-and-branch
165
  CBZ,
166
  CBNZ,
167
  TBZ,
168
  TBNZ,
169
170
  // Tail calls
171
  TC_RETURN,
172
173
  // Custom prefetch handling
174
  PREFETCH,
175
176
  // {s|u}int to FP within a FP register.
177
  SITOF,
178
  UITOF,
179
180
  /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
181
  /// world w.r.t vectors; which causes additional REV instructions to be
182
  /// generated to compensate for the byte-swapping. But sometimes we do
183
  /// need to re-interpret the data in SIMD vector registers in big-endian
184
  /// mode without emitting such REV instructions.
185
  NVCAST,
186
187
  SMULL,
188
  UMULL,
189
190
  // Reciprocal estimates and steps.
191
  FRECPE, FRECPS,
192
  FRSQRTE, FRSQRTS,
193
194
  // NEON Load/Store with post-increment base updates
195
  LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
196
  LD3post,
197
  LD4post,
198
  ST2post,
199
  ST3post,
200
  ST4post,
201
  LD1x2post,
202
  LD1x3post,
203
  LD1x4post,
204
  ST1x2post,
205
  ST1x3post,
206
  ST1x4post,
207
  LD1DUPpost,
208
  LD2DUPpost,
209
  LD3DUPpost,
210
  LD4DUPpost,
211
  LD1LANEpost,
212
  LD2LANEpost,
213
  LD3LANEpost,
214
  LD4LANEpost,
215
  ST2LANEpost,
216
  ST3LANEpost,
217
  ST4LANEpost,
218
219
  STG,
220
  STZG,
221
  ST2G,
222
  STZ2G
223
224
};
225
226
} // end namespace AArch64ISD
227
228
namespace {
229
230
// Any instruction that defines a 32-bit result zeros out the high half of the
231
// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
232
// be copying from a truncate. But any other 32-bit operation will zero-extend
233
// up to 64 bits.
234
// FIXME: X86 also checks for CMOV here. Do we need something similar?
235
13.0k
static inline bool isDef32(const SDNode &N) {
236
13.0k
  unsigned Opc = N.getOpcode();
237
13.0k
  return Opc != ISD::TRUNCATE && Opc != TargetOpcode::EXTRACT_SUBREG &&
238
13.0k
         Opc != ISD::CopyFromReg;
239
13.0k
}
Unexecuted instantiation: AArch64A57FPLoadBalancing.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64AsmPrinter.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64BranchTargets.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64CallingConvention.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64CallLowering.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64CondBrTuning.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64DeadRegisterDefinitionsPass.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64ExpandPseudoInsts.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64FalkorHWPFFix.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64FastISel.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64FrameLowering.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64CompressJumpTables.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
AArch64ISelDAGToDAG.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Line
Count
Source
235
13.0k
static inline bool isDef32(const SDNode &N) {
236
13.0k
  unsigned Opc = N.getOpcode();
237
13.0k
  return Opc != ISD::TRUNCATE && Opc != TargetOpcode::EXTRACT_SUBREG &&
238
13.0k
         Opc != ISD::CopyFromReg;
239
13.0k
}
Unexecuted instantiation: AArch64ISelLowering.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64InstrInfo.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64InstructionSelector.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64LegalizerInfo.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64LoadStoreOptimizer.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64MacroFusion.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64PreLegalizerCombiner.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64RegisterInfo.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64SelectionDAGInfo.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64SpeculationHardening.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64StackTagging.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64Subtarget.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64TargetMachine.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64TargetObjectFile.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
Unexecuted instantiation: AArch64TargetTransformInfo.cpp:llvm::(anonymous namespace)::isDef32(llvm::SDNode const&)
240
241
} // end anonymous namespace
242
243
class AArch64Subtarget;
244
class AArch64TargetMachine;
245
246
class AArch64TargetLowering : public TargetLowering {
247
public:
248
  explicit AArch64TargetLowering(const TargetMachine &TM,
249
                                 const AArch64Subtarget &STI);
250
251
  /// Selects the correct CCAssignFn for a given CallingConvention value.
252
  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
253
254
  /// Selects the correct CCAssignFn for a given CallingConvention value.
255
  CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC) const;
256
257
  /// Determine which of the bits specified in Mask are known to be either zero
258
  /// or one and return them in the KnownZero/KnownOne bitsets.
259
  void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
260
                                     const APInt &DemandedElts,
261
                                     const SelectionDAG &DAG,
262
                                     unsigned Depth = 0) const override;
263
264
  bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
265
                                    TargetLoweringOpt &TLO) const override;
266
267
  MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
268
269
  /// Returns true if the target allows unaligned memory accesses of the
270
  /// specified type.
271
  bool allowsMisalignedMemoryAccesses(
272
      EVT VT, unsigned AddrSpace = 0, unsigned Align = 1,
273
      MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
274
      bool *Fast = nullptr) const override;
275
276
  /// Provide custom lowering hooks for some operations.
277
  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
278
279
  const char *getTargetNodeName(unsigned Opcode) const override;
280
281
  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
282
283
  /// Returns true if a cast between SrcAS and DestAS is a noop.
284
2
  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
285
2
    // Addrspacecasts are always noops.
286
2
    return true;
287
2
  }
288
289
  /// This method returns a target specific FastISel object, or null if the
290
  /// target does not support "fast" ISel.
291
  FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
292
                           const TargetLibraryInfo *libInfo) const override;
293
294
  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
295
296
  bool isFPImmLegal(const APFloat &Imm, EVT VT,
297
                    bool ForCodeSize) const override;
298
299
  /// Return true if the given shuffle mask can be codegen'd directly, or if it
300
  /// should be stack expanded.
301
  bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
302
303
  /// Return the ISD::SETCC ValueType.
304
  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
305
                         EVT VT) const override;
306
307
  SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
308
309
  MachineBasicBlock *EmitF128CSEL(MachineInstr &MI,
310
                                  MachineBasicBlock *BB) const;
311
312
  MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &MI,
313
                                           MachineBasicBlock *BB) const;
314
315
  MachineBasicBlock *EmitLoweredCatchPad(MachineInstr &MI,
316
                                         MachineBasicBlock *BB) const;
317
318
  MachineBasicBlock *
319
  EmitInstrWithCustomInserter(MachineInstr &MI,
320
                              MachineBasicBlock *MBB) const override;
321
322
  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
323
                          MachineFunction &MF,
324
                          unsigned Intrinsic) const override;
325
326
  bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
327
                             EVT NewVT) const override;
328
329
  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
330
  bool isTruncateFree(EVT VT1, EVT VT2) const override;
331
332
  bool isProfitableToHoist(Instruction *I) const override;
333
334
  bool isZExtFree(Type *Ty1, Type *Ty2) const override;
335
  bool isZExtFree(EVT VT1, EVT VT2) const override;
336
  bool isZExtFree(SDValue Val, EVT VT2) const override;
337
338
  bool shouldSinkOperands(Instruction *I,
339
                          SmallVectorImpl<Use *> &Ops) const override;
340
341
  bool hasPairedLoad(EVT LoadedType, unsigned &RequiredAligment) const override;
342
343
516k
  unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
344
345
  bool lowerInterleavedLoad(LoadInst *LI,
346
                            ArrayRef<ShuffleVectorInst *> Shuffles,
347
                            ArrayRef<unsigned> Indices,
348
                            unsigned Factor) const override;
349
  bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
350
                             unsigned Factor) const override;
351
352
  bool isLegalAddImmediate(int64_t) const override;
353
  bool isLegalICmpImmediate(int64_t) const override;
354
355
  bool shouldConsiderGEPOffsetSplit() const override;
356
357
  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
358
                          bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
359
                          const AttributeList &FuncAttributes) const override;
360
361
  /// Return true if the addressing mode represented by AM is legal for this
362
  /// target, for a load/store of the specified type.
363
  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
364
                             unsigned AS,
365
                             Instruction *I = nullptr) const override;
366
367
  /// Return the cost of the scaling factor used in the addressing
368
  /// mode represented by AM for this target, for a load/store
369
  /// of the specified type.
370
  /// If the AM is supported, the return value must be >= 0.
371
  /// If the AM is not supported, it returns a negative value.
372
  int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
373
                           unsigned AS) const override;
374
375
  /// Return true if an FMA operation is faster than a pair of fmul and fadd
376
  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
377
  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
378
  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
379
380
  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
381
382
  /// Returns false if N is a bit extraction pattern of (X >> C) & Mask.
383
  bool isDesirableToCommuteWithShift(const SDNode *N,
384
                                     CombineLevel Level) const override;
385
386
  /// Returns true if it is beneficial to convert a load of a constant
387
  /// to just the constant itself.
388
  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
389
                                         Type *Ty) const override;
390
391
  /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
392
  /// with this index.
393
  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
394
                               unsigned Index) const override;
395
396
  Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
397
                        AtomicOrdering Ord) const override;
398
  Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
399
                              Value *Addr, AtomicOrdering Ord) const override;
400
401
  void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
402
403
  TargetLoweringBase::AtomicExpansionKind
404
  shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
405
  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
406
  TargetLoweringBase::AtomicExpansionKind
407
  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
408
409
  TargetLoweringBase::AtomicExpansionKind
410
  shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
411
412
  bool useLoadStackGuardNode() const override;
413
  TargetLoweringBase::LegalizeTypeAction
414
  getPreferredVectorAction(MVT VT) const override;
415
416
  /// If the target has a standard location for the stack protector cookie,
417
  /// returns the address of that location. Otherwise, returns nullptr.
418
  Value *getIRStackGuard(IRBuilder<> &IRB) const override;
419
420
  void insertSSPDeclarations(Module &M) const override;
421
  Value *getSDagStackGuard(const Module &M) const override;
422
  Function *getSSPStackGuardCheck(const Module &M) const override;
423
424
  /// If the target has a standard location for the unsafe stack pointer,
425
  /// returns the address of that location. Otherwise, returns nullptr.
426
  Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override;
427
428
  /// If a physical register, this returns the register that receives the
429
  /// exception address on entry to an EH pad.
430
  unsigned
431
34.1k
  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
432
34.1k
    // FIXME: This is a guess. Has this been defined yet?
433
34.1k
    return AArch64::X0;
434
34.1k
  }
435
436
  /// If a physical register, this returns the register that receives the
437
  /// exception typeid on entry to a landing pad.
438
  unsigned
439
17.0k
  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
440
17.0k
    // FIXME: This is a guess. Has this been defined yet?
441
17.0k
    return AArch64::X1;
442
17.0k
  }
443
444
  bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
445
446
  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
447
17.0k
                        const SelectionDAG &DAG) const override {
448
17.0k
    // Do not merge to float value size (128 bytes) if no implicit
449
17.0k
    // float attribute is set.
450
17.0k
451
17.0k
    bool NoFloat = DAG.getMachineFunction().getFunction().hasFnAttribute(
452
17.0k
        Attribute::NoImplicitFloat);
453
17.0k
454
17.0k
    if (NoFloat)
455
8
      return (MemVT.getSizeInBits() <= 64);
456
17.0k
    return true;
457
17.0k
  }
458
459
814
  bool isCheapToSpeculateCttz() const override {
460
814
    return true;
461
814
  }
462
463
1.88k
  bool isCheapToSpeculateCtlz() const override {
464
1.88k
    return true;
465
1.88k
  }
466
467
  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
468
469
736
  bool hasAndNotCompare(SDValue V) const override {
470
736
    // We can use bics for any scalar.
471
736
    return V.getValueType().isScalarInteger();
472
736
  }
473
474
724
  bool hasAndNot(SDValue Y) const override {
475
724
    EVT VT = Y.getValueType();
476
724
477
724
    if (!VT.isVector())
478
678
      return hasAndNotCompare(Y);
479
46
480
46
    return VT.getSizeInBits() >= 64; // vector 'bic'
481
46
  }
482
483
27
  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {
484
27
    if (DAG.getMachineFunction().getFunction().hasMinSize())
485
3
      return false;
486
24
    return true;
487
24
  }
488
489
  bool shouldTransformSignedTruncationCheck(EVT XVT,
490
130
                                            unsigned KeptBits) const override {
491
130
    // For vectors, we don't have a preference..
492
130
    if (XVT.isVector())
493
0
      return false;
494
130
495
255
    
auto VTIsOk = [](EVT VT) -> bool 130
{
496
255
      return VT == MVT::i8 || 
VT == MVT::i16238
||
VT == MVT::i32199
||
497
255
             
VT == MVT::i64174
;
498
255
    };
499
130
500
130
    // We are ok with KeptBitsVT being byte/word/dword, what SXT supports.
501
130
    // XVT will be larger than KeptBitsVT.
502
130
    MVT KeptBitsVT = MVT::getIntegerVT(KeptBits);
503
130
    return VTIsOk(XVT) && 
VTIsOk(KeptBitsVT)125
;
504
130
  }
505
506
  bool preferIncOfAddToSubOfNot(EVT VT) const override;
507
508
16.5k
  bool hasBitPreservingFPLogic(EVT VT) const override {
509
16.5k
    // FIXME: Is this always true? It should be true for vectors at least.
510
16.5k
    return VT == MVT::f32 || 
VT == MVT::f6413.5k
;
511
16.5k
  }
512
513
39.1k
  bool supportSplitCSR(MachineFunction *MF) const override {
514
39.1k
    return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
515
39.1k
           
MF->getFunction().hasFnAttribute(Attribute::NoUnwind)14
;
516
39.1k
  }
517
  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
518
  void insertCopiesSplitCSR(
519
      MachineBasicBlock *Entry,
520
      const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
521
522
7.80M
  bool supportSwiftError() const override {
523
7.80M
    return true;
524
7.80M
  }
525
526
  /// Enable aggressive FMA fusion on targets that want it.
527
  bool enableAggressiveFMAFusion(EVT VT) const override;
528
529
  /// Returns the size of the platform's va_list object.
530
  unsigned getVaListSizeInBits(const DataLayout &DL) const override;
531
532
  /// Returns true if \p VecTy is a legal interleaved access type. This
533
  /// function checks the vector element type and the overall width of the
534
  /// vector.
535
  bool isLegalInterleavedAccessType(VectorType *VecTy,
536
                                    const DataLayout &DL) const;
537
538
  /// Returns the number of interleaved accesses that will be generated when
539
  /// lowering accesses of the given type.
540
  unsigned getNumInterleavedAccesses(VectorType *VecTy,
541
                                     const DataLayout &DL) const;
542
543
  MachineMemOperand::Flags getMMOFlags(const Instruction &I) const override;
544
545
  bool functionArgumentNeedsConsecutiveRegisters(Type *Ty,
546
                                                 CallingConv::ID CallConv,
547
                                                 bool isVarArg) const override;
548
  /// Used for exception handling on Win64.
549
  bool needsFixedCatchObjects() const override;
550
private:
551
  /// Keep a pointer to the AArch64Subtarget around so that we can
552
  /// make the right decision when generating code for different targets.
553
  const AArch64Subtarget *Subtarget;
554
555
  bool isExtFreeImpl(const Instruction *Ext) const override;
556
557
  void addTypeForNEON(MVT VT, MVT PromotedBitwiseVT);
558
  void addDRTypeForNEON(MVT VT);
559
  void addQRTypeForNEON(MVT VT);
560
561
  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
562
                               bool isVarArg,
563
                               const SmallVectorImpl<ISD::InputArg> &Ins,
564
                               const SDLoc &DL, SelectionDAG &DAG,
565
                               SmallVectorImpl<SDValue> &InVals) const override;
566
567
  SDValue LowerCall(CallLoweringInfo & /*CLI*/,
568
                    SmallVectorImpl<SDValue> &InVals) const override;
569
570
  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
571
                          CallingConv::ID CallConv, bool isVarArg,
572
                          const SmallVectorImpl<ISD::InputArg> &Ins,
573
                          const SDLoc &DL, SelectionDAG &DAG,
574
                          SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
575
                          SDValue ThisVal) const;
576
577
  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
578
579
  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
580
581
  bool isEligibleForTailCallOptimization(
582
      SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
583
      const SmallVectorImpl<ISD::OutputArg> &Outs,
584
      const SmallVectorImpl<SDValue> &OutVals,
585
      const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
586
587
  /// Finds the incoming stack arguments which overlap the given fixed stack
588
  /// object and incorporates their load into the current chain. This prevents
589
  /// an upcoming store from clobbering the stack argument before it's used.
590
  SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
591
                              MachineFrameInfo &MFI, int ClobberedFI) const;
592
593
  bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
594
595
  void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL,
596
                           SDValue &Chain) const;
597
598
  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
599
                      bool isVarArg,
600
                      const SmallVectorImpl<ISD::OutputArg> &Outs,
601
                      LLVMContext &Context) const override;
602
603
  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
604
                      const SmallVectorImpl<ISD::OutputArg> &Outs,
605
                      const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
606
                      SelectionDAG &DAG) const override;
607
608
  SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
609
                        unsigned Flag) const;
610
  SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
611
                        unsigned Flag) const;
612
  SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
613
                        unsigned Flag) const;
614
  SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
615
                        unsigned Flag) const;
616
  template <class NodeTy>
617
  SDValue getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
618
  template <class NodeTy>
619
  SDValue getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
620
  template <class NodeTy>
621
  SDValue getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
622
  template <class NodeTy>
623
  SDValue getAddrTiny(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
624
  SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
625
  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
626
  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
627
  SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
628
  SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
629
  SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, const SDLoc &DL,
630
                                 SelectionDAG &DAG) const;
631
  SDValue LowerWindowsGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
632
  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
633
  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
634
  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
635
  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
636
  SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS,
637
                         SDValue TVal, SDValue FVal, const SDLoc &dl,
638
                         SelectionDAG &DAG) const;
639
  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
640
  SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
641
  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
642
  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
643
  SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
644
  SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
645
  SDValue LowerWin64_VASTART(SDValue Op, SelectionDAG &DAG) const;
646
  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
647
  SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
648
  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
649
  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
650
  SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const;
651
  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
652
  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
653
  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
654
  SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
655
  SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
656
  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
657
  SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
658
  SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
659
  SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
660
  SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
661
  SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
662
  SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
663
  SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
664
  SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG,
665
                        RTLIB::Libcall Call) const;
666
  SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
667
  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
668
  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
669
  SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
670
  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
671
  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
672
  SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
673
  SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
674
  SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
675
  SDValue LowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
676
  SDValue LowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
677
  SDValue LowerATOMIC_LOAD_AND(SDValue Op, SelectionDAG &DAG) const;
678
  SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
679
  SDValue LowerWindowsDYNAMIC_STACKALLOC(SDValue Op, SDValue Chain,
680
                                         SDValue &Size,
681
                                         SelectionDAG &DAG) const;
682
683
  SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
684
                        SmallVectorImpl<SDNode *> &Created) const override;
685
  SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
686
                          int &ExtraSteps, bool &UseOneConst,
687
                          bool Reciprocal) const override;
688
  SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
689
                           int &ExtraSteps) const override;
690
  unsigned combineRepeatedFPDivisors() const override;
691
692
  ConstraintType getConstraintType(StringRef Constraint) const override;
693
  unsigned getRegisterByName(const char* RegName, EVT VT,
694
                             SelectionDAG &DAG) const override;
695
696
  /// Examine constraint string and operand type and determine a weight value.
697
  /// The operand object must already have been set up with the operand type.
698
  ConstraintWeight
699
  getSingleConstraintMatchWeight(AsmOperandInfo &info,
700
                                 const char *constraint) const override;
701
702
  std::pair<unsigned, const TargetRegisterClass *>
703
  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
704
                               StringRef Constraint, MVT VT) const override;
705
706
  const char *LowerXConstraint(EVT ConstraintVT) const override;
707
708
  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
709
                                    std::vector<SDValue> &Ops,
710
                                    SelectionDAG &DAG) const override;
711
712
41
  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
713
41
    if (ConstraintCode == "Q")
714
2
      return InlineAsm::Constraint_Q;
715
39
    // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
716
39
    //        followed by llvm_unreachable so we'll leave them unimplemented in
717
39
    //        the backend for now.
718
39
    return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
719
39
  }
720
721
  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
722
  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
723
  bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
724
                              ISD::MemIndexedMode &AM, bool &IsInc,
725
                              SelectionDAG &DAG) const;
726
  bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
727
                                 ISD::MemIndexedMode &AM,
728
                                 SelectionDAG &DAG) const override;
729
  bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
730
                                  SDValue &Offset, ISD::MemIndexedMode &AM,
731
                                  SelectionDAG &DAG) const override;
732
733
  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
734
                          SelectionDAG &DAG) const override;
735
736
  bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
737
738
  void finalizeLowering(MachineFunction &MF) const override;
739
};
740
741
namespace AArch64 {
742
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
743
                         const TargetLibraryInfo *libInfo);
744
} // end namespace AArch64
745
746
} // end namespace llvm
747
748
#endif