Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AArch64/AArch64InstrInfo.h
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//===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the AArch64 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
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#include "AArch64.h"
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#include "AArch64RegisterInfo.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/CodeGen/MachineCombinerPattern.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "AArch64GenInstrInfo.inc"
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namespace llvm {
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class AArch64Subtarget;
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class AArch64TargetMachine;
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static const MachineMemOperand::Flags MOSuppressPair =
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    MachineMemOperand::MOTargetFlag1;
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static const MachineMemOperand::Flags MOStridedAccess =
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    MachineMemOperand::MOTargetFlag2;
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#define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access"
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class AArch64InstrInfo final : public AArch64GenInstrInfo {
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  const AArch64RegisterInfo RI;
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  const AArch64Subtarget &Subtarget;
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public:
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  explicit AArch64InstrInfo(const AArch64Subtarget &STI);
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  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
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  /// such, whenever a client has an instance of instruction info, it should
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  /// always be able to get register info as well (through this method).
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180M
  const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
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  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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  bool isAsCheapAsAMove(const MachineInstr &MI) const override;
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  bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
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                             unsigned &DstReg, unsigned &SubIdx) const override;
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  bool
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  areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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                                  const MachineInstr &MIb,
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                                  AliasAnalysis *AA = nullptr) const override;
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  unsigned isLoadFromStackSlot(const MachineInstr &MI,
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                               int &FrameIndex) const override;
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  unsigned isStoreToStackSlot(const MachineInstr &MI,
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                              int &FrameIndex) const override;
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  /// Does this instruction set its full destination register to zero?
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  static bool isGPRZero(const MachineInstr &MI);
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  /// Does this instruction rename a GPR without modifying bits?
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  static bool isGPRCopy(const MachineInstr &MI);
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  /// Does this instruction rename an FPR without modifying bits?
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  static bool isFPRCopy(const MachineInstr &MI);
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  /// Return true if pairing the given load or store is hinted to be
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  /// unprofitable.
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  static bool isLdStPairSuppressed(const MachineInstr &MI);
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  /// Return true if the given load or store is a strided memory access.
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  static bool isStridedAccess(const MachineInstr &MI);
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  /// Return true if this is an unscaled load/store.
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  static bool isUnscaledLdSt(unsigned Opc);
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7.81M
  static bool isUnscaledLdSt(MachineInstr &MI) {
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7.81M
    return isUnscaledLdSt(MI.getOpcode());
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7.81M
  }
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  /// Returns the unscaled load/store for the scaled load/store opcode,
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  /// if there is a corresponding unscaled variant available.
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  static Optional<unsigned> getUnscaledLdSt(unsigned Opc);
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  /// Returns the index for the immediate for a given instruction.
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  static unsigned getLoadStoreImmIdx(unsigned Opc);
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  /// Return true if pairing the given load or store may be paired with another.
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  static bool isPairableLdStInst(const MachineInstr &MI);
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  /// Return the opcode that set flags when possible.  The caller is
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  /// responsible for ensuring the opc has a flag setting equivalent.
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  static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit);
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  /// Return true if this is a load/store that can be potentially paired/merged.
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  bool isCandidateToMergeOrPair(const MachineInstr &MI) const;
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  /// Hint that pairing the given load or store is unprofitable.
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  static void suppressLdStPair(MachineInstr &MI);
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  bool getMemOperandWithOffset(const MachineInstr &MI,
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                               const MachineOperand *&BaseOp,
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                               int64_t &Offset,
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                               const TargetRegisterInfo *TRI) const override;
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  bool getMemOperandWithOffsetWidth(const MachineInstr &MI,
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                                    const MachineOperand *&BaseOp,
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                                    int64_t &Offset, unsigned &Width,
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                                    const TargetRegisterInfo *TRI) const;
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  /// Return the immediate offset of the base register in a load/store \p LdSt.
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  MachineOperand &getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const;
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  /// Returns true if opcode \p Opc is a memory operation. If it is, set
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  /// \p Scale, \p Width, \p MinOffset, and \p MaxOffset accordingly.
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  ///
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  /// For unscaled instructions, \p Scale is set to 1.
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  static bool getMemOpInfo(unsigned Opcode, unsigned &Scale, unsigned &Width,
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                           int64_t &MinOffset, int64_t &MaxOffset);
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  bool shouldClusterMemOps(const MachineOperand &BaseOp1,
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                           const MachineOperand &BaseOp2,
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                           unsigned NumLoads) const override;
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  void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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                        const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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                        bool KillSrc, unsigned Opcode,
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                        llvm::ArrayRef<unsigned> Indices) const;
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  void copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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                       DebugLoc DL, unsigned DestReg, unsigned SrcReg,
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                       bool KillSrc, unsigned Opcode, unsigned ZeroReg,
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                       llvm::ArrayRef<unsigned> Indices) const;
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  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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                   const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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                   bool KillSrc) const override;
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  void storeRegToStackSlot(MachineBasicBlock &MBB,
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                           MachineBasicBlock::iterator MBBI, unsigned SrcReg,
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                           bool isKill, int FrameIndex,
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                           const TargetRegisterClass *RC,
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                           const TargetRegisterInfo *TRI) const override;
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  void loadRegFromStackSlot(MachineBasicBlock &MBB,
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                            MachineBasicBlock::iterator MBBI, unsigned DestReg,
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                            int FrameIndex, const TargetRegisterClass *RC,
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                            const TargetRegisterInfo *TRI) const override;
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  // This tells target independent code that it is okay to pass instructions
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  // with subreg operands to foldMemoryOperandImpl.
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253k
  bool isSubregFoldable() const override { return true; }
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  using TargetInstrInfo::foldMemoryOperandImpl;
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  MachineInstr *
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  foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
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                        ArrayRef<unsigned> Ops,
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                        MachineBasicBlock::iterator InsertPt, int FrameIndex,
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                        LiveIntervals *LIS = nullptr,
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                        VirtRegMap *VRM = nullptr) const override;
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  /// \returns true if a branch from an instruction with opcode \p BranchOpc
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  ///  bytes is capable of jumping to a position \p BrOffset bytes away.
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  bool isBranchOffsetInRange(unsigned BranchOpc,
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                             int64_t BrOffset) const override;
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  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
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  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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                     MachineBasicBlock *&FBB,
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                     SmallVectorImpl<MachineOperand> &Cond,
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                     bool AllowModify = false) const override;
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  unsigned removeBranch(MachineBasicBlock &MBB,
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                        int *BytesRemoved = nullptr) const override;
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  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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                        MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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                        const DebugLoc &DL,
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                        int *BytesAdded = nullptr) const override;
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  bool
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  reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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  bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
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                       unsigned, unsigned, int &, int &, int &) const override;
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  void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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                    const DebugLoc &DL, unsigned DstReg,
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                    ArrayRef<MachineOperand> Cond, unsigned TrueReg,
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                    unsigned FalseReg) const override;
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  void getNoop(MCInst &NopInst) const override;
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  bool isSchedulingBoundary(const MachineInstr &MI,
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                            const MachineBasicBlock *MBB,
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                            const MachineFunction &MF) const override;
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  /// analyzeCompare - For a comparison instruction, return the source registers
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  /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
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  /// Return true if the comparison instruction can be analyzed.
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  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
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                      unsigned &SrcReg2, int &CmpMask,
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                      int &CmpValue) const override;
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  /// optimizeCompareInstr - Convert the instruction supplying the argument to
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  /// the comparison into one that sets the zero bit in the flags register.
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  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
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                            unsigned SrcReg2, int CmpMask, int CmpValue,
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                            const MachineRegisterInfo *MRI) const override;
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  bool optimizeCondBranch(MachineInstr &MI) const override;
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  /// Return true when a code sequence can improve throughput. It
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  /// should be called only for instructions in loops.
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  /// \param Pattern - combiner pattern
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  bool isThroughputPattern(MachineCombinerPattern Pattern) const override;
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  /// Return true when there is potentially a faster code sequence
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  /// for an instruction chain ending in ``Root``. All potential patterns are
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  /// listed in the ``Patterns`` array.
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  bool getMachineCombinerPatterns(
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      MachineInstr &Root,
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      SmallVectorImpl<MachineCombinerPattern> &Patterns) const override;
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  /// Return true when Inst is associative and commutative so that it can be
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  /// reassociated.
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  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
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  /// When getMachineCombinerPatterns() finds patterns, this function generates
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  /// the instructions that could replace the original code sequence
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  void genAlternativeCodeSequence(
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      MachineInstr &Root, MachineCombinerPattern Pattern,
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      SmallVectorImpl<MachineInstr *> &InsInstrs,
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      SmallVectorImpl<MachineInstr *> &DelInstrs,
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      DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
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  /// AArch64 supports MachineCombiner.
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  bool useMachineCombiner() const override;
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  bool expandPostRAPseudo(MachineInstr &MI) const override;
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  std::pair<unsigned, unsigned>
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  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
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  ArrayRef<std::pair<unsigned, const char *>>
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  getSerializableDirectMachineOperandTargetFlags() const override;
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  ArrayRef<std::pair<unsigned, const char *>>
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  getSerializableBitmaskMachineOperandTargetFlags() const override;
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  ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
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  getSerializableMachineMemOperandTargetFlags() const override;
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  bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
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                                   bool OutlineFromLinkOnceODRs) const override;
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  outliner::OutlinedFunction getOutliningCandidateInfo(
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      std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
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  outliner::InstrType
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  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
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  bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
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                              unsigned &Flags) const override;
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  void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
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                          const outliner::OutlinedFunction &OF) const override;
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  MachineBasicBlock::iterator
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  insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
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                     MachineBasicBlock::iterator &It, MachineFunction &MF,
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                     const outliner::Candidate &C) const override;
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  bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
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  /// Returns true if the instruction has a shift by immediate that can be
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  /// executed in one cycle less.
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  static bool isFalkorShiftExtFast(const MachineInstr &MI);
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  /// Return true if the instructions is a SEH instruciton used for unwinding
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  /// on Windows.
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  static bool isSEHInstruction(const MachineInstr &MI);
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#define GET_INSTRINFO_HELPER_DECLS
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#include "AArch64GenInstrInfo.inc"
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protected:
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  /// If the specific machine instruction is a instruction that moves/copies
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  /// value from one register to another register return true along with
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  /// @Source machine operand and @Destination machine operand.
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  bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
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                       const MachineOperand *&Destination) const override;
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private:
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  /// Sets the offsets on outlined instructions in \p MBB which use SP
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  /// so that they will be valid post-outlining.
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  ///
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  /// \param MBB A \p MachineBasicBlock in an outlined function.
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  void fixupPostOutline(MachineBasicBlock &MBB) const;
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  void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
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                             MachineBasicBlock *TBB,
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                             ArrayRef<MachineOperand> Cond) const;
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  bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
289
                           const MachineRegisterInfo *MRI) const;
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  /// Returns an unused general-purpose register which can be used for
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  /// constructing an outlined call if one exists. Returns 0 otherwise.
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  unsigned findRegisterToSaveLRTo(const outliner::Candidate &C) const;
294
};
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/// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
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/// plus Offset.  This is intended to be used from within the prolog/epilog
298
/// insertion (PEI) pass, where a virtual scratch register may be allocated
299
/// if necessary, to be replaced by the scavenger at the end of PEI.
300
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
301
                     const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
302
                     int Offset, const TargetInstrInfo *TII,
303
                     MachineInstr::MIFlag = MachineInstr::NoFlags,
304
                     bool SetNZCV = false, bool NeedsWinCFI = false,
305
                     bool *HasWinCFI = nullptr);
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/// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
308
/// FP. Return false if the offset could not be handled directly in MI, and
309
/// return the left-over portion by reference.
310
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
311
                              unsigned FrameReg, int &Offset,
312
                              const AArch64InstrInfo *TII);
313
314
/// Use to report the frame offset status in isAArch64FrameOffsetLegal.
315
enum AArch64FrameOffsetStatus {
316
  AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
317
  AArch64FrameOffsetIsLegal = 0x1,      ///< Offset is legal.
318
  AArch64FrameOffsetCanUpdate = 0x2     ///< Offset can apply, at least partly.
319
};
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/// Check if the @p Offset is a valid frame offset for @p MI.
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/// The returned value reports the validity of the frame offset for @p MI.
323
/// It uses the values defined by AArch64FrameOffsetStatus for that.
324
/// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
325
/// use an offset.eq
326
/// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
327
/// rewritten in @p MI.
328
/// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
329
/// amount that is off the limit of the legal offset.
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/// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
331
/// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
332
/// If set, @p EmittableOffset contains the amount that can be set in @p MI
333
/// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
334
/// is a legal offset.
335
int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
336
                              bool *OutUseUnscaledOp = nullptr,
337
                              unsigned *OutUnscaledOp = nullptr,
338
                              int *EmittableOffset = nullptr);
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54.5M
static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
Unexecuted instantiation: AArch64A57FPLoadBalancing.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64AdvSIMDScalarPass.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64AsmPrinter.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64BranchTargets.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64CallingConvention.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64CallLowering.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64CleanupLocalDynamicTLSPass.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64CollectLOH.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64CondBrTuning.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64DeadRegisterDefinitionsPass.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64ExpandPseudoInsts.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64FalkorHWPFFix.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64FastISel.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64FrameLowering.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64CompressJumpTables.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64ISelDAGToDAG.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64ISelLowering.cpp:llvm::isUncondBranchOpcode(int)
AArch64InstrInfo.cpp:llvm::isUncondBranchOpcode(int)
Line
Count
Source
340
54.5M
static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
Unexecuted instantiation: AArch64InstructionSelector.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64LegalizerInfo.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64LoadStoreOptimizer.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64MacroFusion.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64PreLegalizerCombiner.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64RegisterBankInfo.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64RegisterInfo.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64SelectionDAGInfo.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64SpeculationHardening.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64StackTagging.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64StorePairSuppress.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64Subtarget.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64TargetMachine.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64TargetObjectFile.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64TargetTransformInfo.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64SIMDInstrOpt.cpp:llvm::isUncondBranchOpcode(int)
Unexecuted instantiation: AArch64AsmParser.cpp:llvm::isUncondBranchOpcode(int)
341
342
46.1M
static inline bool isCondBranchOpcode(int Opc) {
343
46.1M
  switch (Opc) {
344
46.1M
  case AArch64::Bcc:
345
36.6M
  case AArch64::CBZW:
346
36.6M
  case AArch64::CBZX:
347
36.6M
  case AArch64::CBNZW:
348
36.6M
  case AArch64::CBNZX:
349
36.6M
  case AArch64::TBZW:
350
36.6M
  case AArch64::TBZX:
351
36.6M
  case AArch64::TBNZW:
352
36.6M
  case AArch64::TBNZX:
353
36.6M
    return true;
354
36.6M
  default:
355
9.52M
    return false;
356
46.1M
  }
357
46.1M
}
Unexecuted instantiation: AArch64A57FPLoadBalancing.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64AdvSIMDScalarPass.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64AsmPrinter.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64BranchTargets.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64CallingConvention.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64CallLowering.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64CleanupLocalDynamicTLSPass.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64CollectLOH.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64CondBrTuning.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64DeadRegisterDefinitionsPass.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64ExpandPseudoInsts.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64FalkorHWPFFix.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64FastISel.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64FrameLowering.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64CompressJumpTables.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64ISelDAGToDAG.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64ISelLowering.cpp:llvm::isCondBranchOpcode(int)
AArch64InstrInfo.cpp:llvm::isCondBranchOpcode(int)
Line
Count
Source
342
46.1M
static inline bool isCondBranchOpcode(int Opc) {
343
46.1M
  switch (Opc) {
344
46.1M
  case AArch64::Bcc:
345
36.6M
  case AArch64::CBZW:
346
36.6M
  case AArch64::CBZX:
347
36.6M
  case AArch64::CBNZW:
348
36.6M
  case AArch64::CBNZX:
349
36.6M
  case AArch64::TBZW:
350
36.6M
  case AArch64::TBZX:
351
36.6M
  case AArch64::TBNZW:
352
36.6M
  case AArch64::TBNZX:
353
36.6M
    return true;
354
36.6M
  default:
355
9.52M
    return false;
356
46.1M
  }
357
46.1M
}
Unexecuted instantiation: AArch64InstructionSelector.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64LegalizerInfo.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64LoadStoreOptimizer.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64MacroFusion.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64PreLegalizerCombiner.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64RegisterBankInfo.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64RegisterInfo.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64SelectionDAGInfo.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64SpeculationHardening.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64StackTagging.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64StorePairSuppress.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64Subtarget.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64TargetMachine.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64TargetObjectFile.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64TargetTransformInfo.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64SIMDInstrOpt.cpp:llvm::isCondBranchOpcode(int)
Unexecuted instantiation: AArch64AsmParser.cpp:llvm::isCondBranchOpcode(int)
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static inline bool isIndirectBranchOpcode(int Opc) {
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  return Opc == AArch64::BR;
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}
Unexecuted instantiation: AArch64A57FPLoadBalancing.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64AdvSIMDScalarPass.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64AsmPrinter.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64BranchTargets.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64CallingConvention.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64CallLowering.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64CleanupLocalDynamicTLSPass.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64CollectLOH.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64CondBrTuning.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64DeadRegisterDefinitionsPass.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64ExpandPseudoInsts.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64FalkorHWPFFix.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64FastISel.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64FrameLowering.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64CompressJumpTables.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64ISelDAGToDAG.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64ISelLowering.cpp:llvm::isIndirectBranchOpcode(int)
AArch64InstrInfo.cpp:llvm::isIndirectBranchOpcode(int)
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static inline bool isIndirectBranchOpcode(int Opc) {
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  return Opc == AArch64::BR;
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}
Unexecuted instantiation: AArch64InstructionSelector.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64LegalizerInfo.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64LoadStoreOptimizer.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64MacroFusion.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64PreLegalizerCombiner.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64RegisterBankInfo.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64RegisterInfo.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64SelectionDAGInfo.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64SpeculationHardening.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64StackTagging.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64StorePairSuppress.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64Subtarget.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64TargetMachine.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64TargetObjectFile.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64TargetTransformInfo.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64SIMDInstrOpt.cpp:llvm::isIndirectBranchOpcode(int)
Unexecuted instantiation: AArch64AsmParser.cpp:llvm::isIndirectBranchOpcode(int)
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// struct TSFlags {
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#define TSFLAG_ELEMENT_SIZE_TYPE(X)      (X)       // 3-bits
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#define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 1-bit
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// }
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namespace AArch64 {
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enum ElementSizeType {
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  ElementSizeMask = TSFLAG_ELEMENT_SIZE_TYPE(0x7),
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  ElementSizeNone = TSFLAG_ELEMENT_SIZE_TYPE(0x0),
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  ElementSizeB    = TSFLAG_ELEMENT_SIZE_TYPE(0x1),
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  ElementSizeH    = TSFLAG_ELEMENT_SIZE_TYPE(0x2),
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  ElementSizeS    = TSFLAG_ELEMENT_SIZE_TYPE(0x3),
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  ElementSizeD    = TSFLAG_ELEMENT_SIZE_TYPE(0x4),
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};
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enum DestructiveInstType {
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  DestructiveInstTypeMask = TSFLAG_DESTRUCTIVE_INST_TYPE(0x1),
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  NotDestructive          = TSFLAG_DESTRUCTIVE_INST_TYPE(0x0),
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  Destructive             = TSFLAG_DESTRUCTIVE_INST_TYPE(0x1),
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};
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#undef TSFLAG_ELEMENT_SIZE_TYPE
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#undef TSFLAG_DESTRUCTIVE_INST_TYPE
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}
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} // end namespace llvm
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#endif