Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
Line
Count
Source (jump to first uncovered line)
1
//=- AArch64RedundantCopyElimination.cpp - Remove useless copy for AArch64 -=//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
// This pass removes unnecessary copies/moves in BBs based on a dominating
8
// condition.
9
//
10
// We handle three cases:
11
// 1. For BBs that are targets of CBZ/CBNZ instructions, we know the value of
12
//    the CBZ/CBNZ source register is zero on the taken/not-taken path. For
13
//    instance, the copy instruction in the code below can be removed because
14
//    the CBZW jumps to %bb.2 when w0 is zero.
15
//
16
//  %bb.1:
17
//    cbz w0, .LBB0_2
18
//  .LBB0_2:
19
//    mov w0, wzr  ; <-- redundant
20
//
21
// 2. If the flag setting instruction defines a register other than WZR/XZR, we
22
//    can remove a zero copy in some cases.
23
//
24
//  %bb.0:
25
//    subs w0, w1, w2
26
//    str w0, [x1]
27
//    b.ne .LBB0_2
28
//  %bb.1:
29
//    mov w0, wzr  ; <-- redundant
30
//    str w0, [x2]
31
//  .LBB0_2
32
//
33
// 3. Finally, if the flag setting instruction is a comparison against a
34
//    constant (i.e., ADDS[W|X]ri, SUBS[W|X]ri), we can remove a mov immediate
35
//    in some cases.
36
//
37
//  %bb.0:
38
//    subs xzr, x0, #1
39
//    b.eq .LBB0_1
40
//  .LBB0_1:
41
//    orr x0, xzr, #0x1  ; <-- redundant
42
//
43
// This pass should be run after register allocation.
44
//
45
// FIXME: This could also be extended to check the whole dominance subtree below
46
// the comparison if the compile time regression is acceptable.
47
//
48
// FIXME: Add support for handling CCMP instructions.
49
// FIXME: If the known register value is zero, we should be able to rewrite uses
50
//        to use WZR/XZR directly in some cases.
51
//===----------------------------------------------------------------------===//
52
#include "AArch64.h"
53
#include "llvm/ADT/Optional.h"
54
#include "llvm/ADT/SetVector.h"
55
#include "llvm/ADT/Statistic.h"
56
#include "llvm/ADT/iterator_range.h"
57
#include "llvm/CodeGen/LiveRegUnits.h"
58
#include "llvm/CodeGen/MachineFunctionPass.h"
59
#include "llvm/CodeGen/MachineRegisterInfo.h"
60
#include "llvm/Support/Debug.h"
61
62
using namespace llvm;
63
64
#define DEBUG_TYPE "aarch64-copyelim"
65
66
STATISTIC(NumCopiesRemoved, "Number of copies removed.");
67
68
namespace {
69
class AArch64RedundantCopyElimination : public MachineFunctionPass {
70
  const MachineRegisterInfo *MRI;
71
  const TargetRegisterInfo *TRI;
72
73
  // DomBBClobberedRegs is used when computing known values in the dominating
74
  // BB.
75
  LiveRegUnits DomBBClobberedRegs, DomBBUsedRegs;
76
77
  // OptBBClobberedRegs is used when optimizing away redundant copies/moves.
78
  LiveRegUnits OptBBClobberedRegs, OptBBUsedRegs;
79
80
public:
81
  static char ID;
82
8.62k
  AArch64RedundantCopyElimination() : MachineFunctionPass(ID) {
83
8.62k
    initializeAArch64RedundantCopyEliminationPass(
84
8.62k
        *PassRegistry::getPassRegistry());
85
8.62k
  }
86
87
  struct RegImm {
88
    MCPhysReg Reg;
89
    int32_t Imm;
90
400k
    RegImm(MCPhysReg Reg, int32_t Imm) : Reg(Reg), Imm(Imm) {}
91
  };
92
93
  bool knownRegValInBlock(MachineInstr &CondBr, MachineBasicBlock *MBB,
94
                          SmallVectorImpl<RegImm> &KnownRegs,
95
                          MachineBasicBlock::iterator &FirstUse);
96
  bool optimizeBlock(MachineBasicBlock *MBB);
97
  bool runOnMachineFunction(MachineFunction &MF) override;
98
8.58k
  MachineFunctionProperties getRequiredProperties() const override {
99
8.58k
    return MachineFunctionProperties().set(
100
8.58k
        MachineFunctionProperties::Property::NoVRegs);
101
8.58k
  }
102
265k
  StringRef getPassName() const override {
103
265k
    return "AArch64 Redundant Copy Elimination";
104
265k
  }
105
};
106
char AArch64RedundantCopyElimination::ID = 0;
107
}
108
109
INITIALIZE_PASS(AArch64RedundantCopyElimination, "aarch64-copyelim",
110
                "AArch64 redundant copy elimination pass", false, false)
111
112
/// It's possible to determine the value of a register based on a dominating
113
/// condition.  To do so, this function checks to see if the basic block \p MBB
114
/// is the target of a conditional branch \p CondBr with an equality comparison.
115
/// If the branch is a CBZ/CBNZ, we know the value of its source operand is zero
116
/// in \p MBB for some cases.  Otherwise, we find and inspect the NZCV setting
117
/// instruction (e.g., SUBS, ADDS).  If this instruction defines a register
118
/// other than WZR/XZR, we know the value of the destination register is zero in
119
/// \p MMB for some cases.  In addition, if the NZCV setting instruction is
120
/// comparing against a constant we know the other source register is equal to
121
/// the constant in \p MBB for some cases.  If we find any constant values, push
122
/// a physical register and constant value pair onto the KnownRegs vector and
123
/// return true.  Otherwise, return false if no known values were found.
124
bool AArch64RedundantCopyElimination::knownRegValInBlock(
125
    MachineInstr &CondBr, MachineBasicBlock *MBB,
126
2.55M
    SmallVectorImpl<RegImm> &KnownRegs, MachineBasicBlock::iterator &FirstUse) {
127
2.55M
  unsigned Opc = CondBr.getOpcode();
128
2.55M
129
2.55M
  // Check if the current basic block is the target block to which the
130
2.55M
  // CBZ/CBNZ instruction jumps when its Wt/Xt is zero.
131
2.55M
  if (((Opc == AArch64::CBZW || 
Opc == AArch64::CBZX2.46M
) &&
132
2.55M
       
MBB == CondBr.getOperand(1).getMBB()209k
) ||
133
2.55M
      
(2.50M
(2.50M
Opc == AArch64::CBNZW2.50M
||
Opc == AArch64::CBNZX2.30M
) &&
134
2.50M
       
MBB != CondBr.getOperand(1).getMBB()426k
)) {
135
310k
    FirstUse = CondBr;
136
310k
    KnownRegs.push_back(RegImm(CondBr.getOperand(0).getReg(), 0));
137
310k
    return true;
138
310k
  }
139
2.24M
140
2.24M
  // Otherwise, must be a conditional branch.
141
2.24M
  if (Opc != AArch64::Bcc)
142
1.69M
    return false;
143
549k
144
549k
  // Must be an equality check (i.e., == or !=).
145
549k
  AArch64CC::CondCode CC = (AArch64CC::CondCode)CondBr.getOperand(0).getImm();
146
549k
  if (CC != AArch64CC::EQ && 
CC != AArch64CC::NE425k
)
147
278k
    return false;
148
270k
149
270k
  MachineBasicBlock *BrTarget = CondBr.getOperand(1).getMBB();
150
270k
  if ((CC == AArch64CC::EQ && 
BrTarget != MBB124k
) ||
151
270k
      
(196k
CC == AArch64CC::NE196k
&&
BrTarget == MBB146k
))
152
110k
    return false;
153
160k
154
160k
  // Stop if we get to the beginning of PredMBB.
155
160k
  MachineBasicBlock *PredMBB = *MBB->pred_begin();
156
160k
  assert(PredMBB == CondBr.getParent() &&
157
160k
         "Conditional branch not in predecessor block!");
158
160k
  if (CondBr == PredMBB->begin())
159
119
    return false;
160
160k
161
160k
  // Registers clobbered in PredMBB between CondBr instruction and current
162
160k
  // instruction being checked in loop.
163
160k
  DomBBClobberedRegs.clear();
164
160k
  DomBBUsedRegs.clear();
165
160k
166
160k
  // Find compare instruction that sets NZCV used by CondBr.
167
160k
  MachineBasicBlock::reverse_iterator RIt = CondBr.getReverseIterator();
168
168k
  for (MachineInstr &PredI : make_range(std::next(RIt), PredMBB->rend())) {
169
168k
170
168k
    bool IsCMN = false;
171
168k
    switch (PredI.getOpcode()) {
172
168k
    default:
173
8.92k
      break;
174
168k
175
168k
    // CMN is an alias for ADDS with a dead destination register.
176
168k
    case AArch64::ADDSWri:
177
922
    case AArch64::ADDSXri:
178
922
      IsCMN = true;
179
922
      LLVM_FALLTHROUGH;
180
922
    // CMP is an alias for SUBS with a dead destination register.
181
55.9k
    case AArch64::SUBSWri:
182
55.9k
    case AArch64::SUBSXri: {
183
55.9k
      // Sometimes the first operand is a FrameIndex. Bail if tht happens.
184
55.9k
      if (!PredI.getOperand(1).isReg())
185
1
        return false;
186
55.9k
      MCPhysReg DstReg = PredI.getOperand(0).getReg();
187
55.9k
      MCPhysReg SrcReg = PredI.getOperand(1).getReg();
188
55.9k
189
55.9k
      bool Res = false;
190
55.9k
      // If we're comparing against a non-symbolic immediate and the source
191
55.9k
      // register of the compare is not modified (including a self-clobbering
192
55.9k
      // compare) between the compare and conditional branch we known the value
193
55.9k
      // of the 1st source operand.
194
55.9k
      if (PredI.getOperand(2).isImm() && DomBBClobberedRegs.available(SrcReg) &&
195
55.9k
          
SrcReg != DstReg55.9k
) {
196
47.0k
        // We've found the instruction that sets NZCV.
197
47.0k
        int32_t KnownImm = PredI.getOperand(2).getImm();
198
47.0k
        int32_t Shift = PredI.getOperand(3).getImm();
199
47.0k
        KnownImm <<= Shift;
200
47.0k
        if (IsCMN)
201
850
          KnownImm = -KnownImm;
202
47.0k
        FirstUse = PredI;
203
47.0k
        KnownRegs.push_back(RegImm(SrcReg, KnownImm));
204
47.0k
        Res = true;
205
47.0k
      }
206
55.9k
207
55.9k
      // If this instructions defines something other than WZR/XZR, we know it's
208
55.9k
      // result is zero in some cases.
209
55.9k
      if (DstReg == AArch64::WZR || 
DstReg == AArch64::XZR18.3k
)
210
47.0k
        return Res;
211
8.88k
212
8.88k
      // The destination register must not be modified between the NZCV setting
213
8.88k
      // instruction and the conditional branch.
214
8.88k
      if (!DomBBClobberedRegs.available(DstReg))
215
0
        return Res;
216
8.88k
217
8.88k
      FirstUse = PredI;
218
8.88k
      KnownRegs.push_back(RegImm(DstReg, 0));
219
8.88k
      return true;
220
8.88k
    }
221
8.88k
222
8.88k
    // Look for NZCV setting instructions that define something other than
223
8.88k
    // WZR/XZR.
224
103k
    case AArch64::ADCSWr:
225
103k
    case AArch64::ADCSXr:
226
103k
    case AArch64::ADDSWrr:
227
103k
    case AArch64::ADDSWrs:
228
103k
    case AArch64::ADDSWrx:
229
103k
    case AArch64::ADDSXrr:
230
103k
    case AArch64::ADDSXrs:
231
103k
    case AArch64::ADDSXrx:
232
103k
    case AArch64::ADDSXrx64:
233
103k
    case AArch64::ANDSWri:
234
103k
    case AArch64::ANDSWrr:
235
103k
    case AArch64::ANDSWrs:
236
103k
    case AArch64::ANDSXri:
237
103k
    case AArch64::ANDSXrr:
238
103k
    case AArch64::ANDSXrs:
239
103k
    case AArch64::BICSWrr:
240
103k
    case AArch64::BICSWrs:
241
103k
    case AArch64::BICSXrs:
242
103k
    case AArch64::BICSXrr:
243
103k
    case AArch64::SBCSWr:
244
103k
    case AArch64::SBCSXr:
245
103k
    case AArch64::SUBSWrr:
246
103k
    case AArch64::SUBSWrs:
247
103k
    case AArch64::SUBSWrx:
248
103k
    case AArch64::SUBSXrr:
249
103k
    case AArch64::SUBSXrs:
250
103k
    case AArch64::SUBSXrx:
251
103k
    case AArch64::SUBSXrx64: {
252
103k
      MCPhysReg DstReg = PredI.getOperand(0).getReg();
253
103k
      if (DstReg == AArch64::WZR || 
DstReg == AArch64::XZR54.7k
)
254
91.5k
        return false;
255
11.8k
256
11.8k
      // The destination register of the NZCV setting instruction must not be
257
11.8k
      // modified before the conditional branch.
258
11.8k
      if (!DomBBClobberedRegs.available(DstReg))
259
6
        return false;
260
11.8k
261
11.8k
      // We've found the instruction that sets NZCV whose DstReg == 0.
262
11.8k
      FirstUse = PredI;
263
11.8k
      KnownRegs.push_back(RegImm(DstReg, 0));
264
11.8k
      return true;
265
11.8k
    }
266
8.92k
    }
267
8.92k
268
8.92k
    // Bail if we see an instruction that defines NZCV that we don't handle.
269
8.92k
    if (PredI.definesRegister(AArch64::NZCV))
270
912
      return false;
271
8.00k
272
8.00k
    // Track clobbered and used registers.
273
8.00k
    LiveRegUnits::accumulateUsedDefed(PredI, DomBBClobberedRegs, DomBBUsedRegs,
274
8.00k
                                      TRI);
275
8.00k
  }
276
160k
  
return false6
;
277
160k
}
278
279
2.20M
bool AArch64RedundantCopyElimination::optimizeBlock(MachineBasicBlock *MBB) {
280
2.20M
  // Check if the current basic block has a single predecessor.
281
2.20M
  if (MBB->pred_size() != 1)
282
875k
    return false;
283
1.33M
284
1.33M
  // Check if the predecessor has two successors, implying the block ends in a
285
1.33M
  // conditional branch.
286
1.33M
  MachineBasicBlock *PredMBB = *MBB->pred_begin();
287
1.33M
  if (PredMBB->succ_size() != 2)
288
15.0k
    return false;
289
1.31M
290
1.31M
  MachineBasicBlock::iterator CondBr = PredMBB->getLastNonDebugInstr();
291
1.31M
  if (CondBr == PredMBB->end())
292
0
    return false;
293
1.31M
294
1.31M
  // Keep track of the earliest point in the PredMBB block where kill markers
295
1.31M
  // need to be removed if a COPY is removed.
296
1.31M
  MachineBasicBlock::iterator FirstUse;
297
1.31M
  // After calling knownRegValInBlock, FirstUse will either point to a CBZ/CBNZ
298
1.31M
  // or a compare (i.e., SUBS).  In the latter case, we must take care when
299
1.31M
  // updating FirstUse when scanning for COPY instructions.  In particular, if
300
1.31M
  // there's a COPY in between the compare and branch the COPY should not
301
1.31M
  // update FirstUse.
302
1.31M
  bool SeenFirstUse = false;
303
1.31M
  // Registers that contain a known value at the start of MBB.
304
1.31M
  SmallVector<RegImm, 4> KnownRegs;
305
1.31M
306
1.31M
  MachineBasicBlock::iterator Itr = std::next(CondBr);
307
2.55M
  do {
308
2.55M
    --Itr;
309
2.55M
310
2.55M
    if (!knownRegValInBlock(*Itr, MBB, KnownRegs, FirstUse))
311
2.17M
      continue;
312
378k
313
378k
    // Reset the clobbered and used register units.
314
378k
    OptBBClobberedRegs.clear();
315
378k
    OptBBUsedRegs.clear();
316
378k
317
378k
    // Look backward in PredMBB for COPYs from the known reg to find other
318
378k
    // registers that are known to be a constant value.
319
941k
    for (auto PredI = Itr;; 
--PredI563k
) {
320
941k
      if (FirstUse == PredI)
321
378k
        SeenFirstUse = true;
322
941k
323
941k
      if (PredI->isCopy()) {
324
41.3k
        MCPhysReg CopyDstReg = PredI->getOperand(0).getReg();
325
41.3k
        MCPhysReg CopySrcReg = PredI->getOperand(1).getReg();
326
47.3k
        for (auto &KnownReg : KnownRegs) {
327
47.3k
          if (!OptBBClobberedRegs.available(KnownReg.Reg))
328
6.04k
            continue;
329
41.3k
          // If we have X = COPY Y, and Y is known to be zero, then now X is
330
41.3k
          // known to be zero.
331
41.3k
          if (CopySrcReg == KnownReg.Reg &&
332
41.3k
              
OptBBClobberedRegs.available(CopyDstReg)22.2k
) {
333
21.9k
            KnownRegs.push_back(RegImm(CopyDstReg, KnownReg.Imm));
334
21.9k
            if (SeenFirstUse)
335
21.9k
              FirstUse = PredI;
336
21.9k
            break;
337
21.9k
          }
338
19.3k
          // If we have X = COPY Y, and X is known to be zero, then now Y is
339
19.3k
          // known to be zero.
340
19.3k
          if (CopyDstReg == KnownReg.Reg &&
341
19.3k
              
OptBBClobberedRegs.available(CopySrcReg)2.20k
) {
342
163
            KnownRegs.push_back(RegImm(CopySrcReg, KnownReg.Imm));
343
163
            if (SeenFirstUse)
344
163
              FirstUse = PredI;
345
163
            break;
346
163
          }
347
19.3k
        }
348
41.3k
      }
349
941k
350
941k
      // Stop if we get to the beginning of PredMBB.
351
941k
      if (PredI == PredMBB->begin())
352
224k
        break;
353
716k
354
716k
      LiveRegUnits::accumulateUsedDefed(*PredI, OptBBClobberedRegs,
355
716k
                                        OptBBUsedRegs, TRI);
356
716k
      // Stop if all of the known-zero regs have been clobbered.
357
729k
      if (
all_of(KnownRegs, [&](RegImm KnownReg) 716k
{
358
729k
            return !OptBBClobberedRegs.available(KnownReg.Reg);
359
729k
          }))
360
153k
        break;
361
716k
    }
362
378k
    break;
363
378k
364
2.17M
  } while (Itr != PredMBB->begin() && 
Itr->isTerminator()1.93M
);
365
1.31M
366
1.31M
  // We've not found a registers with a known value, time to bail out.
367
2.17M
  if (KnownRegs.empty())
368
940k
    return false;
369
1.23M
370
1.23M
  bool Changed = false;
371
1.23M
  // UsedKnownRegs is the set of KnownRegs that have had uses added to MBB.
372
1.23M
  SmallSetVector<unsigned, 4> UsedKnownRegs;
373
1.23M
  MachineBasicBlock::iterator LastChange = MBB->begin();
374
1.23M
  // Remove redundant copy/move instructions unless KnownReg is modified.
375
2.28M
  for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;) {
376
1.20M
    MachineInstr *MI = &*I;
377
1.20M
    ++I;
378
1.20M
    bool RemovedMI = false;
379
1.20M
    bool IsCopy = MI->isCopy();
380
1.20M
    bool IsMoveImm = MI->isMoveImmediate();
381
1.20M
    if (IsCopy || 
IsMoveImm1.05M
) {
382
323k
      Register DefReg = MI->getOperand(0).getReg();
383
323k
      Register SrcReg = IsCopy ? 
MI->getOperand(1).getReg()149k
:
Register()174k
;
384
323k
      int64_t SrcImm = IsMoveImm ? 
MI->getOperand(1).getImm()174k
:
0149k
;
385
323k
      if (!MRI->isReserved(DefReg) &&
386
323k
          
(323k
(323k
IsCopy323k
&&
(149k
SrcReg == AArch64::XZR149k
||
SrcReg == AArch64::WZR121k
)) ||
387
323k
           
IsMoveImm289k
)) {
388
217k
        for (RegImm &KnownReg : KnownRegs) {
389
217k
          if (KnownReg.Reg != DefReg &&
390
217k
              
!TRI->isSuperRegister(DefReg, KnownReg.Reg)196k
)
391
189k
            continue;
392
28.2k
393
28.2k
          // For a copy, the known value must be a zero.
394
28.2k
          if (IsCopy && 
KnownReg.Imm != 07.34k
)
395
575
            continue;
396
27.6k
397
27.6k
          if (IsMoveImm) {
398
20.8k
            // For a move immediate, the known immediate must match the source
399
20.8k
            // immediate.
400
20.8k
            if (KnownReg.Imm != SrcImm)
401
10.5k
              continue;
402
10.3k
403
10.3k
            // Don't remove a move immediate that implicitly defines the upper
404
10.3k
            // bits when only the lower 32 bits are known.
405
10.3k
            MCPhysReg CmpReg = KnownReg.Reg;
406
10.3k
            if (any_of(MI->implicit_operands(), [CmpReg](MachineOperand &O) {
407
98
                  return !O.isDead() && O.isReg() && O.isDef() &&
408
98
                         O.getReg() != CmpReg;
409
98
                }))
410
77
              continue;
411
17.0k
          }
412
17.0k
413
17.0k
          if (IsCopy)
414
17.0k
            LLVM_DEBUG(dbgs() << "Remove redundant Copy : " << *MI);
415
17.0k
          else
416
17.0k
            LLVM_DEBUG(dbgs() << "Remove redundant Move : " << *MI);
417
17.0k
418
17.0k
          MI->eraseFromParent();
419
17.0k
          Changed = true;
420
17.0k
          LastChange = I;
421
17.0k
          NumCopiesRemoved++;
422
17.0k
          UsedKnownRegs.insert(KnownReg.Reg);
423
17.0k
          RemovedMI = true;
424
17.0k
          break;
425
17.0k
        }
426
208k
      }
427
323k
    }
428
1.20M
429
1.20M
    // Skip to the next instruction if we removed the COPY/MovImm.
430
1.20M
    if (RemovedMI)
431
17.0k
      continue;
432
1.18M
433
1.18M
    // Remove any regs the MI clobbers from the KnownConstRegs set.
434
2.42M
    
for (unsigned RI = 0; 1.18M
RI < KnownRegs.size();)
435
1.24M
      if (MI->modifiesRegister(KnownRegs[RI].Reg, TRI)) {
436
165k
        std::swap(KnownRegs[RI], KnownRegs[KnownRegs.size() - 1]);
437
165k
        KnownRegs.pop_back();
438
165k
        // Don't increment RI since we need to now check the swapped-in
439
165k
        // KnownRegs[RI].
440
1.07M
      } else {
441
1.07M
        ++RI;
442
1.07M
      }
443
1.18M
444
1.18M
    // Continue until the KnownRegs set is empty.
445
1.18M
    if (KnownRegs.empty())
446
153k
      break;
447
1.18M
  }
448
1.23M
449
1.23M
  if (!Changed)
450
361k
    return false;
451
876k
452
876k
  // Add newly used regs to the block's live-in list if they aren't there
453
876k
  // already.
454
876k
  for (MCPhysReg KnownReg : UsedKnownRegs)
455
17.0k
    if (!MBB->isLiveIn(KnownReg))
456
17.0k
      MBB->addLiveIn(KnownReg);
457
876k
458
876k
  // Clear kills in the range where changes were made.  This is conservative,
459
876k
  // but should be okay since kill markers are being phased out.
460
876k
  LLVM_DEBUG(dbgs() << "Clearing kill flags.\n\tFirstUse: " << *FirstUse
461
876k
                    << "\tLastChange: " << *LastChange);
462
876k
  for (MachineInstr &MMI : make_range(FirstUse, PredMBB->end()))
463
29.5k
    MMI.clearKillInfo();
464
876k
  for (MachineInstr &MMI : make_range(MBB->begin(), LastChange))
465
13.0k
    MMI.clearKillInfo();
466
876k
467
876k
  return true;
468
876k
}
469
470
bool AArch64RedundantCopyElimination::runOnMachineFunction(
471
257k
    MachineFunction &MF) {
472
257k
  if (skipFunction(MF.getFunction()))
473
16
    return false;
474
257k
  TRI = MF.getSubtarget().getRegisterInfo();
475
257k
  MRI = &MF.getRegInfo();
476
257k
477
257k
  // Resize the clobbered and used register unit trackers.  We do this once per
478
257k
  // function.
479
257k
  DomBBClobberedRegs.init(*TRI);
480
257k
  DomBBUsedRegs.init(*TRI);
481
257k
  OptBBClobberedRegs.init(*TRI);
482
257k
  OptBBUsedRegs.init(*TRI);
483
257k
484
257k
  bool Changed = false;
485
257k
  for (MachineBasicBlock &MBB : MF)
486
2.20M
    Changed |= optimizeBlock(&MBB);
487
257k
  return Changed;
488
257k
}
489
490
8.62k
FunctionPass *llvm::createAArch64RedundantCopyEliminationPass() {
491
8.62k
  return new AArch64RedundantCopyElimination();
492
8.62k
}