Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
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//==- AArch64RegisterInfo.h - AArch64 Register Information Impl --*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the AArch64 implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
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#define GET_REGINFO_HEADER
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#include "AArch64GenRegisterInfo.inc"
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namespace llvm {
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class MachineFunction;
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class RegScavenger;
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class TargetRegisterClass;
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class Triple;
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class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
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  const Triple &TT;
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public:
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  AArch64RegisterInfo(const Triple &TT);
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  // FIXME: This should be tablegen'd like getDwarfRegNum is
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  int getSEHRegNum(unsigned i) const {
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    return getEncodingValue(i);
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  }
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  bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
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  bool isAnyArgRegReserved(const MachineFunction &MF) const;
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  void emitReservedArgRegCallError(const MachineFunction &MF) const;
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  void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const;
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  void UpdateCustomCallPreservedMask(MachineFunction &MF,
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                                     const uint32_t **Mask) const;
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  /// Code Generation virtual methods...
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  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
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  const MCPhysReg *
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  getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
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  const uint32_t *getCallPreservedMask(const MachineFunction &MF,
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                                       CallingConv::ID) const override;
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  unsigned getCSRFirstUseCost() const override {
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    // The cost will be compared against BlockFrequency where entry has the
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    // value of 1 << 14. A value of 5 will choose to spill or split really
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    // cold path instead of using a callee-saved register.
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    return 5;
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  }
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  const TargetRegisterClass *
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  getSubClassWithSubReg(const TargetRegisterClass *RC,
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                        unsigned Idx) const override;
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  // Calls involved in thread-local variable lookup save more registers than
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  // normal calls, so they need a different mask to represent this.
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  const uint32_t *getTLSCallPreservedMask() const;
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  // Funclets on ARM64 Windows don't preserve any registers.
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  const uint32_t *getNoPreservedMask() const override;
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  /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
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  /// case that 'returned' is on an i64 first argument if the calling convention
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  /// is one that can (partially) model this attribute with a preserved mask
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  /// (i.e. it is a calling convention that uses the same register for the first
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  /// i64 argument and an i64 return value)
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  ///
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  /// Should return NULL in the case that the calling convention does not have
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  /// this property
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  const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
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                                             CallingConv::ID) const;
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  /// Stack probing calls preserve different CSRs to the normal CC.
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  const uint32_t *getWindowsStackProbePreservedMask() const;
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  BitVector getReservedRegs(const MachineFunction &MF) const override;
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  bool isAsmClobberable(const MachineFunction &MF,
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                       unsigned PhysReg) const override;
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  bool isConstantPhysReg(unsigned PhysReg) const override;
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  const TargetRegisterClass *
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  getPointerRegClass(const MachineFunction &MF,
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                     unsigned Kind = 0) const override;
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  const TargetRegisterClass *
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  getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
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  bool requiresRegisterScavenging(const MachineFunction &MF) const override;
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  bool useFPForScavengingIndex(const MachineFunction &MF) const override;
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  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
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  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
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  bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
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                          int64_t Offset) const override;
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  void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
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                                    int FrameIdx,
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                                    int64_t Offset) const override;
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  void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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                         int64_t Offset) const override;
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  void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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                           unsigned FIOperandNum,
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                           RegScavenger *RS = nullptr) const override;
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  bool cannotEliminateFrame(const MachineFunction &MF) const;
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  bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
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  bool hasBasePointer(const MachineFunction &MF) const;
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  unsigned getBaseRegister() const;
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  // Debug information queries.
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  Register getFrameRegister(const MachineFunction &MF) const override;
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  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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                               MachineFunction &MF) const override;
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  bool trackLivenessAfterRegAlloc(const MachineFunction&) const override {
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    return true;
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  }
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  unsigned getLocalAddressRegister(const MachineFunction &MF) const;
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};
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} // end namespace llvm
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#endif