Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AArch64/AArch64Subtarget.h
Line
Count
Source (jump to first uncovered line)
1
//===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
//
9
// This file declares the AArch64 specific subclass of TargetSubtarget.
10
//
11
//===----------------------------------------------------------------------===//
12
13
#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
14
#define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15
16
#include "AArch64FrameLowering.h"
17
#include "AArch64ISelLowering.h"
18
#include "AArch64InstrInfo.h"
19
#include "AArch64RegisterInfo.h"
20
#include "AArch64SelectionDAGInfo.h"
21
#include "llvm/CodeGen/GlobalISel/CallLowering.h"
22
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
23
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
24
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
25
#include "llvm/CodeGen/TargetSubtargetInfo.h"
26
#include "llvm/IR/DataLayout.h"
27
#include <string>
28
29
#define GET_SUBTARGETINFO_HEADER
30
#include "AArch64GenSubtargetInfo.inc"
31
32
namespace llvm {
33
class GlobalValue;
34
class StringRef;
35
class Triple;
36
37
class AArch64Subtarget final : public AArch64GenSubtargetInfo {
38
public:
39
  enum ARMProcFamilyEnum : uint8_t {
40
    Others,
41
    CortexA35,
42
    CortexA53,
43
    CortexA55,
44
    CortexA57,
45
    CortexA72,
46
    CortexA73,
47
    CortexA75,
48
    CortexA76,
49
    Cyclone,
50
    ExynosM1,
51
    ExynosM3,
52
    Falkor,
53
    Kryo,
54
    Saphira,
55
    ThunderX2T99,
56
    ThunderX,
57
    ThunderXT81,
58
    ThunderXT83,
59
    ThunderXT88,
60
    TSV110
61
  };
62
63
protected:
64
  /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
65
  ARMProcFamilyEnum ARMProcFamily = Others;
66
67
  bool HasV8_1aOps = false;
68
  bool HasV8_2aOps = false;
69
  bool HasV8_3aOps = false;
70
  bool HasV8_4aOps = false;
71
  bool HasV8_5aOps = false;
72
73
  bool HasFPARMv8 = false;
74
  bool HasNEON = false;
75
  bool HasCrypto = false;
76
  bool HasDotProd = false;
77
  bool HasCRC = false;
78
  bool HasLSE = false;
79
  bool HasRAS = false;
80
  bool HasRDM = false;
81
  bool HasPerfMon = false;
82
  bool HasFullFP16 = false;
83
  bool HasFP16FML = false;
84
  bool HasSPE = false;
85
86
  // ARMv8.1 extensions
87
  bool HasVH = false;
88
  bool HasPAN = false;
89
  bool HasLOR = false;
90
91
  // ARMv8.2 extensions
92
  bool HasPsUAO = false;
93
  bool HasPAN_RWV = false;
94
  bool HasCCPP = false;
95
96
  // Armv8.2 Crypto extensions
97
  bool HasSM4 = false;
98
  bool HasSHA3 = false;
99
  bool HasSHA2 = false;
100
  bool HasAES = false;
101
102
  // ARMv8.3 extensions
103
  bool HasPA = false;
104
  bool HasJS = false;
105
  bool HasCCIDX = false;
106
  bool HasComplxNum = false;
107
108
  // ARMv8.4 extensions
109
  bool HasNV = false;
110
  bool HasRASv8_4 = false;
111
  bool HasMPAM = false;
112
  bool HasDIT = false;
113
  bool HasTRACEV8_4 = false;
114
  bool HasAM = false;
115
  bool HasSEL2 = false;
116
  bool HasTLB_RMI = false;
117
  bool HasFMI = false;
118
  bool HasRCPC_IMMO = false;
119
120
  bool HasLSLFast = false;
121
  bool HasSVE = false;
122
  bool HasSVE2 = false;
123
  bool HasRCPC = false;
124
  bool HasAggressiveFMA = false;
125
126
  // Armv8.5-A Extensions
127
  bool HasAlternativeNZCV = false;
128
  bool HasFRInt3264 = false;
129
  bool HasSpecRestrict = false;
130
  bool HasSSBS = false;
131
  bool HasSB = false;
132
  bool HasPredRes = false;
133
  bool HasCCDP = false;
134
  bool HasBTI = false;
135
  bool HasRandGen = false;
136
  bool HasMTE = false;
137
138
  // Arm SVE2 extensions
139
  bool HasSVE2AES = false;
140
  bool HasSVE2SM4 = false;
141
  bool HasSVE2SHA3 = false;
142
  bool HasSVE2BitPerm = false;
143
144
  // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
145
  bool HasZeroCycleRegMove = false;
146
147
  // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
148
  bool HasZeroCycleZeroing = false;
149
  bool HasZeroCycleZeroingGP = false;
150
  bool HasZeroCycleZeroingFP = false;
151
  bool HasZeroCycleZeroingFPWorkaround = false;
152
153
  // StrictAlign - Disallow unaligned memory accesses.
154
  bool StrictAlign = false;
155
156
  // NegativeImmediates - transform instructions with negative immediates
157
  bool NegativeImmediates = true;
158
159
  // Enable 64-bit vectorization in SLP.
160
  unsigned MinVectorRegisterBitWidth = 64;
161
162
  bool UseAA = false;
163
  bool PredictableSelectIsExpensive = false;
164
  bool BalanceFPOps = false;
165
  bool CustomAsCheapAsMove = false;
166
  bool ExynosAsCheapAsMove = false;
167
  bool UsePostRAScheduler = false;
168
  bool Misaligned128StoreIsSlow = false;
169
  bool Paired128IsSlow = false;
170
  bool STRQroIsSlow = false;
171
  bool UseAlternateSExtLoadCVTF32Pattern = false;
172
  bool HasArithmeticBccFusion = false;
173
  bool HasArithmeticCbzFusion = false;
174
  bool HasFuseAddress = false;
175
  bool HasFuseAES = false;
176
  bool HasFuseArithmeticLogic = false;
177
  bool HasFuseCCSelect = false;
178
  bool HasFuseCryptoEOR = false;
179
  bool HasFuseLiterals = false;
180
  bool DisableLatencySchedHeuristic = false;
181
  bool UseRSqrt = false;
182
  bool Force32BitJumpTables = false;
183
  bool UseEL1ForTP = false;
184
  bool UseEL2ForTP = false;
185
  bool UseEL3ForTP = false;
186
  uint8_t MaxInterleaveFactor = 2;
187
  uint8_t VectorInsertExtractBaseCost = 3;
188
  uint16_t CacheLineSize = 0;
189
  uint16_t PrefetchDistance = 0;
190
  uint16_t MinPrefetchStride = 1;
191
  unsigned MaxPrefetchIterationsAhead = UINT_MAX;
192
  unsigned PrefFunctionAlignment = 0;
193
  unsigned PrefLoopAlignment = 0;
194
  unsigned MaxJumpTableSize = 0;
195
  unsigned WideningBaseCost = 0;
196
197
  // ReserveXRegister[i] - X#i is not available as a general purpose register.
198
  BitVector ReserveXRegister;
199
200
  // CustomCallUsedXRegister[i] - X#i call saved.
201
  BitVector CustomCallSavedXRegs;
202
203
  bool IsLittle;
204
205
  /// TargetTriple - What processor and OS we're targeting.
206
  Triple TargetTriple;
207
208
  AArch64FrameLowering FrameLowering;
209
  AArch64InstrInfo InstrInfo;
210
  AArch64SelectionDAGInfo TSInfo;
211
  AArch64TargetLowering TLInfo;
212
213
  /// GlobalISel related APIs.
214
  std::unique_ptr<CallLowering> CallLoweringInfo;
215
  std::unique_ptr<InstructionSelector> InstSelector;
216
  std::unique_ptr<LegalizerInfo> Legalizer;
217
  std::unique_ptr<RegisterBankInfo> RegBankInfo;
218
219
private:
220
  /// initializeSubtargetDependencies - Initializes using CPUString and the
221
  /// passed in feature string so that we can use initializer lists for
222
  /// subtarget initialization.
223
  AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
224
                                                    StringRef CPUString);
225
226
  /// Initialize properties based on the selected processor family.
227
  void initializeProperties();
228
229
public:
230
  /// This constructor initializes the data members to match that
231
  /// of the specified triple.
232
  AArch64Subtarget(const Triple &TT, const std::string &CPU,
233
                   const std::string &FS, const TargetMachine &TM,
234
                   bool LittleEndian);
235
236
39.0k
  const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
237
39.0k
    return &TSInfo;
238
39.0k
  }
239
41.0M
  const AArch64FrameLowering *getFrameLowering() const override {
240
41.0M
    return &FrameLowering;
241
41.0M
  }
242
42.7M
  const AArch64TargetLowering *getTargetLowering() const override {
243
42.7M
    return &TLInfo;
244
42.7M
  }
245
257M
  const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
246
162M
  const AArch64RegisterInfo *getRegisterInfo() const override {
247
162M
    return &getInstrInfo()->getRegisterInfo();
248
162M
  }
249
  const CallLowering *getCallLowering() const override;
250
  const InstructionSelector *getInstructionSelector() const override;
251
  const LegalizerInfo *getLegalizerInfo() const override;
252
  const RegisterBankInfo *getRegBankInfo() const override;
253
239k
  const Triple &getTargetTriple() const { return TargetTriple; }
254
1.17M
  bool enableMachineScheduler() const override { return true; }
255
253k
  bool enablePostRAScheduler() const override {
256
253k
    return UsePostRAScheduler;
257
253k
  }
258
259
  /// Returns ARM processor family.
260
  /// Avoid this function! CPU specifics should be kept local to this class
261
  /// and preferably modeled with SubtargetFeatures or properties in
262
  /// initializeProperties().
263
1.54M
  ARMProcFamilyEnum getProcFamily() const {
264
1.54M
    return ARMProcFamily;
265
1.54M
  }
266
267
0
  bool hasV8_1aOps() const { return HasV8_1aOps; }
268
0
  bool hasV8_2aOps() const { return HasV8_2aOps; }
269
15
  bool hasV8_3aOps() const { return HasV8_3aOps; }
270
0
  bool hasV8_4aOps() const { return HasV8_4aOps; }
271
0
  bool hasV8_5aOps() const { return HasV8_5aOps; }
272
273
200k
  bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
274
275
103k
  bool hasZeroCycleZeroingGP() const { return HasZeroCycleZeroingGP; }
276
277
8.23k
  bool hasZeroCycleZeroingFP() const { return HasZeroCycleZeroingFP; }
278
279
9.35k
  bool hasZeroCycleZeroingFPWorkaround() const {
280
9.35k
    return HasZeroCycleZeroingFPWorkaround;
281
9.35k
  }
282
283
779k
  bool requiresStrictAlign() const { return StrictAlign; }
284
285
3
  bool isXRaySupported() const override { return true; }
286
287
240k
  unsigned getMinVectorRegisterBitWidth() const {
288
240k
    return MinVectorRegisterBitWidth;
289
240k
  }
290
291
469M
  bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
292
120
  unsigned getNumXRegisterReserved() const { return ReserveXRegister.count(); }
293
1.76k
  bool isXRegCustomCalleeSaved(size_t i) const {
294
1.76k
    return CustomCallSavedXRegs[i];
295
1.76k
  }
296
1.77M
  bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
297
67.8k
  bool hasFPARMv8() const { return HasFPARMv8; }
298
1.11M
  bool hasNEON() const { return HasNEON; }
299
0
  bool hasCrypto() const { return HasCrypto; }
300
9.11k
  bool hasDotProd() const { return HasDotProd; }
301
9.12k
  bool hasCRC() const { return HasCRC; }
302
45.5k
  bool hasLSE() const { return HasLSE; }
303
0
  bool hasRAS() const { return HasRAS; }
304
9.32k
  bool hasRDM() const { return HasRDM; }
305
0
  bool hasSM4() const { return HasSM4; }
306
0
  bool hasSHA3() const { return HasSHA3; }
307
9.14k
  bool hasSHA2() const { return HasSHA2; }
308
9.21k
  bool hasAES() const { return HasAES; }
309
257k
  bool balanceFPOps() const { return BalanceFPOps; }
310
9.10k
  bool predictableSelectIsExpensive() const {
311
9.10k
    return PredictableSelectIsExpensive;
312
9.10k
  }
313
2.94M
  bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
314
1.36k
  bool hasExynosCheapAsMoveHandling() const { return ExynosAsCheapAsMove; }
315
1.01M
  bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
316
3.76M
  bool isPaired128Slow() const { return Paired128IsSlow; }
317
6.09M
  bool isSTRQroSlow() const { return STRQroIsSlow; }
318
9.14k
  bool useAlternateSExtLoadCVTF32Pattern() const {
319
9.14k
    return UseAlternateSExtLoadCVTF32Pattern;
320
9.14k
  }
321
12.3M
  bool hasArithmeticBccFusion() const { return HasArithmeticBccFusion; }
322
11.3M
  bool hasArithmeticCbzFusion() const { return HasArithmeticCbzFusion; }
323
11.1M
  bool hasFuseAddress() const { return HasFuseAddress; }
324
11.1M
  bool hasFuseAES() const { return HasFuseAES; }
325
11.1M
  bool hasFuseArithmeticLogic() const { return HasFuseArithmeticLogic; }
326
11.1M
  bool hasFuseCCSelect() const { return HasFuseCCSelect; }
327
11.1M
  bool hasFuseCryptoEOR() const { return HasFuseCryptoEOR; }
328
11.1M
  bool hasFuseLiterals() const { return HasFuseLiterals; }
329
330
  /// Return true if the CPU supports any kind of instruction fusion.
331
269k
  bool hasFusion() const {
332
269k
    return hasArithmeticBccFusion() || 
hasArithmeticCbzFusion()27.9k
||
333
269k
           
hasFuseAES()27.9k
||
hasFuseArithmeticLogic()681
||
334
269k
           
hasFuseCCSelect()681
||
hasFuseLiterals()681
;
335
269k
  }
336
337
49
  bool useEL1ForTP() const { return UseEL1ForTP; }
338
50
  bool useEL2ForTP() const { return UseEL2ForTP; }
339
51
  bool useEL3ForTP() const { return UseEL3ForTP; }
340
341
69
  bool useRSqrt() const { return UseRSqrt; }
342
257k
  bool force32BitJumpTables() const { return Force32BitJumpTables; }
343
17.1k
  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
344
958k
  unsigned getVectorInsertExtractBaseCost() const {
345
958k
    return VectorInsertExtractBaseCost;
346
958k
  }
347
18
  unsigned getCacheLineSize() const { return CacheLineSize; }
348
412k
  unsigned getPrefetchDistance() const { return PrefetchDistance; }
349
9.55k
  unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
350
155k
  unsigned getMaxPrefetchIterationsAhead() const {
351
155k
    return MaxPrefetchIterationsAhead;
352
155k
  }
353
9.10k
  unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
354
9.10k
  unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
355
356
9.10k
  unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
357
358
1.08k
  unsigned getWideningBaseCost() const { return WideningBaseCost; }
359
360
  /// CPU has TBI (top byte of addresses is ignored during HW address
361
  /// translation) and OS enables it.
362
  bool supportsAddressTopByteIgnored() const;
363
364
18.2k
  bool hasPerfMon() const { return HasPerfMon; }
365
248k
  bool hasFullFP16() const { return HasFullFP16; }
366
9.11k
  bool hasFP16FML() const { return HasFP16FML; }
367
0
  bool hasSPE() const { return HasSPE; }
368
52.9k
  bool hasLSLFast() const { return HasLSLFast; }
369
0
  bool hasSVE() const { return HasSVE; }
370
0
  bool hasSVE2() const { return HasSVE2; }
371
0
  bool hasRCPC() const { return HasRCPC; }
372
555
  bool hasAggressiveFMA() const { return HasAggressiveFMA; }
373
0
  bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
374
0
  bool hasFRInt3264() const { return HasFRInt3264; }
375
0
  bool hasSpecRestrict() const { return HasSpecRestrict; }
376
0
  bool hasSSBS() const { return HasSSBS; }
377
0
  bool hasSB() const { return HasSB; }
378
0
  bool hasPredRes() const { return HasPredRes; }
379
0
  bool hasCCDP() const { return HasCCDP; }
380
0
  bool hasBTI() const { return HasBTI; }
381
0
  bool hasRandGen() const { return HasRandGen; }
382
9.17k
  bool hasMTE() const { return HasMTE; }
383
  // Arm SVE2 extensions
384
0
  bool hasSVE2AES() const { return HasSVE2AES; }
385
0
  bool hasSVE2SM4() const { return HasSVE2SM4; }
386
0
  bool hasSVE2SHA3() const { return HasSVE2SHA3; }
387
0
  bool hasSVE2BitPerm() const { return HasSVE2BitPerm; }
388
389
521k
  bool isLittleEndian() const { return IsLittle; }
390
391
3.58M
  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
392
0
  bool isTargetIOS() const { return TargetTriple.isiOS(); }
393
0
  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
394
7.86M
  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
395
5.34k
  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
396
5.34k
  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
397
398
500k
  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
399
56
  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
400
1.31M
  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
401
402
3.22M
  bool useAA() const override { return UseAA; }
403
404
0
  bool hasVH() const { return HasVH; }
405
0
  bool hasPAN() const { return HasPAN; }
406
0
  bool hasLOR() const { return HasLOR; }
407
408
0
  bool hasPsUAO() const { return HasPsUAO; }
409
0
  bool hasPAN_RWV() const { return HasPAN_RWV; }
410
0
  bool hasCCPP() const { return HasCCPP; }
411
412
0
  bool hasPA() const { return HasPA; }
413
9.10k
  bool hasJS() const { return HasJS; }
414
0
  bool hasCCIDX() const { return HasCCIDX; }
415
0
  bool hasComplxNum() const { return HasComplxNum; }
416
417
0
  bool hasNV() const { return HasNV; }
418
0
  bool hasRASv8_4() const { return HasRASv8_4; }
419
0
  bool hasMPAM() const { return HasMPAM; }
420
0
  bool hasDIT() const { return HasDIT; }
421
0
  bool hasTRACEV8_4() const { return HasTRACEV8_4; }
422
0
  bool hasAM() const { return HasAM; }
423
0
  bool hasSEL2() const { return HasSEL2; }
424
0
  bool hasTLB_RMI() const { return HasTLB_RMI; }
425
0
  bool hasFMI() const { return HasFMI; }
426
0
  bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
427
428
676k
  bool useSmallAddressing() const {
429
676k
    switch (TLInfo.getTargetMachine().getCodeModel()) {
430
676k
      case CodeModel::Kernel:
431
676k
        // Kernel is currently allowed only for Fuchsia targets,
432
676k
        // where it is the same as Small for almost all purposes.
433
676k
      case CodeModel::Small:
434
676k
        return true;
435
676k
      default:
436
349
        return false;
437
676k
    }
438
676k
  }
439
440
  /// ParseSubtargetFeatures - Parses features string setting specified
441
  /// subtarget options.  Definition of function is auto generated by tblgen.
442
  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
443
444
  /// ClassifyGlobalReference - Find the target operand flags that describe
445
  /// how a global value should be referenced for the current subtarget.
446
  unsigned char ClassifyGlobalReference(const GlobalValue *GV,
447
                                        const TargetMachine &TM) const;
448
449
  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
450
                                                const TargetMachine &TM) const;
451
452
  void overrideSchedPolicy(MachineSchedPolicy &Policy,
453
                           unsigned NumRegionInstrs) const override;
454
455
  bool enableEarlyIfConversion() const override;
456
457
  std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
458
459
1.19M
  bool isCallingConvWin64(CallingConv::ID CC) const {
460
1.19M
    switch (CC) {
461
1.19M
    case CallingConv::C:
462
1.19M
    case CallingConv::Fast:
463
1.19M
    case CallingConv::Swift:
464
1.19M
      return isTargetWindows();
465
1.19M
    case CallingConv::Win64:
466
37
      return true;
467
1.19M
    default:
468
326
      return false;
469
1.19M
    }
470
1.19M
  }
471
472
  void mirFileLoaded(MachineFunction &MF) const override;
473
};
474
} // End llvm namespace
475
476
#endif