Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
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//===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
8
//
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//
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//===----------------------------------------------------------------------===//
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12
#include "AArch64TargetMachine.h"
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#include "AArch64.h"
14
#include "AArch64MacroFusion.h"
15
#include "AArch64Subtarget.h"
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#include "AArch64TargetObjectFile.h"
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#include "AArch64TargetTransformInfo.h"
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
19
#include "TargetInfo/AArch64TargetInfo.h"
20
#include "llvm/ADT/STLExtras.h"
21
#include "llvm/ADT/Triple.h"
22
#include "llvm/Analysis/TargetTransformInfo.h"
23
#include "llvm/CodeGen/CSEConfigBase.h"
24
#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
25
#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
26
#include "llvm/CodeGen/GlobalISel/Legalizer.h"
27
#include "llvm/CodeGen/GlobalISel/Localizer.h"
28
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
29
#include "llvm/CodeGen/MachineScheduler.h"
30
#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
32
#include "llvm/IR/Attributes.h"
33
#include "llvm/IR/Function.h"
34
#include "llvm/MC/MCAsmInfo.h"
35
#include "llvm/MC/MCTargetOptions.h"
36
#include "llvm/Pass.h"
37
#include "llvm/Support/CodeGen.h"
38
#include "llvm/Support/CommandLine.h"
39
#include "llvm/Support/TargetRegistry.h"
40
#include "llvm/Target/TargetLoweringObjectFile.h"
41
#include "llvm/Target/TargetOptions.h"
42
#include "llvm/Transforms/Scalar.h"
43
#include <memory>
44
#include <string>
45
46
using namespace llvm;
47
48
static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
49
                                cl::desc("Enable the CCMP formation pass"),
50
                                cl::init(true), cl::Hidden);
51
52
static cl::opt<bool>
53
    EnableCondBrTuning("aarch64-enable-cond-br-tune",
54
                       cl::desc("Enable the conditional branch tuning pass"),
55
                       cl::init(true), cl::Hidden);
56
57
static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
58
                               cl::desc("Enable the machine combiner pass"),
59
                               cl::init(true), cl::Hidden);
60
61
static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
62
                                          cl::desc("Suppress STP for AArch64"),
63
                                          cl::init(true), cl::Hidden);
64
65
static cl::opt<bool> EnableAdvSIMDScalar(
66
    "aarch64-enable-simd-scalar",
67
    cl::desc("Enable use of AdvSIMD scalar integer instructions"),
68
    cl::init(false), cl::Hidden);
69
70
static cl::opt<bool>
71
    EnablePromoteConstant("aarch64-enable-promote-const",
72
                          cl::desc("Enable the promote constant pass"),
73
                          cl::init(true), cl::Hidden);
74
75
static cl::opt<bool> EnableCollectLOH(
76
    "aarch64-enable-collect-loh",
77
    cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
78
    cl::init(true), cl::Hidden);
79
80
static cl::opt<bool>
81
    EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
82
                                  cl::desc("Enable the pass that removes dead"
83
                                           " definitons and replaces stores to"
84
                                           " them with stores to the zero"
85
                                           " register"),
86
                                  cl::init(true));
87
88
static cl::opt<bool> EnableRedundantCopyElimination(
89
    "aarch64-enable-copyelim",
90
    cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
91
    cl::Hidden);
92
93
static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
94
                                        cl::desc("Enable the load/store pair"
95
                                                 " optimization pass"),
96
                                        cl::init(true), cl::Hidden);
97
98
static cl::opt<bool> EnableAtomicTidy(
99
    "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
100
    cl::desc("Run SimplifyCFG after expanding atomic operations"
101
             " to make use of cmpxchg flow-based information"),
102
    cl::init(true));
103
104
static cl::opt<bool>
105
EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
106
                        cl::desc("Run early if-conversion"),
107
                        cl::init(true));
108
109
static cl::opt<bool>
110
    EnableCondOpt("aarch64-enable-condopt",
111
                  cl::desc("Enable the condition optimizer pass"),
112
                  cl::init(true), cl::Hidden);
113
114
static cl::opt<bool>
115
EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
116
                cl::desc("Work around Cortex-A53 erratum 835769"),
117
                cl::init(false));
118
119
static cl::opt<bool>
120
    EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
121
                 cl::desc("Enable optimizations on complex GEPs"),
122
                 cl::init(false));
123
124
static cl::opt<bool>
125
    BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
126
                     cl::desc("Relax out of range conditional branches"));
127
128
static cl::opt<bool> EnableCompressJumpTables(
129
    "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
130
    cl::desc("Use smallest entry possible for jump tables"));
131
132
// FIXME: Unify control over GlobalMerge.
133
static cl::opt<cl::boolOrDefault>
134
    EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
135
                      cl::desc("Enable the global merge pass"));
136
137
static cl::opt<bool>
138
    EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
139
                           cl::desc("Enable the loop data prefetch pass"),
140
                           cl::init(true));
141
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static cl::opt<int> EnableGlobalISelAtO(
143
    "aarch64-enable-global-isel-at-O", cl::Hidden,
144
    cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
145
    cl::init(0));
146
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static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
148
                                         cl::init(true), cl::Hidden);
149
150
static cl::opt<bool>
151
    EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
152
                        cl::desc("Enable the AAcrh64 branch target pass"),
153
                        cl::init(true));
154
155
139k
extern "C" void LLVMInitializeAArch64Target() {
156
139k
  // Register the target.
157
139k
  RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
158
139k
  RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
159
139k
  RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
160
139k
  auto PR = PassRegistry::getPassRegistry();
161
139k
  initializeGlobalISel(*PR);
162
139k
  initializeAArch64A53Fix835769Pass(*PR);
163
139k
  initializeAArch64A57FPLoadBalancingPass(*PR);
164
139k
  initializeAArch64AdvSIMDScalarPass(*PR);
165
139k
  initializeAArch64BranchTargetsPass(*PR);
166
139k
  initializeAArch64CollectLOHPass(*PR);
167
139k
  initializeAArch64CompressJumpTablesPass(*PR);
168
139k
  initializeAArch64ConditionalComparesPass(*PR);
169
139k
  initializeAArch64ConditionOptimizerPass(*PR);
170
139k
  initializeAArch64DeadRegisterDefinitionsPass(*PR);
171
139k
  initializeAArch64ExpandPseudoPass(*PR);
172
139k
  initializeAArch64LoadStoreOptPass(*PR);
173
139k
  initializeAArch64SIMDInstrOptPass(*PR);
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139k
  initializeAArch64PreLegalizerCombinerPass(*PR);
175
139k
  initializeAArch64PromoteConstantPass(*PR);
176
139k
  initializeAArch64RedundantCopyEliminationPass(*PR);
177
139k
  initializeAArch64StorePairSuppressPass(*PR);
178
139k
  initializeFalkorHWPFFixPass(*PR);
179
139k
  initializeFalkorMarkStridedAccessesLegacyPass(*PR);
180
139k
  initializeLDTLSCleanupPass(*PR);
181
139k
  initializeAArch64SpeculationHardeningPass(*PR);
182
139k
  initializeAArch64StackTaggingPass(*PR);
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139k
}
184
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//===----------------------------------------------------------------------===//
186
// AArch64 Lowering public interface.
187
//===----------------------------------------------------------------------===//
188
9.63k
static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
189
9.63k
  if (TT.isOSBinFormatMachO())
190
7.79k
    return llvm::make_unique<AArch64_MachoTargetObjectFile>();
191
1.83k
  if (TT.isOSBinFormatCOFF())
192
111
    return llvm::make_unique<AArch64_COFFTargetObjectFile>();
193
1.72k
194
1.72k
  return llvm::make_unique<AArch64_ELFTargetObjectFile>();
195
1.72k
}
196
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// Helper function to build a DataLayout string
198
static std::string computeDataLayout(const Triple &TT,
199
                                     const MCTargetOptions &Options,
200
9.63k
                                     bool LittleEndian) {
201
9.63k
  if (Options.getABIName() == "ilp32")
202
0
    return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
203
9.63k
  if (TT.isOSBinFormatMachO())
204
7.79k
    return "e-m:o-i64:64-i128:128-n32:64-S128";
205
1.84k
  if (TT.isOSBinFormatCOFF())
206
112
    return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
207
1.72k
  if (LittleEndian)
208
1.69k
    return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
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36
  return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
210
36
}
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static Reloc::Model getEffectiveRelocModel(const Triple &TT,
213
9.63k
                                           Optional<Reloc::Model> RM) {
214
9.63k
  // AArch64 Darwin and Windows are always PIC.
215
9.63k
  if (TT.isOSDarwin() || 
TT.isOSWindows()1.84k
)
216
7.90k
    return Reloc::PIC_;
217
1.73k
  // On ELF platforms the default static relocation model has a smart enough
218
1.73k
  // linker to cope with referencing external symbols defined in a shared
219
1.73k
  // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
220
1.73k
  if (!RM.hasValue() || 
*RM == Reloc::DynamicNoPIC201
)
221
1.52k
    return Reloc::Static;
222
201
  return *RM;
223
201
}
224
225
static CodeModel::Model
226
getEffectiveAArch64CodeModel(const Triple &TT, Optional<CodeModel::Model> CM,
227
9.63k
                             bool JIT) {
228
9.63k
  if (CM) {
229
58
    if (*CM != CodeModel::Small && 
*CM != CodeModel::Tiny53
&&
230
58
        
*CM != CodeModel::Large29
) {
231
6
      if (!TT.isOSFuchsia())
232
0
        report_fatal_error(
233
0
            "Only small, tiny and large code models are allowed on AArch64");
234
6
      else if (*CM != CodeModel::Kernel)
235
0
        report_fatal_error("Only small, tiny, kernel, and large code models "
236
0
                           "are allowed on AArch64");
237
52
    } else if (*CM == CodeModel::Tiny && 
!TT.isOSBinFormatELF()24
)
238
3
      report_fatal_error("tiny code model is only supported on ELF");
239
55
    return *CM;
240
55
  }
241
9.57k
  // The default MCJIT memory managers make no guarantees about where they can
242
9.57k
  // find an executable page; JITed code needs to be able to refer to globals
243
9.57k
  // no matter how far away they are.
244
9.57k
  if (JIT)
245
0
    return CodeModel::Large;
246
9.57k
  return CodeModel::Small;
247
9.57k
}
248
249
/// Create an AArch64 architecture model.
250
///
251
AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
252
                                           StringRef CPU, StringRef FS,
253
                                           const TargetOptions &Options,
254
                                           Optional<Reloc::Model> RM,
255
                                           Optional<CodeModel::Model> CM,
256
                                           CodeGenOpt::Level OL, bool JIT,
257
                                           bool LittleEndian)
258
    : LLVMTargetMachine(T,
259
                        computeDataLayout(TT, Options.MCOptions, LittleEndian),
260
                        TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM),
261
                        getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
262
9.63k
      TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
263
9.63k
  initAsmInfo();
264
9.63k
265
9.63k
  if (TT.isOSBinFormatMachO()) {
266
7.79k
    this->Options.TrapUnreachable = true;
267
7.79k
    this->Options.NoTrapAfterNoreturn = true;
268
7.79k
  }
269
9.63k
270
9.63k
  if (getMCAsmInfo()->usesWindowsCFI()) {
271
110
    // Unwinding can get confused if the last instruction in an
272
110
    // exception-handling region (function, funclet, try block, etc.)
273
110
    // is a call.
274
110
    //
275
110
    // FIXME: We could elide the trap if the next instruction would be in
276
110
    // the same region anyway.
277
110
    this->Options.TrapUnreachable = true;
278
110
  }
279
9.63k
280
9.63k
  // Enable GlobalISel at or below EnableGlobalISelAt0.
281
9.63k
  if (getOptLevel() <= EnableGlobalISelAtO) {
282
698
    setGlobalISel(true);
283
698
    setGlobalISelAbort(GlobalISelAbortMode::Disable);
284
698
  }
285
9.63k
286
9.63k
  // AArch64 supports the MachineOutliner.
287
9.63k
  setMachineOutliner(true);
288
9.63k
289
9.63k
  // AArch64 supports default outlining behaviour.
290
9.63k
  setSupportsDefaultOutlining(true);
291
9.63k
}
292
293
2.25k
AArch64TargetMachine::~AArch64TargetMachine() = default;
294
295
const AArch64Subtarget *
296
17.2M
AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
297
17.2M
  Attribute CPUAttr = F.getFnAttribute("target-cpu");
298
17.2M
  Attribute FSAttr = F.getFnAttribute("target-features");
299
17.2M
300
17.2M
  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
301
17.2M
                        ? 
CPUAttr.getValueAsString().str()5.52M
302
17.2M
                        : 
TargetCPU11.6M
;
303
17.2M
  std::string FS = !FSAttr.hasAttribute(Attribute::None)
304
17.2M
                       ? 
FSAttr.getValueAsString().str()5.60M
305
17.2M
                       : 
TargetFS11.6M
;
306
17.2M
307
17.2M
  auto &I = SubtargetMap[CPU + FS];
308
17.2M
  if (!I) {
309
9.10k
    // This needs to be done before we create a new subtarget since any
310
9.10k
    // creation will depend on the TM and the code generation flags on the
311
9.10k
    // function that reside in TargetOptions.
312
9.10k
    resetTargetOptions(F);
313
9.10k
    I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
314
9.10k
                                            isLittle);
315
9.10k
  }
316
17.2M
  return I.get();
317
17.2M
}
318
319
0
void AArch64leTargetMachine::anchor() { }
320
321
AArch64leTargetMachine::AArch64leTargetMachine(
322
    const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
323
    const TargetOptions &Options, Optional<Reloc::Model> RM,
324
    Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
325
9.60k
    : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
326
327
0
void AArch64beTargetMachine::anchor() { }
328
329
AArch64beTargetMachine::AArch64beTargetMachine(
330
    const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
331
    const TargetOptions &Options, Optional<Reloc::Model> RM,
332
    Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
333
36
    : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
334
335
namespace {
336
337
/// AArch64 Code Generator Pass Configuration Options.
338
class AArch64PassConfig : public TargetPassConfig {
339
public:
340
  AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
341
9.31k
      : TargetPassConfig(TM, PM) {
342
9.31k
    if (TM.getOptLevel() != CodeGenOpt::None)
343
8.85k
      substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
344
9.31k
  }
345
346
8.75k
  AArch64TargetMachine &getAArch64TargetMachine() const {
347
8.75k
    return getTM<AArch64TargetMachine>();
348
8.75k
  }
349
350
  ScheduleDAGInstrs *
351
256k
  createMachineScheduler(MachineSchedContext *C) const override {
352
256k
    const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
353
256k
    ScheduleDAGMILive *DAG = createGenericSchedLive(C);
354
256k
    DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
355
256k
    DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
356
256k
    if (ST.hasFusion())
357
256k
      DAG->addMutation(createAArch64MacroFusionDAGMutation());
358
256k
    return DAG;
359
256k
  }
360
361
  ScheduleDAGInstrs *
362
12.5k
  createPostMachineScheduler(MachineSchedContext *C) const override {
363
12.5k
    const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
364
12.5k
    if (ST.hasFusion()) {
365
12.4k
      // Run the Macro Fusion after RA again since literals are expanded from
366
12.4k
      // pseudos then (v. addPreSched2()).
367
12.4k
      ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
368
12.4k
      DAG->addMutation(createAArch64MacroFusionDAGMutation());
369
12.4k
      return DAG;
370
12.4k
    }
371
137
372
137
    return nullptr;
373
137
  }
374
375
  void addIRPasses()  override;
376
  bool addPreISel() override;
377
  bool addInstSelector() override;
378
  bool addIRTranslator() override;
379
  void addPreLegalizeMachineIR() override;
380
  bool addLegalizeMachineIR() override;
381
  bool addRegBankSelect() override;
382
  void addPreGlobalInstructionSelect() override;
383
  bool addGlobalInstructionSelect() override;
384
  bool addILPOpts() override;
385
  void addPreRegAlloc() override;
386
  void addPostRegAlloc() override;
387
  void addPreSched2() override;
388
  void addPreEmitPass() override;
389
390
  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
391
};
392
393
} // end anonymous namespace
394
395
TargetTransformInfo
396
11.9M
AArch64TargetMachine::getTargetTransformInfo(const Function &F) {
397
11.9M
  return TargetTransformInfo(AArch64TTIImpl(this, F));
398
11.9M
}
399
400
9.31k
TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
401
9.31k
  return new AArch64PassConfig(*this, PM);
402
9.31k
}
403
404
471k
std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
405
471k
  return getStandardCSEConfigForOpt(TM->getOptLevel());
406
471k
}
407
408
8.78k
void AArch64PassConfig::addIRPasses() {
409
8.78k
  // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
410
8.78k
  // ourselves.
411
8.78k
  addPass(createAtomicExpandPass());
412
8.78k
413
8.78k
  // Cmpxchg instructions are often used with a subsequent comparison to
414
8.78k
  // determine whether it succeeded. We can exploit existing control-flow in
415
8.78k
  // ldrex/strex loops to simplify this, but it needs tidying up.
416
8.78k
  if (TM->getOptLevel() != CodeGenOpt::None && 
EnableAtomicTidy8.62k
)
417
8.58k
    addPass(createCFGSimplificationPass(1, true, true, false, true));
418
8.78k
419
8.78k
  // Run LoopDataPrefetch
420
8.78k
  //
421
8.78k
  // Run this before LSR to remove the multiplies involved in computing the
422
8.78k
  // pointer values N iterations ahead.
423
8.78k
  if (TM->getOptLevel() != CodeGenOpt::None) {
424
8.62k
    if (EnableLoopDataPrefetch)
425
8.62k
      addPass(createLoopDataPrefetchPass());
426
8.62k
    if (EnableFalkorHWPFFix)
427
8.62k
      addPass(createFalkorMarkStridedAccessesPass());
428
8.62k
  }
429
8.78k
430
8.78k
  TargetPassConfig::addIRPasses();
431
8.78k
432
8.78k
  // Match interleaved memory accesses to ldN/stN intrinsics.
433
8.78k
  if (TM->getOptLevel() != CodeGenOpt::None) {
434
8.62k
    addPass(createInterleavedLoadCombinePass());
435
8.62k
    addPass(createInterleavedAccessPass());
436
8.62k
  }
437
8.78k
438
8.78k
  if (TM->getOptLevel() == CodeGenOpt::Aggressive && 
EnableGEPOpt7.30k
) {
439
6
    // Call SeparateConstOffsetFromGEP pass to extract constants within indices
440
6
    // and lower a GEP with multiple indices to either arithmetic operations or
441
6
    // multiple GEPs with single index.
442
6
    addPass(createSeparateConstOffsetFromGEPPass(true));
443
6
    // Call EarlyCSE pass to find and remove subexpressions in the lowered
444
6
    // result.
445
6
    addPass(createEarlyCSEPass());
446
6
    // Do loop invariant code motion in case part of the lowered result is
447
6
    // invariant.
448
6
    addPass(createLICMPass());
449
6
  }
450
8.78k
451
8.78k
  addPass(createAArch64StackTaggingPass());
452
8.78k
}
453
454
// Pass Pipeline Configuration
455
8.78k
bool AArch64PassConfig::addPreISel() {
456
8.78k
  // Run promote constant before global merge, so that the promoted constants
457
8.78k
  // get a chance to be merged
458
8.78k
  if (TM->getOptLevel() != CodeGenOpt::None && 
EnablePromoteConstant8.62k
)
459
8.62k
    addPass(createAArch64PromoteConstantPass());
460
8.78k
  // FIXME: On AArch64, this depends on the type.
461
8.78k
  // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
462
8.78k
  // and the offset has to be a multiple of the related size in bytes.
463
8.78k
  if ((TM->getOptLevel() != CodeGenOpt::None &&
464
8.78k
       
EnableGlobalMerge == cl::BOU_UNSET8.62k
) ||
465
8.78k
      
EnableGlobalMerge == cl::BOU_TRUE177
) {
466
8.62k
    bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
467
8.62k
                               
(EnableGlobalMerge == cl::BOU_UNSET)1.32k
;
468
8.62k
469
8.62k
    // Merging of extern globals is enabled by default on non-Mach-O as we
470
8.62k
    // expect it to be generally either beneficial or harmless. On Mach-O it
471
8.62k
    // is disabled as we emit the .subsections_via_symbols directive which
472
8.62k
    // means that merging extern globals is not safe.
473
8.62k
    bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
474
8.62k
475
8.62k
    // FIXME: extern global merging is only enabled when we optimise for size
476
8.62k
    // because there are some regressions with it also enabled for performance.
477
8.62k
    if (!OnlyOptimizeForSize)
478
7.31k
      MergeExternalByDefault = false;
479
8.62k
480
8.62k
    addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,
481
8.62k
                                  MergeExternalByDefault));
482
8.62k
  }
483
8.78k
484
8.78k
  return false;
485
8.78k
}
486
487
8.75k
bool AArch64PassConfig::addInstSelector() {
488
8.75k
  addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
489
8.75k
490
8.75k
  // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
491
8.75k
  // references to _TLS_MODULE_BASE_ as possible.
492
8.75k
  if (TM->getTargetTriple().isOSBinFormatELF() &&
493
8.75k
      
getOptLevel() != CodeGenOpt::None1.05k
)
494
997
    addPass(createAArch64CleanupLocalDynamicTLSPass());
495
8.75k
496
8.75k
  return false;
497
8.75k
}
498
499
6.78k
bool AArch64PassConfig::addIRTranslator() {
500
6.78k
  addPass(new IRTranslator());
501
6.78k
  return false;
502
6.78k
}
503
504
6.78k
void AArch64PassConfig::addPreLegalizeMachineIR() {
505
6.78k
  addPass(createAArch64PreLegalizeCombiner());
506
6.78k
}
507
508
6.78k
bool AArch64PassConfig::addLegalizeMachineIR() {
509
6.78k
  addPass(new Legalizer());
510
6.78k
  return false;
511
6.78k
}
512
513
6.78k
bool AArch64PassConfig::addRegBankSelect() {
514
6.78k
  addPass(new RegBankSelect());
515
6.78k
  return false;
516
6.78k
}
517
518
6.78k
void AArch64PassConfig::addPreGlobalInstructionSelect() {
519
6.78k
  // Workaround the deficiency of the fast register allocator.
520
6.78k
  if (TM->getOptLevel() == CodeGenOpt::None)
521
106
    addPass(new Localizer());
522
6.78k
}
523
524
6.78k
bool AArch64PassConfig::addGlobalInstructionSelect() {
525
6.78k
  addPass(new InstructionSelect());
526
6.78k
  return false;
527
6.78k
}
528
529
8.62k
bool AArch64PassConfig::addILPOpts() {
530
8.62k
  if (EnableCondOpt)
531
8.62k
    addPass(createAArch64ConditionOptimizerPass());
532
8.62k
  if (EnableCCMP)
533
8.62k
    addPass(createAArch64ConditionalCompares());
534
8.62k
  if (EnableMCR)
535
8.62k
    addPass(&MachineCombinerID);
536
8.62k
  if (EnableCondBrTuning)
537
8.61k
    addPass(createAArch64CondBrTuning());
538
8.62k
  if (EnableEarlyIfConversion)
539
8.62k
    addPass(&EarlyIfConverterID);
540
8.62k
  if (EnableStPairSuppress)
541
8.62k
    addPass(createAArch64StorePairSuppressPass());
542
8.62k
  addPass(createAArch64SIMDInstrOptPass());
543
8.62k
  return true;
544
8.62k
}
545
546
8.78k
void AArch64PassConfig::addPreRegAlloc() {
547
8.78k
  // Change dead register definitions to refer to the zero register.
548
8.78k
  if (TM->getOptLevel() != CodeGenOpt::None && 
EnableDeadRegisterElimination8.62k
)
549
8.62k
    addPass(createAArch64DeadRegisterDefinitions());
550
8.78k
551
8.78k
  // Use AdvSIMD scalar instructions whenever profitable.
552
8.78k
  if (TM->getOptLevel() != CodeGenOpt::None && 
EnableAdvSIMDScalar8.62k
) {
553
5
    addPass(createAArch64AdvSIMDScalar());
554
5
    // The AdvSIMD pass may produce copies that can be rewritten to
555
5
    // be register coaleascer friendly.
556
5
    addPass(&PeepholeOptimizerID);
557
5
  }
558
8.78k
}
559
560
8.78k
void AArch64PassConfig::addPostRegAlloc() {
561
8.78k
  // Remove redundant copy instructions.
562
8.78k
  if (TM->getOptLevel() != CodeGenOpt::None && 
EnableRedundantCopyElimination8.62k
)
563
8.62k
    addPass(createAArch64RedundantCopyEliminationPass());
564
8.78k
565
8.78k
  if (TM->getOptLevel() != CodeGenOpt::None && 
usingDefaultRegAlloc()8.62k
)
566
8.61k
    // Improve performance for some FP/SIMD code for A57.
567
8.61k
    addPass(createAArch64A57FPLoadBalancing());
568
8.78k
}
569
570
8.78k
void AArch64PassConfig::addPreSched2() {
571
8.78k
  // Expand some pseudo instructions to allow proper scheduling.
572
8.78k
  addPass(createAArch64ExpandPseudoPass());
573
8.78k
  // Use load/store pair instructions when possible.
574
8.78k
  if (TM->getOptLevel() != CodeGenOpt::None) {
575
8.62k
    if (EnableLoadStoreOpt)
576
8.61k
      addPass(createAArch64LoadStoreOptimizationPass());
577
8.62k
  }
578
8.78k
579
8.78k
  // The AArch64SpeculationHardeningPass destroys dominator tree and natural
580
8.78k
  // loop info, which is needed for the FalkorHWPFFixPass and also later on.
581
8.78k
  // Therefore, run the AArch64SpeculationHardeningPass before the
582
8.78k
  // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
583
8.78k
  // info.
584
8.78k
  addPass(createAArch64SpeculationHardeningPass());
585
8.78k
586
8.78k
  if (TM->getOptLevel() != CodeGenOpt::None) {
587
8.62k
    if (EnableFalkorHWPFFix)
588
8.62k
      addPass(createFalkorHWPFFixPass());
589
8.62k
  }
590
8.78k
}
591
592
8.78k
void AArch64PassConfig::addPreEmitPass() {
593
8.78k
  // Machine Block Placement might have created new opportunities when run
594
8.78k
  // at O3, where the Tail Duplication Threshold is set to 4 instructions.
595
8.78k
  // Run the load/store optimizer once more.
596
8.78k
  if (TM->getOptLevel() >= CodeGenOpt::Aggressive && 
EnableLoadStoreOpt7.30k
)
597
7.30k
    addPass(createAArch64LoadStoreOptimizationPass());
598
8.78k
599
8.78k
  if (EnableA53Fix835769)
600
3
    addPass(createAArch64A53Fix835769());
601
8.78k
  // Relax conditional branch instructions if they're otherwise out of
602
8.78k
  // range of their destination.
603
8.78k
  if (BranchRelaxation)
604
8.78k
    addPass(&BranchRelaxationPassID);
605
8.78k
606
8.78k
  if (EnableBranchTargets)
607
8.78k
    addPass(createAArch64BranchTargetsPass());
608
8.78k
609
8.78k
  if (TM->getOptLevel() != CodeGenOpt::None && 
EnableCompressJumpTables8.62k
)
610
8.62k
    addPass(createAArch64CompressJumpTablesPass());
611
8.78k
612
8.78k
  if (TM->getOptLevel() != CodeGenOpt::None && 
EnableCollectLOH8.62k
&&
613
8.78k
      
TM->getTargetTriple().isOSBinFormatMachO()8.61k
)
614
7.51k
    addPass(createAArch64CollectLOHPass());
615
8.78k
}