Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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//==- AArch64AsmParser.cpp - Parse AArch64 assembly to MCInst instructions -==//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
9
#include "MCTargetDesc/AArch64AddressingModes.h"
10
#include "MCTargetDesc/AArch64MCExpr.h"
11
#include "MCTargetDesc/AArch64MCTargetDesc.h"
12
#include "MCTargetDesc/AArch64TargetStreamer.h"
13
#include "TargetInfo/AArch64TargetInfo.h"
14
#include "AArch64InstrInfo.h"
15
#include "Utils/AArch64BaseInfo.h"
16
#include "llvm/ADT/APFloat.h"
17
#include "llvm/ADT/APInt.h"
18
#include "llvm/ADT/ArrayRef.h"
19
#include "llvm/ADT/STLExtras.h"
20
#include "llvm/ADT/SmallVector.h"
21
#include "llvm/ADT/StringExtras.h"
22
#include "llvm/ADT/StringMap.h"
23
#include "llvm/ADT/StringRef.h"
24
#include "llvm/ADT/StringSwitch.h"
25
#include "llvm/ADT/Twine.h"
26
#include "llvm/MC/MCContext.h"
27
#include "llvm/MC/MCExpr.h"
28
#include "llvm/MC/MCInst.h"
29
#include "llvm/MC/MCLinkerOptimizationHint.h"
30
#include "llvm/MC/MCObjectFileInfo.h"
31
#include "llvm/MC/MCParser/MCAsmLexer.h"
32
#include "llvm/MC/MCParser/MCAsmParser.h"
33
#include "llvm/MC/MCParser/MCAsmParserExtension.h"
34
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
35
#include "llvm/MC/MCParser/MCTargetAsmParser.h"
36
#include "llvm/MC/MCRegisterInfo.h"
37
#include "llvm/MC/MCStreamer.h"
38
#include "llvm/MC/MCSubtargetInfo.h"
39
#include "llvm/MC/MCSymbol.h"
40
#include "llvm/MC/MCTargetOptions.h"
41
#include "llvm/MC/SubtargetFeature.h"
42
#include "llvm/MC/MCValue.h"
43
#include "llvm/Support/Casting.h"
44
#include "llvm/Support/Compiler.h"
45
#include "llvm/Support/ErrorHandling.h"
46
#include "llvm/Support/MathExtras.h"
47
#include "llvm/Support/SMLoc.h"
48
#include "llvm/Support/TargetParser.h"
49
#include "llvm/Support/TargetRegistry.h"
50
#include "llvm/Support/raw_ostream.h"
51
#include <cassert>
52
#include <cctype>
53
#include <cstdint>
54
#include <cstdio>
55
#include <string>
56
#include <tuple>
57
#include <utility>
58
#include <vector>
59
60
using namespace llvm;
61
62
namespace {
63
64
enum class RegKind {
65
  Scalar,
66
  NeonVector,
67
  SVEDataVector,
68
  SVEPredicateVector
69
};
70
71
enum RegConstraintEqualityTy {
72
  EqualsReg,
73
  EqualsSuperReg,
74
  EqualsSubReg
75
};
76
77
class AArch64AsmParser : public MCTargetAsmParser {
78
private:
79
  StringRef Mnemonic; ///< Instruction mnemonic.
80
81
  // Map of register aliases registers via the .req directive.
82
  StringMap<std::pair<RegKind, unsigned>> RegisterReqs;
83
84
  class PrefixInfo {
85
  public:
86
34.8k
    static PrefixInfo CreateFromInst(const MCInst &Inst, uint64_t TSFlags) {
87
34.8k
      PrefixInfo Prefix;
88
34.8k
      switch (Inst.getOpcode()) {
89
34.8k
      case AArch64::MOVPRFX_ZZ:
90
1.25k
        Prefix.Active = true;
91
1.25k
        Prefix.Dst = Inst.getOperand(0).getReg();
92
1.25k
        break;
93
34.8k
      case AArch64::MOVPRFX_ZPmZ_B:
94
17
      case AArch64::MOVPRFX_ZPmZ_H:
95
17
      case AArch64::MOVPRFX_ZPmZ_S:
96
17
      case AArch64::MOVPRFX_ZPmZ_D:
97
17
        Prefix.Active = true;
98
17
        Prefix.Predicated = true;
99
17
        Prefix.ElementSize = TSFlags & AArch64::ElementSizeMask;
100
17
        assert(Prefix.ElementSize != AArch64::ElementSizeNone &&
101
17
               "No destructive element size set for movprfx");
102
17
        Prefix.Dst = Inst.getOperand(0).getReg();
103
17
        Prefix.Pg = Inst.getOperand(2).getReg();
104
17
        break;
105
910
      case AArch64::MOVPRFX_ZPzZ_B:
106
910
      case AArch64::MOVPRFX_ZPzZ_H:
107
910
      case AArch64::MOVPRFX_ZPzZ_S:
108
910
      case AArch64::MOVPRFX_ZPzZ_D:
109
910
        Prefix.Active = true;
110
910
        Prefix.Predicated = true;
111
910
        Prefix.ElementSize = TSFlags & AArch64::ElementSizeMask;
112
910
        assert(Prefix.ElementSize != AArch64::ElementSizeNone &&
113
910
               "No destructive element size set for movprfx");
114
910
        Prefix.Dst = Inst.getOperand(0).getReg();
115
910
        Prefix.Pg = Inst.getOperand(1).getReg();
116
910
        break;
117
32.6k
      default:
118
32.6k
        break;
119
34.8k
      }
120
34.8k
121
34.8k
      return Prefix;
122
34.8k
    }
123
124
38.3k
    PrefixInfo() : Active(false), Predicated(false) {}
125
34.8k
    bool isActive() const { return Active; }
126
1.57k
    bool isPredicated() const { return Predicated; }
127
477
    unsigned getElementSize() const {
128
477
      assert(Predicated);
129
477
      return ElementSize;
130
477
    }
131
4.12k
    unsigned getDstReg() const { return Dst; }
132
481
    unsigned getPgReg() const {
133
481
      assert(Predicated);
134
481
      return Pg;
135
481
    }
136
137
  private:
138
    bool Active;
139
    bool Predicated;
140
    unsigned ElementSize;
141
    unsigned Dst;
142
    unsigned Pg;
143
  } NextPrefix;
144
145
46
  AArch64TargetStreamer &getTargetStreamer() {
146
46
    MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
147
46
    return static_cast<AArch64TargetStreamer &>(TS);
148
46
  }
149
150
732k
  SMLoc getLoc() const { return getParser().getTok().getLoc(); }
151
152
  bool parseSysAlias(StringRef Name, SMLoc NameLoc, OperandVector &Operands);
153
  void createSysAlias(uint16_t Encoding, OperandVector &Operands, SMLoc S);
154
  AArch64CC::CondCode parseCondCodeString(StringRef Cond);
155
  bool parseCondCode(OperandVector &Operands, bool invertCondCode);
156
  unsigned matchRegisterNameAlias(StringRef Name, RegKind Kind);
157
  bool parseRegister(OperandVector &Operands);
158
  bool parseSymbolicImmVal(const MCExpr *&ImmVal);
159
  bool parseNeonVectorList(OperandVector &Operands);
160
  bool parseOptionalMulOperand(OperandVector &Operands);
161
  bool parseOperand(OperandVector &Operands, bool isCondCode,
162
                    bool invertCondCode);
163
164
  bool showMatchError(SMLoc Loc, unsigned ErrCode, uint64_t ErrorInfo,
165
                      OperandVector &Operands);
166
167
  bool parseDirectiveArch(SMLoc L);
168
  bool parseDirectiveArchExtension(SMLoc L);
169
  bool parseDirectiveCPU(SMLoc L);
170
  bool parseDirectiveInst(SMLoc L);
171
172
  bool parseDirectiveTLSDescCall(SMLoc L);
173
174
  bool parseDirectiveLOH(StringRef LOH, SMLoc L);
175
  bool parseDirectiveLtorg(SMLoc L);
176
177
  bool parseDirectiveReq(StringRef Name, SMLoc L);
178
  bool parseDirectiveUnreq(SMLoc L);
179
  bool parseDirectiveCFINegateRAState();
180
  bool parseDirectiveCFIBKeyFrame();
181
182
  bool validateInstruction(MCInst &Inst, SMLoc &IDLoc,
183
                           SmallVectorImpl<SMLoc> &Loc);
184
  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
185
                               OperandVector &Operands, MCStreamer &Out,
186
                               uint64_t &ErrorInfo,
187
                               bool MatchingInlineAsm) override;
188
/// @name Auto-generated Match Functions
189
/// {
190
191
#define GET_ASSEMBLER_HEADER
192
#include "AArch64GenAsmMatcher.inc"
193
194
  /// }
195
196
  OperandMatchResultTy tryParseScalarRegister(unsigned &Reg);
197
  OperandMatchResultTy tryParseVectorRegister(unsigned &Reg, StringRef &Kind,
198
                                              RegKind MatchKind);
199
  OperandMatchResultTy tryParseOptionalShiftExtend(OperandVector &Operands);
200
  OperandMatchResultTy tryParseBarrierOperand(OperandVector &Operands);
201
  OperandMatchResultTy tryParseMRSSystemRegister(OperandVector &Operands);
202
  OperandMatchResultTy tryParseSysReg(OperandVector &Operands);
203
  OperandMatchResultTy tryParseSysCROperand(OperandVector &Operands);
204
  template <bool IsSVEPrefetch = false>
205
  OperandMatchResultTy tryParsePrefetch(OperandVector &Operands);
206
  OperandMatchResultTy tryParsePSBHint(OperandVector &Operands);
207
  OperandMatchResultTy tryParseBTIHint(OperandVector &Operands);
208
  OperandMatchResultTy tryParseAdrpLabel(OperandVector &Operands);
209
  OperandMatchResultTy tryParseAdrLabel(OperandVector &Operands);
210
  template<bool AddFPZeroAsLiteral>
211
  OperandMatchResultTy tryParseFPImm(OperandVector &Operands);
212
  OperandMatchResultTy tryParseImmWithOptionalShift(OperandVector &Operands);
213
  OperandMatchResultTy tryParseGPR64sp0Operand(OperandVector &Operands);
214
  bool tryParseNeonVectorRegister(OperandVector &Operands);
215
  OperandMatchResultTy tryParseVectorIndex(OperandVector &Operands);
216
  OperandMatchResultTy tryParseGPRSeqPair(OperandVector &Operands);
217
  template <bool ParseShiftExtend,
218
            RegConstraintEqualityTy EqTy = RegConstraintEqualityTy::EqualsReg>
219
  OperandMatchResultTy tryParseGPROperand(OperandVector &Operands);
220
  template <bool ParseShiftExtend, bool ParseSuffix>
221
  OperandMatchResultTy tryParseSVEDataVector(OperandVector &Operands);
222
  OperandMatchResultTy tryParseSVEPredicateVector(OperandVector &Operands);
223
  template <RegKind VectorKind>
224
  OperandMatchResultTy tryParseVectorList(OperandVector &Operands,
225
                                          bool ExpectMatch = false);
226
  OperandMatchResultTy tryParseSVEPattern(OperandVector &Operands);
227
228
public:
229
  enum AArch64MatchResultTy {
230
    Match_InvalidSuffix = FIRST_TARGET_MATCH_RESULT_TY,
231
#define GET_OPERAND_DIAGNOSTIC_TYPES
232
#include "AArch64GenAsmMatcher.inc"
233
  };
234
  bool IsILP32;
235
236
  AArch64AsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
237
                   const MCInstrInfo &MII, const MCTargetOptions &Options)
238
3.49k
    : MCTargetAsmParser(Options, STI, MII) {
239
3.49k
    IsILP32 = Options.getABIName() == "ilp32";
240
3.49k
    MCAsmParserExtension::Initialize(Parser);
241
3.49k
    MCStreamer &S = getParser().getStreamer();
242
3.49k
    if (S.getTargetStreamer() == nullptr)
243
211
      new AArch64TargetStreamer(S);
244
3.49k
245
3.49k
    // Alias .hword/.word/.[dx]word to the target-independent
246
3.49k
    // .2byte/.4byte/.8byte directives as they have the same form and
247
3.49k
    // semantics:
248
3.49k
    ///  ::= (.hword | .word | .dword | .xword ) [ expression (, expression)* ]
249
3.49k
    Parser.addAliasForDirective(".hword", ".2byte");
250
3.49k
    Parser.addAliasForDirective(".word", ".4byte");
251
3.49k
    Parser.addAliasForDirective(".dword", ".8byte");
252
3.49k
    Parser.addAliasForDirective(".xword", ".8byte");
253
3.49k
254
3.49k
    // Initialize the set of available features.
255
3.49k
    setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
256
3.49k
  }
257
258
  bool regsEqual(const MCParsedAsmOperand &Op1,
259
                 const MCParsedAsmOperand &Op2) const override;
260
  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
261
                        SMLoc NameLoc, OperandVector &Operands) override;
262
  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
263
  bool ParseDirective(AsmToken DirectiveID) override;
264
  unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
265
                                      unsigned Kind) override;
266
267
  static bool classifySymbolRef(const MCExpr *Expr,
268
                                AArch64MCExpr::VariantKind &ELFRefKind,
269
                                MCSymbolRefExpr::VariantKind &DarwinRefKind,
270
                                int64_t &Addend);
271
};
272
273
/// AArch64Operand - Instances of this class represent a parsed AArch64 machine
274
/// instruction.
275
class AArch64Operand : public MCParsedAsmOperand {
276
private:
277
  enum KindTy {
278
    k_Immediate,
279
    k_ShiftedImm,
280
    k_CondCode,
281
    k_Register,
282
    k_VectorList,
283
    k_VectorIndex,
284
    k_Token,
285
    k_SysReg,
286
    k_SysCR,
287
    k_Prefetch,
288
    k_ShiftExtend,
289
    k_FPImm,
290
    k_Barrier,
291
    k_PSBHint,
292
    k_BTIHint,
293
  } Kind;
294
295
  SMLoc StartLoc, EndLoc;
296
297
  struct TokOp {
298
    const char *Data;
299
    unsigned Length;
300
    bool IsSuffix; // Is the operand actually a suffix on the mnemonic.
301
  };
302
303
  // Separate shift/extend operand.
304
  struct ShiftExtendOp {
305
    AArch64_AM::ShiftExtendType Type;
306
    unsigned Amount;
307
    bool HasExplicitAmount;
308
  };
309
310
  struct RegOp {
311
    unsigned RegNum;
312
    RegKind Kind;
313
    int ElementWidth;
314
315
    // The register may be allowed as a different register class,
316
    // e.g. for GPR64as32 or GPR32as64.
317
    RegConstraintEqualityTy EqualityTy;
318
319
    // In some cases the shift/extend needs to be explicitly parsed together
320
    // with the register, rather than as a separate operand. This is needed
321
    // for addressing modes where the instruction as a whole dictates the
322
    // scaling/extend, rather than specific bits in the instruction.
323
    // By parsing them as a single operand, we avoid the need to pass an
324
    // extra operand in all CodeGen patterns (because all operands need to
325
    // have an associated value), and we avoid the need to update TableGen to
326
    // accept operands that have no associated bits in the instruction.
327
    //
328
    // An added benefit of parsing them together is that the assembler
329
    // can give a sensible diagnostic if the scaling is not correct.
330
    //
331
    // The default is 'lsl #0' (HasExplicitAmount = false) if no
332
    // ShiftExtend is specified.
333
    ShiftExtendOp ShiftExtend;
334
  };
335
336
  struct VectorListOp {
337
    unsigned RegNum;
338
    unsigned Count;
339
    unsigned NumElements;
340
    unsigned ElementWidth;
341
    RegKind  RegisterKind;
342
  };
343
344
  struct VectorIndexOp {
345
    unsigned Val;
346
  };
347
348
  struct ImmOp {
349
    const MCExpr *Val;
350
  };
351
352
  struct ShiftedImmOp {
353
    const MCExpr *Val;
354
    unsigned ShiftAmount;
355
  };
356
357
  struct CondCodeOp {
358
    AArch64CC::CondCode Code;
359
  };
360
361
  struct FPImmOp {
362
    uint64_t Val; // APFloat value bitcasted to uint64_t.
363
    bool IsExact; // describes whether parsed value was exact.
364
  };
365
366
  struct BarrierOp {
367
    const char *Data;
368
    unsigned Length;
369
    unsigned Val; // Not the enum since not all values have names.
370
  };
371
372
  struct SysRegOp {
373
    const char *Data;
374
    unsigned Length;
375
    uint32_t MRSReg;
376
    uint32_t MSRReg;
377
    uint32_t PStateField;
378
  };
379
380
  struct SysCRImmOp {
381
    unsigned Val;
382
  };
383
384
  struct PrefetchOp {
385
    const char *Data;
386
    unsigned Length;
387
    unsigned Val;
388
  };
389
390
  struct PSBHintOp {
391
    const char *Data;
392
    unsigned Length;
393
    unsigned Val;
394
  };
395
396
  struct BTIHintOp {
397
    const char *Data;
398
    unsigned Length;
399
    unsigned Val;
400
  };
401
402
  struct ExtendOp {
403
    unsigned Val;
404
  };
405
406
  union {
407
    struct TokOp Tok;
408
    struct RegOp Reg;
409
    struct VectorListOp VectorList;
410
    struct VectorIndexOp VectorIndex;
411
    struct ImmOp Imm;
412
    struct ShiftedImmOp ShiftedImm;
413
    struct CondCodeOp CondCode;
414
    struct FPImmOp FPImm;
415
    struct BarrierOp Barrier;
416
    struct SysRegOp SysReg;
417
    struct SysCRImmOp SysCRImm;
418
    struct PrefetchOp Prefetch;
419
    struct PSBHintOp PSBHint;
420
    struct BTIHintOp BTIHint;
421
    struct ShiftExtendOp ShiftExtend;
422
  };
423
424
  // Keep the MCContext around as the MCExprs may need manipulated during
425
  // the add<>Operands() calls.
426
  MCContext &Ctx;
427
428
public:
429
279k
  AArch64Operand(KindTy K, MCContext &Ctx) : Kind(K), Ctx(Ctx) {}
430
431
16
  AArch64Operand(const AArch64Operand &o) : MCParsedAsmOperand(), Ctx(o.Ctx) {
432
16
    Kind = o.Kind;
433
16
    StartLoc = o.StartLoc;
434
16
    EndLoc = o.EndLoc;
435
16
    switch (Kind) {
436
16
    case k_Token:
437
0
      Tok = o.Tok;
438
0
      break;
439
16
    case k_Immediate:
440
16
      Imm = o.Imm;
441
16
      break;
442
16
    case k_ShiftedImm:
443
0
      ShiftedImm = o.ShiftedImm;
444
0
      break;
445
16
    case k_CondCode:
446
0
      CondCode = o.CondCode;
447
0
      break;
448
16
    case k_FPImm:
449
0
      FPImm = o.FPImm;
450
0
      break;
451
16
    case k_Barrier:
452
0
      Barrier = o.Barrier;
453
0
      break;
454
16
    case k_Register:
455
0
      Reg = o.Reg;
456
0
      break;
457
16
    case k_VectorList:
458
0
      VectorList = o.VectorList;
459
0
      break;
460
16
    case k_VectorIndex:
461
0
      VectorIndex = o.VectorIndex;
462
0
      break;
463
16
    case k_SysReg:
464
0
      SysReg = o.SysReg;
465
0
      break;
466
16
    case k_SysCR:
467
0
      SysCRImm = o.SysCRImm;
468
0
      break;
469
16
    case k_Prefetch:
470
0
      Prefetch = o.Prefetch;
471
0
      break;
472
16
    case k_PSBHint:
473
0
      PSBHint = o.PSBHint;
474
0
      break;
475
16
    case k_BTIHint:
476
0
      BTIHint = o.BTIHint;
477
0
      break;
478
16
    case k_ShiftExtend:
479
0
      ShiftExtend = o.ShiftExtend;
480
0
      break;
481
16
    }
482
16
  }
483
484
  /// getStartLoc - Get the location of the first token of this operand.
485
152k
  SMLoc getStartLoc() const override { return StartLoc; }
486
  /// getEndLoc - Get the location of the last token of this operand.
487
1.36k
  SMLoc getEndLoc() const override { return EndLoc; }
488
489
311k
  StringRef getToken() const {
490
311k
    assert(Kind == k_Token && "Invalid access!");
491
311k
    return StringRef(Tok.Data, Tok.Length);
492
311k
  }
493
494
903
  bool isTokenSuffix() const {
495
903
    assert(Kind == k_Token && "Invalid access!");
496
903
    return Tok.IsSuffix;
497
903
  }
498
499
41.6k
  const MCExpr *getImm() const {
500
41.6k
    assert(Kind == k_Immediate && "Invalid access!");
501
41.6k
    return Imm.Val;
502
41.6k
  }
503
504
984
  const MCExpr *getShiftedImmVal() const {
505
984
    assert(Kind == k_ShiftedImm && "Invalid access!");
506
984
    return ShiftedImm.Val;
507
984
  }
508
509
988
  unsigned getShiftedImmShift() const {
510
988
    assert(Kind == k_ShiftedImm && "Invalid access!");
511
988
    return ShiftedImm.ShiftAmount;
512
988
  }
513
514
258
  AArch64CC::CondCode getCondCode() const {
515
258
    assert(Kind == k_CondCode && "Invalid access!");
516
258
    return CondCode.Code;
517
258
  }
518
519
7.33k
  APFloat getFPImm() const {
520
7.33k
    assert (Kind == k_FPImm && "Invalid access!");
521
7.33k
    return APFloat(APFloat::IEEEdouble(), APInt(64, FPImm.Val, true));
522
7.33k
  }
523
524
1.00k
  bool getFPImmIsExact() const {
525
1.00k
    assert (Kind == k_FPImm && "Invalid access!");
526
1.00k
    return FPImm.IsExact;
527
1.00k
  }
528
529
48
  unsigned getBarrier() const {
530
48
    assert(Kind == k_Barrier && "Invalid access!");
531
48
    return Barrier.Val;
532
48
  }
533
534
0
  StringRef getBarrierName() const {
535
0
    assert(Kind == k_Barrier && "Invalid access!");
536
0
    return StringRef(Barrier.Data, Barrier.Length);
537
0
  }
538
539
863k
  unsigned getReg() const override {
540
863k
    assert(Kind == k_Register && "Invalid access!");
541
863k
    return Reg.RegNum;
542
863k
  }
543
544
7.38k
  RegConstraintEqualityTy getRegEqualityTy() const {
545
7.38k
    assert(Kind == k_Register && "Invalid access!");
546
7.38k
    return Reg.EqualityTy;
547
7.38k
  }
548
549
3.70k
  unsigned getVectorListStart() const {
550
3.70k
    assert(Kind == k_VectorList && "Invalid access!");
551
3.70k
    return VectorList.RegNum;
552
3.70k
  }
553
554
0
  unsigned getVectorListCount() const {
555
0
    assert(Kind == k_VectorList && "Invalid access!");
556
0
    return VectorList.Count;
557
0
  }
558
559
1.27k
  unsigned getVectorIndex() const {
560
1.27k
    assert(Kind == k_VectorIndex && "Invalid access!");
561
1.27k
    return VectorIndex.Val;
562
1.27k
  }
563
564
0
  StringRef getSysReg() const {
565
0
    assert(Kind == k_SysReg && "Invalid access!");
566
0
    return StringRef(SysReg.Data, SysReg.Length);
567
0
  }
568
569
616
  unsigned getSysCR() const {
570
616
    assert(Kind == k_SysCR && "Invalid access!");
571
616
    return SysCRImm.Val;
572
616
  }
573
574
522
  unsigned getPrefetch() const {
575
522
    assert(Kind == k_Prefetch && "Invalid access!");
576
522
    return Prefetch.Val;
577
522
  }
578
579
1
  unsigned getPSBHint() const {
580
1
    assert(Kind == k_PSBHint && "Invalid access!");
581
1
    return PSBHint.Val;
582
1
  }
583
584
0
  StringRef getPSBHintName() const {
585
0
    assert(Kind == k_PSBHint && "Invalid access!");
586
0
    return StringRef(PSBHint.Data, PSBHint.Length);
587
0
  }
588
589
6
  unsigned getBTIHint() const {
590
6
    assert(Kind == k_BTIHint && "Invalid access!");
591
6
    return BTIHint.Val;
592
6
  }
593
594
0
  StringRef getBTIHintName() const {
595
0
    assert(Kind == k_BTIHint && "Invalid access!");
596
0
    return StringRef(BTIHint.Data, BTIHint.Length);
597
0
  }
598
599
0
  StringRef getPrefetchName() const {
600
0
    assert(Kind == k_Prefetch && "Invalid access!");
601
0
    return StringRef(Prefetch.Data, Prefetch.Length);
602
0
  }
603
604
6.63k
  AArch64_AM::ShiftExtendType getShiftExtendType() const {
605
6.63k
    if (Kind == k_ShiftExtend)
606
3.79k
      return ShiftExtend.Type;
607
2.84k
    if (Kind == k_Register)
608
2.84k
      return Reg.ShiftExtend.Type;
609
0
    llvm_unreachable("Invalid access!");
610
0
  }
611
612
8.24k
  unsigned getShiftExtendAmount() const {
613
8.24k
    if (Kind == k_ShiftExtend)
614
3.06k
      return ShiftExtend.Amount;
615
5.17k
    if (Kind == k_Register)
616
5.17k
      return Reg.ShiftExtend.Amount;
617
0
    llvm_unreachable("Invalid access!");
618
0
  }
619
620
2.63k
  bool hasShiftExtendAmount() const {
621
2.63k
    if (Kind == k_ShiftExtend)
622
1.18k
      return ShiftExtend.HasExplicitAmount;
623
1.44k
    if (Kind == k_Register)
624
1.44k
      return Reg.ShiftExtend.HasExplicitAmount;
625
0
    llvm_unreachable("Invalid access!");
626
0
  }
627
628
40.4k
  bool isImm() const override { return Kind == k_Immediate; }
629
0
  bool isMem() const override { return false; }
630
631
17
  bool isUImm6() const {
632
17
    if (!isImm())
633
0
      return false;
634
17
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
635
17
    if (!MCE)
636
0
      return false;
637
17
    int64_t Val = MCE->getValue();
638
17
    return (Val >= 0 && 
Val < 6415
);
639
17
  }
640
641
3.47k
  template <int Width> bool isSImm() const { return isSImmScaled<Width, 1>(); }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isSImm<5>() const
Line
Count
Source
641
910
  template <int Width> bool isSImm() const { return isSImmScaled<Width, 1>(); }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isSImm<6>() const
Line
Count
Source
641
72
  template <int Width> bool isSImm() const { return isSImmScaled<Width, 1>(); }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isSImm<8>() const
Line
Count
Source
641
211
  template <int Width> bool isSImm() const { return isSImmScaled<Width, 1>(); }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isSImm<9>() const
Line
Count
Source
641
2.27k
  template <int Width> bool isSImm() const { return isSImmScaled<Width, 1>(); }
642
643
7.91k
  template <int Bits, int Scale> DiagnosticPredicate isSImmScaled() const {
644
7.91k
    return isImmScaled<Bits, Scale>(true);
645
7.91k
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSImmScaled<10, 8>() const
Line
Count
Source
643
76
  template <int Bits, int Scale> DiagnosticPredicate isSImmScaled() const {
644
76
    return isImmScaled<Bits, Scale>(true);
645
76
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSImmScaled<4, 16>() const
Line
Count
Source
643
164
  template <int Bits, int Scale> DiagnosticPredicate isSImmScaled() const {
644
164
    return isImmScaled<Bits, Scale>(true);
645
164
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSImmScaled<4, 1>() const
Line
Count
Source
643
1.41k
  template <int Bits, int Scale> DiagnosticPredicate isSImmScaled() const {
644
1.41k
    return isImmScaled<Bits, Scale>(true);
645
1.41k
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSImmScaled<4, 2>() const
Line
Count
Source
643
284
  template <int Bits, int Scale> DiagnosticPredicate isSImmScaled() const {
644
284
    return isImmScaled<Bits, Scale>(true);
645
284
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSImmScaled<4, 3>() const
Line
Count
Source
643
284
  template <int Bits, int Scale> DiagnosticPredicate isSImmScaled() const {
644
284
    return isImmScaled<Bits, Scale>(true);
645
284
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSImmScaled<4, 4>() const
Line
Count
Source
643
284
  template <int Bits, int Scale> DiagnosticPredicate isSImmScaled() const {
644
284
    return isImmScaled<Bits, Scale>(true);
645
284
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSImmScaled<5, 1>() const
Line
Count
Source
643
910
  template <int Bits, int Scale> DiagnosticPredicate isSImmScaled() const {
644
910
    return isImmScaled<Bits, Scale>(true);
645
910
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSImmScaled<6, 1>() const
Line
Count
Source
643
466
  template <int Bits, int Scale> DiagnosticPredicate isSImmScaled() const {
644
466
    return isImmScaled<Bits, Scale>(true);
645
466
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSImmScaled<7, 16>() const
Line
Count
Source
643
302
  template <int Bits, int Scale> DiagnosticPredicate isSImmScaled() const {
644
302
    return isImmScaled<Bits, Scale>(true);
645
302
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSImmScaled<7, 4>() const
Line
Count
Source
643
244
  template <int Bits, int Scale> DiagnosticPredicate isSImmScaled() const {
644
244
    return isImmScaled<Bits, Scale>(true);
645
244
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSImmScaled<7, 8>() const
Line
Count
Source
643
210
  template <int Bits, int Scale> DiagnosticPredicate isSImmScaled() const {
644
210
    return isImmScaled<Bits, Scale>(true);
645
210
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSImmScaled<8, 1>() const
Line
Count
Source
643
211
  template <int Bits, int Scale> DiagnosticPredicate isSImmScaled() const {
644
211
    return isImmScaled<Bits, Scale>(true);
645
211
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSImmScaled<9, 1>() const
Line
Count
Source
643
2.27k
  template <int Bits, int Scale> DiagnosticPredicate isSImmScaled() const {
644
2.27k
    return isImmScaled<Bits, Scale>(true);
645
2.27k
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSImmScaled<9, 16>() const
Line
Count
Source
643
789
  template <int Bits, int Scale> DiagnosticPredicate isSImmScaled() const {
644
789
    return isImmScaled<Bits, Scale>(true);
645
789
  }
646
647
721
  template <int Bits, int Scale> DiagnosticPredicate isUImmScaled() const {
648
721
    return isImmScaled<Bits, Scale>(false);
649
721
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isUImmScaled<5, 2>() const
Line
Count
Source
647
208
  template <int Bits, int Scale> DiagnosticPredicate isUImmScaled() const {
648
208
    return isImmScaled<Bits, Scale>(false);
649
208
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isUImmScaled<5, 4>() const
Line
Count
Source
647
174
  template <int Bits, int Scale> DiagnosticPredicate isUImmScaled() const {
648
174
    return isImmScaled<Bits, Scale>(false);
649
174
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isUImmScaled<5, 8>() const
Line
Count
Source
647
81
  template <int Bits, int Scale> DiagnosticPredicate isUImmScaled() const {
648
81
    return isImmScaled<Bits, Scale>(false);
649
81
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isUImmScaled<6, 16>() const
Line
Count
Source
647
82
  template <int Bits, int Scale> DiagnosticPredicate isUImmScaled() const {
648
82
    return isImmScaled<Bits, Scale>(false);
649
82
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isUImmScaled<6, 1>() const
Line
Count
Source
647
61
  template <int Bits, int Scale> DiagnosticPredicate isUImmScaled() const {
648
61
    return isImmScaled<Bits, Scale>(false);
649
61
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isUImmScaled<6, 2>() const
Line
Count
Source
647
55
  template <int Bits, int Scale> DiagnosticPredicate isUImmScaled() const {
648
55
    return isImmScaled<Bits, Scale>(false);
649
55
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isUImmScaled<6, 4>() const
Line
Count
Source
647
41
  template <int Bits, int Scale> DiagnosticPredicate isUImmScaled() const {
648
41
    return isImmScaled<Bits, Scale>(false);
649
41
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isUImmScaled<6, 8>() const
Line
Count
Source
647
19
  template <int Bits, int Scale> DiagnosticPredicate isUImmScaled() const {
648
19
    return isImmScaled<Bits, Scale>(false);
649
19
  }
650
651
  template <int Bits, int Scale>
652
8.63k
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
8.63k
    if (!isImm())
654
2.83k
      return DiagnosticPredicateTy::NoMatch;
655
5.79k
656
5.79k
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
5.79k
    if (!MCE)
658
582
      return DiagnosticPredicateTy::NoMatch;
659
5.21k
660
5.21k
    int64_t MinVal, MaxVal;
661
5.21k
    if (Signed) {
662
4.56k
      int64_t Shift = Bits - 1;
663
4.56k
      MinVal = (int64_t(1) << Shift) * -Scale;
664
4.56k
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
4.56k
    } else {
666
653
      MinVal = 0;
667
653
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
653
    }
669
5.21k
670
5.21k
    int64_t Val = MCE->getValue();
671
5.21k
    if (Val >= MinVal && 
Val <= MaxVal4.57k
&&
(Val % Scale) == 03.86k
)
672
3.55k
      return DiagnosticPredicateTy::Match;
673
1.65k
674
1.65k
    return DiagnosticPredicateTy::NearMatch;
675
1.65k
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isImmScaled<10, 8>(bool) const
Line
Count
Source
652
76
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
76
    if (!isImm())
654
8
      return DiagnosticPredicateTy::NoMatch;
655
68
656
68
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
68
    if (!MCE)
658
0
      return DiagnosticPredicateTy::NoMatch;
659
68
660
68
    int64_t MinVal, MaxVal;
661
68
    if (Signed) {
662
68
      int64_t Shift = Bits - 1;
663
68
      MinVal = (int64_t(1) << Shift) * -Scale;
664
68
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
68
    } else {
666
0
      MinVal = 0;
667
0
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
0
    }
669
68
670
68
    int64_t Val = MCE->getValue();
671
68
    if (Val >= MinVal && 
Val <= MaxVal60
&&
(Val % Scale) == 052
)
672
44
      return DiagnosticPredicateTy::Match;
673
24
674
24
    return DiagnosticPredicateTy::NearMatch;
675
24
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isImmScaled<4, 16>(bool) const
Line
Count
Source
652
164
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
164
    if (!isImm())
654
48
      return DiagnosticPredicateTy::NoMatch;
655
116
656
116
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
116
    if (!MCE)
658
0
      return DiagnosticPredicateTy::NoMatch;
659
116
660
116
    int64_t MinVal, MaxVal;
661
116
    if (Signed) {
662
116
      int64_t Shift = Bits - 1;
663
116
      MinVal = (int64_t(1) << Shift) * -Scale;
664
116
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
116
    } else {
666
0
      MinVal = 0;
667
0
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
0
    }
669
116
670
116
    int64_t Val = MCE->getValue();
671
116
    if (Val >= MinVal && 
Val <= MaxVal100
&&
(Val % Scale) == 084
)
672
76
      return DiagnosticPredicateTy::Match;
673
40
674
40
    return DiagnosticPredicateTy::NearMatch;
675
40
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isImmScaled<4, 1>(bool) const
Line
Count
Source
652
1.41k
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
1.41k
    if (!isImm())
654
698
      return DiagnosticPredicateTy::NoMatch;
655
714
656
714
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
714
    if (!MCE)
658
0
      return DiagnosticPredicateTy::NoMatch;
659
714
660
714
    int64_t MinVal, MaxVal;
661
714
    if (Signed) {
662
714
      int64_t Shift = Bits - 1;
663
714
      MinVal = (int64_t(1) << Shift) * -Scale;
664
714
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
714
    } else {
666
0
      MinVal = 0;
667
0
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
0
    }
669
714
670
714
    int64_t Val = MCE->getValue();
671
714
    if (Val >= MinVal && 
Val <= MaxVal614
&&
(Val % Scale) == 0514
)
672
514
      return DiagnosticPredicateTy::Match;
673
200
674
200
    return DiagnosticPredicateTy::NearMatch;
675
200
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isImmScaled<4, 2>(bool) const
Line
Count
Source
652
284
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
284
    if (!isImm())
654
124
      return DiagnosticPredicateTy::NoMatch;
655
160
656
160
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
160
    if (!MCE)
658
0
      return DiagnosticPredicateTy::NoMatch;
659
160
660
160
    int64_t MinVal, MaxVal;
661
160
    if (Signed) {
662
160
      int64_t Shift = Bits - 1;
663
160
      MinVal = (int64_t(1) << Shift) * -Scale;
664
160
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
160
    } else {
666
0
      MinVal = 0;
667
0
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
0
    }
669
160
670
160
    int64_t Val = MCE->getValue();
671
160
    if (Val >= MinVal && 
Val <= MaxVal144
&&
(Val % Scale) == 0128
)
672
96
      return DiagnosticPredicateTy::Match;
673
64
674
64
    return DiagnosticPredicateTy::NearMatch;
675
64
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isImmScaled<4, 3>(bool) const
Line
Count
Source
652
284
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
284
    if (!isImm())
654
124
      return DiagnosticPredicateTy::NoMatch;
655
160
656
160
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
160
    if (!MCE)
658
0
      return DiagnosticPredicateTy::NoMatch;
659
160
660
160
    int64_t MinVal, MaxVal;
661
160
    if (Signed) {
662
160
      int64_t Shift = Bits - 1;
663
160
      MinVal = (int64_t(1) << Shift) * -Scale;
664
160
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
160
    } else {
666
0
      MinVal = 0;
667
0
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
0
    }
669
160
670
160
    int64_t Val = MCE->getValue();
671
160
    if (Val >= MinVal && 
Val <= MaxVal144
&&
(Val % Scale) == 0128
)
672
96
      return DiagnosticPredicateTy::Match;
673
64
674
64
    return DiagnosticPredicateTy::NearMatch;
675
64
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isImmScaled<4, 4>(bool) const
Line
Count
Source
652
284
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
284
    if (!isImm())
654
124
      return DiagnosticPredicateTy::NoMatch;
655
160
656
160
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
160
    if (!MCE)
658
0
      return DiagnosticPredicateTy::NoMatch;
659
160
660
160
    int64_t MinVal, MaxVal;
661
160
    if (Signed) {
662
160
      int64_t Shift = Bits - 1;
663
160
      MinVal = (int64_t(1) << Shift) * -Scale;
664
160
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
160
    } else {
666
0
      MinVal = 0;
667
0
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
0
    }
669
160
670
160
    int64_t Val = MCE->getValue();
671
160
    if (Val >= MinVal && 
Val <= MaxVal144
&&
(Val % Scale) == 0128
)
672
96
      return DiagnosticPredicateTy::Match;
673
64
674
64
    return DiagnosticPredicateTy::NearMatch;
675
64
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isImmScaled<5, 1>(bool) const
Line
Count
Source
652
910
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
910
    if (!isImm())
654
382
      return DiagnosticPredicateTy::NoMatch;
655
528
656
528
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
528
    if (!MCE)
658
0
      return DiagnosticPredicateTy::NoMatch;
659
528
660
528
    int64_t MinVal, MaxVal;
661
528
    if (Signed) {
662
528
      int64_t Shift = Bits - 1;
663
528
      MinVal = (int64_t(1) << Shift) * -Scale;
664
528
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
528
    } else {
666
0
      MinVal = 0;
667
0
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
0
    }
669
528
670
528
    int64_t Val = MCE->getValue();
671
528
    if (Val >= MinVal && 
Val <= MaxVal504
&&
(Val % Scale) == 0480
)
672
480
      return DiagnosticPredicateTy::Match;
673
48
674
48
    return DiagnosticPredicateTy::NearMatch;
675
48
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isImmScaled<6, 1>(bool) const
Line
Count
Source
652
527
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
527
    if (!isImm())
654
358
      return DiagnosticPredicateTy::NoMatch;
655
169
656
169
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
169
    if (!MCE)
658
0
      return DiagnosticPredicateTy::NoMatch;
659
169
660
169
    int64_t MinVal, MaxVal;
661
169
    if (Signed) {
662
122
      int64_t Shift = Bits - 1;
663
122
      MinVal = (int64_t(1) << Shift) * -Scale;
664
122
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
122
    } else {
666
47
      MinVal = 0;
667
47
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
47
    }
669
169
670
169
    int64_t Val = MCE->getValue();
671
169
    if (Val >= MinVal && 
Val <= MaxVal157
&&
(Val % Scale) == 0139
)
672
139
      return DiagnosticPredicateTy::Match;
673
30
674
30
    return DiagnosticPredicateTy::NearMatch;
675
30
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isImmScaled<7, 16>(bool) const
Line
Count
Source
652
302
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
302
    if (!isImm())
654
90
      return DiagnosticPredicateTy::NoMatch;
655
212
656
212
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
212
    if (!MCE)
658
0
      return DiagnosticPredicateTy::NoMatch;
659
212
660
212
    int64_t MinVal, MaxVal;
661
212
    if (Signed) {
662
212
      int64_t Shift = Bits - 1;
663
212
      MinVal = (int64_t(1) << Shift) * -Scale;
664
212
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
212
    } else {
666
0
      MinVal = 0;
667
0
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
0
    }
669
212
670
212
    int64_t Val = MCE->getValue();
671
212
    if (Val >= MinVal && 
Val <= MaxVal190
&&
(Val % Scale) == 0168
)
672
140
      return DiagnosticPredicateTy::Match;
673
72
674
72
    return DiagnosticPredicateTy::NearMatch;
675
72
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isImmScaled<7, 4>(bool) const
Line
Count
Source
652
244
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
244
    if (!isImm())
654
44
      return DiagnosticPredicateTy::NoMatch;
655
200
656
200
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
200
    if (!MCE)
658
0
      return DiagnosticPredicateTy::NoMatch;
659
200
660
200
    int64_t MinVal, MaxVal;
661
200
    if (Signed) {
662
200
      int64_t Shift = Bits - 1;
663
200
      MinVal = (int64_t(1) << Shift) * -Scale;
664
200
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
200
    } else {
666
0
      MinVal = 0;
667
0
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
0
    }
669
200
670
200
    int64_t Val = MCE->getValue();
671
200
    if (Val >= MinVal && 
Val <= MaxVal166
&&
(Val % Scale) == 0120
)
672
80
      return DiagnosticPredicateTy::Match;
673
120
674
120
    return DiagnosticPredicateTy::NearMatch;
675
120
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isImmScaled<7, 8>(bool) const
Line
Count
Source
652
210
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
210
    if (!isImm())
654
24
      return DiagnosticPredicateTy::NoMatch;
655
186
656
186
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
186
    if (!MCE)
658
0
      return DiagnosticPredicateTy::NoMatch;
659
186
660
186
    int64_t MinVal, MaxVal;
661
186
    if (Signed) {
662
186
      int64_t Shift = Bits - 1;
663
186
      MinVal = (int64_t(1) << Shift) * -Scale;
664
186
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
186
    } else {
666
0
      MinVal = 0;
667
0
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
0
    }
669
186
670
186
    int64_t Val = MCE->getValue();
671
186
    if (Val >= MinVal && 
Val <= MaxVal162
&&
(Val % Scale) == 0138
)
672
120
      return DiagnosticPredicateTy::Match;
673
66
674
66
    return DiagnosticPredicateTy::NearMatch;
675
66
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isImmScaled<8, 1>(bool) const
Line
Count
Source
652
211
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
211
    if (!isImm())
654
59
      return DiagnosticPredicateTy::NoMatch;
655
152
656
152
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
152
    if (!MCE)
658
0
      return DiagnosticPredicateTy::NoMatch;
659
152
660
152
    int64_t MinVal, MaxVal;
661
152
    if (Signed) {
662
152
      int64_t Shift = Bits - 1;
663
152
      MinVal = (int64_t(1) << Shift) * -Scale;
664
152
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
152
    } else {
666
0
      MinVal = 0;
667
0
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
0
    }
669
152
670
152
    int64_t Val = MCE->getValue();
671
152
    if (Val >= MinVal && 
Val <= MaxVal146
&&
(Val % Scale) == 0140
)
672
140
      return DiagnosticPredicateTy::Match;
673
12
674
12
    return DiagnosticPredicateTy::NearMatch;
675
12
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isImmScaled<9, 1>(bool) const
Line
Count
Source
652
2.27k
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
2.27k
    if (!isImm())
654
434
      return DiagnosticPredicateTy::NoMatch;
655
1.84k
656
1.84k
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
1.84k
    if (!MCE)
658
582
      return DiagnosticPredicateTy::NoMatch;
659
1.26k
660
1.26k
    int64_t MinVal, MaxVal;
661
1.26k
    if (Signed) {
662
1.26k
      int64_t Shift = Bits - 1;
663
1.26k
      MinVal = (int64_t(1) << Shift) * -Scale;
664
1.26k
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
1.26k
    } else {
666
0
      MinVal = 0;
667
0
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
0
    }
669
1.26k
670
1.26k
    int64_t Val = MCE->getValue();
671
1.26k
    if (Val >= MinVal && 
Val <= MaxVal1.07k
&&
(Val % Scale) == 0846
)
672
846
      return DiagnosticPredicateTy::Match;
673
415
674
415
    return DiagnosticPredicateTy::NearMatch;
675
415
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isImmScaled<5, 2>(bool) const
Line
Count
Source
652
208
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
208
    if (!isImm())
654
16
      return DiagnosticPredicateTy::NoMatch;
655
192
656
192
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
192
    if (!MCE)
658
0
      return DiagnosticPredicateTy::NoMatch;
659
192
660
192
    int64_t MinVal, MaxVal;
661
192
    if (Signed) {
662
0
      int64_t Shift = Bits - 1;
663
0
      MinVal = (int64_t(1) << Shift) * -Scale;
664
0
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
192
    } else {
666
192
      MinVal = 0;
667
192
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
192
    }
669
192
670
192
    int64_t Val = MCE->getValue();
671
192
    if (Val >= MinVal && 
Val <= MaxVal144
&&
(Val % Scale) == 096
)
672
72
      return DiagnosticPredicateTy::Match;
673
120
674
120
    return DiagnosticPredicateTy::NearMatch;
675
120
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isImmScaled<5, 4>(bool) const
Line
Count
Source
652
174
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
174
    if (!isImm())
654
12
      return DiagnosticPredicateTy::NoMatch;
655
162
656
162
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
162
    if (!MCE)
658
0
      return DiagnosticPredicateTy::NoMatch;
659
162
660
162
    int64_t MinVal, MaxVal;
661
162
    if (Signed) {
662
0
      int64_t Shift = Bits - 1;
663
0
      MinVal = (int64_t(1) << Shift) * -Scale;
664
0
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
162
    } else {
666
162
      MinVal = 0;
667
162
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
162
    }
669
162
670
162
    int64_t Val = MCE->getValue();
671
162
    if (Val >= MinVal && 
Val <= MaxVal122
&&
(Val % Scale) == 082
)
672
62
      return DiagnosticPredicateTy::Match;
673
100
674
100
    return DiagnosticPredicateTy::NearMatch;
675
100
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isImmScaled<5, 8>(bool) const
Line
Count
Source
652
81
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
81
    if (!isImm())
654
4
      return DiagnosticPredicateTy::NoMatch;
655
77
656
77
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
77
    if (!MCE)
658
0
      return DiagnosticPredicateTy::NoMatch;
659
77
660
77
    int64_t MinVal, MaxVal;
661
77
    if (Signed) {
662
0
      int64_t Shift = Bits - 1;
663
0
      MinVal = (int64_t(1) << Shift) * -Scale;
664
0
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
77
    } else {
666
77
      MinVal = 0;
667
77
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
77
    }
669
77
670
77
    int64_t Val = MCE->getValue();
671
77
    if (Val >= MinVal && 
Val <= MaxVal61
&&
(Val % Scale) == 045
)
672
37
      return DiagnosticPredicateTy::Match;
673
40
674
40
    return DiagnosticPredicateTy::NearMatch;
675
40
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isImmScaled<6, 16>(bool) const
Line
Count
Source
652
82
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
82
    if (!isImm())
654
4
      return DiagnosticPredicateTy::NoMatch;
655
78
656
78
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
78
    if (!MCE)
658
0
      return DiagnosticPredicateTy::NoMatch;
659
78
660
78
    int64_t MinVal, MaxVal;
661
78
    if (Signed) {
662
0
      int64_t Shift = Bits - 1;
663
0
      MinVal = (int64_t(1) << Shift) * -Scale;
664
0
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
78
    } else {
666
78
      MinVal = 0;
667
78
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
78
    }
669
78
670
78
    int64_t Val = MCE->getValue();
671
78
    if (Val >= MinVal && 
Val <= MaxVal74
&&
(Val % Scale) == 070
)
672
66
      return DiagnosticPredicateTy::Match;
673
12
674
12
    return DiagnosticPredicateTy::NearMatch;
675
12
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isImmScaled<6, 2>(bool) const
Line
Count
Source
652
55
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
55
    if (!isImm())
654
10
      return DiagnosticPredicateTy::NoMatch;
655
45
656
45
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
45
    if (!MCE)
658
0
      return DiagnosticPredicateTy::NoMatch;
659
45
660
45
    int64_t MinVal, MaxVal;
661
45
    if (Signed) {
662
0
      int64_t Shift = Bits - 1;
663
0
      MinVal = (int64_t(1) << Shift) * -Scale;
664
0
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
45
    } else {
666
45
      MinVal = 0;
667
45
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
45
    }
669
45
670
45
    int64_t Val = MCE->getValue();
671
45
    if (Val >= MinVal && 
Val <= MaxVal39
&&
(Val % Scale) == 033
)
672
29
      return DiagnosticPredicateTy::Match;
673
16
674
16
    return DiagnosticPredicateTy::NearMatch;
675
16
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isImmScaled<6, 4>(bool) const
Line
Count
Source
652
41
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
41
    if (!isImm())
654
6
      return DiagnosticPredicateTy::NoMatch;
655
35
656
35
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
35
    if (!MCE)
658
0
      return DiagnosticPredicateTy::NoMatch;
659
35
660
35
    int64_t MinVal, MaxVal;
661
35
    if (Signed) {
662
0
      int64_t Shift = Bits - 1;
663
0
      MinVal = (int64_t(1) << Shift) * -Scale;
664
0
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
35
    } else {
666
35
      MinVal = 0;
667
35
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
35
    }
669
35
670
35
    int64_t Val = MCE->getValue();
671
35
    if (Val >= MinVal && 
Val <= MaxVal29
&&
(Val % Scale) == 023
)
672
19
      return DiagnosticPredicateTy::Match;
673
16
674
16
    return DiagnosticPredicateTy::NearMatch;
675
16
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isImmScaled<6, 8>(bool) const
Line
Count
Source
652
19
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
19
    if (!isImm())
654
2
      return DiagnosticPredicateTy::NoMatch;
655
17
656
17
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
17
    if (!MCE)
658
0
      return DiagnosticPredicateTy::NoMatch;
659
17
660
17
    int64_t MinVal, MaxVal;
661
17
    if (Signed) {
662
0
      int64_t Shift = Bits - 1;
663
0
      MinVal = (int64_t(1) << Shift) * -Scale;
664
0
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
17
    } else {
666
17
      MinVal = 0;
667
17
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
17
    }
669
17
670
17
    int64_t Val = MCE->getValue();
671
17
    if (Val >= MinVal && 
Val <= MaxVal13
&&
(Val % Scale) == 09
)
672
7
      return DiagnosticPredicateTy::Match;
673
10
674
10
    return DiagnosticPredicateTy::NearMatch;
675
10
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isImmScaled<9, 16>(bool) const
Line
Count
Source
652
789
  DiagnosticPredicate isImmScaled(bool Signed) const {
653
789
    if (!isImm())
654
266
      return DiagnosticPredicateTy::NoMatch;
655
523
656
523
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
657
523
    if (!MCE)
658
0
      return DiagnosticPredicateTy::NoMatch;
659
523
660
523
    int64_t MinVal, MaxVal;
661
523
    if (Signed) {
662
523
      int64_t Shift = Bits - 1;
663
523
      MinVal = (int64_t(1) << Shift) * -Scale;
664
523
      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
665
523
    } else {
666
0
      MinVal = 0;
667
0
      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
668
0
    }
669
523
670
523
    int64_t Val = MCE->getValue();
671
523
    if (Val >= MinVal && 
Val <= MaxVal481
&&
(Val % Scale) == 0439
)
672
399
      return DiagnosticPredicateTy::Match;
673
124
674
124
    return DiagnosticPredicateTy::NearMatch;
675
124
  }
676
677
8.32k
  DiagnosticPredicate isSVEPattern() const {
678
8.32k
    if (!isImm())
679
512
      return DiagnosticPredicateTy::NoMatch;
680
7.80k
    auto *MCE = dyn_cast<MCConstantExpr>(getImm());
681
7.80k
    if (!MCE)
682
216
      return DiagnosticPredicateTy::NoMatch;
683
7.59k
    int64_t Val = MCE->getValue();
684
7.59k
    if (Val >= 0 && 
Val < 327.47k
)
685
7.36k
      return DiagnosticPredicateTy::Match;
686
232
    return DiagnosticPredicateTy::NearMatch;
687
232
  }
688
689
582
  bool isSymbolicUImm12Offset(const MCExpr *Expr) const {
690
582
    AArch64MCExpr::VariantKind ELFRefKind;
691
582
    MCSymbolRefExpr::VariantKind DarwinRefKind;
692
582
    int64_t Addend;
693
582
    if (!AArch64AsmParser::classifySymbolRef(Expr, ELFRefKind, DarwinRefKind,
694
582
                                           Addend)) {
695
19
      // If we don't understand the expression, assume the best and
696
19
      // let the fixup and relocation code deal with it.
697
19
      return true;
698
19
    }
699
563
700
563
    if (DarwinRefKind == MCSymbolRefExpr::VK_PAGEOFF ||
701
563
        
ELFRefKind == AArch64MCExpr::VK_LO12557
||
702
563
        
ELFRefKind == AArch64MCExpr::VK_GOT_LO12391
||
703
563
        
ELFRefKind == AArch64MCExpr::VK_DTPREL_LO12319
||
704
563
        
ELFRefKind == AArch64MCExpr::VK_DTPREL_LO12_NC259
||
705
563
        
ELFRefKind == AArch64MCExpr::VK_TPREL_LO12190
||
706
563
        
ELFRefKind == AArch64MCExpr::VK_TPREL_LO12_NC130
||
707
563
        
ELFRefKind == AArch64MCExpr::VK_GOTTPREL_LO12_NC59
||
708
563
        
ELFRefKind == AArch64MCExpr::VK_TLSDESC_LO1228
||
709
563
        
ELFRefKind == AArch64MCExpr::VK_SECREL_LO126
||
710
563
        
ELFRefKind == AArch64MCExpr::VK_SECREL_HI125
) {
711
558
      // Note that we don't range-check the addend. It's adjusted modulo page
712
558
      // size when converted, so there is no "out of range" condition when using
713
558
      // @pageoff.
714
558
      return true;
715
558
    } else 
if (5
DarwinRefKind == MCSymbolRefExpr::VK_GOTPAGEOFF5
||
716
5
               
DarwinRefKind == MCSymbolRefExpr::VK_TLVPPAGEOFF2
) {
717
5
      // @gotpageoff/@tlvppageoff can only be used directly, not with an addend.
718
5
      return Addend == 0;
719
5
    }
720
0
721
0
    return false;
722
0
  }
723
724
1.31k
  template <int Scale> bool isUImm12Offset() const {
725
1.31k
    if (!isImm())
726
201
      return false;
727
1.11k
728
1.11k
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
729
1.11k
    if (!MCE)
730
582
      return isSymbolicUImm12Offset(getImm());
731
528
732
528
    int64_t Val = MCE->getValue();
733
528
    return (Val % Scale) == 0 && 
Val >= 0395
&&
(Val / Scale) < 0x1000303
;
734
528
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isUImm12Offset<16>() const
Line
Count
Source
724
105
  template <int Scale> bool isUImm12Offset() const {
725
105
    if (!isImm())
726
27
      return false;
727
78
728
78
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
729
78
    if (!MCE)
730
50
      return isSymbolicUImm12Offset(getImm());
731
28
732
28
    int64_t Val = MCE->getValue();
733
28
    return (Val % Scale) == 0 && 
Val >= 017
&&
(Val / Scale) < 0x10009
;
734
28
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isUImm12Offset<1>() const
Line
Count
Source
724
243
  template <int Scale> bool isUImm12Offset() const {
725
243
    if (!isImm())
726
38
      return false;
727
205
728
205
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
729
205
    if (!MCE)
730
116
      return isSymbolicUImm12Offset(getImm());
731
89
732
89
    int64_t Val = MCE->getValue();
733
89
    return (Val % Scale) == 0 && Val >= 0 && 
(Val / Scale) < 0x100057
;
734
89
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isUImm12Offset<2>() const
Line
Count
Source
724
251
  template <int Scale> bool isUImm12Offset() const {
725
251
    if (!isImm())
726
42
      return false;
727
209
728
209
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
729
209
    if (!MCE)
730
108
      return isSymbolicUImm12Offset(getImm());
731
101
732
101
    int64_t Val = MCE->getValue();
733
101
    return (Val % Scale) == 0 && 
Val >= 053
&&
(Val / Scale) < 0x100037
;
734
101
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isUImm12Offset<4>() const
Line
Count
Source
724
270
  template <int Scale> bool isUImm12Offset() const {
725
270
    if (!isImm())
726
53
      return false;
727
217
728
217
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
729
217
    if (!MCE)
730
109
      return isSymbolicUImm12Offset(getImm());
731
108
732
108
    int64_t Val = MCE->getValue();
733
108
    return (Val % Scale) == 0 && 
Val >= 069
&&
(Val / Scale) < 0x100053
;
734
108
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isUImm12Offset<8>() const
Line
Count
Source
724
442
  template <int Scale> bool isUImm12Offset() const {
725
442
    if (!isImm())
726
41
      return false;
727
401
728
401
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
729
401
    if (!MCE)
730
199
      return isSymbolicUImm12Offset(getImm());
731
202
732
202
    int64_t Val = MCE->getValue();
733
202
    return (Val % Scale) == 0 && 
Val >= 0167
&&
(Val / Scale) < 0x1000147
;
734
202
  }
735
736
  template <int N, int M>
737
7.13k
  bool isImmInRange() const {
738
7.13k
    if (!isImm())
739
519
      return false;
740
6.62k
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
741
6.62k
    if (!MCE)
742
36
      return false;
743
6.58k
    int64_t Val = MCE->getValue();
744
6.58k
    return (Val >= N && 
Val <= M6.04k
);
745
6.58k
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isImmInRange<0, 127>() const
Line
Count
Source
737
382
  bool isImmInRange() const {
738
382
    if (!isImm())
739
180
      return false;
740
202
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
741
202
    if (!MCE)
742
0
      return false;
743
202
    int64_t Val = MCE->getValue();
744
202
    return (Val >= N && 
Val <= M192
);
745
202
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isImmInRange<0, 15>() const
Line
Count
Source
737
421
  bool isImmInRange() const {
738
421
    if (!isImm())
739
37
      return false;
740
384
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
741
384
    if (!MCE)
742
0
      return false;
743
384
    int64_t Val = MCE->getValue();
744
384
    return (Val >= N && 
Val <= M335
);
745
384
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isImmInRange<0, 1>() const
Line
Count
Source
737
25
  bool isImmInRange() const {
738
25
    if (!isImm())
739
2
      return false;
740
23
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
741
23
    if (!MCE)
742
0
      return false;
743
23
    int64_t Val = MCE->getValue();
744
23
    return (Val >= N && 
Val <= M19
);
745
23
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isImmInRange<0, 255>() const
Line
Count
Source
737
476
  bool isImmInRange() const {
738
476
    if (!isImm())
739
3
      return false;
740
473
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
741
473
    if (!MCE)
742
0
      return false;
743
473
    int64_t Val = MCE->getValue();
744
473
    return (Val >= N && 
Val <= M456
);
745
473
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isImmInRange<0, 31>() const
Line
Count
Source
737
631
  bool isImmInRange() const {
738
631
    if (!isImm())
739
81
      return false;
740
550
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
741
550
    if (!MCE)
742
0
      return false;
743
550
    int64_t Val = MCE->getValue();
744
550
    return (Val >= N && 
Val <= M488
);
745
550
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isImmInRange<0, 63>() const
Line
Count
Source
737
354
  bool isImmInRange() const {
738
354
    if (!isImm())
739
37
      return false;
740
317
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
741
317
    if (!MCE)
742
0
      return false;
743
317
    int64_t Val = MCE->getValue();
744
317
    return (Val >= N && 
Val <= M297
);
745
317
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isImmInRange<0, 7>() const
Line
Count
Source
737
1.35k
  bool isImmInRange() const {
738
1.35k
    if (!isImm())
739
43
      return false;
740
1.31k
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
741
1.31k
    if (!MCE)
742
0
      return false;
743
1.31k
    int64_t Val = MCE->getValue();
744
1.31k
    return (Val >= N && 
Val <= M1.29k
);
745
1.31k
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isImmInRange<1, 16>() const
Line
Count
Source
737
1.57k
  bool isImmInRange() const {
738
1.57k
    if (!isImm())
739
30
      return false;
740
1.54k
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
741
1.54k
    if (!MCE)
742
0
      return false;
743
1.54k
    int64_t Val = MCE->getValue();
744
1.54k
    return (Val >= N && 
Val <= M1.37k
);
745
1.54k
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isImmInRange<1, 32>() const
Line
Count
Source
737
704
  bool isImmInRange() const {
738
704
    if (!isImm())
739
58
      return false;
740
646
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
741
646
    if (!MCE)
742
0
      return false;
743
646
    int64_t Val = MCE->getValue();
744
646
    return (Val >= N && 
Val <= M580
);
745
646
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isImmInRange<1, 64>() const
Line
Count
Source
737
426
  bool isImmInRange() const {
738
426
    if (!isImm())
739
10
      return false;
740
416
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
741
416
    if (!MCE)
742
0
      return false;
743
416
    int64_t Val = MCE->getValue();
744
416
    return (Val >= N && 
Val <= M384
);
745
416
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isImmInRange<1, 8>() const
Line
Count
Source
737
580
  bool isImmInRange() const {
738
580
    if (!isImm())
739
38
      return false;
740
542
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
741
542
    if (!MCE)
742
0
      return false;
743
542
    int64_t Val = MCE->getValue();
744
542
    return (Val >= N && 
Val <= M484
);
745
542
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isImmInRange<32, 63>() const
Line
Count
Source
737
24
  bool isImmInRange() const {
738
24
    if (!isImm())
739
0
      return false;
740
24
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
741
24
    if (!MCE)
742
0
      return false;
743
24
    int64_t Val = MCE->getValue();
744
24
    return (Val >= N && 
Val <= M11
);
745
24
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isImmInRange<0, 65535>() const
Line
Count
Source
737
187
  bool isImmInRange() const {
738
187
    if (!isImm())
739
0
      return false;
740
187
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
741
187
    if (!MCE)
742
36
      return false;
743
151
    int64_t Val = MCE->getValue();
744
151
    return (Val >= N && 
Val <= M137
);
745
151
  }
746
747
  // NOTE: Also used for isLogicalImmNot as anything that can be represented as
748
  // a logical immediate can always be represented when inverted.
749
  template <typename T>
750
1.27k
  bool isLogicalImm() const {
751
1.27k
    if (!isImm())
752
618
      return false;
753
661
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
754
661
    if (!MCE)
755
2
      return false;
756
659
757
659
    int64_t Val = MCE->getValue();
758
659
    int64_t SVal = typename std::make_signed<T>::type(Val);
759
659
    int64_t UVal = typename std::make_unsigned<T>::type(Val);
760
659
    if (Val != SVal && 
Val != UVal245
)
761
58
      return false;
762
601
763
601
    return AArch64_AM::isLogicalImmediate(UVal, sizeof(T) * 8);
764
601
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isLogicalImm<int>() const
Line
Count
Source
750
402
  bool isLogicalImm() const {
751
402
    if (!isImm())
752
201
      return false;
753
201
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
754
201
    if (!MCE)
755
0
      return false;
756
201
757
201
    int64_t Val = MCE->getValue();
758
201
    int64_t SVal = typename std::make_signed<T>::type(Val);
759
201
    int64_t UVal = typename std::make_unsigned<T>::type(Val);
760
201
    if (Val != SVal && 
Val != UVal100
)
761
24
      return false;
762
177
763
177
    return AArch64_AM::isLogicalImmediate(UVal, sizeof(T) * 8);
764
177
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isLogicalImm<long long>() const
Line
Count
Source
750
529
  bool isLogicalImm() const {
751
529
    if (!isImm())
752
282
      return false;
753
247
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
754
247
    if (!MCE)
755
2
      return false;
756
245
757
245
    int64_t Val = MCE->getValue();
758
245
    int64_t SVal = typename std::make_signed<T>::type(Val);
759
245
    int64_t UVal = typename std::make_unsigned<T>::type(Val);
760
245
    if (Val != SVal && 
Val != UVal0
)
761
0
      return false;
762
245
763
245
    return AArch64_AM::isLogicalImmediate(UVal, sizeof(T) * 8);
764
245
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isLogicalImm<signed char>() const
Line
Count
Source
750
103
  bool isLogicalImm() const {
751
103
    if (!isImm())
752
10
      return false;
753
93
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
754
93
    if (!MCE)
755
0
      return false;
756
93
757
93
    int64_t Val = MCE->getValue();
758
93
    int64_t SVal = typename std::make_signed<T>::type(Val);
759
93
    int64_t UVal = typename std::make_unsigned<T>::type(Val);
760
93
    if (Val != SVal && 
Val != UVal63
)
761
14
      return false;
762
79
763
79
    return AArch64_AM::isLogicalImmediate(UVal, sizeof(T) * 8);
764
79
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isLogicalImm<short>() const
Line
Count
Source
750
245
  bool isLogicalImm() const {
751
245
    if (!isImm())
752
125
      return false;
753
120
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
754
120
    if (!MCE)
755
0
      return false;
756
120
757
120
    int64_t Val = MCE->getValue();
758
120
    int64_t SVal = typename std::make_signed<T>::type(Val);
759
120
    int64_t UVal = typename std::make_unsigned<T>::type(Val);
760
120
    if (Val != SVal && 
Val != UVal82
)
761
20
      return false;
762
100
763
100
    return AArch64_AM::isLogicalImmediate(UVal, sizeof(T) * 8);
764
100
  }
765
766
9.29k
  bool isShiftedImm() const { return Kind == k_ShiftedImm; }
767
768
  /// Returns the immediate value as a pair of (imm, shift) if the immediate is
769
  /// a shifted immediate by value 'Shift' or '0', or if it is an unshifted
770
  /// immediate that can be shifted by 'Shift'.
771
  template <unsigned Width>
772
3.71k
  Optional<std::pair<int64_t, unsigned> > getShiftedVal() const {
773
3.71k
    if (isShiftedImm() && 
Width == getShiftedImmShift()970
)
774
966
      if (auto *CE = dyn_cast<MCConstantExpr>(getShiftedImmVal()))
775
924
        return std::make_pair(CE->getValue(), Width);
776
2.79k
777
2.79k
    if (isImm())
778
2.74k
      if (auto *CE = dyn_cast<MCConstantExpr>(getImm())) {
779
2.09k
        int64_t Val = CE->getValue();
780
2.09k
        if ((Val != 0) && 
(uint64_t(Val >> Width) << Width) == uint64_t(Val)1.80k
)
781
627
          return std::make_pair(Val >> Width, Width);
782
1.46k
        else
783
1.46k
          return std::make_pair(Val, 0u);
784
700
      }
785
700
786
700
    return {};
787
700
  }
AArch64AsmParser.cpp:llvm::Optional<std::__1::pair<long long, unsigned int> > (anonymous namespace)::AArch64Operand::getShiftedVal<12u>() const
Line
Count
Source
772
1.57k
  Optional<std::pair<int64_t, unsigned> > getShiftedVal() const {
773
1.57k
    if (isShiftedImm() && 
Width == getShiftedImmShift()220
)
774
216
      if (auto *CE = dyn_cast<MCConstantExpr>(getShiftedImmVal()))
775
174
        return std::make_pair(CE->getValue(), Width);
776
1.40k
777
1.40k
    if (isImm())
778
1.35k
      if (auto *CE = dyn_cast<MCConstantExpr>(getImm())) {
779
703
        int64_t Val = CE->getValue();
780
703
        if ((Val != 0) && 
(uint64_t(Val >> Width) << Width) == uint64_t(Val)643
)
781
39
          return std::make_pair(Val >> Width, Width);
782
664
        else
783
664
          return std::make_pair(Val, 0u);
784
700
      }
785
700
786
700
    return {};
787
700
  }
AArch64AsmParser.cpp:llvm::Optional<std::__1::pair<long long, unsigned int> > (anonymous namespace)::AArch64Operand::getShiftedVal<8u>() const
Line
Count
Source
772
2.14k
  Optional<std::pair<int64_t, unsigned> > getShiftedVal() const {
773
2.14k
    if (isShiftedImm() && 
Width == getShiftedImmShift()750
)
774
750
      if (auto *CE = dyn_cast<MCConstantExpr>(getShiftedImmVal()))
775
750
        return std::make_pair(CE->getValue(), Width);
776
1.39k
777
1.39k
    if (isImm())
778
1.39k
      if (auto *CE = dyn_cast<MCConstantExpr>(getImm())) {
779
1.39k
        int64_t Val = CE->getValue();
780
1.39k
        if ((Val != 0) && 
(uint64_t(Val >> Width) << Width) == uint64_t(Val)1.16k
)
781
588
          return std::make_pair(Val >> Width, Width);
782
802
        else
783
802
          return std::make_pair(Val, 0u);
784
0
      }
785
0
786
0
    return {};
787
0
  }
788
789
1.07k
  bool isAddSubImm() const {
790
1.07k
    if (!isShiftedImm() && 
!isImm()997
)
791
482
      return false;
792
597
793
597
    const MCExpr *Expr;
794
597
795
597
    // An ADD/SUB shifter is either 'lsl #0' or 'lsl #12'.
796
597
    if (isShiftedImm()) {
797
82
      unsigned Shift = ShiftedImm.ShiftAmount;
798
82
      Expr = ShiftedImm.Val;
799
82
      if (Shift != 0 && Shift != 12)
800
4
        return false;
801
515
    } else {
802
515
      Expr = getImm();
803
515
    }
804
597
805
597
    AArch64MCExpr::VariantKind ELFRefKind;
806
593
    MCSymbolRefExpr::VariantKind DarwinRefKind;
807
593
    int64_t Addend;
808
593
    if (AArch64AsmParser::classifySymbolRef(Expr, ELFRefKind,
809
593
                                          DarwinRefKind, Addend)) {
810
194
      return DarwinRefKind == MCSymbolRefExpr::VK_PAGEOFF
811
194
          || 
DarwinRefKind == MCSymbolRefExpr::VK_TLVPPAGEOFF177
812
194
          || 
(175
DarwinRefKind == MCSymbolRefExpr::VK_GOTPAGEOFF175
&&
Addend == 00
)
813
194
          || 
ELFRefKind == AArch64MCExpr::VK_LO12175
814
194
          || 
ELFRefKind == AArch64MCExpr::VK_DTPREL_HI12124
815
194
          || 
ELFRefKind == AArch64MCExpr::VK_DTPREL_LO12118
816
194
          || 
ELFRefKind == AArch64MCExpr::VK_DTPREL_LO12_NC99
817
194
          || 
ELFRefKind == AArch64MCExpr::VK_TPREL_HI1281
818
194
          || 
ELFRefKind == AArch64MCExpr::VK_TPREL_LO1268
819
194
          || 
ELFRefKind == AArch64MCExpr::VK_TPREL_LO12_NC49
820
194
          || 
ELFRefKind == AArch64MCExpr::VK_TLSDESC_LO1229
821
194
          || 
ELFRefKind == AArch64MCExpr::VK_SECREL_HI126
822
194
          || 
ELFRefKind == AArch64MCExpr::VK_SECREL_LO125
;
823
194
    }
824
399
825
399
    // If it's a constant, it should be a real immediate in range.
826
399
    if (auto ShiftedVal = getShiftedVal<12>())
827
295
      return ShiftedVal->first >= 0 && 
ShiftedVal->first <= 0xfff247
;
828
104
829
104
    // If it's an expression, we hope for the best and let the fixup/relocation
830
104
    // code deal with it.
831
104
    return true;
832
104
  }
833
834
1.10k
  bool isAddSubImmNeg() const {
835
1.10k
    if (!isShiftedImm() && 
!isImm()1.01k
)
836
482
      return false;
837
619
838
619
    // Otherwise it should be a real negative immediate in range.
839
619
    if (auto ShiftedVal = getShiftedVal<12>())
840
317
      return ShiftedVal->first < 0 && 
-ShiftedVal->first <= 0xfff70
;
841
302
842
302
    return false;
843
302
  }
844
845
  // Signed value in the range -128 to +127. For element widths of
846
  // 16 bits or higher it may also be a signed multiple of 256 in the
847
  // range -32768 to +32512.
848
  // For element-width of 8 bits a range of -128 to 255 is accepted,
849
  // since a copy of a byte can be either signed/unsigned.
850
  template <typename T>
851
1.51k
  DiagnosticPredicate isSVECpyImm() const {
852
1.51k
    if (!isShiftedImm() && 
(1.27k
!isImm()1.27k
||
!isa<MCConstantExpr>(getImm())546
))
853
727
      return DiagnosticPredicateTy::NoMatch;
854
788
855
788
    bool IsByte =
856
788
        std::is_same<int8_t, typename std::make_signed<T>::type>::value;
857
788
    if (auto ShiftedImm = getShiftedVal<8>())
858
788
      if (!(IsByte && 
ShiftedImm->second112
) &&
859
788
          AArch64_AM::isSVECpyImm<T>(uint64_t(ShiftedImm->first)
860
756
                                     << ShiftedImm->second))
861
550
        return DiagnosticPredicateTy::Match;
862
238
863
238
    return DiagnosticPredicateTy::NearMatch;
864
238
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVECpyImm<short>() const
Line
Count
Source
851
379
  DiagnosticPredicate isSVECpyImm() const {
852
379
    if (!isShiftedImm() && 
(313
!isImm()313
||
!isa<MCConstantExpr>(getImm())146
))
853
167
      return DiagnosticPredicateTy::NoMatch;
854
212
855
212
    bool IsByte =
856
212
        std::is_same<int8_t, typename std::make_signed<T>::type>::value;
857
212
    if (auto ShiftedImm = getShiftedVal<8>())
858
212
      if (!(IsByte && 
ShiftedImm->second0
) &&
859
212
          AArch64_AM::isSVECpyImm<T>(uint64_t(ShiftedImm->first)
860
212
                                     << ShiftedImm->second))
861
162
        return DiagnosticPredicateTy::Match;
862
50
863
50
    return DiagnosticPredicateTy::NearMatch;
864
50
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVECpyImm<int>() const
Line
Count
Source
851
387
  DiagnosticPredicate isSVECpyImm() const {
852
387
    if (!isShiftedImm() && 
(321
!isImm()321
||
!isa<MCConstantExpr>(getImm())150
))
853
171
      return DiagnosticPredicateTy::NoMatch;
854
216
855
216
    bool IsByte =
856
216
        std::is_same<int8_t, typename std::make_signed<T>::type>::value;
857
216
    if (auto ShiftedImm = getShiftedVal<8>())
858
216
      if (!(IsByte && 
ShiftedImm->second0
) &&
859
216
          AArch64_AM::isSVECpyImm<T>(uint64_t(ShiftedImm->first)
860
216
                                     << ShiftedImm->second))
861
148
        return DiagnosticPredicateTy::Match;
862
68
863
68
    return DiagnosticPredicateTy::NearMatch;
864
68
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVECpyImm<long long>() const
Line
Count
Source
851
492
  DiagnosticPredicate isSVECpyImm() const {
852
492
    if (!isShiftedImm() && 
(406
!isImm()406
||
!isa<MCConstantExpr>(getImm())162
))
853
244
      return DiagnosticPredicateTy::NoMatch;
854
248
855
248
    bool IsByte =
856
248
        std::is_same<int8_t, typename std::make_signed<T>::type>::value;
857
248
    if (auto ShiftedImm = getShiftedVal<8>())
858
248
      if (!(IsByte && 
ShiftedImm->second0
) &&
859
248
          AArch64_AM::isSVECpyImm<T>(uint64_t(ShiftedImm->first)
860
248
                                     << ShiftedImm->second))
861
170
        return DiagnosticPredicateTy::Match;
862
78
863
78
    return DiagnosticPredicateTy::NearMatch;
864
78
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVECpyImm<signed char>() const
Line
Count
Source
851
257
  DiagnosticPredicate isSVECpyImm() const {
852
257
    if (!isShiftedImm() && 
(233
!isImm()233
||
!isa<MCConstantExpr>(getImm())88
))
853
145
      return DiagnosticPredicateTy::NoMatch;
854
112
855
112
    bool IsByte =
856
112
        std::is_same<int8_t, typename std::make_signed<T>::type>::value;
857
112
    if (auto ShiftedImm = getShiftedVal<8>())
858
112
      if (!(IsByte && ShiftedImm->second) &&
859
112
          AArch64_AM::isSVECpyImm<T>(uint64_t(ShiftedImm->first)
860
80
                                     << ShiftedImm->second))
861
70
        return DiagnosticPredicateTy::Match;
862
42
863
42
    return DiagnosticPredicateTy::NearMatch;
864
42
  }
865
866
  // Unsigned value in the range 0 to 255. For element widths of
867
  // 16 bits or higher it may also be a signed multiple of 256 in the
868
  // range 0 to 65280.
869
994
  template <typename T> DiagnosticPredicate isSVEAddSubImm() const {
870
994
    if (!isShiftedImm() && 
(714
!isImm()714
||
!isa<MCConstantExpr>(getImm())447
))
871
279
      return DiagnosticPredicateTy::NoMatch;
872
715
873
715
    bool IsByte =
874
715
        std::is_same<int8_t, typename std::make_signed<T>::type>::value;
875
715
    if (auto ShiftedImm = getShiftedVal<8>())
876
715
      if (!(IsByte && 
ShiftedImm->second126
) &&
877
715
          AArch64_AM::isSVEAddSubImm<T>(ShiftedImm->first
878
673
                                        << ShiftedImm->second))
879
533
        return DiagnosticPredicateTy::Match;
880
182
881
182
    return DiagnosticPredicateTy::NearMatch;
882
182
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEAddSubImm<short>() const
Line
Count
Source
869
266
  template <typename T> DiagnosticPredicate isSVEAddSubImm() const {
870
266
    if (!isShiftedImm() && 
(182
!isImm()182
||
!isa<MCConstantExpr>(getImm())110
))
871
84
      return DiagnosticPredicateTy::NoMatch;
872
182
873
182
    bool IsByte =
874
182
        std::is_same<int8_t, typename std::make_signed<T>::type>::value;
875
182
    if (auto ShiftedImm = getShiftedVal<8>())
876
182
      if (!(IsByte && 
ShiftedImm->second0
) &&
877
182
          AArch64_AM::isSVEAddSubImm<T>(ShiftedImm->first
878
182
                                        << ShiftedImm->second))
879
140
        return DiagnosticPredicateTy::Match;
880
42
881
42
    return DiagnosticPredicateTy::NearMatch;
882
42
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEAddSubImm<int>() const
Line
Count
Source
869
247
  template <typename T> DiagnosticPredicate isSVEAddSubImm() const {
870
247
    if (!isShiftedImm() && 
(163
!isImm()163
||
!isa<MCConstantExpr>(getImm())98
))
871
65
      return DiagnosticPredicateTy::NoMatch;
872
182
873
182
    bool IsByte =
874
182
        std::is_same<int8_t, typename std::make_signed<T>::type>::value;
875
182
    if (auto ShiftedImm = getShiftedVal<8>())
876
182
      if (!(IsByte && 
ShiftedImm->second0
) &&
877
182
          AArch64_AM::isSVEAddSubImm<T>(ShiftedImm->first
878
182
                                        << ShiftedImm->second))
879
140
        return DiagnosticPredicateTy::Match;
880
42
881
42
    return DiagnosticPredicateTy::NearMatch;
882
42
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEAddSubImm<long long>() const
Line
Count
Source
869
295
  template <typename T> DiagnosticPredicate isSVEAddSubImm() const {
870
295
    if (!isShiftedImm() && 
(211
!isImm()211
||
!isa<MCConstantExpr>(getImm())141
))
871
70
      return DiagnosticPredicateTy::NoMatch;
872
225
873
225
    bool IsByte =
874
225
        std::is_same<int8_t, typename std::make_signed<T>::type>::value;
875
225
    if (auto ShiftedImm = getShiftedVal<8>())
876
225
      if (!(IsByte && 
ShiftedImm->second0
) &&
877
225
          AArch64_AM::isSVEAddSubImm<T>(ShiftedImm->first
878
225
                                        << ShiftedImm->second))
879
183
        return DiagnosticPredicateTy::Match;
880
42
881
42
    return DiagnosticPredicateTy::NearMatch;
882
42
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEAddSubImm<signed char>() const
Line
Count
Source
869
186
  template <typename T> DiagnosticPredicate isSVEAddSubImm() const {
870
186
    if (!isShiftedImm() && 
(158
!isImm()158
||
!isa<MCConstantExpr>(getImm())98
))
871
60
      return DiagnosticPredicateTy::NoMatch;
872
126
873
126
    bool IsByte =
874
126
        std::is_same<int8_t, typename std::make_signed<T>::type>::value;
875
126
    if (auto ShiftedImm = getShiftedVal<8>())
876
126
      if (!(IsByte && ShiftedImm->second) &&
877
126
          AArch64_AM::isSVEAddSubImm<T>(ShiftedImm->first
878
84
                                        << ShiftedImm->second))
879
70
        return DiagnosticPredicateTy::Match;
880
56
881
56
    return DiagnosticPredicateTy::NearMatch;
882
56
  }
883
884
467
  template <typename T> DiagnosticPredicate isSVEPreferredLogicalImm() const {
885
467
    if (isLogicalImm<T>() && 
!isSVECpyImm<T>()55
)
886
27
      return DiagnosticPredicateTy::Match;
887
440
    return DiagnosticPredicateTy::NoMatch;
888
440
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEPreferredLogicalImm<short>() const
Line
Count
Source
884
137
  template <typename T> DiagnosticPredicate isSVEPreferredLogicalImm() const {
885
137
    if (isLogicalImm<T>() && 
!isSVECpyImm<T>()12
)
886
0
      return DiagnosticPredicateTy::Match;
887
137
    return DiagnosticPredicateTy::NoMatch;
888
137
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEPreferredLogicalImm<int>() const
Line
Count
Source
884
143
  template <typename T> DiagnosticPredicate isSVEPreferredLogicalImm() const {
885
143
    if (isLogicalImm<T>() && 
!isSVECpyImm<T>()18
)
886
10
      return DiagnosticPredicateTy::Match;
887
133
    return DiagnosticPredicateTy::NoMatch;
888
133
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEPreferredLogicalImm<long long>() const
Line
Count
Source
884
187
  template <typename T> DiagnosticPredicate isSVEPreferredLogicalImm() const {
885
187
    if (isLogicalImm<T>() && 
!isSVECpyImm<T>()25
)
886
17
      return DiagnosticPredicateTy::Match;
887
170
    return DiagnosticPredicateTy::NoMatch;
888
170
  }
889
890
280
  bool isCondCode() const { return Kind == k_CondCode; }
891
892
8
  bool isSIMDImmType10() const {
893
8
    if (!isImm())
894
0
      return false;
895
8
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
896
8
    if (!MCE)
897
0
      return false;
898
8
    return AArch64_AM::isAdvSIMDModImmType10(MCE->getValue());
899
8
  }
900
901
  template<int N>
902
1.15k
  bool isBranchTarget() const {
903
1.15k
    if (!isImm())
904
792
      return false;
905
360
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
906
360
    if (!MCE)
907
309
      return true;
908
51
    int64_t Val = MCE->getValue();
909
51
    if (Val & 0x3)
910
8
      return false;
911
43
    assert(N > 0 && "Branch target immediate cannot be 0 bits!");
912
43
    return (Val >= -((1<<(N-1)) << 2) && 
Val <= (((1<<(N-1))-1) << 2)35
);
913
43
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isBranchTarget<14>() const
Line
Count
Source
902
29
  bool isBranchTarget() const {
903
29
    if (!isImm())
904
0
      return false;
905
29
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
906
29
    if (!MCE)
907
26
      return true;
908
3
    int64_t Val = MCE->getValue();
909
3
    if (Val & 0x3)
910
0
      return false;
911
3
    assert(N > 0 && "Branch target immediate cannot be 0 bits!");
912
3
    return (Val >= -((1<<(N-1)) << 2) && Val <= (((1<<(N-1))-1) << 2));
913
3
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isBranchTarget<26>() const
Line
Count
Source
902
226
  bool isBranchTarget() const {
903
226
    if (!isImm())
904
117
      return false;
905
109
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
906
109
    if (!MCE)
907
96
      return true;
908
13
    int64_t Val = MCE->getValue();
909
13
    if (Val & 0x3)
910
2
      return false;
911
11
    assert(N > 0 && "Branch target immediate cannot be 0 bits!");
912
11
    return (Val >= -((1<<(N-1)) << 2) && 
Val <= (((1<<(N-1))-1) << 2)9
);
913
11
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isBranchTarget<19>() const
Line
Count
Source
902
897
  bool isBranchTarget() const {
903
897
    if (!isImm())
904
675
      return false;
905
222
    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
906
222
    if (!MCE)
907
187
      return true;
908
35
    int64_t Val = MCE->getValue();
909
35
    if (Val & 0x3)
910
6
      return false;
911
29
    assert(N > 0 && "Branch target immediate cannot be 0 bits!");
912
29
    return (Val >= -((1<<(N-1)) << 2) && 
Val <= (((1<<(N-1))-1) << 2)23
);
913
29
  }
914
915
  bool
916
843
  isMovWSymbol(ArrayRef<AArch64MCExpr::VariantKind> AllowedModifiers) const {
917
843
    if (!isImm())
918
0
      return false;
919
843
920
843
    AArch64MCExpr::VariantKind ELFRefKind;
921
843
    MCSymbolRefExpr::VariantKind DarwinRefKind;
922
843
    int64_t Addend;
923
843
    if (!AArch64AsmParser::classifySymbolRef(getImm(), ELFRefKind,
924
843
                                             DarwinRefKind, Addend)) {
925
182
      return false;
926
182
    }
927
661
    if (DarwinRefKind != MCSymbolRefExpr::VK_None)
928
0
      return false;
929
661
930
5.18k
    
for (unsigned i = 0; 661
i != AllowedModifiers.size();
++i4.52k
) {
931
4.83k
      if (ELFRefKind == AllowedModifiers[i])
932
309
        return true;
933
4.83k
    }
934
661
935
661
    
return false352
;
936
661
  }
937
938
55
  bool isMovWSymbolG3() const {
939
55
    return isMovWSymbol({AArch64MCExpr::VK_ABS_G3, AArch64MCExpr::VK_PREL_G3});
940
55
  }
941
942
126
  bool isMovWSymbolG2() const {
943
126
    return isMovWSymbol(
944
126
        {AArch64MCExpr::VK_ABS_G2, AArch64MCExpr::VK_ABS_G2_S,
945
126
         AArch64MCExpr::VK_ABS_G2_NC, AArch64MCExpr::VK_PREL_G2,
946
126
         AArch64MCExpr::VK_PREL_G2_NC, AArch64MCExpr::VK_TPREL_G2,
947
126
         AArch64MCExpr::VK_DTPREL_G2});
948
126
  }
949
950
278
  bool isMovWSymbolG1() const {
951
278
    return isMovWSymbol(
952
278
        {AArch64MCExpr::VK_ABS_G1, AArch64MCExpr::VK_ABS_G1_S,
953
278
         AArch64MCExpr::VK_ABS_G1_NC, AArch64MCExpr::VK_PREL_G1,
954
278
         AArch64MCExpr::VK_PREL_G1_NC, AArch64MCExpr::VK_GOTTPREL_G1,
955
278
         AArch64MCExpr::VK_TPREL_G1, AArch64MCExpr::VK_TPREL_G1_NC,
956
278
         AArch64MCExpr::VK_DTPREL_G1, AArch64MCExpr::VK_DTPREL_G1_NC});
957
278
  }
958
959
384
  bool isMovWSymbolG0() const {
960
384
    return isMovWSymbol(
961
384
        {AArch64MCExpr::VK_ABS_G0, AArch64MCExpr::VK_ABS_G0_S,
962
384
         AArch64MCExpr::VK_ABS_G0_NC, AArch64MCExpr::VK_PREL_G0,
963
384
         AArch64MCExpr::VK_PREL_G0_NC, AArch64MCExpr::VK_GOTTPREL_G0_NC,
964
384
         AArch64MCExpr::VK_TPREL_G0, AArch64MCExpr::VK_TPREL_G0_NC,
965
384
         AArch64MCExpr::VK_DTPREL_G0, AArch64MCExpr::VK_DTPREL_G0_NC});
966
384
  }
967
968
  template<int RegWidth, int Shift>
969
114
  bool isMOVZMovAlias() const {
970
114
    if (!isImm()) 
return false72
;
971
42
972
42
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
973
42
    if (!CE) 
return false8
;
974
34
    uint64_t Value = CE->getValue();
975
34
976
34
    return AArch64_AM::isMOVZMovAlias(Value, Shift, RegWidth);
977
34
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMOVZMovAlias<32, 0>() const
Line
Count
Source
969
17
  bool isMOVZMovAlias() const {
970
17
    if (!isImm()) 
return false8
;
971
9
972
9
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
973
9
    if (!CE) 
return false0
;
974
9
    uint64_t Value = CE->getValue();
975
9
976
9
    return AArch64_AM::isMOVZMovAlias(Value, Shift, RegWidth);
977
9
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMOVZMovAlias<32, 16>() const
Line
Count
Source
969
13
  bool isMOVZMovAlias() const {
970
13
    if (!isImm()) 
return false8
;
971
5
972
5
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
973
5
    if (!CE) 
return false0
;
974
5
    uint64_t Value = CE->getValue();
975
5
976
5
    return AArch64_AM::isMOVZMovAlias(Value, Shift, RegWidth);
977
5
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMOVZMovAlias<64, 0>() const
Line
Count
Source
969
28
  bool isMOVZMovAlias() const {
970
28
    if (!isImm()) 
return false14
;
971
14
972
14
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
973
14
    if (!CE) 
return false2
;
974
12
    uint64_t Value = CE->getValue();
975
12
976
12
    return AArch64_AM::isMOVZMovAlias(Value, Shift, RegWidth);
977
12
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMOVZMovAlias<64, 16>() const
Line
Count
Source
969
19
  bool isMOVZMovAlias() const {
970
19
    if (!isImm()) 
return false14
;
971
5
972
5
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
973
5
    if (!CE) 
return false2
;
974
3
    uint64_t Value = CE->getValue();
975
3
976
3
    return AArch64_AM::isMOVZMovAlias(Value, Shift, RegWidth);
977
3
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMOVZMovAlias<64, 32>() const
Line
Count
Source
969
19
  bool isMOVZMovAlias() const {
970
19
    if (!isImm()) 
return false14
;
971
5
972
5
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
973
5
    if (!CE) 
return false2
;
974
3
    uint64_t Value = CE->getValue();
975
3
976
3
    return AArch64_AM::isMOVZMovAlias(Value, Shift, RegWidth);
977
3
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMOVZMovAlias<64, 48>() const
Line
Count
Source
969
18
  bool isMOVZMovAlias() const {
970
18
    if (!isImm()) 
return false14
;
971
4
972
4
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
973
4
    if (!CE) 
return false2
;
974
2
    uint64_t Value = CE->getValue();
975
2
976
2
    return AArch64_AM::isMOVZMovAlias(Value, Shift, RegWidth);
977
2
  }
978
979
  template<int RegWidth, int Shift>
980
91
  bool isMOVNMovAlias() const {
981
91
    if (!isImm()) 
return false72
;
982
19
983
19
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
984
19
    if (!CE) 
return false8
;
985
11
    uint64_t Value = CE->getValue();
986
11
987
11
    return AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth);
988
11
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMOVNMovAlias<32, 0>() const
Line
Count
Source
980
13
  bool isMOVNMovAlias() const {
981
13
    if (!isImm()) 
return false8
;
982
5
983
5
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
984
5
    if (!CE) 
return false0
;
985
5
    uint64_t Value = CE->getValue();
986
5
987
5
    return AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth);
988
5
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMOVNMovAlias<32, 16>() const
Line
Count
Source
980
9
  bool isMOVNMovAlias() const {
981
9
    if (!isImm()) 
return false8
;
982
1
983
1
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
984
1
    if (!CE) 
return false0
;
985
1
    uint64_t Value = CE->getValue();
986
1
987
1
    return AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth);
988
1
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMOVNMovAlias<64, 0>() const
Line
Count
Source
980
18
  bool isMOVNMovAlias() const {
981
18
    if (!isImm()) 
return false14
;
982
4
983
4
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
984
4
    if (!CE) 
return false2
;
985
2
    uint64_t Value = CE->getValue();
986
2
987
2
    return AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth);
988
2
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMOVNMovAlias<64, 16>() const
Line
Count
Source
980
17
  bool isMOVNMovAlias() const {
981
17
    if (!isImm()) 
return false14
;
982
3
983
3
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
984
3
    if (!CE) 
return false2
;
985
1
    uint64_t Value = CE->getValue();
986
1
987
1
    return AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth);
988
1
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMOVNMovAlias<64, 32>() const
Line
Count
Source
980
17
  bool isMOVNMovAlias() const {
981
17
    if (!isImm()) 
return false14
;
982
3
983
3
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
984
3
    if (!CE) 
return false2
;
985
1
    uint64_t Value = CE->getValue();
986
1
987
1
    return AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth);
988
1
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMOVNMovAlias<64, 48>() const
Line
Count
Source
980
17
  bool isMOVNMovAlias() const {
981
17
    if (!isImm()) 
return false14
;
982
3
983
3
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
984
3
    if (!CE) 
return false2
;
985
1
    uint64_t Value = CE->getValue();
986
1
987
1
    return AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth);
988
1
  }
989
990
5.42k
  bool isFPImm() const {
991
5.42k
    return Kind == k_FPImm &&
992
5.42k
           
AArch64_AM::getFP64Imm(getFPImm().bitcastToAPInt()) != -14.06k
;
993
5.42k
  }
994
995
52
  bool isBarrier() const { return Kind == k_Barrier; }
996
4.83k
  bool isSysReg() const { return Kind == k_SysReg; }
997
998
1.49k
  bool isMRSSystemRegister() const {
999
1.49k
    if (!isSysReg()) 
return false0
;
1000
1.49k
1001
1.49k
    return SysReg.MRSReg != -1U;
1002
1.49k
  }
1003
1004
1.49k
  bool isMSRSystemRegister() const {
1005
1.49k
    if (!isSysReg()) 
return false0
;
1006
1.49k
    return SysReg.MSRReg != -1U;
1007
1.49k
  }
1008
1009
1.22k
  bool isSystemPStateFieldWithImm0_1() const {
1010
1.22k
    if (!isSysReg()) 
return false0
;
1011
1.22k
    return (SysReg.PStateField == AArch64PState::PAN ||
1012
1.22k
            
SysReg.PStateField == AArch64PState::DIT1.20k
||
1013
1.22k
            
SysReg.PStateField == AArch64PState::UAO1.19k
||
1014
1.22k
            
SysReg.PStateField == AArch64PState::SSBS1.19k
);
1015
1.22k
  }
1016
1017
615
  bool isSystemPStateFieldWithImm0_15() const {
1018
615
    if (!isSysReg() || isSystemPStateFieldWithImm0_1()) 
return false25
;
1019
590
    return SysReg.PStateField != -1U;
1020
590
  }
1021
1022
635k
  bool isReg() const override {
1023
635k
    return Kind == k_Register;
1024
635k
  }
1025
1026
281
  bool isScalarReg() const {
1027
281
    return Kind == k_Register && 
Reg.Kind == RegKind::Scalar280
;
1028
281
  }
1029
1030
55.0k
  bool isNeonVectorReg() const {
1031
55.0k
    return Kind == k_Register && 
Reg.Kind == RegKind::NeonVector53.7k
;
1032
55.0k
  }
1033
1034
237
  bool isNeonVectorRegLo() const {
1035
237
    return Kind == k_Register && Reg.Kind == RegKind::NeonVector &&
1036
237
           AArch64MCRegisterClasses[AArch64::FPR128_loRegClassID].contains(
1037
231
               Reg.RegNum);
1038
237
  }
1039
1040
287k
  template <unsigned Class> bool isSVEVectorReg() const {
1041
287k
    RegKind RK;
1042
287k
    switch (Class) {
1043
287k
    case AArch64::ZPRRegClassID:
1044
212k
    case AArch64::ZPR_3bRegClassID:
1045
212k
    case AArch64::ZPR_4bRegClassID:
1046
212k
      RK = RegKind::SVEDataVector;
1047
212k
      break;
1048
212k
    case AArch64::PPRRegClassID:
1049
74.6k
    case AArch64::PPR_3bRegClassID:
1050
74.6k
      RK = RegKind::SVEPredicateVector;
1051
74.6k
      break;
1052
25.2k
    default:
1053
0
      llvm_unreachable("Unsupport register class");
1054
287k
    }
1055
287k
1056
287k
    return (Kind == k_Register && Reg.Kind == RK) &&
1057
287k
           AArch64MCRegisterClasses[Class].contains(getReg());
1058
287k
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isSVEVectorReg<2u>() const
Line
Count
Source
1040
25.2k
  template <unsigned Class> bool isSVEVectorReg() const {
1041
25.2k
    RegKind RK;
1042
25.2k
    switch (Class) {
1043
25.2k
    case AArch64::ZPRRegClassID:
1044
0
    case AArch64::ZPR_3bRegClassID:
1045
0
    case AArch64::ZPR_4bRegClassID:
1046
0
      RK = RegKind::SVEDataVector;
1047
0
      break;
1048
25.2k
    case AArch64::PPRRegClassID:
1049
25.2k
    case AArch64::PPR_3bRegClassID:
1050
25.2k
      RK = RegKind::SVEPredicateVector;
1051
25.2k
      break;
1052
25.2k
    default:
1053
0
      llvm_unreachable("Unsupport register class");
1054
25.2k
    }
1055
25.2k
1056
25.2k
    return (Kind == k_Register && Reg.Kind == RK) &&
1057
25.2k
           AArch64MCRegisterClasses[Class].contains(getReg());
1058
25.2k
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isSVEVectorReg<3u>() const
Line
Count
Source
1040
49.4k
  template <unsigned Class> bool isSVEVectorReg() const {
1041
49.4k
    RegKind RK;
1042
49.4k
    switch (Class) {
1043
49.4k
    case AArch64::ZPRRegClassID:
1044
0
    case AArch64::ZPR_3bRegClassID:
1045
0
    case AArch64::ZPR_4bRegClassID:
1046
0
      RK = RegKind::SVEDataVector;
1047
0
      break;
1048
0
    case AArch64::PPRRegClassID:
1049
49.4k
    case AArch64::PPR_3bRegClassID:
1050
49.4k
      RK = RegKind::SVEPredicateVector;
1051
49.4k
      break;
1052
0
    default:
1053
0
      llvm_unreachable("Unsupport register class");
1054
49.4k
    }
1055
49.4k
1056
49.4k
    return (Kind == k_Register && Reg.Kind == RK) &&
1057
49.4k
           AArch64MCRegisterClasses[Class].contains(getReg());
1058
49.4k
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isSVEVectorReg<39u>() const
Line
Count
Source
1040
211k
  template <unsigned Class> bool isSVEVectorReg() const {
1041
211k
    RegKind RK;
1042
211k
    switch (Class) {
1043
211k
    case AArch64::ZPRRegClassID:
1044
211k
    case AArch64::ZPR_3bRegClassID:
1045
211k
    case AArch64::ZPR_4bRegClassID:
1046
211k
      RK = RegKind::SVEDataVector;
1047
211k
      break;
1048
211k
    case AArch64::PPRRegClassID:
1049
0
    case AArch64::PPR_3bRegClassID:
1050
0
      RK = RegKind::SVEPredicateVector;
1051
0
      break;
1052
0
    default:
1053
0
      llvm_unreachable("Unsupport register class");
1054
211k
    }
1055
211k
1056
211k
    return (Kind == k_Register && Reg.Kind == RK) &&
1057
211k
           AArch64MCRegisterClasses[Class].contains(getReg());
1058
211k
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isSVEVectorReg<42u>() const
Line
Count
Source
1040
702
  template <unsigned Class> bool isSVEVectorReg() const {
1041
702
    RegKind RK;
1042
702
    switch (Class) {
1043
702
    case AArch64::ZPRRegClassID:
1044
702
    case AArch64::ZPR_3bRegClassID:
1045
702
    case AArch64::ZPR_4bRegClassID:
1046
702
      RK = RegKind::SVEDataVector;
1047
702
      break;
1048
702
    case AArch64::PPRRegClassID:
1049
0
    case AArch64::PPR_3bRegClassID:
1050
0
      RK = RegKind::SVEPredicateVector;
1051
0
      break;
1052
0
    default:
1053
0
      llvm_unreachable("Unsupport register class");
1054
702
    }
1055
702
1056
702
    return (Kind == k_Register && Reg.Kind == RK) &&
1057
702
           AArch64MCRegisterClasses[Class].contains(getReg());
1058
702
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isSVEVectorReg<41u>() const
Line
Count
Source
1040
687
  template <unsigned Class> bool isSVEVectorReg() const {
1041
687
    RegKind RK;
1042
687
    switch (Class) {
1043
687
    case AArch64::ZPRRegClassID:
1044
0
    case AArch64::ZPR_3bRegClassID:
1045
687
    case AArch64::ZPR_4bRegClassID:
1046
687
      RK = RegKind::SVEDataVector;
1047
687
      break;
1048
0
    case AArch64::PPRRegClassID:
1049
0
    case AArch64::PPR_3bRegClassID:
1050
0
      RK = RegKind::SVEPredicateVector;
1051
0
      break;
1052
0
    default:
1053
0
      llvm_unreachable("Unsupport register class");
1054
687
    }
1055
687
1056
687
    return (Kind == k_Register && Reg.Kind == RK) &&
1057
687
           AArch64MCRegisterClasses[Class].contains(getReg());
1058
687
  }
1059
1060
603
  template <unsigned Class> bool isFPRasZPR() const {
1061
603
    return Kind == k_Register && 
Reg.Kind == RegKind::Scalar484
&&
1062
603
           
AArch64MCRegisterClasses[Class].contains(getReg())51
;
1063
603
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isFPRasZPR<0u>() const
Line
Count
Source
1060
106
  template <unsigned Class> bool isFPRasZPR() const {
1061
106
    return Kind == k_Register && 
Reg.Kind == RegKind::Scalar88
&&
1062
106
           
AArch64MCRegisterClasses[Class].contains(getReg())9
;
1063
106
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isFPRasZPR<1u>() const
Line
Count
Source
1060
140
  template <unsigned Class> bool isFPRasZPR() const {
1061
140
    return Kind == k_Register && 
Reg.Kind == RegKind::Scalar110
&&
1062
140
           
AArch64MCRegisterClasses[Class].contains(getReg())9
;
1063
140
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isFPRasZPR<5u>() const
Line
Count
Source
1060
146
  template <unsigned Class> bool isFPRasZPR() const {
1061
146
    return Kind == k_Register && 
Reg.Kind == RegKind::Scalar112
&&
1062
146
           
AArch64MCRegisterClasses[Class].contains(getReg())11
;
1063
146
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isFPRasZPR<16u>() const
Line
Count
Source
1060
192
  template <unsigned Class> bool isFPRasZPR() const {
1061
192
    return Kind == k_Register && 
Reg.Kind == RegKind::Scalar155
&&
1062
192
           
AArch64MCRegisterClasses[Class].contains(getReg())17
;
1063
192
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isFPRasZPR<38u>() const
Line
Count
Source
1060
19
  template <unsigned Class> bool isFPRasZPR() const {
1061
19
    return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
1062
19
           
AArch64MCRegisterClasses[Class].contains(getReg())5
;
1063
19
  }
1064
1065
  template <int ElementWidth, unsigned Class>
1066
85.1k
  DiagnosticPredicate isSVEPredicateVectorRegOfWidth() const {
1067
85.1k
    if (Kind != k_Register || 
Reg.Kind != RegKind::SVEPredicateVector84.5k
)
1068
10.5k
      return DiagnosticPredicateTy::NoMatch;
1069
74.6k
1070
74.6k
    if (isSVEVectorReg<Class>() && 
(Reg.ElementWidth == ElementWidth)72.8k
)
1071
58.8k
      return DiagnosticPredicateTy::Match;
1072
15.8k
1073
15.8k
    return DiagnosticPredicateTy::NearMatch;
1074
15.8k
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEPredicateVectorRegOfWidth<16, 2u>() const
Line
Count
Source
1066
7.19k
  DiagnosticPredicate isSVEPredicateVectorRegOfWidth() const {
1067
7.19k
    if (Kind != k_Register || Reg.Kind != RegKind::SVEPredicateVector)
1068
1.25k
      return DiagnosticPredicateTy::NoMatch;
1069
5.93k
1070
5.93k
    if (isSVEVectorReg<Class>() && (Reg.ElementWidth == ElementWidth))
1071
1.12k
      return DiagnosticPredicateTy::Match;
1072
4.81k
1073
4.81k
    return DiagnosticPredicateTy::NearMatch;
1074
4.81k
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEPredicateVectorRegOfWidth<32, 2u>() const
Line
Count
Source
1066
6.55k
  DiagnosticPredicate isSVEPredicateVectorRegOfWidth() const {
1067
6.55k
    if (Kind != k_Register || 
Reg.Kind != RegKind::SVEPredicateVector6.53k
)
1068
1.27k
      return DiagnosticPredicateTy::NoMatch;
1069
5.27k
1070
5.27k
    if (isSVEVectorReg<Class>() && (Reg.ElementWidth == ElementWidth))
1071
1.98k
      return DiagnosticPredicateTy::Match;
1072
3.29k
1073
3.29k
    return DiagnosticPredicateTy::NearMatch;
1074
3.29k
  }
Unexecuted instantiation: AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEPredicateVectorRegOfWidth<16, 3u>() const
Unexecuted instantiation: AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEPredicateVectorRegOfWidth<32, 3u>() const
Unexecuted instantiation: AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEPredicateVectorRegOfWidth<64, 3u>() const
Unexecuted instantiation: AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEPredicateVectorRegOfWidth<8, 3u>() const
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEPredicateVectorRegOfWidth<0, 3u>() const
Line
Count
Source
1066
51.3k
  DiagnosticPredicate isSVEPredicateVectorRegOfWidth() const {
1067
51.3k
    if (Kind != k_Register || 
Reg.Kind != RegKind::SVEPredicateVector51.1k
)
1068
1.93k
      return DiagnosticPredicateTy::NoMatch;
1069
49.4k
1070
49.4k
    if (isSVEVectorReg<Class>() && 
(Reg.ElementWidth == ElementWidth)47.6k
)
1071
46.9k
      return DiagnosticPredicateTy::Match;
1072
2.49k
1073
2.49k
    return DiagnosticPredicateTy::NearMatch;
1074
2.49k
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEPredicateVectorRegOfWidth<64, 2u>() const
Line
Count
Source
1066
4.96k
  DiagnosticPredicate isSVEPredicateVectorRegOfWidth() const {
1067
4.96k
    if (Kind != k_Register || Reg.Kind != RegKind::SVEPredicateVector)
1068
1.25k
      return DiagnosticPredicateTy::NoMatch;
1069
3.70k
1070
3.70k
    if (isSVEVectorReg<Class>() && (Reg.ElementWidth == ElementWidth))
1071
902
      return DiagnosticPredicateTy::Match;
1072
2.80k
1073
2.80k
    return DiagnosticPredicateTy::NearMatch;
1074
2.80k
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEPredicateVectorRegOfWidth<8, 2u>() const
Line
Count
Source
1066
7.98k
  DiagnosticPredicate isSVEPredicateVectorRegOfWidth() const {
1067
7.98k
    if (Kind != k_Register || 
Reg.Kind != RegKind::SVEPredicateVector7.95k
)
1068
3.06k
      return DiagnosticPredicateTy::NoMatch;
1069
4.92k
1070
4.92k
    if (isSVEVectorReg<Class>() && (Reg.ElementWidth == ElementWidth))
1071
2.58k
      return DiagnosticPredicateTy::Match;
1072
2.33k
1073
2.33k
    return DiagnosticPredicateTy::NearMatch;
1074
2.33k
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEPredicateVectorRegOfWidth<0, 2u>() const
Line
Count
Source
1066
7.11k
  DiagnosticPredicate isSVEPredicateVectorRegOfWidth() const {
1067
7.11k
    if (Kind != k_Register || 
Reg.Kind != RegKind::SVEPredicateVector6.73k
)
1068
1.74k
      return DiagnosticPredicateTy::NoMatch;
1069
5.37k
1070
5.37k
    if (isSVEVectorReg<Class>() && (Reg.ElementWidth == ElementWidth))
1071
5.30k
      return DiagnosticPredicateTy::Match;
1072
72
1073
72
    return DiagnosticPredicateTy::NearMatch;
1074
72
  }
1075
1076
  template <int ElementWidth, unsigned Class>
1077
302k
  DiagnosticPredicate isSVEDataVectorRegOfWidth() const {
1078
302k
    if (Kind != k_Register || 
Reg.Kind != RegKind::SVEDataVector259k
)
1079
89.4k
      return DiagnosticPredicateTy::NoMatch;
1080
212k
1081
212k
    if (isSVEVectorReg<Class>() && 
Reg.ElementWidth == ElementWidth212k
)
1082
94.3k
      return DiagnosticPredicateTy::Match;
1083
118k
1084
118k
    return DiagnosticPredicateTy::NearMatch;
1085
118k
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegOfWidth<128, 39u>() const
Line
Count
Source
1077
1.93k
  DiagnosticPredicate isSVEDataVectorRegOfWidth() const {
1078
1.93k
    if (Kind != k_Register || 
Reg.Kind != RegKind::SVEDataVector1.89k
)
1079
373
      return DiagnosticPredicateTy::NoMatch;
1080
1.55k
1081
1.55k
    if (isSVEVectorReg<Class>() && Reg.ElementWidth == ElementWidth)
1082
101
      return DiagnosticPredicateTy::Match;
1083
1.45k
1084
1.45k
    return DiagnosticPredicateTy::NearMatch;
1085
1.45k
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegOfWidth<16, 39u>() const
Line
Count
Source
1077
68.2k
  DiagnosticPredicate isSVEDataVectorRegOfWidth() const {
1078
68.2k
    if (Kind != k_Register || 
Reg.Kind != RegKind::SVEDataVector64.0k
)
1079
15.1k
      return DiagnosticPredicateTy::NoMatch;
1080
53.0k
1081
53.0k
    if (isSVEVectorReg<Class>() && Reg.ElementWidth == ElementWidth)
1082
15.6k
      return DiagnosticPredicateTy::Match;
1083
37.3k
1084
37.3k
    return DiagnosticPredicateTy::NearMatch;
1085
37.3k
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegOfWidth<32, 39u>() const
Line
Count
Source
1077
89.8k
  DiagnosticPredicate isSVEDataVectorRegOfWidth() const {
1078
89.8k
    if (Kind != k_Register || 
Reg.Kind != RegKind::SVEDataVector75.0k
)
1079
28.5k
      return DiagnosticPredicateTy::NoMatch;
1080
61.2k
1081
61.2k
    if (isSVEVectorReg<Class>() && Reg.ElementWidth == ElementWidth)
1082
21.7k
      return DiagnosticPredicateTy::Match;
1083
39.4k
1084
39.4k
    return DiagnosticPredicateTy::NearMatch;
1085
39.4k
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegOfWidth<16, 42u>() const
Line
Count
Source
1077
537
  DiagnosticPredicate isSVEDataVectorRegOfWidth() const {
1078
537
    if (Kind != k_Register || 
Reg.Kind != RegKind::SVEDataVector533
)
1079
4
      return DiagnosticPredicateTy::NoMatch;
1080
533
1081
533
    if (isSVEVectorReg<Class>() && 
Reg.ElementWidth == ElementWidth393
)
1082
393
      return DiagnosticPredicateTy::Match;
1083
140
1084
140
    return DiagnosticPredicateTy::NearMatch;
1085
140
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegOfWidth<32, 42u>() const
Line
Count
Source
1077
131
  DiagnosticPredicate isSVEDataVectorRegOfWidth() const {
1078
131
    if (Kind != k_Register || 
Reg.Kind != RegKind::SVEDataVector127
)
1079
4
      return DiagnosticPredicateTy::NoMatch;
1080
127
1081
127
    if (isSVEVectorReg<Class>() && 
Reg.ElementWidth == ElementWidth95
)
1082
95
      return DiagnosticPredicateTy::Match;
1083
32
1084
32
    return DiagnosticPredicateTy::NearMatch;
1085
32
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegOfWidth<8, 42u>() const
Line
Count
Source
1077
42
  DiagnosticPredicate isSVEDataVectorRegOfWidth() const {
1078
42
    if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector)
1079
0
      return DiagnosticPredicateTy::NoMatch;
1080
42
1081
42
    if (isSVEVectorReg<Class>() && 
Reg.ElementWidth == ElementWidth30
)
1082
30
      return DiagnosticPredicateTy::Match;
1083
12
1084
12
    return DiagnosticPredicateTy::NearMatch;
1085
12
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegOfWidth<16, 41u>() const
Line
Count
Source
1077
86
  DiagnosticPredicate isSVEDataVectorRegOfWidth() const {
1078
86
    if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector)
1079
0
      return DiagnosticPredicateTy::NoMatch;
1080
86
1081
86
    if (isSVEVectorReg<Class>() && 
Reg.ElementWidth == ElementWidth62
)
1082
62
      return DiagnosticPredicateTy::Match;
1083
24
1084
24
    return DiagnosticPredicateTy::NearMatch;
1085
24
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegOfWidth<32, 41u>() const
Line
Count
Source
1077
426
  DiagnosticPredicate isSVEDataVectorRegOfWidth() const {
1078
426
    if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector)
1079
0
      return DiagnosticPredicateTy::NoMatch;
1080
426
1081
426
    if (isSVEVectorReg<Class>() && 
Reg.ElementWidth == ElementWidth314
)
1082
314
      return DiagnosticPredicateTy::Match;
1083
112
1084
112
    return DiagnosticPredicateTy::NearMatch;
1085
112
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegOfWidth<64, 41u>() const
Line
Count
Source
1077
181
  DiagnosticPredicate isSVEDataVectorRegOfWidth() const {
1078
181
    if (Kind != k_Register || 
Reg.Kind != RegKind::SVEDataVector175
)
1079
6
      return DiagnosticPredicateTy::NoMatch;
1080
175
1081
175
    if (isSVEVectorReg<Class>() && 
Reg.ElementWidth == ElementWidth139
)
1082
139
      return DiagnosticPredicateTy::Match;
1083
36
1084
36
    return DiagnosticPredicateTy::NearMatch;
1085
36
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegOfWidth<64, 39u>() const
Line
Count
Source
1077
102k
  DiagnosticPredicate isSVEDataVectorRegOfWidth() const {
1078
102k
    if (Kind != k_Register || 
Reg.Kind != RegKind::SVEDataVector81.1k
)
1079
36.6k
      return DiagnosticPredicateTy::NoMatch;
1080
65.9k
1081
65.9k
    if (isSVEVectorReg<Class>() && Reg.ElementWidth == ElementWidth)
1082
41.8k
      return DiagnosticPredicateTy::Match;
1083
24.1k
1084
24.1k
    return DiagnosticPredicateTy::NearMatch;
1085
24.1k
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegOfWidth<8, 39u>() const
Line
Count
Source
1077
32.2k
  DiagnosticPredicate isSVEDataVectorRegOfWidth() const {
1078
32.2k
    if (Kind != k_Register || 
Reg.Kind != RegKind::SVEDataVector30.1k
)
1079
7.55k
      return DiagnosticPredicateTy::NoMatch;
1080
24.6k
1081
24.6k
    if (isSVEVectorReg<Class>() && Reg.ElementWidth == ElementWidth)
1082
10.1k
      return DiagnosticPredicateTy::Match;
1083
14.5k
1084
14.5k
    return DiagnosticPredicateTy::NearMatch;
1085
14.5k
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegOfWidth<0, 39u>() const
Line
Count
Source
1077
6.20k
  DiagnosticPredicate isSVEDataVectorRegOfWidth() const {
1078
6.20k
    if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector)
1079
1.11k
      return DiagnosticPredicateTy::NoMatch;
1080
5.09k
1081
5.09k
    if (isSVEVectorReg<Class>() && Reg.ElementWidth == ElementWidth)
1082
3.83k
      return DiagnosticPredicateTy::Match;
1083
1.25k
1084
1.25k
    return DiagnosticPredicateTy::NearMatch;
1085
1.25k
  }
1086
1087
  template <int ElementWidth, unsigned Class,
1088
            AArch64_AM::ShiftExtendType ShiftExtendTy, int ShiftWidth,
1089
            bool ShiftWidthAlwaysSame>
1090
9.15k
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
9.15k
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
9.15k
    if (!VectorMatch.isMatch())
1093
4.77k
      return DiagnosticPredicateTy::NoMatch;
1094
4.37k
1095
4.37k
    // Give a more specific diagnostic when the user has explicitly typed in
1096
4.37k
    // a shift-amount that does not match what is expected, but for which
1097
4.37k
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
4.37k
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
4.37k
    if (!MatchShift && 
(821
ShiftExtendTy == AArch64_AM::UXTW821
||
1100
821
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
4.37k
        
!ShiftWidthAlwaysSame72
&&
hasShiftExtendAmount()1.44k
&&
ShiftWidth == 8395
)
1102
524
      return DiagnosticPredicateTy::NoMatch;
1103
3.85k
1104
3.85k
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()2.03k
)
1105
887
      return DiagnosticPredicateTy::Match;
1106
2.96k
1107
2.96k
    return DiagnosticPredicateTy::NearMatch;
1108
2.96k
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<32, 39u, (llvm::AArch64_AM::ShiftExtendType)0, 16, false>() const
Line
Count
Source
1090
33
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
33
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
33
    if (!VectorMatch.isMatch())
1093
2
      return DiagnosticPredicateTy::NoMatch;
1094
31
1095
31
    // Give a more specific diagnostic when the user has explicitly typed in
1096
31
    // a shift-amount that does not match what is expected, but for which
1097
31
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
31
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
31
    if (!MatchShift && 
(26
ShiftExtendTy == AArch64_AM::UXTW26
||
1100
26
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
31
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()0
&&
ShiftWidth == 80
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
31
1104
31
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()5
)
1105
5
      return DiagnosticPredicateTy::Match;
1106
26
1107
26
    return DiagnosticPredicateTy::NearMatch;
1108
26
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<32, 39u, (llvm::AArch64_AM::ShiftExtendType)0, 32, false>() const
Line
Count
Source
1090
30
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
30
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
30
    if (!VectorMatch.isMatch())
1093
2
      return DiagnosticPredicateTy::NoMatch;
1094
28
1095
28
    // Give a more specific diagnostic when the user has explicitly typed in
1096
28
    // a shift-amount that does not match what is expected, but for which
1097
28
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
28
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
28
    if (!MatchShift && 
(23
ShiftExtendTy == AArch64_AM::UXTW23
||
1100
23
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
28
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()0
&&
ShiftWidth == 80
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
28
1104
28
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()5
)
1105
5
      return DiagnosticPredicateTy::Match;
1106
23
1107
23
    return DiagnosticPredicateTy::NearMatch;
1108
23
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<32, 39u, (llvm::AArch64_AM::ShiftExtendType)0, 64, false>() const
Line
Count
Source
1090
27
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
27
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
27
    if (!VectorMatch.isMatch())
1093
2
      return DiagnosticPredicateTy::NoMatch;
1094
25
1095
25
    // Give a more specific diagnostic when the user has explicitly typed in
1096
25
    // a shift-amount that does not match what is expected, but for which
1097
25
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
25
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
25
    if (!MatchShift && 
(20
ShiftExtendTy == AArch64_AM::UXTW20
||
1100
20
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
25
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()0
&&
ShiftWidth == 80
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
25
1104
25
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()5
)
1105
5
      return DiagnosticPredicateTy::Match;
1106
20
1107
20
    return DiagnosticPredicateTy::NearMatch;
1108
20
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<32, 39u, (llvm::AArch64_AM::ShiftExtendType)0, 8, false>() const
Line
Count
Source
1090
24
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
24
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
24
    if (!VectorMatch.isMatch())
1093
2
      return DiagnosticPredicateTy::NoMatch;
1094
22
1095
22
    // Give a more specific diagnostic when the user has explicitly typed in
1096
22
    // a shift-amount that does not match what is expected, but for which
1097
22
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
22
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
22
    if (!MatchShift && 
(8
ShiftExtendTy == AArch64_AM::UXTW8
||
1100
8
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
22
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()0
&&
ShiftWidth == 80
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
22
1104
22
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()14
)
1105
10
      return DiagnosticPredicateTy::Match;
1106
12
1107
12
    return DiagnosticPredicateTy::NearMatch;
1108
12
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<32, 39u, (llvm::AArch64_AM::ShiftExtendType)11, 16, false>() const
Line
Count
Source
1090
339
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
339
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
339
    if (!VectorMatch.isMatch())
1093
191
      return DiagnosticPredicateTy::NoMatch;
1094
148
1095
148
    // Give a more specific diagnostic when the user has explicitly typed in
1096
148
    // a shift-amount that does not match what is expected, but for which
1097
148
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
148
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
148
    if (!MatchShift && 
(0
ShiftExtendTy == AArch64_AM::UXTW0
||
1100
0
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
148
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()76
&&
ShiftWidth == 812
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
148
1104
148
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()72
)
1105
30
      return DiagnosticPredicateTy::Match;
1106
118
1107
118
    return DiagnosticPredicateTy::NearMatch;
1108
118
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<32, 39u, (llvm::AArch64_AM::ShiftExtendType)11, 32, false>() const
Line
Count
Source
1090
273
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
273
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
273
    if (!VectorMatch.isMatch())
1093
177
      return DiagnosticPredicateTy::NoMatch;
1094
96
1095
96
    // Give a more specific diagnostic when the user has explicitly typed in
1096
96
    // a shift-amount that does not match what is expected, but for which
1097
96
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
96
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
96
    if (!MatchShift && 
(0
ShiftExtendTy == AArch64_AM::UXTW0
||
1100
0
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
96
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()48
&&
ShiftWidth == 88
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
96
1104
96
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()48
)
1105
20
      return DiagnosticPredicateTy::Match;
1106
76
1107
76
    return DiagnosticPredicateTy::NearMatch;
1108
76
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<32, 39u, (llvm::AArch64_AM::ShiftExtendType)11, 64, false>() const
Line
Count
Source
1090
109
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
109
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
109
    if (!VectorMatch.isMatch())
1093
97
      return DiagnosticPredicateTy::NoMatch;
1094
12
1095
12
    // Give a more specific diagnostic when the user has explicitly typed in
1096
12
    // a shift-amount that does not match what is expected, but for which
1097
12
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
12
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
12
    if (!MatchShift && 
(0
ShiftExtendTy == AArch64_AM::UXTW0
||
1100
0
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
12
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()2
&&
ShiftWidth == 80
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
12
1104
12
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()10
)
1105
5
      return DiagnosticPredicateTy::Match;
1106
7
1107
7
    return DiagnosticPredicateTy::NearMatch;
1108
7
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<32, 39u, (llvm::AArch64_AM::ShiftExtendType)11, 8, false>() const
Line
Count
Source
1090
352
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
352
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
352
    if (!VectorMatch.isMatch())
1093
168
      return DiagnosticPredicateTy::NoMatch;
1094
184
1095
184
    // Give a more specific diagnostic when the user has explicitly typed in
1096
184
    // a shift-amount that does not match what is expected, but for which
1097
184
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
184
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
184
    if (!MatchShift && 
(0
ShiftExtendTy == AArch64_AM::UXTW0
||
1100
0
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
184
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()88
&&
ShiftWidth == 80
)
1102
88
      return DiagnosticPredicateTy::NoMatch;
1103
96
1104
96
    if (MatchShift && ShiftExtendTy == getShiftExtendType())
1105
40
      return DiagnosticPredicateTy::Match;
1106
56
1107
56
    return DiagnosticPredicateTy::NearMatch;
1108
56
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<32, 39u, (llvm::AArch64_AM::ShiftExtendType)11, 8, true>() const
Line
Count
Source
1090
271
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
271
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
271
    if (!VectorMatch.isMatch())
1093
173
      return DiagnosticPredicateTy::NoMatch;
1094
98
1095
98
    // Give a more specific diagnostic when the user has explicitly typed in
1096
98
    // a shift-amount that does not match what is expected, but for which
1097
98
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
98
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
98
    if (!MatchShift && 
(0
ShiftExtendTy == AArch64_AM::UXTW0
||
1100
0
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
98
        
!ShiftWidthAlwaysSame12
&&
hasShiftExtendAmount()0
&&
ShiftWidth == 80
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
98
1104
98
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()86
)
1105
25
      return DiagnosticPredicateTy::Match;
1106
73
1107
73
    return DiagnosticPredicateTy::NearMatch;
1108
73
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<32, 39u, (llvm::AArch64_AM::ShiftExtendType)7, 16, false>() const
Line
Count
Source
1090
306
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
306
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
306
    if (!VectorMatch.isMatch())
1093
191
      return DiagnosticPredicateTy::NoMatch;
1094
115
1095
115
    // Give a more specific diagnostic when the user has explicitly typed in
1096
115
    // a shift-amount that does not match what is expected, but for which
1097
115
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
115
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
115
    if (!MatchShift && 
(0
ShiftExtendTy == AArch64_AM::UXTW0
||
1100
0
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
115
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()61
&&
ShiftWidth == 812
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
115
1104
115
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()54
)
1105
30
      return DiagnosticPredicateTy::Match;
1106
85
1107
85
    return DiagnosticPredicateTy::NearMatch;
1108
85
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<32, 39u, (llvm::AArch64_AM::ShiftExtendType)7, 32, false>() const
Line
Count
Source
1090
252
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
252
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
252
    if (!VectorMatch.isMatch())
1093
177
      return DiagnosticPredicateTy::NoMatch;
1094
75
1095
75
    // Give a more specific diagnostic when the user has explicitly typed in
1096
75
    // a shift-amount that does not match what is expected, but for which
1097
75
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
75
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
75
    if (!MatchShift && 
(0
ShiftExtendTy == AArch64_AM::UXTW0
||
1100
0
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
75
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()39
&&
ShiftWidth == 88
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
75
1104
75
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()36
)
1105
20
      return DiagnosticPredicateTy::Match;
1106
55
1107
55
    return DiagnosticPredicateTy::NearMatch;
1108
55
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<32, 39u, (llvm::AArch64_AM::ShiftExtendType)7, 64, false>() const
Line
Count
Source
1090
106
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
106
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
106
    if (!VectorMatch.isMatch())
1093
97
      return DiagnosticPredicateTy::NoMatch;
1094
9
1095
9
    // Give a more specific diagnostic when the user has explicitly typed in
1096
9
    // a shift-amount that does not match what is expected, but for which
1097
9
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
9
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
9
    if (!MatchShift && 
(0
ShiftExtendTy == AArch64_AM::UXTW0
||
1100
0
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
9
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()2
&&
ShiftWidth == 80
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
9
1104
9
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()7
)
1105
5
      return DiagnosticPredicateTy::Match;
1106
4
1107
4
    return DiagnosticPredicateTy::NearMatch;
1108
4
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<32, 39u, (llvm::AArch64_AM::ShiftExtendType)7, 8, false>() const
Line
Count
Source
1090
304
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
304
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
304
    if (!VectorMatch.isMatch())
1093
168
      return DiagnosticPredicateTy::NoMatch;
1094
136
1095
136
    // Give a more specific diagnostic when the user has explicitly typed in
1096
136
    // a shift-amount that does not match what is expected, but for which
1097
136
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
136
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
136
    if (!MatchShift && 
(0
ShiftExtendTy == AArch64_AM::UXTW0
||
1100
0
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
136
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()64
&&
ShiftWidth == 80
)
1102
64
      return DiagnosticPredicateTy::NoMatch;
1103
72
1104
72
    if (MatchShift && ShiftExtendTy == getShiftExtendType())
1105
40
      return DiagnosticPredicateTy::Match;
1106
32
1107
32
    return DiagnosticPredicateTy::NearMatch;
1108
32
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<32, 39u, (llvm::AArch64_AM::ShiftExtendType)7, 8, true>() const
Line
Count
Source
1090
256
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
256
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
256
    if (!VectorMatch.isMatch())
1093
173
      return DiagnosticPredicateTy::NoMatch;
1094
83
1095
83
    // Give a more specific diagnostic when the user has explicitly typed in
1096
83
    // a shift-amount that does not match what is expected, but for which
1097
83
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
83
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
83
    if (!MatchShift && 
(0
ShiftExtendTy == AArch64_AM::UXTW0
||
1100
0
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
83
        
!ShiftWidthAlwaysSame12
&&
hasShiftExtendAmount()0
&&
ShiftWidth == 80
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
83
1104
83
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()71
)
1105
35
      return DiagnosticPredicateTy::Match;
1106
48
1107
48
    return DiagnosticPredicateTy::NearMatch;
1108
48
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<64, 39u, (llvm::AArch64_AM::ShiftExtendType)0, 16, false>() const
Line
Count
Source
1090
462
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
462
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
462
    if (!VectorMatch.isMatch())
1093
188
      return DiagnosticPredicateTy::NoMatch;
1094
274
1095
274
    // Give a more specific diagnostic when the user has explicitly typed in
1096
274
    // a shift-amount that does not match what is expected, but for which
1097
274
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
274
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
274
    if (!MatchShift && 
(167
ShiftExtendTy == AArch64_AM::UXTW167
||
1100
167
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
274
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()0
&&
ShiftWidth == 80
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
274
1104
274
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()107
)
1105
37
      return DiagnosticPredicateTy::Match;
1106
237
1107
237
    return DiagnosticPredicateTy::NearMatch;
1108
237
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<64, 39u, (llvm::AArch64_AM::ShiftExtendType)0, 32, false>() const
Line
Count
Source
1090
489
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
489
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
489
    if (!VectorMatch.isMatch())
1093
208
      return DiagnosticPredicateTy::NoMatch;
1094
281
1095
281
    // Give a more specific diagnostic when the user has explicitly typed in
1096
281
    // a shift-amount that does not match what is expected, but for which
1097
281
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
281
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
281
    if (!MatchShift && 
(172
ShiftExtendTy == AArch64_AM::UXTW172
||
1100
172
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
281
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()0
&&
ShiftWidth == 80
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
281
1104
281
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()109
)
1105
37
      return DiagnosticPredicateTy::Match;
1106
244
1107
244
    return DiagnosticPredicateTy::NearMatch;
1108
244
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<64, 39u, (llvm::AArch64_AM::ShiftExtendType)0, 64, false>() const
Line
Count
Source
1090
370
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
370
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
370
    if (!VectorMatch.isMatch())
1093
170
      return DiagnosticPredicateTy::NoMatch;
1094
200
1095
200
    // Give a more specific diagnostic when the user has explicitly typed in
1096
200
    // a shift-amount that does not match what is expected, but for which
1097
200
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
200
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
200
    if (!MatchShift && 
(121
ShiftExtendTy == AArch64_AM::UXTW121
||
1100
121
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
200
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()0
&&
ShiftWidth == 80
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
200
1104
200
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()79
)
1105
27
      return DiagnosticPredicateTy::Match;
1106
173
1107
173
    return DiagnosticPredicateTy::NearMatch;
1108
173
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<64, 39u, (llvm::AArch64_AM::ShiftExtendType)0, 8, false>() const
Line
Count
Source
1090
1.08k
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
1.08k
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
1.08k
    if (!VectorMatch.isMatch())
1093
486
      return DiagnosticPredicateTy::NoMatch;
1094
601
1095
601
    // Give a more specific diagnostic when the user has explicitly typed in
1096
601
    // a shift-amount that does not match what is expected, but for which
1097
601
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
601
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
601
    if (!MatchShift && 
(284
ShiftExtendTy == AArch64_AM::UXTW284
||
1100
284
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
601
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()0
&&
ShiftWidth == 80
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
601
1104
601
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()317
)
1105
107
      return DiagnosticPredicateTy::Match;
1106
494
1107
494
    return DiagnosticPredicateTy::NearMatch;
1108
494
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<64, 39u, (llvm::AArch64_AM::ShiftExtendType)11, 16, false>() const
Line
Count
Source
1090
412
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
412
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
412
    if (!VectorMatch.isMatch())
1093
188
      return DiagnosticPredicateTy::NoMatch;
1094
224
1095
224
    // Give a more specific diagnostic when the user has explicitly typed in
1096
224
    // a shift-amount that does not match what is expected, but for which
1097
224
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
224
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
224
    if (!MatchShift && 
(0
ShiftExtendTy == AArch64_AM::UXTW0
||
1100
0
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
224
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()140
&&
ShiftWidth == 868
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
224
1104
224
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()84
)
1105
35
      return DiagnosticPredicateTy::Match;
1106
189
1107
189
    return DiagnosticPredicateTy::NearMatch;
1108
189
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<64, 39u, (llvm::AArch64_AM::ShiftExtendType)11, 32, false>() const
Line
Count
Source
1090
439
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
439
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
439
    if (!VectorMatch.isMatch())
1093
208
      return DiagnosticPredicateTy::NoMatch;
1094
231
1095
231
    // Give a more specific diagnostic when the user has explicitly typed in
1096
231
    // a shift-amount that does not match what is expected, but for which
1097
231
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
231
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
231
    if (!MatchShift && 
(0
ShiftExtendTy == AArch64_AM::UXTW0
||
1100
0
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
231
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()145
&&
ShiftWidth == 873
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
231
1104
231
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()86
)
1105
35
      return DiagnosticPredicateTy::Match;
1106
196
1107
196
    return DiagnosticPredicateTy::NearMatch;
1108
196
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<64, 39u, (llvm::AArch64_AM::ShiftExtendType)11, 64, false>() const
Line
Count
Source
1090
332
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
332
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
332
    if (!VectorMatch.isMatch())
1093
170
      return DiagnosticPredicateTy::NoMatch;
1094
162
1095
162
    // Give a more specific diagnostic when the user has explicitly typed in
1096
162
    // a shift-amount that does not match what is expected, but for which
1097
162
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
162
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
162
    if (!MatchShift && 
(0
ShiftExtendTy == AArch64_AM::UXTW0
||
1100
0
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
162
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()100
&&
ShiftWidth == 852
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
162
1104
162
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()62
)
1105
27
      return DiagnosticPredicateTy::Match;
1106
135
1107
135
    return DiagnosticPredicateTy::NearMatch;
1108
135
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<64, 39u, (llvm::AArch64_AM::ShiftExtendType)11, 8, false>() const
Line
Count
Source
1090
682
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
682
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
682
    if (!VectorMatch.isMatch())
1093
292
      return DiagnosticPredicateTy::NoMatch;
1094
390
1095
390
    // Give a more specific diagnostic when the user has explicitly typed in
1096
390
    // a shift-amount that does not match what is expected, but for which
1097
390
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
390
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
390
    if (!MatchShift && 
(0
ShiftExtendTy == AArch64_AM::UXTW0
||
1100
0
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
390
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()210
&&
ShiftWidth == 80
)
1102
210
      return DiagnosticPredicateTy::NoMatch;
1103
180
1104
180
    if (MatchShift && ShiftExtendTy == getShiftExtendType())
1105
75
      return DiagnosticPredicateTy::Match;
1106
105
1107
105
    return DiagnosticPredicateTy::NearMatch;
1108
105
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<64, 39u, (llvm::AArch64_AM::ShiftExtendType)11, 8, true>() const
Line
Count
Source
1090
290
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
290
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
290
    if (!VectorMatch.isMatch())
1093
194
      return DiagnosticPredicateTy::NoMatch;
1094
96
1095
96
    // Give a more specific diagnostic when the user has explicitly typed in
1096
96
    // a shift-amount that does not match what is expected, but for which
1097
96
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
96
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
96
    if (!MatchShift && 
(0
ShiftExtendTy == AArch64_AM::UXTW0
||
1100
0
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
96
        
!ShiftWidthAlwaysSame24
&&
hasShiftExtendAmount()0
&&
ShiftWidth == 80
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
96
1104
96
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()72
)
1105
30
      return DiagnosticPredicateTy::Match;
1106
66
1107
66
    return DiagnosticPredicateTy::NearMatch;
1108
66
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<64, 39u, (llvm::AArch64_AM::ShiftExtendType)7, 16, false>() const
Line
Count
Source
1090
362
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
362
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
362
    if (!VectorMatch.isMatch())
1093
188
      return DiagnosticPredicateTy::NoMatch;
1094
174
1095
174
    // Give a more specific diagnostic when the user has explicitly typed in
1096
174
    // a shift-amount that does not match what is expected, but for which
1097
174
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
174
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
174
    if (!MatchShift && 
(0
ShiftExtendTy == AArch64_AM::UXTW0
||
1100
0
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
174
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()111
&&
ShiftWidth == 857
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
174
1104
174
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()63
)
1105
35
      return DiagnosticPredicateTy::Match;
1106
139
1107
139
    return DiagnosticPredicateTy::NearMatch;
1108
139
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<64, 39u, (llvm::AArch64_AM::ShiftExtendType)7, 32, false>() const
Line
Count
Source
1090
389
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
389
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
389
    if (!VectorMatch.isMatch())
1093
208
      return DiagnosticPredicateTy::NoMatch;
1094
181
1095
181
    // Give a more specific diagnostic when the user has explicitly typed in
1096
181
    // a shift-amount that does not match what is expected, but for which
1097
181
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
181
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
181
    if (!MatchShift && 
(0
ShiftExtendTy == AArch64_AM::UXTW0
||
1100
0
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
181
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()116
&&
ShiftWidth == 862
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
181
1104
181
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()65
)
1105
37
      return DiagnosticPredicateTy::Match;
1106
144
1107
144
    return DiagnosticPredicateTy::NearMatch;
1108
144
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<64, 39u, (llvm::AArch64_AM::ShiftExtendType)7, 64, false>() const
Line
Count
Source
1090
294
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
294
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
294
    if (!VectorMatch.isMatch())
1093
170
      return DiagnosticPredicateTy::NoMatch;
1094
124
1095
124
    // Give a more specific diagnostic when the user has explicitly typed in
1096
124
    // a shift-amount that does not match what is expected, but for which
1097
124
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
124
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
124
    if (!MatchShift && 
(0
ShiftExtendTy == AArch64_AM::UXTW0
||
1100
0
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
124
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()79
&&
ShiftWidth == 843
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
124
1104
124
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()45
)
1105
25
      return DiagnosticPredicateTy::Match;
1106
99
1107
99
    return DiagnosticPredicateTy::NearMatch;
1108
99
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<64, 39u, (llvm::AArch64_AM::ShiftExtendType)7, 8, false>() const
Line
Count
Source
1090
589
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
589
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
589
    if (!VectorMatch.isMatch())
1093
292
      return DiagnosticPredicateTy::NoMatch;
1094
297
1095
297
    // Give a more specific diagnostic when the user has explicitly typed in
1096
297
    // a shift-amount that does not match what is expected, but for which
1097
297
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
297
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
297
    if (!MatchShift && 
(0
ShiftExtendTy == AArch64_AM::UXTW0
||
1100
0
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
297
        
!ShiftWidthAlwaysSame0
&&
hasShiftExtendAmount()162
&&
ShiftWidth == 80
)
1102
162
      return DiagnosticPredicateTy::NoMatch;
1103
135
1104
135
    if (MatchShift && ShiftExtendTy == getShiftExtendType())
1105
75
      return DiagnosticPredicateTy::Match;
1106
60
1107
60
    return DiagnosticPredicateTy::NearMatch;
1108
60
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isSVEDataVectorRegWithShiftExtend<64, 39u, (llvm::AArch64_AM::ShiftExtendType)7, 8, true>() const
Line
Count
Source
1090
272
  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
1091
272
    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
1092
272
    if (!VectorMatch.isMatch())
1093
194
      return DiagnosticPredicateTy::NoMatch;
1094
78
1095
78
    // Give a more specific diagnostic when the user has explicitly typed in
1096
78
    // a shift-amount that does not match what is expected, but for which
1097
78
    // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
1098
78
    bool MatchShift = getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
1099
78
    if (!MatchShift && 
(0
ShiftExtendTy == AArch64_AM::UXTW0
||
1100
0
                        ShiftExtendTy == AArch64_AM::SXTW) &&
1101
78
        
!ShiftWidthAlwaysSame24
&&
hasShiftExtendAmount()0
&&
ShiftWidth == 80
)
1102
0
      return DiagnosticPredicateTy::NoMatch;
1103
78
1104
78
    if (MatchShift && 
ShiftExtendTy == getShiftExtendType()54
)
1105
30
      return DiagnosticPredicateTy::Match;
1106
48
1107
48
    return DiagnosticPredicateTy::NearMatch;
1108
48
  }
1109
1110
25
  bool isGPR32as64() const {
1111
25
    return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
1112
25
      AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum);
1113
25
  }
1114
1115
3.42k
  bool isGPR64as32() const {
1116
3.42k
    return Kind == k_Register && 
Reg.Kind == RegKind::Scalar732
&&
1117
3.42k
      
AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(Reg.RegNum)732
;
1118
3.42k
  }
1119
1120
101
  bool isWSeqPair() const {
1121
101
    return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
1122
101
           AArch64MCRegisterClasses[AArch64::WSeqPairsClassRegClassID].contains(
1123
101
               Reg.RegNum);
1124
101
  }
1125
1126
70
  bool isXSeqPair() const {
1127
70
    return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
1128
70
           AArch64MCRegisterClasses[AArch64::XSeqPairsClassRegClassID].contains(
1129
70
               Reg.RegNum);
1130
70
  }
1131
1132
  template<int64_t Angle, int64_t Remainder>
1133
821
  DiagnosticPredicate isComplexRotation() const {
1134
821
    if (!isImm()) 
return DiagnosticPredicateTy::NoMatch131
;
1135
690
1136
690
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1137
690
    if (!CE) 
return DiagnosticPredicateTy::NoMatch0
;
1138
690
    uint64_t Value = CE->getValue();
1139
690
1140
690
    if (Value % Angle == Remainder && 
Value <= 270669
)
1141
645
      return DiagnosticPredicateTy::Match;
1142
45
    return DiagnosticPredicateTy::NearMatch;
1143
45
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isComplexRotation<90ll, 0ll>() const
Line
Count
Source
1133
625
  DiagnosticPredicate isComplexRotation() const {
1134
625
    if (!isImm()) 
return DiagnosticPredicateTy::NoMatch131
;
1135
494
1136
494
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1137
494
    if (!CE) 
return DiagnosticPredicateTy::NoMatch0
;
1138
494
    uint64_t Value = CE->getValue();
1139
494
1140
494
    if (Value % Angle == Remainder && 
Value <= 270490
)
1141
472
      return DiagnosticPredicateTy::Match;
1142
22
    return DiagnosticPredicateTy::NearMatch;
1143
22
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isComplexRotation<180ll, 90ll>() const
Line
Count
Source
1133
196
  DiagnosticPredicate isComplexRotation() const {
1134
196
    if (!isImm()) 
return DiagnosticPredicateTy::NoMatch0
;
1135
196
1136
196
    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1137
196
    if (!CE) 
return DiagnosticPredicateTy::NoMatch0
;
1138
196
    uint64_t Value = CE->getValue();
1139
196
1140
196
    if (Value % Angle == Remainder && 
Value <= 270179
)
1141
173
      return DiagnosticPredicateTy::Match;
1142
23
    return DiagnosticPredicateTy::NearMatch;
1143
23
  }
1144
1145
28.4k
  template <unsigned RegClassID> bool isGPR64() const {
1146
28.4k
    return Kind == k_Register && 
Reg.Kind == RegKind::Scalar28.4k
&&
1147
28.4k
           
AArch64MCRegisterClasses[RegClassID].contains(getReg())22.9k
;
1148
28.4k
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isGPR64<19u>() const
Line
Count
Source
1145
879
  template <unsigned RegClassID> bool isGPR64() const {
1146
879
    return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
1147
879
           AArch64MCRegisterClasses[RegClassID].contains(getReg());
1148
879
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isGPR64<17u>() const
Line
Count
Source
1145
211
  template <unsigned RegClassID> bool isGPR64() const {
1146
211
    return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
1147
211
           AArch64MCRegisterClasses[RegClassID].contains(getReg());
1148
211
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isGPR64<18u>() const
Line
Count
Source
1145
133
  template <unsigned RegClassID> bool isGPR64() const {
1146
133
    return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
1147
133
           AArch64MCRegisterClasses[RegClassID].contains(getReg());
1148
133
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isGPR64<0u>() const
Line
Count
Source
1145
4.34k
  template <unsigned RegClassID> bool isGPR64() const {
1146
4.34k
    return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
1147
4.34k
           
AArch64MCRegisterClasses[RegClassID].contains(getReg())3.58k
;
1148
4.34k
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isGPR64<1u>() const
Line
Count
Source
1145
4.84k
  template <unsigned RegClassID> bool isGPR64() const {
1146
4.84k
    return Kind == k_Register && 
Reg.Kind == RegKind::Scalar4.83k
&&
1147
4.84k
           
AArch64MCRegisterClasses[RegClassID].contains(getReg())3.59k
;
1148
4.84k
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isGPR64<5u>() const
Line
Count
Source
1145
6.61k
  template <unsigned RegClassID> bool isGPR64() const {
1146
6.61k
    return Kind == k_Register && 
Reg.Kind == RegKind::Scalar6.60k
&&
1147
6.61k
           
AArch64MCRegisterClasses[RegClassID].contains(getReg())5.20k
;
1148
6.61k
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isGPR64<16u>() const
Line
Count
Source
1145
6.13k
  template <unsigned RegClassID> bool isGPR64() const {
1146
6.13k
    return Kind == k_Register && 
Reg.Kind == RegKind::Scalar6.12k
&&
1147
6.13k
           
AArch64MCRegisterClasses[RegClassID].contains(getReg())4.86k
;
1148
6.13k
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isGPR64<38u>() const
Line
Count
Source
1145
5.32k
  template <unsigned RegClassID> bool isGPR64() const {
1146
5.32k
    return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
1147
5.32k
           
AArch64MCRegisterClasses[RegClassID].contains(getReg())4.45k
;
1148
5.32k
  }
1149
1150
  template <unsigned RegClassID, int ExtWidth>
1151
3.73k
  DiagnosticPredicate isGPR64WithShiftExtend() const {
1152
3.73k
    if (Kind != k_Register || 
Reg.Kind != RegKind::Scalar2.15k
)
1153
2.64k
      return DiagnosticPredicateTy::NoMatch;
1154
1.09k
1155
1.09k
    if (isGPR64<RegClassID>() && 
getShiftExtendType() == AArch64_AM::LSL806
&&
1156
1.09k
        
getShiftExtendAmount() == Log2_32(ExtWidth / 8)798
)
1157
646
      return DiagnosticPredicateTy::Match;
1158
444
    return DiagnosticPredicateTy::NearMatch;
1159
444
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isGPR64WithShiftExtend<19u, 16>() const
Line
Count
Source
1151
879
  DiagnosticPredicate isGPR64WithShiftExtend() const {
1152
879
    if (Kind != k_Register || 
Reg.Kind != RegKind::Scalar466
)
1153
646
      return DiagnosticPredicateTy::NoMatch;
1154
233
1155
233
    if (isGPR64<RegClassID>() && 
getShiftExtendType() == AArch64_AM::LSL171
&&
1156
233
        
getShiftExtendAmount() == Log2_32(ExtWidth / 8)169
)
1157
129
      return DiagnosticPredicateTy::Match;
1158
104
    return DiagnosticPredicateTy::NearMatch;
1159
104
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isGPR64WithShiftExtend<19u, 32>() const
Line
Count
Source
1151
790
  DiagnosticPredicate isGPR64WithShiftExtend() const {
1152
790
    if (Kind != k_Register || 
Reg.Kind != RegKind::Scalar431
)
1153
572
      return DiagnosticPredicateTy::NoMatch;
1154
218
1155
218
    if (isGPR64<RegClassID>() && 
getShiftExtendType() == AArch64_AM::LSL156
&&
1156
218
        
getShiftExtendAmount() == Log2_32(ExtWidth / 8)154
)
1157
114
      return DiagnosticPredicateTy::Match;
1158
104
    return DiagnosticPredicateTy::NearMatch;
1159
104
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isGPR64WithShiftExtend<19u, 64>() const
Line
Count
Source
1151
598
  DiagnosticPredicate isGPR64WithShiftExtend() const {
1152
598
    if (Kind != k_Register || 
Reg.Kind != RegKind::Scalar293
)
1153
410
      return DiagnosticPredicateTy::NoMatch;
1154
188
1155
188
    if (isGPR64<RegClassID>() && 
getShiftExtendType() == AArch64_AM::LSL132
&&
1156
188
        
getShiftExtendAmount() == Log2_32(ExtWidth / 8)130
)
1157
94
      return DiagnosticPredicateTy::Match;
1158
94
    return DiagnosticPredicateTy::NearMatch;
1159
94
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isGPR64WithShiftExtend<19u, 8>() const
Line
Count
Source
1151
873
  DiagnosticPredicate isGPR64WithShiftExtend() const {
1152
873
    if (Kind != k_Register || 
Reg.Kind != RegKind::Scalar406
)
1153
633
      return DiagnosticPredicateTy::NoMatch;
1154
240
1155
240
    if (isGPR64<RegClassID>() && 
getShiftExtendType() == AArch64_AM::LSL178
&&
1156
240
        
getShiftExtendAmount() == Log2_32(ExtWidth / 8)176
)
1157
154
      return DiagnosticPredicateTy::Match;
1158
86
    return DiagnosticPredicateTy::NearMatch;
1159
86
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isGPR64WithShiftExtend<17u, 16>() const
Line
Count
Source
1151
204
  DiagnosticPredicate isGPR64WithShiftExtend() const {
1152
204
    if (Kind != k_Register || 
Reg.Kind != RegKind::Scalar194
)
1153
138
      return DiagnosticPredicateTy::NoMatch;
1154
66
1155
66
    if (isGPR64<RegClassID>() && 
getShiftExtendType() == AArch64_AM::LSL54
&&
1156
66
        
getShiftExtendAmount() == Log2_32(ExtWidth / 8)54
)
1157
50
      return DiagnosticPredicateTy::Match;
1158
16
    return DiagnosticPredicateTy::NearMatch;
1159
16
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isGPR64WithShiftExtend<17u, 32>() const
Line
Count
Source
1151
158
  DiagnosticPredicate isGPR64WithShiftExtend() const {
1152
158
    if (Kind != k_Register || 
Reg.Kind != RegKind::Scalar152
)
1153
112
      return DiagnosticPredicateTy::NoMatch;
1154
46
1155
46
    if (isGPR64<RegClassID>() && 
getShiftExtendType() == AArch64_AM::LSL34
&&
1156
46
        
getShiftExtendAmount() == Log2_32(ExtWidth / 8)34
)
1157
30
      return DiagnosticPredicateTy::Match;
1158
16
    return DiagnosticPredicateTy::NearMatch;
1159
16
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isGPR64WithShiftExtend<17u, 64>() const
Line
Count
Source
1151
56
  DiagnosticPredicate isGPR64WithShiftExtend() const {
1152
56
    if (Kind != k_Register || 
Reg.Kind != RegKind::Scalar54
)
1153
38
      return DiagnosticPredicateTy::NoMatch;
1154
18
1155
18
    if (isGPR64<RegClassID>() && 
getShiftExtendType() == AArch64_AM::LSL12
&&
1156
18
        
getShiftExtendAmount() == Log2_32(ExtWidth / 8)12
)
1157
10
      return DiagnosticPredicateTy::Match;
1158
8
    return DiagnosticPredicateTy::NearMatch;
1159
8
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isGPR64WithShiftExtend<17u, 8>() const
Line
Count
Source
1151
177
  DiagnosticPredicate isGPR64WithShiftExtend() const {
1152
177
    if (Kind != k_Register || 
Reg.Kind != RegKind::Scalar163
)
1153
96
      return DiagnosticPredicateTy::NoMatch;
1154
81
1155
81
    if (isGPR64<RegClassID>() && 
getShiftExtendType() == AArch64_AM::LSL69
&&
1156
81
        
getShiftExtendAmount() == Log2_32(ExtWidth / 8)69
)
1157
65
      return DiagnosticPredicateTy::Match;
1158
16
    return DiagnosticPredicateTy::NearMatch;
1159
16
  }
1160
1161
  /// Is this a vector list with the type implicit (presumably attached to the
1162
  /// instruction itself)?
1163
  template <RegKind VectorKind, unsigned NumRegs>
1164
1.94k
  bool isImplicitlyTypedVectorList() const {
1165
1.94k
    return Kind == k_VectorList && VectorList.Count == NumRegs &&
1166
1.94k
           
VectorList.NumElements == 01.05k
&&
1167
1.94k
           
VectorList.RegisterKind == VectorKind1.05k
;
1168
1.94k
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isImplicitlyTypedVectorList<((anonymous namespace)::RegKind)1, 4u>() const
Line
Count
Source
1164
634
  bool isImplicitlyTypedVectorList() const {
1165
634
    return Kind == k_VectorList && VectorList.Count == NumRegs &&
1166
634
           
VectorList.NumElements == 0286
&&
1167
634
           
VectorList.RegisterKind == VectorKind286
;
1168
634
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isImplicitlyTypedVectorList<((anonymous namespace)::RegKind)1, 1u>() const
Line
Count
Source
1164
460
  bool isImplicitlyTypedVectorList() const {
1165
460
    return Kind == k_VectorList && VectorList.Count == NumRegs &&
1166
460
           
VectorList.NumElements == 0196
&&
1167
460
           
VectorList.RegisterKind == VectorKind196
;
1168
460
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isImplicitlyTypedVectorList<((anonymous namespace)::RegKind)1, 3u>() const
Line
Count
Source
1164
474
  bool isImplicitlyTypedVectorList() const {
1165
474
    return Kind == k_VectorList && VectorList.Count == NumRegs &&
1166
474
           
VectorList.NumElements == 0294
&&
1167
474
           
VectorList.RegisterKind == VectorKind294
;
1168
474
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isImplicitlyTypedVectorList<((anonymous namespace)::RegKind)1, 2u>() const
Line
Count
Source
1164
376
  bool isImplicitlyTypedVectorList() const {
1165
376
    return Kind == k_VectorList && VectorList.Count == NumRegs &&
1166
376
           
VectorList.NumElements == 0280
&&
1167
376
           
VectorList.RegisterKind == VectorKind280
;
1168
376
  }
1169
1170
  template <RegKind VectorKind, unsigned NumRegs, unsigned NumElements,
1171
            unsigned ElementWidth>
1172
111k
  bool isTypedVectorList() const {
1173
111k
    if (Kind != k_VectorList)
1174
45.2k
      return false;
1175
66.4k
    if (VectorList.Count != NumRegs)
1176
17.8k
      return false;
1177
48.6k
    if (VectorList.RegisterKind != VectorKind)
1178
858
      return false;
1179
47.8k
    if (VectorList.ElementWidth != ElementWidth)
1180
26.3k
      return false;
1181
21.4k
    return VectorList.NumElements == NumElements;
1182
21.4k
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 4u, 16u, 8u>() const
Line
Count
Source
1172
2.19k
  bool isTypedVectorList() const {
1173
2.19k
    if (Kind != k_VectorList)
1174
766
      return false;
1175
1.42k
    if (VectorList.Count != NumRegs)
1176
806
      return false;
1177
620
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
620
    if (VectorList.ElementWidth != ElementWidth)
1180
445
      return false;
1181
175
    return VectorList.NumElements == NumElements;
1182
175
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 4u, 1u, 64u>() const
Line
Count
Source
1172
1.61k
  bool isTypedVectorList() const {
1173
1.61k
    if (Kind != k_VectorList)
1174
590
      return false;
1175
1.02k
    if (VectorList.Count != NumRegs)
1176
756
      return false;
1177
267
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
267
    if (VectorList.ElementWidth != ElementWidth)
1180
196
      return false;
1181
71
    return VectorList.NumElements == NumElements;
1182
71
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 4u, 2u, 64u>() const
Line
Count
Source
1172
2.06k
  bool isTypedVectorList() const {
1173
2.06k
    if (Kind != k_VectorList)
1174
766
      return false;
1175
1.30k
    if (VectorList.Count != NumRegs)
1176
768
      return false;
1177
532
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
532
    if (VectorList.ElementWidth != ElementWidth)
1180
420
      return false;
1181
112
    return VectorList.NumElements == NumElements;
1182
112
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 4u, 2u, 32u>() const
Line
Count
Source
1172
2.02k
  bool isTypedVectorList() const {
1173
2.02k
    if (Kind != k_VectorList)
1174
766
      return false;
1175
1.25k
    if (VectorList.Count != NumRegs)
1176
768
      return false;
1177
489
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
489
    if (VectorList.ElementWidth != ElementWidth)
1180
350
      return false;
1181
139
    return VectorList.NumElements == NumElements;
1182
139
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 4u, 4u, 16u>() const
Line
Count
Source
1172
1.98k
  bool isTypedVectorList() const {
1173
1.98k
    if (Kind != k_VectorList)
1174
766
      return false;
1175
1.21k
    if (VectorList.Count != NumRegs)
1176
768
      return false;
1177
449
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
449
    if (VectorList.ElementWidth != ElementWidth)
1180
305
      return false;
1181
144
    return VectorList.NumElements == NumElements;
1182
144
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 4u, 4u, 32u>() const
Line
Count
Source
1172
1.93k
  bool isTypedVectorList() const {
1173
1.93k
    if (Kind != k_VectorList)
1174
766
      return false;
1175
1.16k
    if (VectorList.Count != NumRegs)
1176
768
      return false;
1177
399
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
399
    if (VectorList.ElementWidth != ElementWidth)
1180
305
      return false;
1181
94
    return VectorList.NumElements == NumElements;
1182
94
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 4u, 8u, 8u>() const
Line
Count
Source
1172
1.89k
  bool isTypedVectorList() const {
1173
1.89k
    if (Kind != k_VectorList)
1174
766
      return false;
1175
1.12k
    if (VectorList.Count != NumRegs)
1176
768
      return false;
1177
360
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
360
    if (VectorList.ElementWidth != ElementWidth)
1180
242
      return false;
1181
118
    return VectorList.NumElements == NumElements;
1182
118
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 4u, 8u, 16u>() const
Line
Count
Source
1172
1.84k
  bool isTypedVectorList() const {
1173
1.84k
    if (Kind != k_VectorList)
1174
766
      return false;
1175
1.08k
    if (VectorList.Count != NumRegs)
1176
768
      return false;
1177
314
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
314
    if (VectorList.ElementWidth != ElementWidth)
1180
216
      return false;
1181
98
    return VectorList.NumElements == NumElements;
1182
98
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 4u, 0u, 8u>() const
Line
Count
Source
1172
212
  bool isTypedVectorList() const {
1173
212
    if (Kind != k_VectorList)
1174
90
      return false;
1175
122
    if (VectorList.Count != NumRegs)
1176
12
      return false;
1177
110
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
110
    if (VectorList.ElementWidth != ElementWidth)
1180
84
      return false;
1181
26
    return VectorList.NumElements == NumElements;
1182
26
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 4u, 0u, 64u>() const
Line
Count
Source
1172
194
  bool isTypedVectorList() const {
1173
194
    if (Kind != k_VectorList)
1174
90
      return false;
1175
104
    if (VectorList.Count != NumRegs)
1176
12
      return false;
1177
92
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
92
    if (VectorList.ElementWidth != ElementWidth)
1180
56
      return false;
1181
36
    return VectorList.NumElements == NumElements;
1182
36
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 4u, 0u, 16u>() const
Line
Count
Source
1172
180
  bool isTypedVectorList() const {
1173
180
    if (Kind != k_VectorList)
1174
90
      return false;
1175
90
    if (VectorList.Count != NumRegs)
1176
12
      return false;
1177
78
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
78
    if (VectorList.ElementWidth != ElementWidth)
1180
58
      return false;
1181
20
    return VectorList.NumElements == NumElements;
1182
20
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 4u, 0u, 32u>() const
Line
Count
Source
1172
162
  bool isTypedVectorList() const {
1173
162
    if (Kind != k_VectorList)
1174
90
      return false;
1175
72
    if (VectorList.Count != NumRegs)
1176
12
      return false;
1177
60
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
60
    if (VectorList.ElementWidth != ElementWidth)
1180
42
      return false;
1181
18
    return VectorList.NumElements == NumElements;
1182
18
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 1u, 16u, 8u>() const
Line
Count
Source
1172
1.53k
  bool isTypedVectorList() const {
1173
1.53k
    if (Kind != k_VectorList)
1174
590
      return false;
1175
948
    if (VectorList.Count != NumRegs)
1176
473
      return false;
1177
475
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
475
    if (VectorList.ElementWidth != ElementWidth)
1180
337
      return false;
1181
138
    return VectorList.NumElements == NumElements;
1182
138
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 1u, 1u, 64u>() const
Line
Count
Source
1172
1.46k
  bool isTypedVectorList() const {
1173
1.46k
    if (Kind != k_VectorList)
1174
590
      return false;
1175
875
    if (VectorList.Count != NumRegs)
1176
445
      return false;
1177
430
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
430
    if (VectorList.ElementWidth != ElementWidth)
1180
327
      return false;
1181
103
    return VectorList.NumElements == NumElements;
1182
103
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 1u, 2u, 64u>() const
Line
Count
Source
1172
1.44k
  bool isTypedVectorList() const {
1173
1.44k
    if (Kind != k_VectorList)
1174
590
      return false;
1175
850
    if (VectorList.Count != NumRegs)
1176
445
      return false;
1177
405
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
405
    if (VectorList.ElementWidth != ElementWidth)
1180
327
      return false;
1181
78
    return VectorList.NumElements == NumElements;
1182
78
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 1u, 2u, 32u>() const
Line
Count
Source
1172
1.41k
  bool isTypedVectorList() const {
1173
1.41k
    if (Kind != k_VectorList)
1174
590
      return false;
1175
827
    if (VectorList.Count != NumRegs)
1176
445
      return false;
1177
382
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
382
    if (VectorList.ElementWidth != ElementWidth)
1180
288
      return false;
1181
94
    return VectorList.NumElements == NumElements;
1182
94
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 1u, 4u, 16u>() const
Line
Count
Source
1172
1.39k
  bool isTypedVectorList() const {
1173
1.39k
    if (Kind != k_VectorList)
1174
590
      return false;
1175
805
    if (VectorList.Count != NumRegs)
1176
445
      return false;
1177
360
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
360
    if (VectorList.ElementWidth != ElementWidth)
1180
249
      return false;
1181
111
    return VectorList.NumElements == NumElements;
1182
111
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 1u, 4u, 32u>() const
Line
Count
Source
1172
1.36k
  bool isTypedVectorList() const {
1173
1.36k
    if (Kind != k_VectorList)
1174
590
      return false;
1175
778
    if (VectorList.Count != NumRegs)
1176
445
      return false;
1177
333
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
333
    if (VectorList.ElementWidth != ElementWidth)
1180
264
      return false;
1181
69
    return VectorList.NumElements == NumElements;
1182
69
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 1u, 8u, 8u>() const
Line
Count
Source
1172
1.34k
  bool isTypedVectorList() const {
1173
1.34k
    if (Kind != k_VectorList)
1174
590
      return false;
1175
757
    if (VectorList.Count != NumRegs)
1176
445
      return false;
1177
312
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
312
    if (VectorList.ElementWidth != ElementWidth)
1180
213
      return false;
1181
99
    return VectorList.NumElements == NumElements;
1182
99
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 1u, 8u, 16u>() const
Line
Count
Source
1172
1.32k
  bool isTypedVectorList() const {
1173
1.32k
    if (Kind != k_VectorList)
1174
590
      return false;
1175
732
    if (VectorList.Count != NumRegs)
1176
445
      return false;
1177
287
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
287
    if (VectorList.ElementWidth != ElementWidth)
1180
201
      return false;
1181
86
    return VectorList.NumElements == NumElements;
1182
86
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 1u, 0u, 8u>() const
Line
Count
Source
1172
446
  bool isTypedVectorList() const {
1173
446
    if (Kind != k_VectorList)
1174
190
      return false;
1175
256
    if (VectorList.Count != NumRegs)
1176
108
      return false;
1177
148
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
148
    if (VectorList.ElementWidth != ElementWidth)
1180
103
      return false;
1181
45
    return VectorList.NumElements == NumElements;
1182
45
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 1u, 0u, 64u>() const
Line
Count
Source
1172
428
  bool isTypedVectorList() const {
1173
428
    if (Kind != k_VectorList)
1174
190
      return false;
1175
238
    if (VectorList.Count != NumRegs)
1176
108
      return false;
1177
130
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
130
    if (VectorList.ElementWidth != ElementWidth)
1180
100
      return false;
1181
30
    return VectorList.NumElements == NumElements;
1182
30
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 1u, 0u, 16u>() const
Line
Count
Source
1172
414
  bool isTypedVectorList() const {
1173
414
    if (Kind != k_VectorList)
1174
190
      return false;
1175
224
    if (VectorList.Count != NumRegs)
1176
108
      return false;
1177
116
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
116
    if (VectorList.ElementWidth != ElementWidth)
1180
84
      return false;
1181
32
    return VectorList.NumElements == NumElements;
1182
32
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 1u, 0u, 32u>() const
Line
Count
Source
1172
398
  bool isTypedVectorList() const {
1173
398
    if (Kind != k_VectorList)
1174
190
      return false;
1175
208
    if (VectorList.Count != NumRegs)
1176
108
      return false;
1177
100
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
100
    if (VectorList.ElementWidth != ElementWidth)
1180
79
      return false;
1181
21
    return VectorList.NumElements == NumElements;
1182
21
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 3u, 16u, 8u>() const
Line
Count
Source
1172
1.88k
  bool isTypedVectorList() const {
1173
1.88k
    if (Kind != k_VectorList)
1174
774
      return false;
1175
1.11k
    if (VectorList.Count != NumRegs)
1176
496
      return false;
1177
616
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
616
    if (VectorList.ElementWidth != ElementWidth)
1180
456
      return false;
1181
160
    return VectorList.NumElements == NumElements;
1182
160
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 3u, 1u, 64u>() const
Line
Count
Source
1172
1.30k
  bool isTypedVectorList() const {
1173
1.30k
    if (Kind != k_VectorList)
1174
590
      return false;
1175
716
    if (VectorList.Count != NumRegs)
1176
462
      return false;
1177
254
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
254
    if (VectorList.ElementWidth != ElementWidth)
1180
190
      return false;
1181
64
    return VectorList.NumElements == NumElements;
1182
64
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 3u, 2u, 64u>() const
Line
Count
Source
1172
1.77k
  bool isTypedVectorList() const {
1173
1.77k
    if (Kind != k_VectorList)
1174
774
      return false;
1175
1.00k
    if (VectorList.Count != NumRegs)
1176
474
      return false;
1177
526
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
526
    if (VectorList.ElementWidth != ElementWidth)
1180
437
      return false;
1181
89
    return VectorList.NumElements == NumElements;
1182
89
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 3u, 2u, 32u>() const
Line
Count
Source
1172
1.72k
  bool isTypedVectorList() const {
1173
1.72k
    if (Kind != k_VectorList)
1174
774
      return false;
1175
955
    if (VectorList.Count != NumRegs)
1176
474
      return false;
1177
481
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
481
    if (VectorList.ElementWidth != ElementWidth)
1180
325
      return false;
1181
156
    return VectorList.NumElements == NumElements;
1182
156
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 3u, 4u, 16u>() const
Line
Count
Source
1172
1.68k
  bool isTypedVectorList() const {
1173
1.68k
    if (Kind != k_VectorList)
1174
774
      return false;
1175
915
    if (VectorList.Count != NumRegs)
1176
474
      return false;
1177
441
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
441
    if (VectorList.ElementWidth != ElementWidth)
1180
281
      return false;
1181
160
    return VectorList.NumElements == NumElements;
1182
160
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 3u, 4u, 32u>() const
Line
Count
Source
1172
1.64k
  bool isTypedVectorList() const {
1173
1.64k
    if (Kind != k_VectorList)
1174
774
      return false;
1175
868
    if (VectorList.Count != NumRegs)
1176
474
      return false;
1177
394
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
394
    if (VectorList.ElementWidth != ElementWidth)
1180
281
      return false;
1181
113
    return VectorList.NumElements == NumElements;
1182
113
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 3u, 8u, 8u>() const
Line
Count
Source
1172
1.60k
  bool isTypedVectorList() const {
1173
1.60k
    if (Kind != k_VectorList)
1174
774
      return false;
1175
827
    if (VectorList.Count != NumRegs)
1176
474
      return false;
1177
353
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
353
    if (VectorList.ElementWidth != ElementWidth)
1180
254
      return false;
1181
99
    return VectorList.NumElements == NumElements;
1182
99
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 3u, 8u, 16u>() const
Line
Count
Source
1172
1.55k
  bool isTypedVectorList() const {
1173
1.55k
    if (Kind != k_VectorList)
1174
774
      return false;
1175
784
    if (VectorList.Count != NumRegs)
1176
474
      return false;
1177
310
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
310
    if (VectorList.ElementWidth != ElementWidth)
1180
193
      return false;
1181
117
    return VectorList.NumElements == NumElements;
1182
117
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 3u, 0u, 8u>() const
Line
Count
Source
1172
210
  bool isTypedVectorList() const {
1173
210
    if (Kind != k_VectorList)
1174
84
      return false;
1175
126
    if (VectorList.Count != NumRegs)
1176
12
      return false;
1177
114
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
114
    if (VectorList.ElementWidth != ElementWidth)
1180
96
      return false;
1181
18
    return VectorList.NumElements == NumElements;
1182
18
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 3u, 0u, 64u>() const
Line
Count
Source
1172
196
  bool isTypedVectorList() const {
1173
196
    if (Kind != k_VectorList)
1174
84
      return false;
1175
112
    if (VectorList.Count != NumRegs)
1176
12
      return false;
1177
100
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
100
    if (VectorList.ElementWidth != ElementWidth)
1180
80
      return false;
1181
20
    return VectorList.NumElements == NumElements;
1182
20
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 3u, 0u, 16u>() const
Line
Count
Source
1172
178
  bool isTypedVectorList() const {
1173
178
    if (Kind != k_VectorList)
1174
84
      return false;
1175
94
    if (VectorList.Count != NumRegs)
1176
12
      return false;
1177
82
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
82
    if (VectorList.ElementWidth != ElementWidth)
1180
52
      return false;
1181
30
    return VectorList.NumElements == NumElements;
1182
30
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 3u, 0u, 32u>() const
Line
Count
Source
1172
164
  bool isTypedVectorList() const {
1173
164
    if (Kind != k_VectorList)
1174
84
      return false;
1175
80
    if (VectorList.Count != NumRegs)
1176
12
      return false;
1177
68
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
68
    if (VectorList.ElementWidth != ElementWidth)
1180
30
      return false;
1181
38
    return VectorList.NumElements == NumElements;
1182
38
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 2u, 16u, 8u>() const
Line
Count
Source
1172
1.73k
  bool isTypedVectorList() const {
1173
1.73k
    if (Kind != k_VectorList)
1174
760
      return false;
1175
971
    if (VectorList.Count != NumRegs)
1176
355
      return false;
1177
616
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
616
    if (VectorList.ElementWidth != ElementWidth)
1180
450
      return false;
1181
166
    return VectorList.NumElements == NumElements;
1182
166
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 2u, 1u, 64u>() const
Line
Count
Source
1172
1.15k
  bool isTypedVectorList() const {
1173
1.15k
    if (Kind != k_VectorList)
1174
590
      return false;
1175
566
    if (VectorList.Count != NumRegs)
1176
311
      return false;
1177
255
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
255
    if (VectorList.ElementWidth != ElementWidth)
1180
184
      return false;
1181
71
    return VectorList.NumElements == NumElements;
1182
71
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 2u, 2u, 64u>() const
Line
Count
Source
1172
1.62k
  bool isTypedVectorList() const {
1173
1.62k
    if (Kind != k_VectorList)
1174
760
      return false;
1175
865
    if (VectorList.Count != NumRegs)
1176
335
      return false;
1177
530
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
530
    if (VectorList.ElementWidth != ElementWidth)
1180
436
      return false;
1181
94
    return VectorList.NumElements == NumElements;
1182
94
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 2u, 2u, 32u>() const
Line
Count
Source
1172
1.58k
  bool isTypedVectorList() const {
1173
1.58k
    if (Kind != k_VectorList)
1174
760
      return false;
1175
822
    if (VectorList.Count != NumRegs)
1176
335
      return false;
1177
487
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
487
    if (VectorList.ElementWidth != ElementWidth)
1180
336
      return false;
1181
151
    return VectorList.NumElements == NumElements;
1182
151
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 2u, 4u, 16u>() const
Line
Count
Source
1172
1.54k
  bool isTypedVectorList() const {
1173
1.54k
    if (Kind != k_VectorList)
1174
760
      return false;
1175
782
    if (VectorList.Count != NumRegs)
1176
335
      return false;
1177
447
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
447
    if (VectorList.ElementWidth != ElementWidth)
1180
292
      return false;
1181
155
    return VectorList.NumElements == NumElements;
1182
155
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 2u, 4u, 32u>() const
Line
Count
Source
1172
1.49k
  bool isTypedVectorList() const {
1173
1.49k
    if (Kind != k_VectorList)
1174
760
      return false;
1175
733
    if (VectorList.Count != NumRegs)
1176
335
      return false;
1177
398
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
398
    if (VectorList.ElementWidth != ElementWidth)
1180
292
      return false;
1181
106
    return VectorList.NumElements == NumElements;
1182
106
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 2u, 8u, 8u>() const
Line
Count
Source
1172
1.45k
  bool isTypedVectorList() const {
1173
1.45k
    if (Kind != k_VectorList)
1174
760
      return false;
1175
694
    if (VectorList.Count != NumRegs)
1176
335
      return false;
1177
359
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
359
    if (VectorList.ElementWidth != ElementWidth)
1180
248
      return false;
1181
111
    return VectorList.NumElements == NumElements;
1182
111
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 2u, 8u, 16u>() const
Line
Count
Source
1172
1.40k
  bool isTypedVectorList() const {
1173
1.40k
    if (Kind != k_VectorList)
1174
760
      return false;
1175
649
    if (VectorList.Count != NumRegs)
1176
335
      return false;
1177
314
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
314
    if (VectorList.ElementWidth != ElementWidth)
1180
204
      return false;
1181
110
    return VectorList.NumElements == NumElements;
1182
110
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 2u, 0u, 8u>() const
Line
Count
Source
1172
230
  bool isTypedVectorList() const {
1173
230
    if (Kind != k_VectorList)
1174
84
      return false;
1175
146
    if (VectorList.Count != NumRegs)
1176
24
      return false;
1177
122
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
122
    if (VectorList.ElementWidth != ElementWidth)
1180
90
      return false;
1181
32
    return VectorList.NumElements == NumElements;
1182
32
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 2u, 0u, 64u>() const
Line
Count
Source
1172
214
  bool isTypedVectorList() const {
1173
214
    if (Kind != k_VectorList)
1174
84
      return false;
1175
130
    if (VectorList.Count != NumRegs)
1176
24
      return false;
1177
106
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
106
    if (VectorList.ElementWidth != ElementWidth)
1180
86
      return false;
1181
20
    return VectorList.NumElements == NumElements;
1182
20
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 2u, 0u, 16u>() const
Line
Count
Source
1172
196
  bool isTypedVectorList() const {
1173
196
    if (Kind != k_VectorList)
1174
84
      return false;
1175
112
    if (VectorList.Count != NumRegs)
1176
24
      return false;
1177
88
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
88
    if (VectorList.ElementWidth != ElementWidth)
1180
58
      return false;
1181
30
    return VectorList.NumElements == NumElements;
1182
30
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)1, 2u, 0u, 32u>() const
Line
Count
Source
1172
180
  bool isTypedVectorList() const {
1173
180
    if (Kind != k_VectorList)
1174
84
      return false;
1175
96
    if (VectorList.Count != NumRegs)
1176
24
      return false;
1177
72
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
72
    if (VectorList.ElementWidth != ElementWidth)
1180
42
      return false;
1181
30
    return VectorList.NumElements == NumElements;
1182
30
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)2, 1u, 0u, 8u>() const
Line
Count
Source
1172
2.32k
  bool isTypedVectorList() const {
1173
2.32k
    if (Kind != k_VectorList)
1174
836
      return false;
1175
1.48k
    if (VectorList.Count != NumRegs)
1176
47
      return false;
1177
1.43k
    if (VectorList.RegisterKind != VectorKind)
1178
40
      return false;
1179
1.39k
    if (VectorList.ElementWidth != ElementWidth)
1180
1.01k
      return false;
1181
386
    return VectorList.NumElements == NumElements;
1182
386
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)2, 1u, 0u, 16u>() const
Line
Count
Source
1172
4.82k
  bool isTypedVectorList() const {
1173
4.82k
    if (Kind != k_VectorList)
1174
1.76k
      return false;
1175
3.05k
    if (VectorList.Count != NumRegs)
1176
71
      return false;
1177
2.98k
    if (VectorList.RegisterKind != VectorKind)
1178
66
      return false;
1179
2.92k
    if (VectorList.ElementWidth != ElementWidth)
1180
2.21k
      return false;
1181
703
    return VectorList.NumElements == NumElements;
1182
703
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)2, 1u, 0u, 32u>() const
Line
Count
Source
1172
19.3k
  bool isTypedVectorList() const {
1173
19.3k
    if (Kind != k_VectorList)
1174
7.30k
      return false;
1175
12.0k
    if (VectorList.Count != NumRegs)
1176
265
      return false;
1177
11.7k
    if (VectorList.RegisterKind != VectorKind)
1178
260
      return false;
1179
11.5k
    if (VectorList.ElementWidth != ElementWidth)
1180
7.17k
      return false;
1181
4.35k
    return VectorList.NumElements == NumElements;
1182
4.35k
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)2, 1u, 0u, 64u>() const
Line
Count
Source
1172
25.6k
  bool isTypedVectorList() const {
1173
25.6k
    if (Kind != k_VectorList)
1174
10.9k
      return false;
1175
14.6k
    if (VectorList.Count != NumRegs)
1176
401
      return false;
1177
14.2k
    if (VectorList.RegisterKind != VectorKind)
1178
390
      return false;
1179
13.9k
    if (VectorList.ElementWidth != ElementWidth)
1180
5.25k
      return false;
1181
8.64k
    return VectorList.NumElements == NumElements;
1182
8.64k
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)2, 2u, 0u, 8u>() const
Line
Count
Source
1172
361
  bool isTypedVectorList() const {
1173
361
    if (Kind != k_VectorList)
1174
33
      return false;
1175
328
    if (VectorList.Count != NumRegs)
1176
22
      return false;
1177
306
    if (VectorList.RegisterKind != VectorKind)
1178
16
      return false;
1179
290
    if (VectorList.ElementWidth != ElementWidth)
1180
2
      return false;
1181
288
    return VectorList.NumElements == NumElements;
1182
288
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)2, 2u, 0u, 16u>() const
Line
Count
Source
1172
315
  bool isTypedVectorList() const {
1173
315
    if (Kind != k_VectorList)
1174
9
      return false;
1175
306
    if (VectorList.Count != NumRegs)
1176
14
      return false;
1177
292
    if (VectorList.RegisterKind != VectorKind)
1178
12
      return false;
1179
280
    if (VectorList.ElementWidth != ElementWidth)
1180
0
      return false;
1181
280
    return VectorList.NumElements == NumElements;
1182
280
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)2, 2u, 0u, 32u>() const
Line
Count
Source
1172
313
  bool isTypedVectorList() const {
1173
313
    if (Kind != k_VectorList)
1174
7
      return false;
1175
306
    if (VectorList.Count != NumRegs)
1176
14
      return false;
1177
292
    if (VectorList.RegisterKind != VectorKind)
1178
12
      return false;
1179
280
    if (VectorList.ElementWidth != ElementWidth)
1180
0
      return false;
1181
280
    return VectorList.NumElements == NumElements;
1182
280
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)2, 2u, 0u, 64u>() const
Line
Count
Source
1172
325
  bool isTypedVectorList() const {
1173
325
    if (Kind != k_VectorList)
1174
13
      return false;
1175
312
    if (VectorList.Count != NumRegs)
1176
16
      return false;
1177
296
    if (VectorList.RegisterKind != VectorKind)
1178
14
      return false;
1179
282
    if (VectorList.ElementWidth != ElementWidth)
1180
0
      return false;
1181
282
    return VectorList.NumElements == NumElements;
1182
282
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)2, 3u, 0u, 8u>() const
Line
Count
Source
1172
282
  bool isTypedVectorList() const {
1173
282
    if (Kind != k_VectorList)
1174
0
      return false;
1175
282
    if (VectorList.Count != NumRegs)
1176
12
      return false;
1177
270
    if (VectorList.RegisterKind != VectorKind)
1178
12
      return false;
1179
258
    if (VectorList.ElementWidth != ElementWidth)
1180
0
      return false;
1181
258
    return VectorList.NumElements == NumElements;
1182
258
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)2, 3u, 0u, 16u>() const
Line
Count
Source
1172
294
  bool isTypedVectorList() const {
1173
294
    if (Kind != k_VectorList)
1174
0
      return false;
1175
294
    if (VectorList.Count != NumRegs)
1176
12
      return false;
1177
282
    if (VectorList.RegisterKind != VectorKind)
1178
12
      return false;
1179
270
    if (VectorList.ElementWidth != ElementWidth)
1180
0
      return false;
1181
270
    return VectorList.NumElements == NumElements;
1182
270
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)2, 3u, 0u, 32u>() const
Line
Count
Source
1172
294
  bool isTypedVectorList() const {
1173
294
    if (Kind != k_VectorList)
1174
0
      return false;
1175
294
    if (VectorList.Count != NumRegs)
1176
12
      return false;
1177
282
    if (VectorList.RegisterKind != VectorKind)
1178
12
      return false;
1179
270
    if (VectorList.ElementWidth != ElementWidth)
1180
0
      return false;
1181
270
    return VectorList.NumElements == NumElements;
1182
270
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)2, 3u, 0u, 64u>() const
Line
Count
Source
1172
294
  bool isTypedVectorList() const {
1173
294
    if (Kind != k_VectorList)
1174
0
      return false;
1175
294
    if (VectorList.Count != NumRegs)
1176
12
      return false;
1177
282
    if (VectorList.RegisterKind != VectorKind)
1178
12
      return false;
1179
270
    if (VectorList.ElementWidth != ElementWidth)
1180
0
      return false;
1181
270
    return VectorList.NumElements == NumElements;
1182
270
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)2, 4u, 0u, 8u>() const
Line
Count
Source
1172
270
  bool isTypedVectorList() const {
1173
270
    if (Kind != k_VectorList)
1174
0
      return false;
1175
270
    if (VectorList.Count != NumRegs)
1176
12
      return false;
1177
258
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
258
    if (VectorList.ElementWidth != ElementWidth)
1180
0
      return false;
1181
258
    return VectorList.NumElements == NumElements;
1182
258
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)2, 4u, 0u, 16u>() const
Line
Count
Source
1172
282
  bool isTypedVectorList() const {
1173
282
    if (Kind != k_VectorList)
1174
0
      return false;
1175
282
    if (VectorList.Count != NumRegs)
1176
12
      return false;
1177
270
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
270
    if (VectorList.ElementWidth != ElementWidth)
1180
0
      return false;
1181
270
    return VectorList.NumElements == NumElements;
1182
270
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)2, 4u, 0u, 32u>() const
Line
Count
Source
1172
282
  bool isTypedVectorList() const {
1173
282
    if (Kind != k_VectorList)
1174
0
      return false;
1175
282
    if (VectorList.Count != NumRegs)
1176
12
      return false;
1177
270
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
270
    if (VectorList.ElementWidth != ElementWidth)
1180
0
      return false;
1181
270
    return VectorList.NumElements == NumElements;
1182
270
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isTypedVectorList<((anonymous namespace)::RegKind)2, 4u, 0u, 64u>() const
Line
Count
Source
1172
282
  bool isTypedVectorList() const {
1173
282
    if (Kind != k_VectorList)
1174
0
      return false;
1175
282
    if (VectorList.Count != NumRegs)
1176
12
      return false;
1177
270
    if (VectorList.RegisterKind != VectorKind)
1178
0
      return false;
1179
270
    if (VectorList.ElementWidth != ElementWidth)
1180
0
      return false;
1181
270
    return VectorList.NumElements == NumElements;
1182
270
  }
1183
1184
  template <int Min, int Max>
1185
2.67k
  DiagnosticPredicate isVectorIndex() const {
1186
2.67k
    if (Kind != k_VectorIndex)
1187
47
      return DiagnosticPredicateTy::NoMatch;
1188
2.63k
    if (VectorIndex.Val >= Min && 
VectorIndex.Val <= Max2.63k
)
1189
2.06k
      return DiagnosticPredicateTy::Match;
1190
570
    return DiagnosticPredicateTy::NearMatch;
1191
570
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isVectorIndex<0, 63>() const
Line
Count
Source
1185
28
  DiagnosticPredicate isVectorIndex() const {
1186
28
    if (Kind != k_VectorIndex)
1187
0
      return DiagnosticPredicateTy::NoMatch;
1188
28
    if (VectorIndex.Val >= Min && VectorIndex.Val <= Max)
1189
20
      return DiagnosticPredicateTy::Match;
1190
8
    return DiagnosticPredicateTy::NearMatch;
1191
8
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isVectorIndex<0, 7>() const
Line
Count
Source
1185
868
  DiagnosticPredicate isVectorIndex() const {
1186
868
    if (Kind != k_VectorIndex)
1187
11
      return DiagnosticPredicateTy::NoMatch;
1188
857
    if (VectorIndex.Val >= Min && VectorIndex.Val <= Max)
1189
662
      return DiagnosticPredicateTy::Match;
1190
195
    return DiagnosticPredicateTy::NearMatch;
1191
195
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isVectorIndex<0, 31>() const
Line
Count
Source
1185
28
  DiagnosticPredicate isVectorIndex() const {
1186
28
    if (Kind != k_VectorIndex)
1187
0
      return DiagnosticPredicateTy::NoMatch;
1188
28
    if (VectorIndex.Val >= Min && VectorIndex.Val <= Max)
1189
20
      return DiagnosticPredicateTy::Match;
1190
8
    return DiagnosticPredicateTy::NearMatch;
1191
8
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isVectorIndex<0, 3>() const
Line
Count
Source
1185
951
  DiagnosticPredicate isVectorIndex() const {
1186
951
    if (Kind != k_VectorIndex)
1187
14
      return DiagnosticPredicateTy::NoMatch;
1188
937
    if (VectorIndex.Val >= Min && VectorIndex.Val <= Max)
1189
698
      return DiagnosticPredicateTy::Match;
1190
239
    return DiagnosticPredicateTy::NearMatch;
1191
239
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isVectorIndex<0, 15>() const
Line
Count
Source
1185
234
  DiagnosticPredicate isVectorIndex() const {
1186
234
    if (Kind != k_VectorIndex)
1187
10
      return DiagnosticPredicateTy::NoMatch;
1188
224
    if (VectorIndex.Val >= Min && VectorIndex.Val <= Max)
1189
204
      return DiagnosticPredicateTy::Match;
1190
20
    return DiagnosticPredicateTy::NearMatch;
1191
20
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isVectorIndex<1, 1>() const
Line
Count
Source
1185
13
  DiagnosticPredicate isVectorIndex() const {
1186
13
    if (Kind != k_VectorIndex)
1187
0
      return DiagnosticPredicateTy::NoMatch;
1188
13
    if (VectorIndex.Val >= Min && 
VectorIndex.Val <= Max12
)
1189
11
      return DiagnosticPredicateTy::Match;
1190
2
    return DiagnosticPredicateTy::NearMatch;
1191
2
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isVectorIndex<0, 1>() const
Line
Count
Source
1185
556
  DiagnosticPredicate isVectorIndex() const {
1186
556
    if (Kind != k_VectorIndex)
1187
12
      return DiagnosticPredicateTy::NoMatch;
1188
544
    if (VectorIndex.Val >= Min && VectorIndex.Val <= Max)
1189
446
      return DiagnosticPredicateTy::Match;
1190
98
    return DiagnosticPredicateTy::NearMatch;
1191
98
  }
1192
1193
1.21M
  bool isToken() const override { return Kind == k_Token; }
1194
1195
0
  bool isTokenEqual(StringRef Str) const {
1196
0
    return Kind == k_Token && getToken() == Str;
1197
0
  }
1198
1.08k
  bool isSysCR() const { return Kind == k_SysCR; }
1199
7.57k
  bool isPrefetch() const { return Kind == k_Prefetch; }
1200
3
  bool isPSBHint() const { return Kind == k_PSBHint; }
1201
12
  bool isBTIHint() const { return Kind == k_BTIHint; }
1202
1.11k
  bool isShiftExtend() const { return Kind == k_ShiftExtend; }
1203
675
  bool isShifter() const {
1204
675
    if (!isShiftExtend())
1205
0
      return false;
1206
675
1207
675
    AArch64_AM::ShiftExtendType ST = getShiftExtendType();
1208
675
    return (ST == AArch64_AM::LSL || 
ST == AArch64_AM::LSR394
||
1209
675
            
ST == AArch64_AM::ASR280
||
ST == AArch64_AM::ROR160
||
1210
675
            
ST == AArch64_AM::MSL139
);
1211
675
  }
1212
1213
1.20k
  template <unsigned ImmEnum> DiagnosticPredicate isExactFPImm() const {
1214
1.20k
    if (Kind != k_FPImm)
1215
192
      return DiagnosticPredicateTy::NoMatch;
1216
1.00k
1217
1.00k
    if (getFPImmIsExact()) {
1218
896
      // Lookup the immediate from table of supported immediates.
1219
896
      auto *Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmEnum);
1220
896
      assert(Desc && "Unknown enum value");
1221
896
1222
896
      // Calculate its FP value.
1223
896
      APFloat RealVal(APFloat::IEEEdouble());
1224
896
      if (RealVal.convertFromString(Desc->Repr, APFloat::rmTowardZero) !=
1225
896
          APFloat::opOK)
1226
896
        
llvm_unreachable0
("FP immediate is not exact");
1227
896
1228
896
      if (getFPImm().bitwiseIsEqual(RealVal))
1229
522
        return DiagnosticPredicateTy::Match;
1230
486
    }
1231
486
1232
486
    return DiagnosticPredicateTy::NearMatch;
1233
486
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isExactFPImm<1u>() const
Line
Count
Source
1213
285
  template <unsigned ImmEnum> DiagnosticPredicate isExactFPImm() const {
1214
285
    if (Kind != k_FPImm)
1215
48
      return DiagnosticPredicateTy::NoMatch;
1216
237
1217
237
    if (getFPImmIsExact()) {
1218
205
      // Lookup the immediate from table of supported immediates.
1219
205
      auto *Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmEnum);
1220
205
      assert(Desc && "Unknown enum value");
1221
205
1222
205
      // Calculate its FP value.
1223
205
      APFloat RealVal(APFloat::IEEEdouble());
1224
205
      if (RealVal.convertFromString(Desc->Repr, APFloat::rmTowardZero) !=
1225
205
          APFloat::opOK)
1226
205
        
llvm_unreachable0
("FP immediate is not exact");
1227
205
1228
205
      if (getFPImm().bitwiseIsEqual(RealVal))
1229
80
        return DiagnosticPredicateTy::Match;
1230
157
    }
1231
157
1232
157
    return DiagnosticPredicateTy::NearMatch;
1233
157
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isExactFPImm<2u>() const
Line
Count
Source
1213
556
  template <unsigned ImmEnum> DiagnosticPredicate isExactFPImm() const {
1214
556
    if (Kind != k_FPImm)
1215
84
      return DiagnosticPredicateTy::NoMatch;
1216
472
1217
472
    if (getFPImmIsExact()) {
1218
424
      // Lookup the immediate from table of supported immediates.
1219
424
      auto *Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmEnum);
1220
424
      assert(Desc && "Unknown enum value");
1221
424
1222
424
      // Calculate its FP value.
1223
424
      APFloat RealVal(APFloat::IEEEdouble());
1224
424
      if (RealVal.convertFromString(Desc->Repr, APFloat::rmTowardZero) !=
1225
424
          APFloat::opOK)
1226
424
        
llvm_unreachable0
("FP immediate is not exact");
1227
424
1228
424
      if (getFPImm().bitwiseIsEqual(RealVal))
1229
312
        return DiagnosticPredicateTy::Match;
1230
160
    }
1231
160
1232
160
    return DiagnosticPredicateTy::NearMatch;
1233
160
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isExactFPImm<3u>() const
Line
Count
Source
1213
76
  template <unsigned ImmEnum> DiagnosticPredicate isExactFPImm() const {
1214
76
    if (Kind != k_FPImm)
1215
12
      return DiagnosticPredicateTy::NoMatch;
1216
64
1217
64
    if (getFPImmIsExact()) {
1218
56
      // Lookup the immediate from table of supported immediates.
1219
56
      auto *Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmEnum);
1220
56
      assert(Desc && "Unknown enum value");
1221
56
1222
56
      // Calculate its FP value.
1223
56
      APFloat RealVal(APFloat::IEEEdouble());
1224
56
      if (RealVal.convertFromString(Desc->Repr, APFloat::rmTowardZero) !=
1225
56
          APFloat::opOK)
1226
56
        
llvm_unreachable0
("FP immediate is not exact");
1227
56
1228
56
      if (getFPImm().bitwiseIsEqual(RealVal))
1229
40
        return DiagnosticPredicateTy::Match;
1230
24
    }
1231
24
1232
24
    return DiagnosticPredicateTy::NearMatch;
1233
24
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isExactFPImm<0u>() const
Line
Count
Source
1213
283
  template <unsigned ImmEnum> DiagnosticPredicate isExactFPImm() const {
1214
283
    if (Kind != k_FPImm)
1215
48
      return DiagnosticPredicateTy::NoMatch;
1216
235
1217
235
    if (getFPImmIsExact()) {
1218
211
      // Lookup the immediate from table of supported immediates.
1219
211
      auto *Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmEnum);
1220
211
      assert(Desc && "Unknown enum value");
1221
211
1222
211
      // Calculate its FP value.
1223
211
      APFloat RealVal(APFloat::IEEEdouble());
1224
211
      if (RealVal.convertFromString(Desc->Repr, APFloat::rmTowardZero) !=
1225
211
          APFloat::opOK)
1226
211
        
llvm_unreachable0
("FP immediate is not exact");
1227
211
1228
211
      if (getFPImm().bitwiseIsEqual(RealVal))
1229
90
        return DiagnosticPredicateTy::Match;
1230
145
    }
1231
145
1232
145
    return DiagnosticPredicateTy::NearMatch;
1233
145
  }
1234
1235
  template <unsigned ImmA, unsigned ImmB>
1236
568
  DiagnosticPredicate isExactFPImm() const {
1237
568
    DiagnosticPredicate Res = DiagnosticPredicateTy::NoMatch;
1238
568
    if ((Res = isExactFPImm<ImmA>()))
1239
170
      return DiagnosticPredicateTy::Match;
1240
398
    if ((Res = isExactFPImm<ImmB>()))
1241
220
      return DiagnosticPredicateTy::Match;
1242
178
    return Res;
1243
178
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isExactFPImm<1u, 2u>() const
Line
Count
Source
1236
216
  DiagnosticPredicate isExactFPImm() const {
1237
216
    DiagnosticPredicate Res = DiagnosticPredicateTy::NoMatch;
1238
216
    if ((Res = isExactFPImm<ImmA>()))
1239
60
      return DiagnosticPredicateTy::Match;
1240
156
    if ((Res = isExactFPImm<ImmB>()))
1241
90
      return DiagnosticPredicateTy::Match;
1242
66
    return Res;
1243
66
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isExactFPImm<1u, 3u>() const
Line
Count
Source
1236
69
  DiagnosticPredicate isExactFPImm() const {
1237
69
    DiagnosticPredicate Res = DiagnosticPredicateTy::NoMatch;
1238
69
    if ((Res = isExactFPImm<ImmA>()))
1239
20
      return DiagnosticPredicateTy::Match;
1240
49
    if ((Res = isExactFPImm<ImmB>()))
1241
25
      return DiagnosticPredicateTy::Match;
1242
24
    return Res;
1243
24
  }
AArch64AsmParser.cpp:llvm::DiagnosticPredicate (anonymous namespace)::AArch64Operand::isExactFPImm<0u, 2u>() const
Line
Count
Source
1236
283
  DiagnosticPredicate isExactFPImm() const {
1237
283
    DiagnosticPredicate Res = DiagnosticPredicateTy::NoMatch;
1238
283
    if ((Res = isExactFPImm<ImmA>()))
1239
90
      return DiagnosticPredicateTy::Match;
1240
193
    if ((Res = isExactFPImm<ImmB>()))
1241
105
      return DiagnosticPredicateTy::Match;
1242
88
    return Res;
1243
88
  }
1244
1245
426
  bool isExtend() const {
1246
426
    if (!isShiftExtend())
1247
0
      return false;
1248
426
1249
426
    AArch64_AM::ShiftExtendType ET = getShiftExtendType();
1250
426
    return (ET == AArch64_AM::UXTB || 
ET == AArch64_AM::SXTB397
||
1251
426
            
ET == AArch64_AM::UXTH370
||
ET == AArch64_AM::SXTH342
||
1252
426
            
ET == AArch64_AM::UXTW318
||
ET == AArch64_AM::SXTW247
||
1253
426
            
ET == AArch64_AM::UXTX187
||
ET == AArch64_AM::SXTX156
||
1254
426
            
ET == AArch64_AM::LSL112
) &&
1255
426
           
getShiftExtendAmount() <= 4378
;
1256
426
  }
1257
1258
42
  bool isExtend64() const {
1259
42
    if (!isExtend())
1260
2
      return false;
1261
40
    // Make sure the extend expects a 32-bit source register.
1262
40
    AArch64_AM::ShiftExtendType ET = getShiftExtendType();
1263
40
    return ET == AArch64_AM::UXTB || 
ET == AArch64_AM::SXTB36
||
1264
40
           
ET == AArch64_AM::UXTH31
||
ET == AArch64_AM::SXTH23
||
1265
40
           
ET == AArch64_AM::UXTW16
||
ET == AArch64_AM::SXTW9
;
1266
40
  }
1267
1268
70
  bool isExtendLSL64() const {
1269
70
    if (!isExtend())
1270
38
      return false;
1271
32
    AArch64_AM::ShiftExtendType ET = getShiftExtendType();
1272
32
    return (ET == AArch64_AM::UXTX || 
ET == AArch64_AM::SXTX16
||
1273
32
            
ET == AArch64_AM::LSL6
) &&
1274
32
           
getShiftExtendAmount() <= 430
;
1275
32
  }
1276
1277
47
  template<int Width> bool isMemXExtend() const {
1278
47
    if (!isExtend())
1279
0
      return false;
1280
47
    AArch64_AM::ShiftExtendType ET = getShiftExtendType();
1281
47
    return (ET == AArch64_AM::LSL || 
ET == AArch64_AM::SXTX22
) &&
1282
47
           
(43
getShiftExtendAmount() == Log2_32(Width / 8)43
||
1283
43
            
getShiftExtendAmount() == 020
);
1284
47
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMemXExtend<128>() const
Line
Count
Source
1277
6
  template<int Width> bool isMemXExtend() const {
1278
6
    if (!isExtend())
1279
0
      return false;
1280
6
    AArch64_AM::ShiftExtendType ET = getShiftExtendType();
1281
6
    return (ET == AArch64_AM::LSL || 
ET == AArch64_AM::SXTX3
) &&
1282
6
           (getShiftExtendAmount() == Log2_32(Width / 8) ||
1283
6
            
getShiftExtendAmount() == 03
);
1284
6
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMemXExtend<16>() const
Line
Count
Source
1277
6
  template<int Width> bool isMemXExtend() const {
1278
6
    if (!isExtend())
1279
0
      return false;
1280
6
    AArch64_AM::ShiftExtendType ET = getShiftExtendType();
1281
6
    return (ET == AArch64_AM::LSL || 
ET == AArch64_AM::SXTX3
) &&
1282
6
           (getShiftExtendAmount() == Log2_32(Width / 8) ||
1283
6
            
getShiftExtendAmount() == 03
);
1284
6
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMemXExtend<32>() const
Line
Count
Source
1277
15
  template<int Width> bool isMemXExtend() const {
1278
15
    if (!isExtend())
1279
0
      return false;
1280
15
    AArch64_AM::ShiftExtendType ET = getShiftExtendType();
1281
15
    return (ET == AArch64_AM::LSL || 
ET == AArch64_AM::SXTX9
) &&
1282
15
           
(11
getShiftExtendAmount() == Log2_32(Width / 8)11
||
1283
11
            
getShiftExtendAmount() == 05
);
1284
15
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMemXExtend<64>() const
Line
Count
Source
1277
14
  template<int Width> bool isMemXExtend() const {
1278
14
    if (!isExtend())
1279
0
      return false;
1280
14
    AArch64_AM::ShiftExtendType ET = getShiftExtendType();
1281
14
    return (ET == AArch64_AM::LSL || 
ET == AArch64_AM::SXTX5
) &&
1282
14
           (getShiftExtendAmount() == Log2_32(Width / 8) ||
1283
14
            
getShiftExtendAmount() == 07
);
1284
14
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMemXExtend<8>() const
Line
Count
Source
1277
6
  template<int Width> bool isMemXExtend() const {
1278
6
    if (!isExtend())
1279
0
      return false;
1280
6
    AArch64_AM::ShiftExtendType ET = getShiftExtendType();
1281
6
    return (ET == AArch64_AM::LSL || 
ET == AArch64_AM::SXTX2
) &&
1282
6
           (getShiftExtendAmount() == Log2_32(Width / 8) ||
1283
6
            
getShiftExtendAmount() == 02
);
1284
6
  }
1285
1286
64
  template<int Width> bool isMemWExtend() const {
1287
64
    if (!isExtend())
1288
2
      return false;
1289
62
    AArch64_AM::ShiftExtendType ET = getShiftExtendType();
1290
62
    return (ET == AArch64_AM::UXTW || 
ET == AArch64_AM::SXTW38
) &&
1291
62
           
(56
getShiftExtendAmount() == Log2_32(Width / 8)56
||
1292
56
            
getShiftExtendAmount() == 042
);
1293
62
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMemWExtend<128>() const
Line
Count
Source
1286
13
  template<int Width> bool isMemWExtend() const {
1287
13
    if (!isExtend())
1288
2
      return false;
1289
11
    AArch64_AM::ShiftExtendType ET = getShiftExtendType();
1290
11
    return (ET == AArch64_AM::UXTW || 
ET == AArch64_AM::SXTW5
) &&
1291
11
           (getShiftExtendAmount() == Log2_32(Width / 8) ||
1292
11
            
getShiftExtendAmount() == 08
);
1293
11
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMemWExtend<16>() const
Line
Count
Source
1286
12
  template<int Width> bool isMemWExtend() const {
1287
12
    if (!isExtend())
1288
0
      return false;
1289
12
    AArch64_AM::ShiftExtendType ET = getShiftExtendType();
1290
12
    return (ET == AArch64_AM::UXTW || 
ET == AArch64_AM::SXTW7
) &&
1291
12
           (getShiftExtendAmount() == Log2_32(Width / 8) ||
1292
12
            
getShiftExtendAmount() == 010
);
1293
12
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMemWExtend<32>() const
Line
Count
Source
1286
16
  template<int Width> bool isMemWExtend() const {
1287
16
    if (!isExtend())
1288
0
      return false;
1289
16
    AArch64_AM::ShiftExtendType ET = getShiftExtendType();
1290
16
    return (ET == AArch64_AM::UXTW || 
ET == AArch64_AM::SXTW11
) &&
1291
16
           
(12
getShiftExtendAmount() == Log2_32(Width / 8)12
||
1292
12
            
getShiftExtendAmount() == 010
);
1293
16
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMemWExtend<64>() const
Line
Count
Source
1286
15
  template<int Width> bool isMemWExtend() const {
1287
15
    if (!isExtend())
1288
0
      return false;
1289
15
    AArch64_AM::ShiftExtendType ET = getShiftExtendType();
1290
15
    return (ET == AArch64_AM::UXTW || 
ET == AArch64_AM::SXTW9
) &&
1291
15
           
(13
getShiftExtendAmount() == Log2_32(Width / 8)13
||
1292
13
            
getShiftExtendAmount() == 010
);
1293
15
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isMemWExtend<8>() const
Line
Count
Source
1286
8
  template<int Width> bool isMemWExtend() const {
1287
8
    if (!isExtend())
1288
0
      return false;
1289
8
    AArch64_AM::ShiftExtendType ET = getShiftExtendType();
1290
8
    return (ET == AArch64_AM::UXTW || 
ET == AArch64_AM::SXTW6
) &&
1291
8
           (getShiftExtendAmount() == Log2_32(Width / 8) ||
1292
8
            
getShiftExtendAmount() == 04
);
1293
8
  }
1294
1295
  template <unsigned width>
1296
419
  bool isArithmeticShifter() const {
1297
419
    if (!isShifter())
1298
120
      return false;
1299
299
1300
299
    // An arithmetic shifter is LSL, LSR, or ASR.
1301
299
    AArch64_AM::ShiftExtendType ST = getShiftExtendType();
1302
299
    return (ST == AArch64_AM::LSL || 
ST == AArch64_AM::LSR190
||
1303
299
            
ST == AArch64_AM::ASR93
) &&
getShiftExtendAmount() < width297
;
1304
299
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isArithmeticShifter<32u>() const
Line
Count
Source
1296
236
  bool isArithmeticShifter() const {
1297
236
    if (!isShifter())
1298
89
      return false;
1299
147
1300
147
    // An arithmetic shifter is LSL, LSR, or ASR.
1301
147
    AArch64_AM::ShiftExtendType ST = getShiftExtendType();
1302
147
    return (ST == AArch64_AM::LSL || 
ST == AArch64_AM::LSR86
||
1303
147
            
ST == AArch64_AM::ASR43
) && getShiftExtendAmount() < width;
1304
147
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isArithmeticShifter<64u>() const
Line
Count
Source
1296
183
  bool isArithmeticShifter() const {
1297
183
    if (!isShifter())
1298
31
      return false;
1299
152
1300
152
    // An arithmetic shifter is LSL, LSR, or ASR.
1301
152
    AArch64_AM::ShiftExtendType ST = getShiftExtendType();
1302
152
    return (ST == AArch64_AM::LSL || 
ST == AArch64_AM::LSR104
||
1303
152
            
ST == AArch64_AM::ASR50
) &&
getShiftExtendAmount() < width150
;
1304
152
  }
1305
1306
  template <unsigned width>
1307
123
  bool isLogicalShifter() const {
1308
123
    if (!isShifter())
1309
0
      return false;
1310
123
1311
123
    // A logical shifter is LSL, LSR, ASR or ROR.
1312
123
    AArch64_AM::ShiftExtendType ST = getShiftExtendType();
1313
123
    return (ST == AArch64_AM::LSL || 
ST == AArch64_AM::LSR65
||
1314
123
            
ST == AArch64_AM::ASR48
||
ST == AArch64_AM::ROR19
) &&
1315
123
           getShiftExtendAmount() < width;
1316
123
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isLogicalShifter<32u>() const
Line
Count
Source
1307
63
  bool isLogicalShifter() const {
1308
63
    if (!isShifter())
1309
0
      return false;
1310
63
1311
63
    // A logical shifter is LSL, LSR, ASR or ROR.
1312
63
    AArch64_AM::ShiftExtendType ST = getShiftExtendType();
1313
63
    return (ST == AArch64_AM::LSL || 
ST == AArch64_AM::LSR35
||
1314
63
            
ST == AArch64_AM::ASR26
||
ST == AArch64_AM::ROR10
) &&
1315
63
           getShiftExtendAmount() < width;
1316
63
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isLogicalShifter<64u>() const
Line
Count
Source
1307
60
  bool isLogicalShifter() const {
1308
60
    if (!isShifter())
1309
0
      return false;
1310
60
1311
60
    // A logical shifter is LSL, LSR, ASR or ROR.
1312
60
    AArch64_AM::ShiftExtendType ST = getShiftExtendType();
1313
60
    return (ST == AArch64_AM::LSL || 
ST == AArch64_AM::LSR30
||
1314
60
            
ST == AArch64_AM::ASR22
||
ST == AArch64_AM::ROR9
) &&
1315
60
           getShiftExtendAmount() < width;
1316
60
  }
1317
1318
15
  bool isMovImm32Shifter() const {
1319
15
    if (!isShifter())
1320
0
      return false;
1321
15
1322
15
    // A MOVi shifter is LSL of 0, 16, 32, or 48.
1323
15
    AArch64_AM::ShiftExtendType ST = getShiftExtendType();
1324
15
    if (ST != AArch64_AM::LSL)
1325
0
      return false;
1326
15
    uint64_t Val = getShiftExtendAmount();
1327
15
    return (Val == 0 || 
Val == 1613
);
1328
15
  }
1329
1330
16
  bool isMovImm64Shifter() const {
1331
16
    if (!isShifter())
1332
0
      return false;
1333
16
1334
16
    // A MOVi shifter is LSL of 0 or 16.
1335
16
    AArch64_AM::ShiftExtendType ST = getShiftExtendType();
1336
16
    if (ST != AArch64_AM::LSL)
1337
0
      return false;
1338
16
    uint64_t Val = getShiftExtendAmount();
1339
16
    return (Val == 0 || Val == 16 || 
Val == 3210
||
Val == 486
);
1340
16
  }
1341
1342
102
  bool isLogicalVecShifter() const {
1343
102
    if (!isShifter())
1344
0
      return false;
1345
102
1346
102
    // A logical vector shifter is a left shift by 0, 8, 16, or 24.
1347
102
    unsigned Shift = getShiftExtendAmount();
1348
102
    return getShiftExtendType() == AArch64_AM::LSL &&
1349
102
           
(83
Shift == 083
||
Shift == 867
||
Shift == 1635
||
Shift == 2418
);
1350
102
  }
1351
1352
27
  bool isLogicalVecHalfWordShifter() const {
1353
27
    if (!isLogicalVecShifter())
1354
2
      return false;
1355
25
1356
25
    // A logical vector shifter is a left shift by 0 or 8.
1357
25
    unsigned Shift = getShiftExtendAmount();
1358
25
    return getShiftExtendType() == AArch64_AM::LSL &&
1359
25
           (Shift == 0 || 
Shift == 817
);
1360
25
  }
1361
1362
18
  bool isMoveVecShifter() const {
1363
18
    if (!isShiftExtend())
1364
0
      return false;
1365
18
1366
18
    // A logical vector shifter is a left shift by 8 or 16.
1367
18
    unsigned Shift = getShiftExtendAmount();
1368
18
    return getShiftExtendType() == AArch64_AM::MSL &&
1369
18
           (Shift == 8 || 
Shift == 1610
);
1370
18
  }
1371
1372
  // Fallback unscaled operands are for aliases of LDR/STR that fall back
1373
  // to LDUR/STUR when the offset is not legal for the former but is for
1374
  // the latter. As such, in addition to checking for being a legal unscaled
1375
  // address, also check that it is not a legal scaled address. This avoids
1376
  // ambiguity in the matcher.
1377
  template<int Width>
1378
1.11k
  bool isSImm9OffsetFB() const {
1379
1.11k
    return isSImm<9>() && 
!isUImm12Offset<Width / 8>()228
;
1380
1.11k
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isSImm9OffsetFB<128>() const
Line
Count
Source
1378
95
  bool isSImm9OffsetFB() const {
1379
95
    return isSImm<9>() && 
!isUImm12Offset<Width / 8>()15
;
1380
95
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isSImm9OffsetFB<16>() const
Line
Count
Source
1378
222
  bool isSImm9OffsetFB() const {
1379
222
    return isSImm<9>() && 
!isUImm12Offset<Width / 8>()43
;
1380
222
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isSImm9OffsetFB<32>() const
Line
Count
Source
1378
237
  bool isSImm9OffsetFB() const {
1379
237
    return isSImm<9>() && 
!isUImm12Offset<Width / 8>()44
;
1380
237
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isSImm9OffsetFB<64>() const
Line
Count
Source
1378
345
  bool isSImm9OffsetFB() const {
1379
345
    return isSImm<9>() && 
!isUImm12Offset<Width / 8>()93
;
1380
345
  }
AArch64AsmParser.cpp:bool (anonymous namespace)::AArch64Operand::isSImm9OffsetFB<8>() const
Line
Count
Source
1378
216
  bool isSImm9OffsetFB() const {
1379
216
    return isSImm<9>() && 
!isUImm12Offset<Width / 8>()33
;
1380
216
  }
1381
1382
217
  bool isAdrpLabel() const {
1383
217
    // Validation was handled during parsing, so we just sanity check that
1384
217
    // something didn't go haywire.
1385
217
    if (!isImm())
1386
0
        return false;
1387
217
1388
217
    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1389
16
      int64_t Val = CE->getValue();
1390
16
      int64_t Min = - (4096 * (1LL << (21 - 1)));
1391
16
      int64_t Max = 4096 * ((1LL << (21 - 1)) - 1);
1392
16
      return (Val % 4096) == 0 && 
Val >= Min10
&&
Val <= Max8
;
1393
16
    }
1394
201
1395
201
    return true;
1396
201
  }
1397
1398
45
  bool isAdrLabel() const {
1399
45
    // Validation was handled during parsing, so we just sanity check that
1400
45
    // something didn't go haywire.
1401
45
    if (!isImm())
1402
0
        return false;
1403
45
1404
45
    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1405
15
      int64_t Val = CE->getValue();
1406
15
      int64_t Min = - (1LL << (21 - 1));
1407
15
      int64_t Max = ((1LL << (21 - 1)) - 1);
1408
15
      return Val >= Min && 
Val <= Max13
;
1409
15
    }
1410
30
1411
30
    return true;
1412
30
  }
1413
1414
8.32k
  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1415
8.32k
    // Add as immediates when possible.  Null MCExpr = 0.
1416
8.32k
    if (!Expr)
1417
0
      Inst.addOperand(MCOperand::createImm(0));
1418
8.32k
    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1419
7.18k
      Inst.addOperand(MCOperand::createImm(CE->getValue()));
1420
1.13k
    else
1421
1.13k
      Inst.addOperand(MCOperand::createExpr(Expr));
1422
8.32k
  }
1423
1424
66.9k
  void addRegOperands(MCInst &Inst, unsigned N) const {
1425
66.9k
    assert(N == 1 && "Invalid number of operands!");
1426
66.9k
    Inst.addOperand(MCOperand::createReg(getReg()));
1427
66.9k
  }
1428
1429
9
  void addGPR32as64Operands(MCInst &Inst, unsigned N) const {
1430
9
    assert(N == 1 && "Invalid number of operands!");
1431
9
    assert(
1432
9
        AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(getReg()));
1433
9
1434
9
    const MCRegisterInfo *RI = Ctx.getRegisterInfo();
1435
9
    uint32_t Reg = RI->getRegClass(AArch64::GPR32RegClassID).getRegister(
1436
9
        RI->getEncodingValue(getReg()));
1437
9
1438
9
    Inst.addOperand(MCOperand::createReg(Reg));
1439
9
  }
1440
1441
88
  void addGPR64as32Operands(MCInst &Inst, unsigned N) const {
1442
88
    assert(N == 1 && "Invalid number of operands!");
1443
88
    assert(
1444
88
        AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(getReg()));
1445
88
1446
88
    const MCRegisterInfo *RI = Ctx.getRegisterInfo();
1447
88
    uint32_t Reg = RI->getRegClass(AArch64::GPR64RegClassID).getRegister(
1448
88
        RI->getEncodingValue(getReg()));
1449
88
1450
88
    Inst.addOperand(MCOperand::createReg(Reg));
1451
88
  }
1452
1453
  template <int Width>
1454
17
  void addFPRasZPRRegOperands(MCInst &Inst, unsigned N) const {
1455
17
    unsigned Base;
1456
17
    switch (Width) {
1457
17
    
case 8: Base = AArch64::B0; break3
;
1458
17
    
case 16: Base = AArch64::H0; break3
;
1459
17
    
case 32: Base = AArch64::S0; break3
;
1460
17
    
case 64: Base = AArch64::D0; break5
;
1461
17
    
case 128: Base = AArch64::Q0; break3
;
1462
17
    default:
1463
0
      llvm_unreachable("Unsupported width");
1464
17
    }
1465
17
    Inst.addOperand(MCOperand::createReg(AArch64::Z0 + getReg() - Base));
1466
17
  }
AArch64AsmParser.cpp:void (anonymous namespace)::AArch64Operand::addFPRasZPRRegOperands<128>(llvm::MCInst&, unsigned int) const
Line
Count
Source
1454
3
  void addFPRasZPRRegOperands(MCInst &Inst, unsigned N) const {
1455
3
    unsigned Base;
1456
3
    switch (Width) {
1457
3
    
case 8: Base = AArch64::B0; break0
;
1458
3
    
case 16: Base = AArch64::H0; break0
;
1459
3
    
case 32: Base = AArch64::S0; break0
;
1460
3
    
case 64: Base = AArch64::D0; break0
;
1461
3
    case 128: Base = AArch64::Q0; break;
1462
3
    default:
1463
0
      llvm_unreachable("Unsupported width");
1464
3
    }
1465
3
    Inst.addOperand(MCOperand::createReg(AArch64::Z0 + getReg() - Base));
1466
3
  }
AArch64AsmParser.cpp:void (anonymous namespace)::AArch64Operand::addFPRasZPRRegOperands<16>(llvm::MCInst&, unsigned int) const
Line
Count
Source
1454
3
  void addFPRasZPRRegOperands(MCInst &Inst, unsigned N) const {
1455
3
    unsigned Base;
1456
3
    switch (Width) {
1457
3
    
case 8: Base = AArch64::B0; break0
;
1458
3
    case 16:  Base = AArch64::H0; break;
1459
3
    
case 32: Base = AArch64::S0; break0
;
1460
3
    
case 64: Base = AArch64::D0; break0
;
1461
3
    
case 128: Base = AArch64::Q0; break0
;
1462
3
    default:
1463
0
      llvm_unreachable("Unsupported width");
1464
3
    }
1465
3
    Inst.addOperand(MCOperand::createReg(AArch64::Z0 + getReg() - Base));
1466
3
  }
AArch64AsmParser.cpp:void (anonymous namespace)::AArch64Operand::addFPRasZPRRegOperands<32>(llvm::MCInst&, unsigned int) const
Line
Count
Source
1454
3
  void addFPRasZPRRegOperands(MCInst &Inst, unsigned N) const {
1455
3
    unsigned Base;
1456
3
    switch (Width) {
1457
3
    
case 8: Base = AArch64::B0; break0
;
1458
3
    
case 16: Base = AArch64::H0; break0
;
1459
3
    case 32:  Base = AArch64::S0; break;
1460
3
    
case 64: Base = AArch64::D0; break0
;
1461
3
    
case 128: Base = AArch64::Q0; break0
;
1462
3
    default:
1463
0
      llvm_unreachable("Unsupported width");
1464
3
    }
1465
3
    Inst.addOperand(MCOperand::createReg(AArch64::Z0 + getReg() - Base));
1466
3
  }
AArch64AsmParser.cpp:void (anonymous namespace)::AArch64Operand::addFPRasZPRRegOperands<64>(llvm::MCInst&, unsigned int) const
Line
Count
Source
1454
5
  void addFPRasZPRRegOperands(MCInst &Inst, unsigned N) const {
1455
5
    unsigned Base;
1456
5
    switch (Width) {
1457
5
    
case 8: Base = AArch64::B0; break0
;
1458
5
    
case 16: Base = AArch64::H0; break0
;
1459
5
    
case 32: Base = AArch64::S0; break0
;
1460
5
    case 64:  Base = AArch64::D0; break;
1461
5
    
case 128: Base = AArch64::Q0; break0
;
1462
5
    default:
1463
0
      llvm_unreachable("Unsupported width");
1464
5
    }
1465
5
    Inst.addOperand(MCOperand::createReg(AArch64::Z0 + getReg() - Base));
1466