Coverage Report

Created: 2019-07-24 05:18

/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
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//===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===//
2
//
3
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4
// See https://llvm.org/LICENSE.txt for license information.
5
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6
//
7
//===----------------------------------------------------------------------===//
8
9
#include "MCTargetDesc/AArch64FixupKinds.h"
10
#include "MCTargetDesc/AArch64MCExpr.h"
11
#include "MCTargetDesc/AArch64MCTargetDesc.h"
12
#include "Utils/AArch64BaseInfo.h"
13
#include "llvm/ADT/Triple.h"
14
#include "llvm/BinaryFormat/MachO.h"
15
#include "llvm/MC/MCAsmBackend.h"
16
#include "llvm/MC/MCAssembler.h"
17
#include "llvm/MC/MCContext.h"
18
#include "llvm/MC/MCDirectives.h"
19
#include "llvm/MC/MCELFObjectWriter.h"
20
#include "llvm/MC/MCFixupKindInfo.h"
21
#include "llvm/MC/MCObjectWriter.h"
22
#include "llvm/MC/MCRegisterInfo.h"
23
#include "llvm/MC/MCSectionELF.h"
24
#include "llvm/MC/MCSectionMachO.h"
25
#include "llvm/MC/MCTargetOptions.h"
26
#include "llvm/MC/MCValue.h"
27
#include "llvm/Support/ErrorHandling.h"
28
#include "llvm/Support/TargetRegistry.h"
29
using namespace llvm;
30
31
namespace {
32
33
class AArch64AsmBackend : public MCAsmBackend {
34
  static const unsigned PCRelFlagVal =
35
      MCFixupKindInfo::FKF_IsAlignedDownTo32Bits | MCFixupKindInfo::FKF_IsPCRel;
36
  Triple TheTriple;
37
38
public:
39
  AArch64AsmBackend(const Target &T, const Triple &TT, bool IsLittleEndian)
40
      : MCAsmBackend(IsLittleEndian ? support::little : support::big),
41
12.0k
        TheTriple(TT) {}
42
43
0
  unsigned getNumFixupKinds() const override {
44
0
    return AArch64::NumTargetFixupKinds;
45
0
  }
46
47
  Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
48
49
12.9M
  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
50
12.9M
    const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
51
12.9M
        // This table *must* be in the order that the fixup_* kinds are defined
52
12.9M
        // in AArch64FixupKinds.h.
53
12.9M
        //
54
12.9M
        // Name                           Offset (bits) Size (bits)     Flags
55
12.9M
        {"fixup_aarch64_pcrel_adr_imm21", 0, 32, PCRelFlagVal},
56
12.9M
        {"fixup_aarch64_pcrel_adrp_imm21", 0, 32, PCRelFlagVal},
57
12.9M
        {"fixup_aarch64_add_imm12", 10, 12, 0},
58
12.9M
        {"fixup_aarch64_ldst_imm12_scale1", 10, 12, 0},
59
12.9M
        {"fixup_aarch64_ldst_imm12_scale2", 10, 12, 0},
60
12.9M
        {"fixup_aarch64_ldst_imm12_scale4", 10, 12, 0},
61
12.9M
        {"fixup_aarch64_ldst_imm12_scale8", 10, 12, 0},
62
12.9M
        {"fixup_aarch64_ldst_imm12_scale16", 10, 12, 0},
63
12.9M
        {"fixup_aarch64_ldr_pcrel_imm19", 5, 19, PCRelFlagVal},
64
12.9M
        {"fixup_aarch64_movw", 5, 16, 0},
65
12.9M
        {"fixup_aarch64_pcrel_branch14", 5, 14, PCRelFlagVal},
66
12.9M
        {"fixup_aarch64_pcrel_branch19", 5, 19, PCRelFlagVal},
67
12.9M
        {"fixup_aarch64_pcrel_branch26", 0, 26, PCRelFlagVal},
68
12.9M
        {"fixup_aarch64_pcrel_call26", 0, 26, PCRelFlagVal},
69
12.9M
        {"fixup_aarch64_tlsdesc_call", 0, 0, 0}};
70
12.9M
71
12.9M
    if (Kind < FirstTargetFixupKind)
72
1.38M
      return MCAsmBackend::getFixupKindInfo(Kind);
73
11.5M
74
11.5M
    assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
75
11.5M
           "Invalid kind!");
76
11.5M
    return Infos[Kind - FirstTargetFixupKind];
77
11.5M
  }
78
79
  void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
80
                  const MCValue &Target, MutableArrayRef<char> Data,
81
                  uint64_t Value, bool IsResolved,
82
                  const MCSubtargetInfo *STI) const override;
83
84
  bool mayNeedRelaxation(const MCInst &Inst,
85
                         const MCSubtargetInfo &STI) const override;
86
  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
87
                            const MCRelaxableFragment *DF,
88
                            const MCAsmLayout &Layout) const override;
89
  void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
90
                        MCInst &Res) const override;
91
  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
92
93
0
  void HandleAssemblerFlag(MCAssemblerFlag Flag) {}
94
95
0
  unsigned getPointerSize() const { return 8; }
96
97
  unsigned getFixupKindContainereSizeInBytes(unsigned Kind) const;
98
99
  bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
100
                             const MCValue &Target) override;
101
};
102
103
} // end anonymous namespace
104
105
/// The number of bytes the fixup may change.
106
4.27M
static unsigned getFixupKindNumBytes(unsigned Kind) {
107
4.27M
  switch (Kind) {
108
4.27M
  default:
109
0
    llvm_unreachable("Unknown fixup kind!");
110
4.27M
111
4.27M
  case FK_NONE:
112
23
  case AArch64::fixup_aarch64_tlsdesc_call:
113
23
    return 0;
114
23
115
24.9k
  case FK_Data_1:
116
24.9k
    return 1;
117
23
118
10.8k
  case FK_Data_2:
119
10.8k
  case FK_SecRel_2:
120
10.8k
    return 2;
121
10.8k
122
1.77M
  case AArch64::fixup_aarch64_movw:
123
1.77M
  case AArch64::fixup_aarch64_pcrel_branch14:
124
1.77M
  case AArch64::fixup_aarch64_add_imm12:
125
1.77M
  case AArch64::fixup_aarch64_ldst_imm12_scale1:
126
1.77M
  case AArch64::fixup_aarch64_ldst_imm12_scale2:
127
1.77M
  case AArch64::fixup_aarch64_ldst_imm12_scale4:
128
1.77M
  case AArch64::fixup_aarch64_ldst_imm12_scale8:
129
1.77M
  case AArch64::fixup_aarch64_ldst_imm12_scale16:
130
1.77M
  case AArch64::fixup_aarch64_ldr_pcrel_imm19:
131
1.77M
  case AArch64::fixup_aarch64_pcrel_branch19:
132
1.77M
    return 3;
133
1.77M
134
2.15M
  case AArch64::fixup_aarch64_pcrel_adr_imm21:
135
2.15M
  case AArch64::fixup_aarch64_pcrel_adrp_imm21:
136
2.15M
  case AArch64::fixup_aarch64_pcrel_branch26:
137
2.15M
  case AArch64::fixup_aarch64_pcrel_call26:
138
2.15M
  case FK_Data_4:
139
2.15M
  case FK_SecRel_4:
140
2.15M
    return 4;
141
2.15M
142
2.15M
  case FK_Data_8:
143
311k
    return 8;
144
4.27M
  }
145
4.27M
}
146
147
2.35k
static unsigned AdrImmBits(unsigned Value) {
148
2.35k
  unsigned lo2 = Value & 0x3;
149
2.35k
  unsigned hi19 = (Value & 0x1ffffc) >> 2;
150
2.35k
  return (hi19 << 5) | (lo2 << 29);
151
2.35k
}
152
153
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target,
154
                                 uint64_t Value, MCContext &Ctx,
155
1.70M
                                 const Triple &TheTriple, bool IsResolved) {
156
1.70M
  unsigned Kind = Fixup.getKind();
157
1.70M
  int64_t SignedValue = static_cast<int64_t>(Value);
158
1.70M
  switch (Kind) {
159
1.70M
  default:
160
0
    llvm_unreachable("Unknown fixup kind!");
161
1.70M
  case AArch64::fixup_aarch64_pcrel_adr_imm21:
162
2.35k
    if (SignedValue > 2097151 || 
SignedValue < -20971522.35k
)
163
2
      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
164
2.35k
    return AdrImmBits(Value & 0x1fffffULL);
165
1.70M
  case AArch64::fixup_aarch64_pcrel_adrp_imm21:
166
4
    assert(!IsResolved);
167
4
    if (TheTriple.isOSBinFormatCOFF())
168
3
      return AdrImmBits(Value & 0x1fffffULL);
169
1
    return AdrImmBits((Value & 0x1fffff000ULL) >> 12);
170
1.03M
  case AArch64::fixup_aarch64_ldr_pcrel_imm19:
171
1.03M
  case AArch64::fixup_aarch64_pcrel_branch19:
172
1.03M
    // Signed 21-bit immediate
173
1.03M
    if (SignedValue > 2097151 || 
SignedValue < -20971521.03M
)
174
5
      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
175
1.03M
    if (Value & 0x3)
176
4
      Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");
177
1.03M
    // Low two bits are not encoded.
178
1.03M
    return (Value >> 2) & 0x7ffff;
179
1.03M
  case AArch64::fixup_aarch64_add_imm12:
180
98
  case AArch64::fixup_aarch64_ldst_imm12_scale1:
181
98
    if (TheTriple.isOSBinFormatCOFF() && 
!IsResolved5
)
182
4
      Value &= 0xfff;
183
98
    // Unsigned 12-bit immediate
184
98
    if (Value >= 0x1000)
185
20
      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
186
98
    return Value;
187
98
  case AArch64::fixup_aarch64_ldst_imm12_scale2:
188
4
    if (TheTriple.isOSBinFormatCOFF() && 
!IsResolved2
)
189
0
      Value &= 0xfff;
190
4
    // Unsigned 12-bit immediate which gets multiplied by 2
191
4
    if (Value >= 0x2000)
192
2
      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
193
4
    if (Value & 0x1)
194
2
      Ctx.reportError(Fixup.getLoc(), "fixup must be 2-byte aligned");
195
4
    return Value >> 1;
196
98
  case AArch64::fixup_aarch64_ldst_imm12_scale4:
197
4
    if (TheTriple.isOSBinFormatCOFF() && 
!IsResolved2
)
198
0
      Value &= 0xfff;
199
4
    // Unsigned 12-bit immediate which gets multiplied by 4
200
4
    if (Value >= 0x4000)
201
2
      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
202
4
    if (Value & 0x3)
203
2
      Ctx.reportError(Fixup.getLoc(), "fixup must be 4-byte aligned");
204
4
    return Value >> 2;
205
98
  case AArch64::fixup_aarch64_ldst_imm12_scale8:
206
5
    if (TheTriple.isOSBinFormatCOFF() && 
!IsResolved3
)
207
1
      Value &= 0xfff;
208
5
    // Unsigned 12-bit immediate which gets multiplied by 8
209
5
    if (Value >= 0x8000)
210
2
      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
211
5
    if (Value & 0x7)
212
4
      Ctx.reportError(Fixup.getLoc(), "fixup must be 8-byte aligned");
213
5
    return Value >> 3;
214
98
  case AArch64::fixup_aarch64_ldst_imm12_scale16:
215
4
    if (TheTriple.isOSBinFormatCOFF() && 
!IsResolved2
)
216
0
      Value &= 0xfff;
217
4
    // Unsigned 12-bit immediate which gets multiplied by 16
218
4
    if (Value >= 0x10000)
219
2
      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
220
4
    if (Value & 0xf)
221
2
      Ctx.reportError(Fixup.getLoc(), "fixup must be 16-byte aligned");
222
4
    return Value >> 4;
223
98
  case AArch64::fixup_aarch64_movw: {
224
38
    AArch64MCExpr::VariantKind RefKind =
225
38
        static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
226
38
    if (AArch64MCExpr::getSymbolLoc(RefKind) != AArch64MCExpr::VK_ABS &&
227
38
        
AArch64MCExpr::getSymbolLoc(RefKind) != AArch64MCExpr::VK_SABS14
) {
228
2
      // VK_GOTTPREL, VK_TPREL, VK_DTPREL are movw fixups, but they can't
229
2
      // ever be resolved in the assembler.
230
2
      Ctx.reportError(Fixup.getLoc(),
231
2
                      "relocation for a thread-local variable points to an "
232
2
                      "absolute symbol");
233
2
      return Value;
234
2
    }
235
36
236
36
    if (!IsResolved) {
237
0
      // FIXME: Figure out when this can actually happen, and verify our
238
0
      // behavior.
239
0
      Ctx.reportError(Fixup.getLoc(), "unresolved movw fixup not yet "
240
0
                                      "implemented");
241
0
      return Value;
242
0
    }
243
36
244
36
    if (AArch64MCExpr::getSymbolLoc(RefKind) == AArch64MCExpr::VK_SABS) {
245
12
      switch (AArch64MCExpr::getAddressFrag(RefKind)) {
246
12
      case AArch64MCExpr::VK_G0:
247
6
        break;
248
12
      case AArch64MCExpr::VK_G1:
249
4
        SignedValue = SignedValue >> 16;
250
4
        break;
251
12
      case AArch64MCExpr::VK_G2:
252
2
        SignedValue = SignedValue >> 32;
253
2
        break;
254
12
      case AArch64MCExpr::VK_G3:
255
0
        SignedValue = SignedValue >> 48;
256
0
        break;
257
12
      default:
258
0
        llvm_unreachable("Variant kind doesn't correspond to fixup");
259
24
      }
260
24
261
24
    } else {
262
24
      switch (AArch64MCExpr::getAddressFrag(RefKind)) {
263
24
      case AArch64MCExpr::VK_G0:
264
8
        break;
265
24
      case AArch64MCExpr::VK_G1:
266
8
        Value = Value >> 16;
267
8
        break;
268
24
      case AArch64MCExpr::VK_G2:
269
6
        Value = Value >> 32;
270
6
        break;
271
24
      case AArch64MCExpr::VK_G3:
272
2
        Value = Value >> 48;
273
2
        break;
274
24
      default:
275
0
        llvm_unreachable("Variant kind doesn't correspond to fixup");
276
36
      }
277
36
    }
278
36
279
36
    if (RefKind & AArch64MCExpr::VK_NC) {
280
12
      Value &= 0xFFFF;
281
12
    }
282
24
    else if (AArch64MCExpr::getSymbolLoc(RefKind) == AArch64MCExpr::VK_SABS) {
283
12
      if (SignedValue > 0xFFFF || 
SignedValue < -0xFFFF8
)
284
4
        Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
285
12
286
12
      // Invert the negative immediate because it will feed into a MOVN.
287
12
      if (SignedValue < 0)
288
4
        SignedValue = ~SignedValue;
289
12
      Value = static_cast<uint64_t>(SignedValue);
290
12
    }
291
12
    else if (Value > 0xFFFF) {
292
4
      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
293
4
    }
294
36
    return Value;
295
36
  }
296
86.8k
  case AArch64::fixup_aarch64_pcrel_branch14:
297
86.8k
    // Signed 16-bit immediate
298
86.8k
    if (SignedValue > 32767 || 
SignedValue < -3276886.8k
)
299
2
      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
300
86.8k
    // Low two bits are not encoded (4-byte alignment assumed).
301
86.8k
    if (Value & 0x3)
302
2
      Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");
303
86.8k
    return (Value >> 2) & 0x3fff;
304
295k
  case AArch64::fixup_aarch64_pcrel_branch26:
305
295k
  case AArch64::fixup_aarch64_pcrel_call26:
306
295k
    // Signed 28-bit immediate
307
295k
    if (SignedValue > 134217727 || 
SignedValue < -134217728295k
)
308
2
      Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
309
295k
    // Low two bits are not encoded (4-byte alignment assumed).
310
295k
    if (Value & 0x3)
311
2
      Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");
312
295k
    return (Value >> 2) & 0x3ffffff;
313
295k
  case FK_NONE:
314
288k
  case FK_Data_1:
315
288k
  case FK_Data_2:
316
288k
  case FK_Data_4:
317
288k
  case FK_Data_8:
318
288k
  case FK_SecRel_2:
319
288k
  case FK_SecRel_4:
320
288k
    return Value;
321
1.70M
  }
322
1.70M
}
323
324
4
Optional<MCFixupKind> AArch64AsmBackend::getFixupKind(StringRef Name) const {
325
4
  if (TheTriple.isOSBinFormatELF() && Name == "R_AARCH64_NONE")
326
4
    return FK_NONE;
327
0
  return MCAsmBackend::getFixupKind(Name);
328
0
}
329
330
/// getFixupKindContainereSizeInBytes - The number of bytes of the
331
/// container involved in big endian or 0 if the item is little endian
332
1.70M
unsigned AArch64AsmBackend::getFixupKindContainereSizeInBytes(unsigned Kind) const {
333
1.70M
  if (Endian == support::little)
334
1.70M
    return 0;
335
21
336
21
  switch (Kind) {
337
21
  default:
338
0
    llvm_unreachable("Unknown fixup kind!");
339
21
340
21
  case FK_Data_1:
341
0
    return 1;
342
21
  case FK_Data_2:
343
0
    return 2;
344
21
  case FK_Data_4:
345
20
    return 4;
346
21
  case FK_Data_8:
347
0
    return 8;
348
21
349
21
  case AArch64::fixup_aarch64_tlsdesc_call:
350
1
  case AArch64::fixup_aarch64_movw:
351
1
  case AArch64::fixup_aarch64_pcrel_branch14:
352
1
  case AArch64::fixup_aarch64_add_imm12:
353
1
  case AArch64::fixup_aarch64_ldst_imm12_scale1:
354
1
  case AArch64::fixup_aarch64_ldst_imm12_scale2:
355
1
  case AArch64::fixup_aarch64_ldst_imm12_scale4:
356
1
  case AArch64::fixup_aarch64_ldst_imm12_scale8:
357
1
  case AArch64::fixup_aarch64_ldst_imm12_scale16:
358
1
  case AArch64::fixup_aarch64_ldr_pcrel_imm19:
359
1
  case AArch64::fixup_aarch64_pcrel_branch19:
360
1
  case AArch64::fixup_aarch64_pcrel_adr_imm21:
361
1
  case AArch64::fixup_aarch64_pcrel_adrp_imm21:
362
1
  case AArch64::fixup_aarch64_pcrel_branch26:
363
1
  case AArch64::fixup_aarch64_pcrel_call26:
364
1
    // Instructions are always little endian
365
1
    return 0;
366
21
  }
367
21
}
368
369
void AArch64AsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
370
                                   const MCValue &Target,
371
                                   MutableArrayRef<char> Data, uint64_t Value,
372
                                   bool IsResolved,
373
4.27M
                                   const MCSubtargetInfo *STI) const {
374
4.27M
  unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
375
4.27M
  if (!Value)
376
2.57M
    return; // Doesn't change encoding.
377
1.70M
  MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
378
1.70M
  MCContext &Ctx = Asm.getContext();
379
1.70M
  int64_t SignedValue = static_cast<int64_t>(Value);
380
1.70M
  // Apply any target-specific value adjustments.
381
1.70M
  Value = adjustFixupValue(Fixup, Target, Value, Ctx, TheTriple, IsResolved);
382
1.70M
383
1.70M
  // Shift the value into position.
384
1.70M
  Value <<= Info.TargetOffset;
385
1.70M
386
1.70M
  unsigned Offset = Fixup.getOffset();
387
1.70M
  assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
388
1.70M
389
1.70M
  // Used to point to big endian bytes.
390
1.70M
  unsigned FulleSizeInBytes = getFixupKindContainereSizeInBytes(Fixup.getKind());
391
1.70M
392
1.70M
  // For each byte of the fragment that the fixup touches, mask in the
393
1.70M
  // bits from the fixup value.
394
1.70M
  if (FulleSizeInBytes == 0) {
395
1.70M
    // Handle as little-endian
396
8.12M
    for (unsigned i = 0; i != NumBytes; 
++i6.41M
) {
397
6.41M
      Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
398
6.41M
    }
399
1.70M
  } else {
400
20
    // Handle as big-endian
401
20
    assert((Offset + FulleSizeInBytes) <= Data.size() && "Invalid fixup size!");
402
20
    assert(NumBytes <= FulleSizeInBytes && "Invalid fixup size!");
403
100
    for (unsigned i = 0; i != NumBytes; 
++i80
) {
404
80
      unsigned Idx = FulleSizeInBytes - 1 - i;
405
80
      Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
406
80
    }
407
20
  }
408
1.70M
409
1.70M
  // FIXME: getFixupKindInfo() and getFixupKindNumBytes() could be fixed to
410
1.70M
  // handle this more cleanly. This may affect the output of -show-mc-encoding.
411
1.70M
  AArch64MCExpr::VariantKind RefKind =
412
1.70M
    static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
413
1.70M
  if (AArch64MCExpr::getSymbolLoc(RefKind) == AArch64MCExpr::VK_SABS) {
414
12
    // If the immediate is negative, generate MOVN else MOVZ.
415
12
    // (Bit 30 = 0) ==> MOVN, (Bit 30 = 1) ==> MOVZ.
416
12
    if (SignedValue < 0)
417
4
      Data[Offset + 3] &= ~(1 << 6);
418
8
    else
419
8
      Data[Offset + 3] |= (1 << 6);
420
12
  }
421
1.70M
}
422
423
bool AArch64AsmBackend::mayNeedRelaxation(const MCInst &Inst,
424
14.5M
                                          const MCSubtargetInfo &STI) const {
425
14.5M
  return false;
426
14.5M
}
427
428
bool AArch64AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
429
                                             uint64_t Value,
430
                                             const MCRelaxableFragment *DF,
431
0
                                             const MCAsmLayout &Layout) const {
432
0
  // FIXME:  This isn't correct for AArch64. Just moving the "generic" logic
433
0
  // into the targets for now.
434
0
  //
435
0
  // Relax if the value is too big for a (signed) i8.
436
0
  return int64_t(Value) != int64_t(int8_t(Value));
437
0
}
438
439
void AArch64AsmBackend::relaxInstruction(const MCInst &Inst,
440
                                         const MCSubtargetInfo &STI,
441
0
                                         MCInst &Res) const {
442
0
  llvm_unreachable("AArch64AsmBackend::relaxInstruction() unimplemented");
443
0
}
444
445
242k
bool AArch64AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
446
242k
  // If the count is not 4-byte aligned, we must be writing data into the text
447
242k
  // section (otherwise we have unaligned instructions, and thus have far
448
242k
  // bigger problems), so just write zeros instead.
449
242k
  OS.write_zeros(Count % 4);
450
242k
451
242k
  // We are properly aligned, so write NOPs as requested.
452
242k
  Count /= 4;
453
244k
  for (uint64_t i = 0; i != Count; 
++i2.05k
)
454
2.05k
    support::endian::write<uint32_t>(OS, 0xd503201f, Endian);
455
242k
  return true;
456
242k
}
457
458
bool AArch64AsmBackend::shouldForceRelocation(const MCAssembler &Asm,
459
                                              const MCFixup &Fixup,
460
1.56M
                                              const MCValue &Target) {
461
1.56M
  unsigned Kind = Fixup.getKind();
462
1.56M
  if (Kind == FK_NONE)
463
1
    return true;
464
1.56M
465
1.56M
  // The ADRP instruction adds some multiple of 0x1000 to the current PC &
466
1.56M
  // ~0xfff. This means that the required offset to reach a symbol can vary by
467
1.56M
  // up to one step depending on where the ADRP is in memory. For example:
468
1.56M
  //
469
1.56M
  //     ADRP x0, there
470
1.56M
  //  there:
471
1.56M
  //
472
1.56M
  // If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and
473
1.56M
  // we'll need that as an offset. At any other address "there" will be in the
474
1.56M
  // same page as the ADRP and the instruction should encode 0x0. Assuming the
475
1.56M
  // section isn't 0x1000-aligned, we therefore need to delegate this decision
476
1.56M
  // to the linker -- a relocation!
477
1.56M
  if (Kind == AArch64::fixup_aarch64_pcrel_adrp_imm21)
478
28
    return true;
479
1.56M
480
1.56M
  AArch64MCExpr::VariantKind RefKind =
481
1.56M
      static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
482
1.56M
  AArch64MCExpr::VariantKind SymLoc = AArch64MCExpr::getSymbolLoc(RefKind);
483
1.56M
  // LDR GOT relocations need a relocation
484
1.56M
  if (Kind == AArch64::fixup_aarch64_ldr_pcrel_imm19 &&
485
1.56M
      
SymLoc == AArch64MCExpr::VK_GOT8
)
486
0
    return true;
487
1.56M
  return false;
488
1.56M
}
489
490
namespace {
491
492
namespace CU {
493
494
/// Compact unwind encoding values.
495
enum CompactUnwindEncodings {
496
  /// A "frameless" leaf function, where no non-volatile registers are
497
  /// saved. The return remains in LR throughout the function.
498
  UNWIND_ARM64_MODE_FRAMELESS = 0x02000000,
499
500
  /// No compact unwind encoding available. Instead the low 23-bits of
501
  /// the compact unwind encoding is the offset of the DWARF FDE in the
502
  /// __eh_frame section. This mode is never used in object files. It is only
503
  /// generated by the linker in final linked images, which have only DWARF info
504
  /// for a function.
505
  UNWIND_ARM64_MODE_DWARF = 0x03000000,
506
507
  /// This is a standard arm64 prologue where FP/LR are immediately
508
  /// pushed on the stack, then SP is copied to FP. If there are any
509
  /// non-volatile register saved, they are copied into the stack fame in pairs
510
  /// in a contiguous ranger right below the saved FP/LR pair. Any subset of the
511
  /// five X pairs and four D pairs can be saved, but the memory layout must be
512
  /// in register number order.
513
  UNWIND_ARM64_MODE_FRAME = 0x04000000,
514
515
  /// Frame register pair encodings.
516
  UNWIND_ARM64_FRAME_X19_X20_PAIR = 0x00000001,
517
  UNWIND_ARM64_FRAME_X21_X22_PAIR = 0x00000002,
518
  UNWIND_ARM64_FRAME_X23_X24_PAIR = 0x00000004,
519
  UNWIND_ARM64_FRAME_X25_X26_PAIR = 0x00000008,
520
  UNWIND_ARM64_FRAME_X27_X28_PAIR = 0x00000010,
521
  UNWIND_ARM64_FRAME_D8_D9_PAIR = 0x00000100,
522
  UNWIND_ARM64_FRAME_D10_D11_PAIR = 0x00000200,
523
  UNWIND_ARM64_FRAME_D12_D13_PAIR = 0x00000400,
524
  UNWIND_ARM64_FRAME_D14_D15_PAIR = 0x00000800
525
};
526
527
} // end CU namespace
528
529
// FIXME: This should be in a separate file.
530
class DarwinAArch64AsmBackend : public AArch64AsmBackend {
531
  const MCRegisterInfo &MRI;
532
  bool IsILP32;
533
534
  /// Encode compact unwind stack adjustment for frameless functions.
535
  /// See UNWIND_ARM64_FRAMELESS_STACK_SIZE_MASK in compact_unwind_encoding.h.
536
  /// The stack size always needs to be 16 byte aligned.
537
265
  uint32_t encodeStackAdjustment(uint32_t StackSize) const {
538
265
    return (StackSize / 16) << 12;
539
265
  }
540
541
public:
542
  DarwinAArch64AsmBackend(const Target &T, const Triple &TT,
543
                          const MCRegisterInfo &MRI, bool IsILP32)
544
      : AArch64AsmBackend(T, TT, /*IsLittleEndian*/ true), MRI(MRI),
545
7.68k
        IsILP32(IsILP32) {}
546
547
  std::unique_ptr<MCObjectTargetWriter>
548
7.68k
  createObjectTargetWriter() const override {
549
7.68k
    if (IsILP32)
550
1
      return createAArch64MachObjectWriter(
551
1
          MachO::CPU_TYPE_ARM64_32, MachO::CPU_SUBTYPE_ARM64_32_V8, true);
552
7.67k
    else
553
7.67k
      return createAArch64MachObjectWriter(MachO::CPU_TYPE_ARM64,
554
7.67k
                                           MachO::CPU_SUBTYPE_ARM64_ALL, false);
555
7.68k
  }
556
557
  /// Generate the compact unwind encoding from the CFI directives.
558
  uint32_t generateCompactUnwindEncoding(
559
39.0k
                             ArrayRef<MCCFIInstruction> Instrs) const override {
560
39.0k
    if (Instrs.empty())
561
8.32k
      return CU::UNWIND_ARM64_MODE_FRAMELESS;
562
30.6k
563
30.6k
    bool HasFP = false;
564
30.6k
    unsigned StackSize = 0;
565
30.6k
566
30.6k
    uint32_t CompactUnwindEncoding = 0;
567
141k
    for (size_t i = 0, e = Instrs.size(); i != e; 
++i110k
) {
568
110k
      const MCCFIInstruction &Inst = Instrs[i];
569
110k
570
110k
      switch (Inst.getOperation()) {
571
110k
      default:
572
0
        // Cannot handle this directive:  bail out.
573
0
        return CU::UNWIND_ARM64_MODE_DWARF;
574
110k
      case MCCFIInstruction::OpDefCfa: {
575
30.2k
        // Defines a frame pointer.
576
30.2k
        unsigned XReg =
577
30.2k
            getXRegFromWReg(MRI.getLLVMRegNum(Inst.getRegister(), true));
578
30.2k
579
30.2k
        // Other CFA registers than FP are not supported by compact unwind.
580
30.2k
        // Fallback on DWARF.
581
30.2k
        // FIXME: When opt-remarks are supported in MC, add a remark to notify
582
30.2k
        // the user.
583
30.2k
        if (XReg != AArch64::FP)
584
1
          return CU::UNWIND_ARM64_MODE_DWARF;
585
30.2k
586
30.2k
        assert(XReg == AArch64::FP && "Invalid frame pointer!");
587
30.2k
        assert(i + 2 < e && "Insufficient CFI instructions to define a frame!");
588
30.2k
589
30.2k
        const MCCFIInstruction &LRPush = Instrs[++i];
590
30.2k
        assert(LRPush.getOperation() == MCCFIInstruction::OpOffset &&
591
30.2k
               "Link register not pushed!");
592
30.2k
        const MCCFIInstruction &FPPush = Instrs[++i];
593
30.2k
        assert(FPPush.getOperation() == MCCFIInstruction::OpOffset &&
594
30.2k
               "Frame pointer not pushed!");
595
30.2k
596
30.2k
        unsigned LRReg = MRI.getLLVMRegNum(LRPush.getRegister(), true);
597
30.2k
        unsigned FPReg = MRI.getLLVMRegNum(FPPush.getRegister(), true);
598
30.2k
599
30.2k
        LRReg = getXRegFromWReg(LRReg);
600
30.2k
        FPReg = getXRegFromWReg(FPReg);
601
30.2k
602
30.2k
        assert(LRReg == AArch64::LR && FPReg == AArch64::FP &&
603
30.2k
               "Pushing invalid registers for frame!");
604
30.2k
605
30.2k
        // Indicate that the function has a frame.
606
30.2k
        CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAME;
607
30.2k
        HasFP = true;
608
30.2k
        break;
609
30.2k
      }
610
30.2k
      case MCCFIInstruction::OpDefCfaOffset: {
611
431
        assert(StackSize == 0 && "We already have the CFA offset!");
612
431
        StackSize = std::abs(Inst.getOffset());
613
431
        break;
614
30.2k
      }
615
80.0k
      case MCCFIInstruction::OpOffset: {
616
80.0k
        // Registers are saved in pairs. We expect there to be two consecutive
617
80.0k
        // `.cfi_offset' instructions with the appropriate registers specified.
618
80.0k
        unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true);
619
80.0k
        if (i + 1 == e)
620
0
          return CU::UNWIND_ARM64_MODE_DWARF;
621
80.0k
622
80.0k
        const MCCFIInstruction &Inst2 = Instrs[++i];
623
80.0k
        if (Inst2.getOperation() != MCCFIInstruction::OpOffset)
624
0
          return CU::UNWIND_ARM64_MODE_DWARF;
625
80.0k
        unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true);
626
80.0k
627
80.0k
        // N.B. The encodings must be in register number order, and the X
628
80.0k
        // registers before the D registers.
629
80.0k
630
80.0k
        // X19/X20 pair = 0x00000001,
631
80.0k
        // X21/X22 pair = 0x00000002,
632
80.0k
        // X23/X24 pair = 0x00000004,
633
80.0k
        // X25/X26 pair = 0x00000008,
634
80.0k
        // X27/X28 pair = 0x00000010
635
80.0k
        Reg1 = getXRegFromWReg(Reg1);
636
80.0k
        Reg2 = getXRegFromWReg(Reg2);
637
80.0k
638
80.0k
        if (Reg1 == AArch64::X19 && 
Reg2 == AArch64::X2026.5k
&&
639
80.0k
            
(CompactUnwindEncoding & 0xF1E) == 026.5k
)
640
26.5k
          CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X19_X20_PAIR;
641
53.4k
        else if (Reg1 == AArch64::X21 && 
Reg2 == AArch64::X2218.5k
&&
642
53.4k
                 
(CompactUnwindEncoding & 0xF1C) == 018.5k
)
643
18.5k
          CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X21_X22_PAIR;
644
34.9k
        else if (Reg1 == AArch64::X23 && 
Reg2 == AArch64::X2412.7k
&&
645
34.9k
                 
(CompactUnwindEncoding & 0xF18) == 012.7k
)
646
12.7k
          CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X23_X24_PAIR;
647
22.1k
        else if (Reg1 == AArch64::X25 && 
Reg2 == AArch64::X269.89k
&&
648
22.1k
                 
(CompactUnwindEncoding & 0xF10) == 09.89k
)
649
9.89k
          CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X25_X26_PAIR;
650
12.3k
        else if (Reg1 == AArch64::X27 && 
Reg2 == AArch64::X287.49k
&&
651
12.3k
                 
(CompactUnwindEncoding & 0xF00) == 07.49k
)
652
7.49k
          CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X27_X28_PAIR;
653
4.81k
        else {
654
4.81k
          Reg1 = getDRegFromBReg(Reg1);
655
4.81k
          Reg2 = getDRegFromBReg(Reg2);
656
4.81k
657
4.81k
          // D8/D9 pair   = 0x00000100,
658
4.81k
          // D10/D11 pair = 0x00000200,
659
4.81k
          // D12/D13 pair = 0x00000400,
660
4.81k
          // D14/D15 pair = 0x00000800
661
4.81k
          if (Reg1 == AArch64::D8 && 
Reg2 == AArch64::D92.51k
&&
662
4.81k
              
(CompactUnwindEncoding & 0xE00) == 02.51k
)
663
2.51k
            CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D8_D9_PAIR;
664
2.29k
          else if (Reg1 == AArch64::D10 && 
Reg2 == AArch64::D111.02k
&&
665
2.29k
                   
(CompactUnwindEncoding & 0xC00) == 01.02k
)
666
1.02k
            CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D10_D11_PAIR;
667
1.27k
          else if (Reg1 == AArch64::D12 && 
Reg2 == AArch64::D13643
&&
668
1.27k
                   
(CompactUnwindEncoding & 0x800) == 0643
)
669
643
            CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D12_D13_PAIR;
670
630
          else if (Reg1 == AArch64::D14 && 
Reg2 == AArch64::D15464
)
671
464
            CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D14_D15_PAIR;
672
166
          else
673
166
            // A pair was pushed which we cannot handle.
674
166
            return CU::UNWIND_ARM64_MODE_DWARF;
675
79.9k
        }
676
79.9k
677
79.9k
        break;
678
79.9k
      }
679
110k
      }
680
110k
    }
681
30.6k
682
30.6k
    
if (30.5k
!HasFP30.5k
) {
683
265
      // With compact unwind info we can only represent stack adjustments of up
684
265
      // to 65520 bytes.
685
265
      if (StackSize > 65520)
686
0
        return CU::UNWIND_ARM64_MODE_DWARF;
687
265
688
265
      CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAMELESS;
689
265
      CompactUnwindEncoding |= encodeStackAdjustment(StackSize);
690
265
    }
691
30.5k
692
30.5k
    return CompactUnwindEncoding;
693
30.5k
  }
694
};
695
696
} // end anonymous namespace
697
698
namespace {
699
700
class ELFAArch64AsmBackend : public AArch64AsmBackend {
701
public:
702
  uint8_t OSABI;
703
  bool IsILP32;
704
705
  ELFAArch64AsmBackend(const Target &T, const Triple &TT, uint8_t OSABI,
706
                       bool IsLittleEndian, bool IsILP32)
707
      : AArch64AsmBackend(T, TT, IsLittleEndian), OSABI(OSABI),
708
4.31k
        IsILP32(IsILP32) {}
709
710
  std::unique_ptr<MCObjectTargetWriter>
711
4.31k
  createObjectTargetWriter() const override {
712
4.31k
    return createAArch64ELFObjectWriter(OSABI, IsILP32);
713
4.31k
  }
714
};
715
716
}
717
718
namespace {
719
class COFFAArch64AsmBackend : public AArch64AsmBackend {
720
public:
721
  COFFAArch64AsmBackend(const Target &T, const Triple &TheTriple)
722
91
      : AArch64AsmBackend(T, TheTriple, /*IsLittleEndian*/ true) {}
723
724
  std::unique_ptr<MCObjectTargetWriter>
725
91
  createObjectTargetWriter() const override {
726
91
    return createAArch64WinCOFFObjectWriter();
727
91
  }
728
};
729
}
730
731
MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
732
                                              const MCSubtargetInfo &STI,
733
                                              const MCRegisterInfo &MRI,
734
12.0k
                                              const MCTargetOptions &Options) {
735
12.0k
  const Triple &TheTriple = STI.getTargetTriple();
736
12.0k
  if (TheTriple.isOSBinFormatMachO()) {
737
7.68k
    const bool IsILP32 = TheTriple.isArch32Bit();
738
7.68k
    return new DarwinAArch64AsmBackend(T, TheTriple, MRI, IsILP32);
739
7.68k
  }
740
4.37k
741
4.37k
  if (TheTriple.isOSBinFormatCOFF())
742
91
    return new COFFAArch64AsmBackend(T, TheTriple);
743
4.28k
744
4.28k
  assert(TheTriple.isOSBinFormatELF() && "Invalid target");
745
4.28k
746
4.28k
  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
747
4.28k
  bool IsILP32 = Options.getABIName() == "ilp32";
748
4.28k
  return new ELFAArch64AsmBackend(T, TheTriple, OSABI, /*IsLittleEndian=*/true,
749
4.28k
                                  IsILP32);
750
4.28k
}
751
752
MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T,
753
                                              const MCSubtargetInfo &STI,
754
                                              const MCRegisterInfo &MRI,
755
35
                                              const MCTargetOptions &Options) {
756
35
  const Triple &TheTriple = STI.getTargetTriple();
757
35
  assert(TheTriple.isOSBinFormatELF() &&
758
35
         "Big endian is only supported for ELF targets!");
759
35
  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
760
35
  bool IsILP32 = Options.getABIName() == "ilp32";
761
35
  return new ELFAArch64AsmBackend(T, TheTriple, OSABI, /*IsLittleEndian=*/false,
762
35
                                  IsILP32);
763
35
}